A PCB electromagnetic compatibility diagnosis method

Abstract

This invention provides a PCB electromagnetic compatibility (EMC) diagnostic method. It acquires and parses schematic and PCB data from EDA (Engineering Design Automation) projects to generate a unified intermediate structured representation. An EMC rule base and pre-screening engine are constructed to quickly pre-screen deterministic issues and output evidence. An EMC knowledge base is built and RAG (Research and Analysis Group) retrieval enhancement is implemented. EMC standards / regulatory clauses and chip manufacturer layout guidelines are structurally stored. A "defect-cause-countermeasure" case library is established to support automatic scenario-based retrieval and citation. An EMC expert language model is trained and aligned, with supervised fine-tuning based on labeled cases and standard Q&A, and alignment incorporating engineer preferences. An evaluation set and access control mechanism are established to ensure high-risk conclusions have a chain of evidence. Finally, plug-in interaction and closed-loop feedback are achieved, providing one-click / partial diagnosis, visual annotation, and click-to-locate re-inspection within the EDA system, and supporting report export for review and archiving.

Description

Technical Field

[0001] This invention belongs to the field of PCB layout and electromagnetic compatibility technology, and in particular relates to a PCB electromagnetic compatibility diagnostic method. Background Technology

[0002] With the rapid development of electronic devices towards higher frequencies, higher speeds, and higher densities, the electromagnetic compatibility (EMC) of printed circuit boards (PCBs) has become a key factor determining the success or failure of a product. Poor EMC performance not only leads to the deterioration of internal signal integrity and system instability, but also makes the device a serious source of electromagnetic interference, failing to meet mandatory domestic and international certification standards (such as FCC and CE), resulting in product launch delays or even research and development failures.

[0003] Traditional EMC verification heavily relies on anechoic chamber testing in the later stages of product manufacturing. This method suffers from significant delays, high costs, and diagnostic blind spots: problems can only be discovered after hardware manufacturing is complete, and each failed test means high financial and time costs for iterations; more challenging is that anechoic chamber testing can only determine "whether it exceeds the standard," but it is difficult to accurately locate "where the root cause of the problem is on the PCB," and subsequent rectification relies heavily on the engineer's experience, making the process like "finding a needle in a haystack."

[0004] Meanwhile, the physical root of EMC problems is fundamentally embedded in the PCB layout and routing stages. Design flaws such as discontinuous signal return paths, excessive current loop area, and improper filter circuit layout can all turn PCB copper foil into highly efficient "accidental antennas" under high-speed signal excitation. However, in today's highly complex multilayer board designs, it is nearly impossible to completely avoid these risks through manual inspection.

[0005] Against this backdrop, the industry urgently needs early, rapid, and accurate EMC risk warning technologies during the design phase. While existing EDA tools offer powerful electrical rule checks and simulation capabilities, their full-wave simulations are time-consuming and complex to set up, making them unsuitable for routine, rapid screening. Recent breakthroughs in machine vision and deep learning technologies have provided a new path to solving this problem. By encoding senior engineers' EMC design experience and electromagnetic field theoretical models into automatically executable image recognition algorithms, it becomes possible to predict potential EMC risks directly from the physical design characteristics of PCBs, laying the technological foundation for achieving the ideal of "design right the first time."

[0006] As electronic products develop towards higher frequencies, higher speeds, and higher densities, electromagnetic compatibility (EMC) issues for PCBs are becoming increasingly prominent. Traditional EMC verification relies heavily on anechoic chamber testing during the prototype stage, which has shortcomings such as delayed discovery of problems, high rectification costs, and difficulty in locating issues. Summary of the Invention

[0007] In view of this, the present invention aims to overcome the shortcomings of the above-mentioned problems in the prior art and proposes a PCB electromagnetic compatibility diagnostic method.

[0008] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0009] In a first aspect, the present invention provides a PCB electromagnetic compatibility diagnostic method, which specifically includes the following steps:

[0010] Step 1: Extract structured design data from the PCB design project through the open interface of EDA software. The structured design data includes netlist, bill of materials, key net annotations, layout geometry and process information. If the EDA software interface is limited or the project data cannot be completely exported, a partial rendering image is used as supplementary input.

[0011] Step 2: The design data extracted in Step 1 is parsed and simplified, and the original geometric information is transformed into a structured description language / feature map that can be understood by the large model. The structured description language / feature map includes network-level features, component-level features, and region-level features. Then, a rule-based pre-screening engine is used to identify significant violations using a deterministic geometric topology algorithm to form a set of candidate issues.

[0012] Step 3: Input the candidate question set and structured description language / feature map from Step 2 into the AI ​​expert kernel layer, and sequentially execute EMC-RAG knowledge base construction, multimodal spatial perception feature extraction, expert inference chain analysis, identify high-frequency noise sources in PCB design, check electromagnetic compatibility design defects of noise source networks, identify coupling risks between sensitive objects and noise sources, give risk level judgment based on geometric thresholds, and output diagnostic results.

[0013] Step 4: Display the diagnostic results from Step 3 in the EDA canvas as an overlay of markers / highlighted boxes / heatmaps. Simultaneously display the problem explanation, standard basis, and rectification steps in the sidebar. Clicking on rectification suggestions will automatically locate the corresponding problem object. It also supports exporting the diagnostic report for review and archiving. If the diagnostic results do not meet the design requirements, return to Step 1 to re-integrate the data and perform diagnostic optimization.

[0014] Furthermore, the layout geometry and process information mentioned in step 1 includes the stack-up structure, line width / spacing, via coordinates and type, and reference plane information; the key network annotations include clock, USB, and DDR network annotations.

[0015] Furthermore, the network-level features include length, line width, line spacing, layer distribution, number of vias, segmented topology, continuity of the return reference layer, and distance from the board edge;

[0016] The component-level features include the geometric distance / trace length between the decoupling capacitor and the power pin of the target IC, and the layout density around key components, including crystal oscillators, DC-DC converters, LDOs, connectors, and ADCs / DACs.

[0017] The regional features include ground plane segmentation zones, windows, via fences, copper sheet gaps, and cross-segment routing;

[0018] The significant violations include right-angle routing, crossing the split reference plane, high-speed lines being too close to the board edge, and broken return paths.

[0019] Furthermore, the construction method of the EMC-RAG knowledge base mentioned in step 3 is as follows: EMC standard clauses, chip manufacturer official routing guidelines, and defect-countermeasure case library are sliced, cleaned, and indexed to build a vector database based on Milvus / FAISS; when a specific PCB design object and scenario are detected, the corresponding clauses and guide paragraphs in the database are automatically retrieved as the basis for reasoning. The specific scenarios include high-speed differential lines, clock sources, switching power supply loops, and analog sampling network design scenarios.

[0020] Furthermore, the specific method for multimodal spatial perception feature extraction in step 3 is as follows: the netlist and layout relationship are constructed into a graph structure, with devices, pads, and networks as nodes and connections, couplings, and shared loops as edges. High-order features of current loop closure, shared return path, and coupling adjacency relationship are extracted through graph neural network and used as the input of the embedding large model. If there is missing or incomplete EDA data, a visual language model is introduced to perform alignment verification on the local rendering graph.

[0021] Furthermore, in step 3:

[0022] The high-frequency noise source includes a switching power supply (SW) node, a crystal oscillator / clock generator, and a high-speed interface;

[0023] The sensitive objects include analog sampling networks, LDO feedback, and ADC / DAC;

[0024] The geometric thresholds include the 3W principle threshold, the via number threshold, the plate edge distance threshold, and the reflow breakage criterion threshold;

[0025] The risk levels are divided into three levels: high, medium, and low.

[0026] Furthermore, the large language model of the AI ​​expert kernel layer is trained and aligned in the following ways:

[0027] Training data construction: EMC standard clauses and manufacturer layout guidelines are sliced ​​to generate "question-answer-basis" samples, historical project EMC issues and modification records are collected to form closed-loop samples, simulation / anechoic chamber test out-of-standard frequency bands and suspected source labels are introduced to enhance the monitoring signal, and disturbance samples of typical error layouts are automatically generated based on the rule engine;

[0028] Model training: The model is trained using structured DSL+ retrieved evidence fragments as input and standardized diagnostic reports as output. The standardized diagnostic reports include problem points, risk levels, basis, rectification steps, coordinates / object IDs; senior engineer preference annotations are introduced to align the model output; the training model calls the tool interfaces of rule engine, geometry calculator, impedance calculator, and differential length checker.

[0029] Model evaluation: Construct a high-quality test set covering power circuit, clock, DDR / USB, analog sampling, connector / ESD scenarios, and evaluate the model using recall, false alarm rate, positioning accuracy of coordinate hits, and feasibility of suggestions as indicators;

[0030] Model deployment: Deploy qualified models locally or privately. EDA plugins call inference services via local HTTP / RPC.

[0031] Furthermore, after the model is deployed, engineering data is parsed and feature extracted locally first, and the anonymized structured features and retrieval requests are uploaded only when necessary.

[0032] Furthermore, in step 4, the problem object ID includes the component RefDes, network name, trace segment number, via ID, and copper area ID.

[0033] Secondly, the present invention provides a PCB electromagnetic compatibility diagnostic system, including...

[0034] The EDA plugin layer includes a data access module, a one-click diagnosis module, and a result display module.

[0035] The middleware gateway layer includes an engineering data parsing module and a rule pre-screening engine module;

[0036] The AI ​​expert kernel layer includes the EMC-RAG knowledge base module, the multimodal perception module, and the expert reasoning chain module;

[0037] The EDA plugin layer, the middleware gateway layer, and the AI ​​expert kernel layer are connected in sequence.

[0038] Compared with existing technologies, the PCB electromagnetic compatibility diagnostic method of the present invention has the following advantages:

[0039] (1) In terms of R&D cycle and cost: the discovery point of EMC problems is brought forward from the final "product testing stage" to the "design verification" or "first article production" stage, realizing early warning of problems;

[0040] (2) In terms of quality assurance and reliability: It fundamentally changed the EMC quality control model. It shifted from passively seeking solutions after test failures to proactively identifying and eliminating risks at the design source, realizing the forward shift of quality management and improving the first-time success rate of products;

[0041] (3) In terms of engineering capabilities and efficiency: It can accurately pinpoint potential problems to specific wiring, components, or areas. This provides engineers with clear rectification targets and greatly improves rectification efficiency;

[0042] (4) In terms of application scenarios and flexibility: the software can be adapted to different models of experimental teaching devices, laying the foundation for subsequent development. Attached Figure Description

[0043] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0044] Figure 1 This is a schematic diagram of the overall process of the present invention;

[0045] Figure 2 This is a schematic diagram of the three-layer architecture of the present invention;

[0046] Figure 3 This is a schematic diagram of the EDA plug-in layer of the present invention;

[0047] Figure 4 This is a schematic diagram of the middleware gateway layer of the present invention;

[0048] Figure 5 This is a schematic diagram of the AI ​​expert kernel layer of the present invention. Detailed Implementation

[0049] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0050] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0051] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0052] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0053] Example 1

[0054] This invention advances PCB electromagnetic compatibility (EMC) risk assessment to the schematic / PCB design stage. By analyzing the structured design information output by EDA (such as netlists, BOMs, layer stack-ups, trace geometry and topology), it establishes an interpretable correlation and risk classification mechanism between "design features and EMC risks," enabling early identification, traceability, and reviewability of design defects. Simultaneously, within the EDA interface, it performs coordinate-level location of problematic objects (nets, trace segments, vias, component pads / areas) and generates actionable remediation suggestions. This reduces reliance on the experience of senior EMC engineers, improves design iteration efficiency and first-article test pass rate, thereby reducing the risk of rework and certification failure and improving R&D efficiency. To achieve the above objectives, this invention directly acquires and parses schematic and PCB data from EDA projects and generates a unified intermediate structured representation (such as DSL / JSON feature maps); it constructs an EMC rule base and pre-screening engine to quickly pre-screen deterministic issues such as cross-segment backflow, differential length exceeding thresholds, via anomalies, and long-distance parallelism between sensitive and noisy networks, and outputs evidence; it builds an EMC knowledge base and implements RAG retrieval enhancement, structurally stores EMC standards / regulatory clauses and chip manufacturer layout guidelines, and establishes a "defect-cause-countermeasure" case library to support automatic retrieval and citation based on scenarios; it trains and aligns an EMC expert large language model, performs supervised fine-tuning based on labeled cases and standard Q&A, and aligns with engineer preferences, establishing an evaluation set and access control mechanism to ensure that high-risk conclusions have an evidence chain; finally, it realizes plug-in interaction and closed-loop feedback, providing one-click / partial diagnosis, visual annotation, and click-to-locate re-inspection within EDA, and supports exporting reports for review and archiving.

[0055] This embodiment uses DeepSeek-R1 as an example for illustration, and the process is as follows: Figure 1 This method relies on a PCB EMC intelligent diagnostic plug-in system integrated into EDA software. The system employs a three-layer architecture: EDA plug-in layer + middleware gateway layer + AI expert kernel layer. The core workflow of the method is data extraction and semanticization → EMC inference chain → closed-loop feedback, as follows: Figure 2 As shown, this method enables automatic identification, location, and generation of rectification suggestions for EMC risks in schematic diagrams and PCB routing designs.

[0056] First, there's the EDA plugin layer, such as... Figure 3As shown, this plugin is primarily responsible for design data access and interaction loop. Running on the designer's local computer, it prioritizes directly acquiring engineering data through the EDA software's open interface, rather than relying on screenshots. The plugin extracts from the project: Netlist, Bill of Materials (BOM), key net labels (such as Clock / USB / DDR), layout geometry and process information, including stackup structure, line width / spacing, via coordinates and types, reference plane information, and some intermediate structured formats for subsequent inference. The plugin provides a "one-click diagnostic" entry point. The AI-returned results include object IDs and coordinate regions (including component RefDes, net name, trace segment number, via ID, copper area ID, etc.). The plugin is displayed in the EDA canvas as a Maker / highlighted box / heatmap overlay. The sidebar simultaneously displays problem explanations, standard references, and rectification steps; clicking on suggestions automatically locates the corresponding object. When the EDA software interface is limited or engineering data cannot be completely exported, a partial rendering image can be used as supplementary input, but the main system path still prioritizes structured design data.

[0057] Middle platform gateway layer such as Figure 4 As shown, this layer is responsible for parsing, compressing, and pre-screening the uploaded engineering data according to rules. Because the original PCB file geometric data is enormous, directly inputting it into a large model would lead to high costs, high noise, and unstable inference. Therefore, a middleware gateway layer is set up to structure, semanticize, and pre-screen the data. The first step is parsing and simplification, transforming the original geometric information into a "structured description language (DSL) / feature map" that the large model can understand, including but not limited to:

[0058] Network-level characteristics: length, line width, line spacing, layer distribution, number of vias, segmented topology, continuity of return reference layer, and distance from board edge;

[0059] Component-level characteristics: geometric distance / trace length between decoupling capacitors and the power supply pins of the target IC, and the layout density around key components (crystal oscillators, DC-DC converters, LDOs, connectors, ADCs / DACs, etc.);

[0060] Regional features: ground plane segmentation zones, windows, via fences, copper gaps, cross-segment routing, etc.

[0061] Next is the rule-based pre-screening engine: it uses a deterministic geometric topology algorithm to first identify "significant violations," forming a candidate problem set to reduce the inference pressure on large models and improve consistency. Examples include: right-angled routing, crossing the segmentation reference plane, high-speed lines too close to the board edge, and broken return paths. The pre-screening results will be input into the AI ​​expert kernel as "evidence and features."

[0062] AI expert kernel layer such as Figure 5The system comprises three tasks: EMC-RAG, multimodal perception, and expert reasoning chain. The first step involves building the EMC-RAG knowledge base. The primary sources of material include GB / T 17626 (IEC 61000), CISPR 32, and official routing guidelines from chip manufacturers (such as TI and STM32's "High-Speed ​​Layout Guide"), along with a "defect-countermeasure" case library. These materials are then sliced, cleaned, and indexed to construct a vector database (such as Milvus / FAISS). When the system detects specific objects and scenarios (such as high-speed differential lines, clock sources, switching power supply loops, and analog sampling networks), it automatically retrieves the corresponding clauses and guide paragraphs as the basis for reasoning, ensuring that rectification recommendations are grounded in evidence. The multimodal spatial awareness component constructs a graph structure for the netlist and layout relationships (devices / pads / networks as nodes, connections / coupled loops / shared loops as edges). It uses a graph neural network to extract high-order features such as "current loop closure, shared return paths, and coupling adjacency relationships" as input to the embedding model, improving the understanding of "source-path-sensitive points." When it is necessary to identify local geometric details (silicone markings, trace corner shapes, local decoupling distances, etc.), a visual language model can be introduced to align and verify the local rendered image, compensating for situations where some EDA data is missing or incompletely labeled.

[0063] The AI ​​expert kernel simulates the thought process of a senior EMC engineer, sequentially completing the following steps: identifying high-frequency noise sources (switching power supply SW nodes, crystal oscillators / clock generators, high-speed interfaces, etc.) from the BOM / Netlist / layout; checking the reference plane continuity of the above networks, whether they are split across ground, whether they form large loops, and whether they are parallel to sensitive networks at long distances; identifying whether sensitive objects such as analog sampling networks, LDO feedback, ADC / DAC, etc., are too close to noise sources or share return current; and combining the results of rule-based pre-screening with geometric thresholds (such as the 3W principle, via number threshold, board edge distance threshold, return current breakage criterion, etc.) to determine the risk level (high / medium / low). Figure 2 Output example: "A 12V power line return path near U5 was detected to cross the ground plane partition, posing a high risk of common-mode radiation; it is recommended to move via V12 or fill in the Layer 2 copper area and add a ground via fence."

[0064] Regarding the stable engineering diagnostic capabilities of the Vision large model, this invention provides the following training / alignment process (which can be implemented locally or in a private environment).

[0065] Firstly, regarding the construction of training data, standard clauses and manufacturer layout guidelines are sliced ​​to generate "question-answer-basis" samples (input: scene features; output: rule explanation + cited basis + rectification strategy). Additionally, historical EMC issues and modification records from projects can be collected to form a closed-loop sample of "defect → location → modification → retest results." Simultaneously, out-of-standard frequency bands and suspected source labels from simulation / anechoic chamber tests can be introduced to enhance the supervisory signal. Furthermore, perturbation samples based on the rule engine, automatically generated as "typical error maps" (such as intentionally crossing segments, intentionally widening decoupling, and intentionally increasing loops), improve the model's generalization to boundary conditions.

[0066] During the model training phase, a structured DSL+ evidence fragment is used as input, outputting a standardized diagnostic report (problem points, risk level, basis, rectification steps, coordinates / object ID). Senior engineer preference annotations (more executable, more standard-compliant, fewer false positives) are introduced to align the model output and reduce suggestions that seem reasonable but are impractical. The trained model learns to call tool interfaces such as "rule engine / geometry calculator / impedance calculator / differential length checker" to ensure that key numerical judgments are verifiable.

[0067] Regarding model evaluation, a "golden test set" (covering scenarios such as power circuit, clock, DDR / USB, analog sampling, connector / ESD, etc.) is constructed, with recall rate, false alarm rate, positioning accuracy (coordinate hit) and suggestion executability as indicators.

[0068] After training, the model is deployed locally or privately, and the plugin calls the inference service via local HTTP / RPC. Engineering data is parsed and feature extracted locally first, and only anonymized structured features and retrieval requests are uploaded when necessary to ensure the security and controllability of enterprise design data.

[0069] Example 2

[0070] A PCB electromagnetic compatibility diagnostic system, comprising:

[0071] The EDA plugin layer includes a data access module, a one-click diagnosis module, and a result display module.

[0072] The middleware gateway layer includes an engineering data parsing module and a rule pre-screening engine module;

[0073] The AI ​​expert kernel layer includes the EMC-RAG knowledge base module, the multimodal perception module, and the expert reasoning chain module;

[0074] The EDA plugin layer, the middleware gateway layer, and the AI ​​expert kernel layer are connected in sequence.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for diagnosing electromagnetic compatibility (EMC) of a PCB, characterized in that: Specifically, the steps include the following: Step 1: Extract structured design data from the PCB design project through the open interface of EDA software. The structured design data includes netlist, bill of materials, key net annotations, layout geometry and process information. If the EDA software interface is limited or the engineering data cannot be fully exported, use a partial rendering image as supplementary input. Step 2: Analyze and simplify the design data extracted in Step 1, and transform the original geometric information into a structured description language / feature map that can be understood by the large model. The structured description language / feature map includes network-level features, component-level features, and region-level features. Then, a rule-based pre-screening engine uses a deterministic geometric topology algorithm to identify significant violations, forming a set of candidate issues; Step 3: Input the candidate question set and structured description language / feature map from Step 2 into the AI ​​expert kernel layer, and sequentially execute EMC-RAG knowledge base construction, multimodal spatial perception feature extraction, expert inference chain analysis, identify high-frequency noise sources in PCB design, check electromagnetic compatibility design defects of noise source networks, identify coupling risks between sensitive objects and noise sources, give risk level judgment based on geometric thresholds, and output diagnostic results. Step 4: Display the diagnostic results from Step 3 in the EDA canvas as an overlay of markers / highlighted boxes / heatmaps. Simultaneously display the problem explanation, standard basis, and rectification steps in the sidebar. Clicking on rectification suggestions will automatically locate the corresponding problem object. It also supports exporting the diagnostic report for review and archiving. If the diagnostic results do not meet the design requirements, return to Step 1 to re-integrate the data and perform diagnostic optimization.

2. The PCB electromagnetic compatibility diagnostic method according to claim 1, characterized in that: The layout geometry and process information mentioned in step 1 includes the stack-up structure, line width / spacing, via coordinates and type, and reference plane information; the key network annotations include clock, USB, and DDR network annotations.

3. The PCB electromagnetic compatibility diagnostic method according to claim 1, characterized in that: The network-level features include length, line width, line spacing, layer distribution, number of vias, segmented topology, continuity of the return reference layer, and distance from the board edge; The component-level features include the geometric distance / trace length between the decoupling capacitor and the power pin of the target IC, and the layout density around key components, including crystal oscillators, DC-DC converters, LDOs, connectors, and ADCs / DACs. The regional features include ground plane segmentation zones, windows, via fences, copper sheet gaps, and cross-segment routing; The significant violations include right-angle routing, crossing the split reference plane, high-speed lines being too close to the board edge, and broken return paths.

4. The PCB electromagnetic compatibility diagnostic method according to claim 1, characterized in that: The EMC-RAG knowledge base described in step 3 is constructed as follows: EMC standard clauses, chip manufacturer official routing guidelines, and defect-countermeasure case libraries are sliced, cleaned, and indexed to build a vector database based on Milvus / FAISS; when a specific PCB design object and scenario are detected, the corresponding clauses and guide paragraphs in the database are automatically retrieved as the basis for reasoning. The specific scenarios include high-speed differential lines, clock sources, switching power supply loops, and analog sampling network design scenarios.

5. The PCB electromagnetic compatibility diagnostic method according to claim 1, characterized in that: The specific method for multimodal spatial perception feature extraction in step 3 is as follows: construct the netlist and layout relationship into a graph structure, with devices, pads, and networks as nodes and connections, couplings, and shared loops as edges. Extract high-order features of current loop closure, shared return path, and coupling adjacency relationship through graph neural network as the input of the embedding large model; if there is missing or incomplete EDA data, introduce a visual language model to perform alignment verification on the local rendering graph.

6. The PCB electromagnetic compatibility diagnostic method according to claim 1, characterized in that: In step 3: The high-frequency noise source includes a switching power supply (SW) node, a crystal oscillator / clock generator, and a high-speed interface; The sensitive objects include analog sampling networks, LDO feedback, and ADC / DAC; The geometric thresholds include the 3W principle threshold, the via number threshold, the plate edge distance threshold, and the reflow breakage criterion threshold; The risk levels are divided into three levels: high, medium, and low.

7. The PCB electromagnetic compatibility diagnostic method according to claim 1, characterized in that: The large language model of the AI ​​expert kernel layer is trained and aligned in the following ways: Training data construction: EMC standard clauses and manufacturer layout guidelines are sliced ​​to generate "question-answer-basis" samples, historical project EMC issues and modification records are collected to form closed-loop samples, simulation / anechoic chamber test out-of-standard frequency bands and suspected source labels are introduced to enhance the monitoring signal, and disturbance samples of typical error layouts are automatically generated based on the rule engine; Model training: The model is trained using structured DSL+ retrieved evidence fragments as input and standardized diagnostic reports as output. The standardized diagnostic reports include problem points, risk levels, basis, rectification steps, coordinates / object IDs; senior engineer preference annotations are introduced to align the model output; the training model calls the tool interfaces of rule engine, geometry calculator, impedance calculator, and differential length checker. Model evaluation: Construct a high-quality test set covering power circuit, clock, DDR / USB, analog sampling, and connector / ESD scenarios, and evaluate the model using recall, false alarm rate, positioning accuracy of coordinate hits, and feasibility of suggestions as indicators; Model deployment: Deploy qualified models locally or privately. EDA plugins call inference services via local HTTP / RPC.

8. A PCB electromagnetic compatibility diagnostic method according to claim 7, characterized in that: After the model is deployed, engineering data is parsed and feature extracted locally first, and the anonymized structured features and retrieval requests are uploaded only when necessary.

9. A PCB electromagnetic compatibility diagnostic method according to claim 1, characterized in that: In step 4, the problem object ID includes the component RefDes, network name, trace segment number, via ID, and copper area ID.

10. A PCB electromagnetic compatibility diagnostic system, characterized in that: include The EDA plugin layer includes a data access module, a one-click diagnosis module, and a result display module. The middleware gateway layer includes an engineering data parsing module and a rule pre-screening engine module; The AI ​​expert kernel layer includes the EMC-RAG knowledge base module, the multimodal perception module, and the expert reasoning chain module; The EDA plugin layer, the middleware gateway layer, and the AI ​​expert kernel layer are connected in sequence.

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