Layout test case generation method, apparatus and related equipment

Abstract

This disclosure provides a layout test case generation method, apparatus, and related equipment. The layout test cases are used for design rule checking of semiconductor devices. The method includes: converting the design rules of the semiconductor device into a first numerical vector using a first encoding method; converting the first layout test cases into a second numerical vector using a second encoding method; calling a pre-trained neural network model, and using the neural network model to output a second layout test case based on the first and second numerical vectors; wherein the first and second numerical vectors are one-dimensional numerical sequences including multiple values.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device fabrication technology, and in particular to a layout test case generation method, apparatus and related equipment. Background Technology

[0002] Design Rule Check (DRC) is used to verify whether the layout design conforms to the process manufacturing rules provided by the foundry.

[0003] Existing layout test cases for design rule checks typically rely on the personal experience and intuition of senior verification engineers. Engineers manually draw graphical structures that trigger specific rules in layout editing tools by reading and understanding DRC rule files, and save them as layout test cases.

[0004] However, manually designed layout test cases are not only inefficient to generate, but also difficult to fully cover all design rules.

[0005] Therefore, providing a method for generating layout test cases to improve the efficiency and coverage of layout test case generation, thereby more effectively verifying the correctness of DRC, has become a challenge. Summary of the Invention

[0006] To address the aforementioned technical problems, this disclosure provides a layout test case generation method, apparatus, and related equipment, which can not only improve the generation efficiency of layout test cases but also increase the coverage of the output layout test cases.

[0007] In a first aspect, embodiments of this disclosure provide a layout test case generation method, wherein the layout test cases are used for design rule checks of semiconductor devices, and the method includes: The design rules of the semiconductor device are converted into a first numerical vector using a first encoding method; The first layout test cases are converted into a second numerical vector using a second encoding method. Call the pre-trained neural network model, and use the neural network model to output the second layout test cases based on the first numerical vector and the second numerical vector; Wherein, the first numerical vector and the second numerical vector are one-dimensional numerical sequences including multiple numerical values.

[0008] Optionally, the first encoding method and the second encoding method are the same.

[0009] Optionally, the first encoding method and the second encoding method include a hybrid encoding method, which is an encoding method that includes at least two different encoding rules.

[0010] Optionally, the hybrid encoding method includes at least: Parametric geometric coding and discrete rule coding.

[0011] Optionally, the pre-trained neural network model includes a first sub-model and a second sub-model, wherein: The first sub-model is configured to output a target design rule based on the first numerical vector and the second numerical vector, wherein the target design rule is a design rule in the design rules of the semiconductor device that is not covered by the first layout test case; The second sub-model is configured to output second layout test cases based on the target design rules.

[0012] Optionally, the first sub-model includes a multilayer perceptron; The second sub-model includes a conditional generative adversarial network, which comprises a generator and a discriminator, wherein: The generator includes a deconvolutional neural network model; The discriminator includes a convolutional neural network model.

[0013] Optionally, the first sub-model is trained based on a first training dataset, which includes multiple first training samples. Each first training sample includes first sample features and first sample labels. The first sample features include design rule features and layout test case features designed for the design rules. The first sample labels include the test results of the layout test cases on the testing tool, and the test results include test pass and test fail.

[0014] Optionally, the second sub-model is trained based on a second training dataset, which includes multiple second training samples and multiple third training samples. The second training samples include second sample features and second sample labels, and the third training samples include third sample features and third sample labels, wherein: The second sample features include the features of the third layout test cases and the features of the design rules triggered by the third layout test cases; the second sample label is real. The third sample feature includes a fourth layout test case feature and a first design rule feature. The fourth layout test case feature is generated by the generator based on the first design rule.

[0015] Secondly, embodiments of this disclosure provide a layout test case generation apparatus, wherein the layout test cases are used for design rule checks of semiconductor devices, and the apparatus includes: The first data processing circuit is configured to convert the design rules of the semiconductor device into a first numerical vector using a first encoding method. The second data processing circuit is configured to convert the first layout test cases into a second numerical vector using a second encoding method. The processor is configured to invoke a pre-trained neural network model and, using the neural network model, output second layout test cases based on the first numerical vector and the second numerical vector. Wherein, the first numerical vector and the second numerical vector are one-dimensional numerical sequences including multiple numerical values.

[0016] Thirdly, embodiments of this disclosure provide a storage medium storing a computer program thereon, wherein the computer program, when run by a processor, executes the steps of the layout test case generation method described in any of the above embodiments.

[0017] Fourthly, embodiments of this disclosure provide a computer program product, including a computer program, wherein the computer program, when running, executes the steps of the layout test case generation method described in any of the above embodiments.

[0018] The layout test case generation method provided in this disclosure uses a first encoding method to convert the design rules of the semiconductor device into a one-dimensional numerical sequence including multiple values, i.e., a first numerical vector. A second encoding method is used to convert the first layout test case into a one-dimensional numerical sequence including multiple values, i.e., a second numerical vector. A pre-trained neural network model is then invoked, and the neural network model outputs a second layout test case based on the first and second numerical vectors. As can be seen, this method, by converting the semiconductor device design rules into a first numerical vector and the first layout test case into a second numerical vector, establishes a correspondence between data of different modalities, allowing the neural network model to learn the matching relationship between the physical rules in the design rules and the geometric structures in the first layout test case. Furthermore, compared to converting the semiconductor device design rules into text, converting them into a first numerical vector improves the accuracy of the physical rules acquired by the neural network model; and compared to converting the first layout test case into a pixel image, it improves the accuracy of the geometric structures acquired by the neural network model. Therefore, this method not only improves the generation efficiency of layout test cases but also increases the coverage of the output layout test cases. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0020] Figure 1 A flowchart illustrating a layout test case generation method consistent with some embodiments of this disclosure is shown.

[0021] Figure 2 A structural example diagram of a layout test case generation apparatus consistent with some embodiments of this disclosure is shown. Detailed Implementation

[0022] Manually designed layout test cases are not only inefficient to generate, but also difficult to fully cover all design rules.

[0023] To facilitate understanding, the following is a brief introduction to DRC and the technical issues it presents.

[0024] In the physical implementation phase of integrated circuit design, designers use electronic design automation (EDA) tools to complete the layout design. This layout consists of geometric shapes of different process layers and is used for subsequent photomask manufacturing and chip tape-out.

[0025] To ensure that the designed layout matches the specified semiconductor process manufacturing capabilities, thereby improving product yield, physical verification must be performed. Design Rule Checking (DRC) is the core component of physical verification. DRC compares the geometry in the layout with the design rules provided by the foundry to check for violations of process constraints, such as insufficient minimum linewidth, excessively close spacing, excessive pattern density, or antenna effects. These design rules are key geometric constraints extracted by the foundry based on the physical limits and empirical data of process equipment such as photolithography, etching, and chemical mechanical polishing.

[0026] DRC verification typically relies on DRC Runset files (i.e., rule set files) provided by the foundry. This file is a specific code set (such as Calibre SVRF, Synopsys TCL+, etc.) that translates design rules described in natural language (such as "the width of metal layer 1 must be greater than or equal to 0.18 micrometers") into instructions recognizable by EDA tools. After loading the Runset file, the verification tool performs calculations and measurements on the layout, ultimately outputting the coordinates of the points that violate the rules, i.e., DRC errors. The DRC Runset file is provided by the foundry and developed by PDK engineers based on the DR (Design Rule) file according to the syntax of EDA tools (such as Calibre's SVRF syntax). Users use the DRC Runset file to perform DRC checks on the layout.

[0027] DRC QA is a quality check of the DRC Runset file. The check includes whether the DRC Runset covers every rule in the DR and whether it can accurately detect every DRC error.

[0028] The DRC QA test case set is a series of test cases (patterns) designed by PDK engineers when performing QA on the DRC Runset. Essentially, it is a layout, divided into Good Pattern and Bad Pattern. A Good Pattern is a pattern that does not violate DRC and is expected to result in no DRC error; a Bad Pattern is a pattern that violates DRC and is expected to result in a DRC error.

[0029] Traditional DRC QA typically relies on manually constructed test cases, which is not only inefficient but also prone to overlooking certain boundary conditions or complex combination rules. This can lead to defective layouts going undetected, resulting in economic losses from tape-out failures. As process technology continues to advance to more advanced nodes (such as 7nm, 5nm and below), the number of design rules is exploding, and the logical relationships between rules are becoming increasingly complex. This brings about the following technical problems: Firstly, test case coverage heavily relies on experience and cannot guarantee comprehensiveness. Engineers' mindset and knowledge gaps can lead to coverage blind spots in the test case set.

[0030] Secondly, it is inefficient and cannot cope with the rapid iteration of rule files. Manually designing test cases for typical and boundary cases for each new rule is an extremely time-consuming and labor-intensive process. At advanced process nodes, DRC rules are updated frequently, making it difficult for the QA team to respond quickly.

[0031] Thirdly, it is difficult to construct test cases for complex interactive scenarios. Many DRC errors occur under complex spatial interactions involving multiple rules and layers. It is difficult for humans to conceive and draw the layout scenarios that can accurately trigger such complex interaction patterns.

[0032] Fourthly, test cases suffer from redundancy and efficiency bottlenecks. Over time, the test case library becomes large and bloated, containing a large number of functionally redundant test cases. Executing all test cases takes a long time, but it is difficult to effectively optimize the minimum set manually, leading to a waste of computing resources and an extension of the QA cycle.

[0033] As can be seen from the above, providing a more comprehensive and higher-quality DRC QA test case set is of great significance for improving the quality and reliability of DRC.

[0034] To address the aforementioned issues, embodiments of this disclosure provide several methods for generating layout test cases. These methods employ a first encoding method to convert the design rules of the semiconductor device into a one-dimensional numerical sequence comprising multiple values, i.e., a first numerical vector. A second encoding method is then used to convert the first layout test case into a one-dimensional numerical sequence comprising multiple values, i.e., a second numerical vector. By calling a pre-trained neural network model, the neural network model outputs a second layout test case based on the first and second numerical vectors. As can be seen, by converting the semiconductor device design rules into a first numerical vector and the first layout test case into a second numerical vector, the method, on the one hand, establishes a correspondence between data of different modalities, enabling the neural network model to learn the matching relationship between the physical rules in the design rules and the geometric structures in the first layout test case; on the other hand, compared to converting the semiconductor device design rules into text, converting them into a first numerical vector improves the accuracy of the physical rules acquired by the neural network model; and compared to converting the first layout test case into a pixel image, it improves the accuracy of the geometric structures acquired by the neural network model. Therefore, the method not only improves the efficiency of layout test case generation but also increases the coverage of the output layout test cases.

[0035] To enable those skilled in the art to better understand and implement the embodiments of this disclosure, the concepts, schemes, principles, and advantages of the embodiments of this disclosure are described in detail below with reference to the accompanying drawings and through specific application examples.

[0036] Figure 1A flowchart illustrating a layout test case generation method consistent with some embodiments of this disclosure is shown. In some embodiments, the method can be executed by an integrated circuit. In some embodiments, the method can be executed by a processor, which may include logic processing units, arithmetic processing units, and storage units such as registers and caches. In one implementation, the processor may be a central processing unit (CPU), a microprocessor, or an FPGA (field programmable gate array). Furthermore, the processor can also implement certain functions through the logical relationships of hardware circuits, which may be fixed or reconfigurable, such as hardware circuits implemented by the processor for a PLD, or an FPGA. In reconfigurable hardware circuits, the process of the processor loading a configuration document to configure the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units.

[0037] Reference Figure 1 In some embodiments, the layout test case generation method may include steps A, B, C, and D. It is understood that the layout test case generation method may include more or fewer steps, and the order of the steps may be the same or different.

[0038] Step A: The design rules of the semiconductor device are converted into a first numerical vector using a first encoding method.

[0039] In some embodiments, the first encoding method includes a hybrid encoding method, which is an encoding method that includes at least two different encoding rules.

[0040] In some embodiments, the hybrid encoding method includes at least: parametric geometric encoding and discrete rule encoding.

[0041] In some embodiments, parametric geometric coding is a coding method for extracting parameterizable features (e.g., line width, spacing, graphic complexity, etc.).

[0042] In some embodiments, discrete rule encoding includes one-hot encoding.

[0043] In some embodiments, DRC rules are typically written in a specific rule file (such as Calibre SVRF, Synopsys TCL+, OpenAccess, etc.).

[0044] In some embodiments, the design rules of a semiconductor device can be converted into a first numerical vector by following these steps: S1: Parse each DRC rule from the text (such as Calibre SVRF syntax) to extract key elements, such as rule type, layer, parameters, and constraints.

[0045] S2: Convert the parsed results into structured data.

[0046] In some embodiments, rule types (such as "width", "spacing", "area", etc.) can be converted into structured data through one-hot encoding.

[0047] In some embodiments, layers (such as “metal”, “polysilicon gate”, etc.) can be converted into structured data through one-hot encoding.

[0048] In some embodiments, constraint values ​​(such as min space 0.12 μm) can be converted into structured data through parametric geometric encoding.

[0049] In some embodiments, geometric relationships (such as "parallel", "perpendicular", "containment", etc.) can be converted into structured data through one-hot encoding.

[0050] S3: Concatenate all features into the final vector.

[0051] The following example illustrates how to use a first encoding method to convert the design rules of a semiconductor device into a first numerical vector.

[0052] For example, the DRC rule is: metal1 spacing >= 0.12.

[0053] The key elements identified are: Rule type: Spacing; Layer: Metal 1; Constraint value: 0.12; Geometric relationship: Parallel.

[0054] The parsed results are converted into structured data as follows: Rule type: Spacing → [1,0,0] (assuming three types: width, spacing, area); Layer: Metal 1 → [0,1,0,0] (four-layer one-hot encoding); Constraint value: 0.12; Geometric relationship: Parallel → [1,0] (two relationships: parallel, perpendicular); First numerical vector: [1,0,0,0,1,0,0,0.12,1,0].

[0055] Step B involves using a second encoding method to convert the first layout test cases into a second numerical vector.

[0056] In some embodiments, a first layout test case may include a graphical structure that can trigger specific rules, which is manually drawn by an engineer in a layout editing tool according to the design rules of a semiconductor device, and saved as a test case.

[0057] In some embodiments, the first encoding method and the second encoding method are the same.

[0058] By using the above embodiments, when converting the design rules of semiconductor devices into a first numerical vector and the first layout test cases into a second numerical vector, the same encoding method can be used to establish an accurate mapping relationship between unstructured or structured design rules and structured or geometric first layout test cases. This can further improve the learning efficiency and accuracy of the neural network model in learning the matching relationship between the physical rules in the design rules and the geometric structure in the first layout test cases, thereby further improving the coverage of the output layout test cases.

[0059] In some embodiments, the second encoding method includes a hybrid encoding method, which is an encoding method that includes at least two different encoding rules.

[0060] In some embodiments, the first layout test cases are typically in GDSII format.

[0061] In some embodiments, the first layout test cases can be converted into a second numerical vector by following these steps: S1: Use the open-source GDSII to parse Python scripts (such as gdstk or gdspy) to extract geometric shapes and their attributes (layers, coordinates, shape types, etc.).

[0062] S2: Structural feature extraction.

[0063] In some embodiments, structural features may include graphic type (rectangle, polygon, path), layer information, key dimensions (width, spacing, area), and topological relationships (adjacent, overlapping, containing).

[0064] S3: Structural feature encoding.

[0065] In some embodiments, one-hot encoding may be used for shape types.

[0066] In some embodiments, one-hot encoding may be used for layers.

[0067] In some embodiments, a parametric geometric encoding method may be used for dimensions.

[0068] In some embodiments, the numerical values ​​obtained using parametric geometric encoding can be normalized.

[0069] S4: Aggregate into a fixed vector.

[0070] In some embodiments, if a test case contains multiple graphs, they can be aggregated into a fixed-length vector using pooling (e.g., mean, maximum) or a graph neural network.

[0071] The following example illustrates how to use a second encoding method to convert test cases from a first layout into a second numerical vector.

[0072] For example, a first-layout test case might consist of two rectangles with layer MET1 and a spacing of 0.08 μm, with the expected error message.

[0073] The structural characteristics of the extracted first version of the test cases are as follows: Shape type: rectangle; Layer: MET1; Dimensions: width 0.1μm, spacing 0.08μm; Geometric relationship: parallel.

[0074] The structural feature encoding is as follows: Shape type: Rectangle → [1,0] (two-layer one-hot encoding); Layer: MET1→[0,1,0,0] (four-layer one-hot encoding); Dimensions: Width 0.1μm, Spacing 0.08μm; Geometric relationship: parallel; Second numerical vector: [1,0,0,1,0,0,0.1,0.08,1,0].

[0075] Step C: Invoke the pre-trained neural network model and use the neural network model to output the second layout test cases based on the first numerical vector and the second numerical vector.

[0076] In some embodiments, the pre-trained neural network model includes a first sub-model and a second sub-model, wherein: The first sub-model is configured to output a target design rule based on the first numerical vector and the second numerical vector, wherein the target design rule is a design rule in the design rules of the semiconductor device that is not covered by the first layout test case; The second sub-model is configured to output second layout test cases based on the target design rules.

[0077] By adopting the above embodiments, the matching relationship between the physical rules in the design rules and the geometric structures in the first layout test case can be learned through the first sub-model, and the design rules not covered by the first layout test case in the design rules of semiconductor devices can be output. Through the second sub-model, a second layout test case covering the design rules not covered by the first layout test case can be output. On the one hand, by outputting the second layout test case through the second sub-model, the coverage blind spots caused by insufficient manual experience can be avoided, and the generation efficiency of layout test cases can be improved to match the frequently updated DRC rules. On the other hand, by detecting the coverage rate of the existing first layout test case through the first sub-model, directly outputting the design rules not covered by the first layout test case in the design rules of semiconductor devices, and then generating a second layout test case by the second sub-model for the design rules not covered by the first layout test case, the coverage rate of the layout test case can be improved, so as to more effectively verify the correctness of DRC.

[0078] In some embodiments, the first sub-model may include a multi-layer perceptron.

[0079] In some embodiments, the multi-layer perceptron may include an input layer, a hidden layer, and an output layer. The input layer is used to receive the features of the original data. The hidden layer is located between the input layer and the output layer and is the core computing unit of the multi-layer perceptron. A multi-layer perceptron may have one or more hidden layers. The neurons in each hidden layer receive the outputs of all neurons in the previous layer, and after calculation, they are passed to the next layer. The output layer generates the final prediction result.

[0080] By adopting the above embodiments, since there is a clear numerical threshold or linear inequality relationship between the design rules of semiconductor devices and the first layout test case, for example, width < min_width, and the hidden layer of the multi-layer perceptron can efficiently express this relationship through a piecewise linear activation function, the accuracy of the output target design rules can be improved.

[0081] In addition, since the first numerical vector and the second numerical vector are obtained through a hierarchical encoding method such as parametric geometric encoding and discrete rule encoding, the physical characteristics of the design rules and the first layout test case can be retained, so that each value of the first numerical vector and the second numerical vector can correspond to an actual physical meaning, and each value of the multi-layer perceptron corresponds to a neuron in the input layer, and the number of neurons in the input layer is equal to the feature dimension. By adopting the above solution, the multi-layer perceptron can perform accurate numerical comparison and constraint learning, thereby further improving the accuracy of the output target design rules.

[0082] In some embodiments, the first sub-model is trained based on a first training dataset, which includes multiple first training samples. Each first training sample includes first sample features and first sample labels. The first sample features include design rule features and layout test case features designed for the design rules. The first sample labels include the test results of the layout test cases on a testing tool, and the test results include test pass and test fail.

[0083] In some embodiments, the design rule features may include a first numerical vector of the design rule obtained by conversion using a first encoding method.

[0084] In some embodiments, the layout test case features designed for the design rules may include a second numerical vector of the layout test cases obtained by conversion using a second encoding method.

[0085] In some embodiments, the sample label may come from historical DRCQA execution results, i.e., whether this layout test case actually triggered the rule (e.g., the DRC tool reported an error). This label is obtained after being checked by a DRC EDA tool (e.g., calibre).

[0086] The following example illustrates how to obtain the first training sample.

[0087] The first numerical vector obtained by transforming based on the DRC rule "metal1 spacing>= 0.12" is [1,0,0,0,1,0,0,0.12,1,0].

[0088] The second numerical vector obtained by converting the first layout test case "containing two rectangles of layer MET1 with a spacing of 0.08μm, expected to report an error" is [1,0,0,1,0,0,0.1,0.08,1,0].

[0089] When the test result of the first layout test case on the DRC EDA tool is a pass, the sample label can be set to 1; when the test result of the first layout test case on the DRC EDA tool is a failure, the sample label can be set to 0.

[0090] By concatenating the first and second numerical vectors and adding corresponding labels, such as 1, we can obtain the training samples: [1,0,0,0,1,0,0,0.12,1,0,1,0,0,1,0,0,0.1,0.08,1,0,1].

[0091] In some embodiments, the second sub-model includes a conditional generative adversarial network, which includes a generator and a discriminator, wherein: The generator includes a deconvolutional neural network model; The discriminator includes a convolutional neural network model.

[0092] In some embodiments, the second sub-model is trained based on a second training dataset, which includes multiple second training samples and multiple third training samples. The second training samples include second sample features and second sample labels, and the third training samples include third sample features and third sample labels, wherein: The second sample features include the features of the third layout test cases and the features of the design rules triggered by the third layout test cases; the second sample label is real. The third sample feature includes a fourth layout test case feature and a first design rule feature. The fourth layout test case feature is generated by the generator based on the first design rule.

[0093] In some embodiments, third layout test cases may include engineers manually drawing graphical structures in a layout editing tool that can trigger specific rules according to the design rules of semiconductor devices, and saving them as test cases.

[0094] In some embodiments, the features of the third layout test case may include a second numerical vector of the layout test case obtained by conversion using a second encoding method.

[0095] In some embodiments, the design rules that the third layout test cases can trigger include a first numerical vector of the design rules obtained by conversion using a first encoding method.

[0096] In some embodiments, the fourth layout test case features may include a second numerical vector of the layout test cases obtained by conversion using a second encoding method.

[0097] In some embodiments, the first design rule feature may include a first numerical vector of the design rule obtained by conversion using a first encoding method.

[0098] In some embodiments, the first design rule may include the design rule for any semiconductor device.

[0099] The following example illustrates how to obtain a second training sample.

[0100] The first numerical vector obtained by transforming based on the DRC rule "metal1 spacing>= 0.12" is [1,0,0,0,1,0,0,0.12,1,0].

[0101] The second numerical vector obtained by the third-page test case that can trigger the above DRC rule, "containing two rectangles with MET1 layer and a spacing of 0.08μm", is [1,0,0,1,0,0,0.1,0.08,1,0].

[0102] The sample is labeled "real", for example, it can be represented by the number "1".

[0103] The following example illustrates how to obtain a third training sample.

[0104] Input the following to the generator: the first numerical vector of the design rule obtained by the first encoding method + random noise z; Generator output: Initially a random map, which gradually approximates the real map after training; The sample is labeled "fake," for example, it can be represented by the number "0."

[0105] The following example illustrates the model architecture and workflow of the second sub-model.

[0106] Model architecture: The test case generation model uses a conditional generative adversarial network, which includes two core components: I. Generator Input: Numerical vector R of the target DRC rule + random noise vector z (normally distributed sampling).

[0107] Output: A numerical representation of the layout structure Network structure: Deconvolutional neural network, which maps low-dimensional conditional vectors and noise into a layout representation in a high-dimensional space.

[0108] II. Discriminator Input: Numerical representation of the layout structure + corresponding DRC rule vector R.

[0109] Output: A scalar indicating whether the layout matches the rule.

[0110] Network structure: Convolutional Neural Network.

[0111] Workflow: I. Training Phase Constructing a training set from historical data: Real samples (second training samples): a layout representation of existing test cases + the DRC rule vectors that can be triggered (labeled "real").

[0112] Fake sample (third training sample): The layout representation generated by the generator + the corresponding rule vector (labeled "fake").

[0113] The generator attempts to produce a layout sufficient to fool the discriminator, while the discriminator tries to distinguish between real and fake layouts. Both are trained adversarially to optimize the layout, and eventually the generator learns to produce layouts that effectively trigger specified rules.

[0114] II. Application Phase Input a numerical vector R of a DRC rule for “undercoverage” output by the first sub-model.

[0115] The generator produces a corresponding layout representation.

[0116] The numerical layout representation is converted to GDSII format and added to the test set as a new test case.

[0117] This disclosure also provides a layout test case generation apparatus. (Refer to...) Figure 2 The diagram shown is a structural example of a layout test case generation apparatus consistent with some embodiments of this disclosure. In some embodiments, the layout test case generation apparatus T may include: The first data processing circuit T1 is configured to use a first encoding method to convert the design rules of the semiconductor device into a first numerical vector.

[0118] The second data processing circuit T2 is configured to use a second encoding method to convert the first layout test cases into a second numerical vector.

[0119] In some embodiments of this disclosure, the first data processing circuit and the second data processing circuit can be implemented using integrated circuits. In some embodiments, the first data processing circuit and the second data processing circuit can be implemented using processors, such as central processing units (CPUs), microprocessors, or field-programmable gate arrays (FPGAs). In some embodiments, the first data processing circuit and the second data processing circuit can be implemented using a combination of integrated circuits and processors.

[0120] Processor T3 is configured to call a pre-trained neural network model and use the neural network model to output second layout test cases based on the first numerical vector and the second numerical vector; Wherein, the first numerical vector and the second numerical vector are one-dimensional numerical sequences including multiple numerical values.

[0121] In some embodiments of this disclosure, the processor may include a central processing unit (CPU), a microprocessor, or a field programmable gate array (FPGA), etc.

[0122] In this embodiment of the disclosure, the layout test case generation device can use the layout test case generation method described in any of the foregoing embodiments to generate a second layout test case. The specific steps can be found in the foregoing embodiments and will not be repeated here.

[0123] This disclosure also provides a storage medium storing a computer program, which, when executed by a processor, performs the steps of the layout test case generation method described in any of the above embodiments. Specific steps can be found in the foregoing embodiments and will not be repeated here.

[0124] In some embodiments of this disclosure, the storage medium may be various suitable readable storage media such as optical discs, hard disk drives, and solid-state drives.

[0125] This disclosure also provides a computer program product, including a computer program that, when executed, performs the steps of the layout test case generation method described in any of the above embodiments. Specific steps can be found in the foregoing embodiments and will not be repeated here.

[0126] It should be noted that the circuits in the embodiments of this disclosure can be composed of discrete components or implemented by a single electrical chip.

[0127] In this disclosure, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish and describe related objects, and should not be construed as indicating or implying the relative importance or order between related objects. Furthermore, ordinal numbers do not represent the quantity of related objects.

[0128] The terms "or" and "and / or" in this disclosure are used to describe relationships between related objects, indicating a non-exclusive inclusion. For example, "A and / or B" and "A or B" can both include: "A alone," "B alone," or "A and B," where "A" and "B" can include a single object or multiple objects. Similarly, "A, B and / or C," "A, B or C," and "A, B and C" can both include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B and C," where "A," "B," and "C" can include a single object or multiple objects. Additionally, the " / " in this disclosure is used to indicate an "or" relationship between related objects. The meanings of "at least one of A or B" and "one or more of A and B" in this disclosure are the same as the meaning of "A or B" above. The meanings of "one or more of A, B, and C" and "at least one of A, B, or C" are the same as the meaning of "A, B, or C" above. The meaning of "one or more of A, B, and C" is the same as the meaning of "A, B, or C" above.

[0129] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the above embodiments can be freely combined as needed. Although the embodiments of this disclosure have been disclosed above, this disclosure is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this disclosure.

Claims

1. A method for generating layout test cases, characterized in that, The layout test cases are used for design rule checks on semiconductor devices, and the method includes: The design rules of the semiconductor device are converted into a first numerical vector using a first encoding method; The first layout test cases are converted into a second numerical vector using a second encoding method. Call the pre-trained neural network model, and use the neural network model to output the second layout test cases based on the first numerical vector and the second numerical vector; Wherein, the first numerical vector and the second numerical vector are one-dimensional numerical sequences including multiple numerical values.

2. The method according to claim 1, characterized in that, The first encoding method and the second encoding method are the same.

3. The method according to claim 2, characterized in that, The first encoding method and the second encoding method include a hybrid encoding method, which is an encoding method that includes at least two different encoding rules.

4. The method according to claim 3, characterized in that, The hybrid encoding method includes at least the following: Parametric geometric coding and discrete rule coding.

5. The method according to claim 1, characterized in that, The pre-trained neural network model includes a first sub-model and a second sub-model, wherein: The first sub-model is configured to output a target design rule based on the first numerical vector and the second numerical vector, wherein the target design rule is a design rule in the design rules of the semiconductor device that is not covered by the first layout test case; The second sub-model is configured to output second layout test cases based on the target design rules.

6. The method according to claim 5, characterized in that, The first sub-model includes a multilayer perceptron; The second sub-model includes a conditional generative adversarial network, which comprises a generator and a discriminator, wherein: The generator includes a deconvolutional neural network model; The discriminator includes a convolutional neural network model.

7. The method according to claim 6, characterized in that, The first sub-model is trained based on a first training dataset, which includes multiple first training samples. Each first training sample includes first sample features and first sample labels. The first sample features include design rule features and layout test case features designed for the design rules. The first sample labels include the test results of the layout test cases on the testing tool, and the test results include test pass and test fail.

8. The method according to claim 6, characterized in that, The second sub-model is trained based on a second training dataset, which includes multiple second training samples and multiple third training samples. The second training samples include second sample features and second sample labels, and the third training samples include third sample features and third sample labels, wherein: The second sample features include the features of the third layout test cases and the features of the design rules triggered by the third layout test cases; the second sample label is real. The third sample feature includes a fourth layout test case feature and a first design rule feature. The fourth layout test case feature is generated by the generator based on the first design rule.

9. A layout test case generation device, characterized in that, The layout test cases are used for design rule checks on semiconductor devices, and the apparatus includes: The first data processing circuit is configured to convert the design rules of the semiconductor device into a first numerical vector using a first encoding method. The second data processing circuit is configured to convert the first layout test cases into a second numerical vector using a second encoding method. The processor is configured to invoke a pre-trained neural network model and, using the neural network model, output second layout test cases based on the first numerical vector and the second numerical vector. Wherein, the first numerical vector and the second numerical vector are one-dimensional numerical sequences including multiple numerical values.

10. A storage medium having a computer program stored thereon, characterized in that, The computer program, when executed by a processor, performs the steps of the layout test case generation method according to any one of claims 1 to 8; and A computer program product, comprising a computer program, characterized in that, The computer program executes the steps of the layout test case generation method according to any one of claims 1 to 8 when it runs.

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