A fragmented wafer reconstruction method, apparatus and system

Abstract

This invention discloses a fragmented wafer reconstruction method, device, and system, relating to the field of wafer defect scanning. It includes: driving a detection machine to sequentially scan the dies in the wafer; if the current die is a normal die, acquiring the coordinate information of the current die; if the current die is an abnormal die, calculating the coordinate information of the next normal die based on the coordinate information of the previous die, and using the calculated next normal die as the current die; generating a continuous wafer map based on the coordinate information. Using this invention, the advantages of complete reconstruction logic and a continuous coordinate chip map are achieved.

Description

Technical Field

[0001] This invention relates to the field of wafer defect scanning, and more particularly to a method, apparatus and system for reconstructing fragmented wafers. Background Technology

[0002] In existing technologies, the industry generally adopts a method based on manual partitioning and independent scanning for dealing with LED wafers with fractures. This involves manually delineating multiple physically continuous independent test areas in the tester software interface based on the physical cracks on the wafer surface. Furthermore, for each partition, the operator needs to manually find and set a local feature point located in that area as a temporary coordinate origin under the assistance of a microscope. After the partitioning is completed, the testing machine treats each area as an independent "sub-wafer" and performs automatic testing in sequence. After the test is completed, each partition will generate an independent test data file with coordinate data that is only valid within it, providing a basis for possible subsequent data processing.

[0003] Existing technologies rely heavily on manual positioning by operators. The selection of the partition origin is highly subjective and has poor repeatability, which can easily introduce alignment errors. In addition, existing manual partitioning methods can only complete local testing, and the generated data are scattered "information silos" that cannot be directly used for automated chip sorting.

[0004] Therefore, it is imperative to develop an intelligent crack-crossing mechanism to reconstruct a logically complete and coordinate-continuous chip map on a physically incomplete wafer. Summary of the Invention

[0005] The problem to be solved by this invention is to provide a fragmented wafer reconstruction method and computer equipment, which realizes the construction of a complete and accurate chip map.

[0006] To address the aforementioned technical problems, this invention provides a fragmented wafer reconstruction method, comprising: driving a testing machine to sequentially scan the dies in the wafer; if the current die is a normal die, acquiring the coordinate information of the current die; if the current die is an abnormal die, calculating the coordinate information of the next normal die based on the coordinate information of the previous die, and using the calculated next normal die as the current die; and generating a continuous wafer map based on the coordinate information.

[0007] As an improvement to the above solution, a fragmented wafer reconstruction method further includes: driving the inspection platform to move to the reference position corresponding to the calculated coordinate information of the next normal die; driving the inspection platform to identify the die at the reference position to determine whether the die at the reference position is a normal die; if the determination is yes, it indicates that the coordinate information is accurate; if the determination is no, it indicates that the coordinate information is incorrect.

[0008] As an improvement to the above scheme, the step of calculating the coordinate information of the next normal grain based on the coordinate information of the previous grain includes: According to the formula Calculate the abscissa information of the next normal grain; According to the formula Calculate the ordinate information of the next normal grain; in, The x-coordinate represents the previous grain. Represents the ordinate of the previous grain. Indicates the standard length of a single grain. Indicates the standard width of a single grain. This indicates the preset number of abnormal grains to be skipped. The x-coordinate represents the next normal grain. The ordinate represents the next normal grain.

[0009] As an improvement to the above solution, a fragmented wafer reconstruction method further includes: driving the testing machine to test the performance parameters of each die in the wafer according to the wafer pattern; and driving the dicing machine to dice the wafer into independent chips according to the die pattern on the wafer.

[0010] Accordingly, the present invention also provides a fragmented wafer reconstruction device, comprising: a first driving module for driving a testing machine to sequentially scan the dies in the wafer; a data acquisition module for acquiring the coordinate information of the current die if the current die is a normal die; a calculation module for calculating the coordinate information of the next normal die based on the coordinate information of the previous die if the current die is an abnormal die; and a pattern generation module for generating a continuous wafer pattern based on the coordinate information.

[0011] As an improvement to the above solution, a fragmented wafer reconstruction device further includes: a second driving module for driving the inspection platform to move to the reference position corresponding to the calculated coordinate information of the next normal die; and a third driving module for driving the inspection platform to identify the die at the reference position.

[0012] As an improvement to the above solution, a fragmented wafer reconstruction device further includes: a fourth driving module, used to drive the testing machine to test the performance parameters of each die in the wafer according to the wafer pattern; and a fifth driving module, used to drive the dicing machine to dice the wafer into independent chips according to the die pattern on the wafer.

[0013] Accordingly, the present invention also provides a fragmented wafer reconstruction system, comprising: the aforementioned fragmented wafer reconstruction equipment; a testing machine for sequentially scanning the dies in the wafer, identifying the dies at the reference position, and testing the performance parameters of each die in the wafer; and a dicing machine for dicing the wafer into individual chips according to the die pattern on the wafer.

[0014] Implementing this invention has the following beneficial effects: This invention generates a logically complete and coordinate-continuous wafer spectrum through a visual positioning and verification mechanism. The continuous wafer spectrum completely eliminates "information silos" and provides a unique and accurate data benchmark for all subsequent processes. Furthermore, based on the continuous wafer spectrum, the present invention adds a performance measurement step, which generates a "yield map" with direct engineering application value by deeply binding geometric coordinate information with electro-optical performance, greatly improving the usability of the data; Even better, the cutting equipment plans its path based on a complete spectrum that incorporates performance information, ensuring that all qualified chips are cut completely and accurately. For areas with a high concentration of defective chips, the cutting path can be simplified or skipped, thus concentrating processing time, tool wear, and other resources on valuable chips, achieving targeted and resource-optimized on-demand cutting. Attached Figure Description

[0015] Figure 1 This is a flowchart of the first embodiment of a fragmented wafer reconstruction method of the present invention; Figure 2 This is a flowchart of a second embodiment of a fragmented wafer reconstruction method of the present invention; Figure 3 This is a schematic diagram of an embodiment of the fragmented wafer reconstruction device of the present invention; Figure 4 This is a schematic diagram of an embodiment of the fragmented wafer reconstruction system of the present invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. It is hereby declared that the directional terms such as up, down, left, right, front, back, inside, and outside used in this text are based solely on the accompanying drawings and are not intended to specifically limit the invention.

[0017] like Figure 1 As shown, Figure 1 The flowchart of a first embodiment of a fragmented wafer reconstruction method of the present invention is shown, which includes: S101, Drive the inspection machine to scan the grains in the wafer sequentially; Specifically, the wafer to be tested is loaded onto the wafer carrier of the inspection machine by a robotic arm. The vision system of the inspection machine first performs a global scan to identify the flat edges or notches of the wafer for coarse positioning, so that the wafer coordinate system is initially aligned with the mechanical platform coordinate system. Then, the host computer software generates a grid-like scanning path covering the entire wafer based on the wafer size (such as 4 inches or 6 inches) and the preset die standard size (such as length W=500μm, width H=500μm). According to the generated scanning path, each grain enters the image recognition center and is recognized by image processing algorithms (such as template matching and edge detection). The recognition parameters (such as matching score threshold and brightness range) can be preset. When the matching score is higher than the set threshold (e.g., 90%), it is determined to be a "normal grain". S102. If the current grain is a normal grain, then obtain the coordinate information of the current grain; Specifically, once the die is identified as a normal die, the system immediately records the precise coordinates (X,Y) of the die in the global coordinate system of the mechanical platform and stores them in the dynamically generated wafer map data array; at the same time, additional data such as the image feature value and recognition confidence of the die can be recorded.

[0018] S103. If the current grain is an abnormal grain, calculate the coordinate information of the next normal grain based on the coordinate information of the previous grain, and use the calculated next normal grain as the current grain. Specifically, the abnormal data detection can be flexibly configured, such as: Condition A (Consecutive Missing): At the current theoretical location, no grain matching the characteristics is identified for N consecutive times (e.g., N=3); Condition B (Feature Anomaly): The shape, size, or brightness of the identified object differs greatly from the standard grain template and is classified as "damaged grain" or "foreign object". In this embodiment, the visual feature of blank "grooves" appearing in the MAP image is often used as a preset condition. When there is a physical crack on the wafer surface, that is, the grains on it will not be able to be identified normally due to abnormal image features, and it is identified as abnormal data and the theoretical coordinates of the next expected normal grain are calculated. Once any of the above preset conditions are met, the system immediately determines that it has entered an "abnormal region," and immediately suspends the normal sequential scanning process. It then calculates the coordinates of the next normal grain. The steps for calculating the next coordinates are as follows:

[0019]

[0020] in: Indicates the position of normal grains before the abnormal region. Axis coordinates; Indicates the position of normal grains before the abnormal region. Axis coordinates; Indicates the standard length of a single grain; Indicates the standard width of a single grain; This indicates the preset number of abnormal grains to be skipped; This indicates the theoretical calculation of normal grains. Axis coordinates; Theoretical calculations show that normal grains are derived. Axis coordinates.

[0021] It should be noted that the jump coefficient M is an adjustable parameter, and its setting is based on the following strategies: Preset empirical value: Based on historical crack data of incoming wafers, a large safety value is preset, for example, M=10.

[0022] Dynamic estimation: Combine the scanning situation before the abnormality is triggered (such as the number of failures to identify), dynamically estimate the initial value of M. For example, if there are 3 consecutive failures, M can be set to 4 or 5 to try to skip the current small crack.

[0023] Adaptive adjustment: The initial value of M can be set to 1. If the verification fails after the first jump, it will be increased by a certain step size (such as +1) and repeated multiple times until a normal grain is found.

[0024] S104. Generate a continuous wafer pattern based on the coordinate information.

[0025] This invention generates a logically complete and coordinately continuous wafer map through the aforementioned steps. This wafer map completely eliminates "information silos" caused by physical cracks, providing a unique and accurate data benchmark for subsequent die testing and dicing processes. Furthermore, the continuous map ensures global consistency of coordinate data, avoiding alignment errors introduced by manual partitioning, and significantly improving the automation and reliability of wafer processing. Based on this map, the system can seamlessly integrate testing and dicing processes, achieving resource optimization and efficiency improvement.

[0026] like Figure 2 As shown, Figure 2 A flowchart of a second embodiment of a fragmented wafer reconstruction method of the present invention is shown, which includes: S201, Drive the inspection machine to scan the grains in the wafer sequentially; S202. If the current grain is a normal grain, then obtain the coordinate information of the current grain. S203. If the current grain is an abnormal grain, calculate the coordinate information of the next normal grain based on the coordinate information of the previous grain, and use the calculated next normal grain as the current grain. S204. Generate a continuous wafer pattern based on the coordinate information.

[0027] S205. Drive the detection machine to move to the reference position corresponding to the calculated coordinate information of the next normal grain; S206. Drive the detection machine to identify the grains at the reference position to determine whether the grains at the reference position are normal grains; if the determination is yes, it means that the coordinate information is accurate; if the determination is no, it means that the coordinate information is incorrect.

[0028] and Figure 1 Unlike the first embodiment shown, this embodiment introduces steps S205 and S206 to achieve secondary verification of the grain position information, providing a solid guarantee for the accuracy of the grain data.

[0029] Specifically, the step of driving the detection machine to identify the grains at the reference position includes: (1) Based on the position of the normal grain before the abnormal region, and combined with the standard grain size and the precise stepping distance of the mechanical platform, calculate the theoretical coordinates of the next normal grain. (2) Scan the grain data of the theoretical coordinates and determine whether the theoretical coordinates are normal grains.

[0030] If the grain of the theoretical coordinates is a normal grain, it means that the coordinate information is accurate, and the actual accurate coordinates of the grain are recorded as valid data, and the current coordinate reference is updated to continue the subsequent scanning process; If the grain of the theoretical coordinates is an abnormal grain, it indicates that the coordinate information is incorrect. The next normal grain can be calculated as needed. The calculation method includes: reselection of step distance and local search strategy. Step distance reselection: Update different step distances and repeat the above steps until an accurate data is finally obtained; Local search strategy: Search within a certain range around the theoretical coordinates until the nearest normal grain is located and its coordinates are recorded as valid data.

[0031] The search range (e.g., a square area with a side length of 2mm centered on the theoretical coordinates) and search mode (e.g., spiral search, grid scan) of this strategy can be preset.

[0032] Spiral search: Starting from the theoretical coordinate point, a spiral traversal is performed with a gradually increasing radius and a fixed angle until a normal grain is first found. This mode is highly efficient and can quickly cover the surrounding area.

[0033] Grid scan: Traverses a defined rectangular area by fixed rows and columns. This method is more systematic and ensures no omissions.

[0034] During the search process, rapid image recognition is performed at each new location. Once the nearest normal grain is located, its precise coordinates are recorded, and the scan is resumed using this as the new reference.

[0035] It should be noted that if the image recognition algorithm identifies a normal grain (matching score higher than the threshold) at the current theoretical coordinate position, the system further extracts the precise coordinates (X_actual, Y_actual) of the grain's center using positioning technology. This actual coordinate (not the theoretical coordinate) is recorded as valid data, and the current scan reference position is updated; subsequently, the system immediately resumes the regular scanning process described in S1 from that point.

[0036] Finally, the system generates a globally continuous wafer spectrum; the spectrum file contains the absolute coordinates, status indicators (such as normal, abnormal, retrieved through compensation), and possible identification confidence information of all identified normal grains.

[0037] Compared with existing technologies, this invention uses an active continuation process of "computational prediction + visual verification" to make the system no longer simply skip unrecognizable areas, but actively calculate the theoretical position based on the grain size and step distance, and drive the image to perform secondary precise positioning.

[0038] In addition, the present invention also includes chip testing and chip dicing, which will be described in detail below: I. Chip Testing Based on the continuous wafer spectrum, the performance of all chips on the wafer is measured, including forward voltage, reverse current, and wavelength.

[0039] (1) Based on the continuous wafer spectrum and real-time image, locate the specific position of the chip; Specifically, the testing system obtains the absolute coordinates of the next chip under test through the continuous wafer spectrum; (2) Based on the specific location, drive the probe to be electrically connected to the electrode of the chip and measure the chip performance, the chip performance including forward voltage, reverse current and wavelength; The control system drives a precision mechanical platform to move the wafer, positioning the target chip precisely below the test probe and ensuring that the probe is accurately aligned with the tiny electrode pads on the chip. The miniature probes on the probe card move downwards with controllable force and stroke under the drive of piezoelectric ceramics or servo motors, forming stable ohmic contacts with the anode and cathode pads of the chip.

[0040] The source measurement unit integrated inside the testing machine begins to operate: VF Measurement: The SMU applies a constant standard forward current (IF, e.g., 20mA) to the chip and measures the voltage across the chip with high precision. This reading is the forward voltage (VF).

[0041] IV Measurement: Subsequently, the SMU switches to voltage source mode, applies a constant reverse bias voltage (VR, e.g., 5V) to the chip, and measures the resulting tiny current value, which is the reverse current (IV).

[0042] WLD Measurement: Optical measurements are performed while the chip emits light through a forward current. There are typically two integration methods: Integrated Spectrometer Method: The light emitted by the chip is guided to a high-speed miniature spectrometer via optical fiber. The spectrometer quickly analyzes the light, obtains its spectral distribution, and calculates parameters such as the dominant wavelength (WLD), half-width, and light intensity. This method is highly accurate and can acquire complete spectral information. Filter-Photodetector Method: A set of preset wavelength filters and corresponding photodetectors are used to measure light intensity. By comparing the response values ​​of different channels, the dominant wavelength and light intensity can be calculated. This method is faster, lower in cost, and suitable for the grading requirements in large-scale production.

[0043] There are no restrictions on specific chip performance test items here; chips can be tested according to actual needs.

[0044] (3) Record and output the chip performance of the chip on the wafer.

[0045] All measured parameters (VF, IV, WLD, etc.) are bound in real time to the chip's global coordinates and a unique chip ID, and recorded in a structured test data file.

[0046] Compared with the above embodiments, this embodiment further realizes the measurement of chip performance through the continuous wafer spectrum. The data file generated by this embodiment is a usable yield report, which clearly marks the location and performance of each qualified and unqualified chip on the entire wafer, providing irreplaceable data support for subsequent automatic chip sorting, yield analysis and process improvement.

[0047] II. Chip Cutting This stage is a crucial step in separating the individual chips (dies) on the entire wafer into individual units. The core value of this invention lies in the fact that the dicing process is not carried out blindly, but is precisely guided by a global wafer map generated from the aforementioned steps, which contains the absolute coordinates and state information of the chips. This enables a highly efficient and low-loss conversion from a "whole wafer" to a "single chip with known performance".

[0048] Accordingly, such as Figure 3 As shown, the present invention also provides a fragmented wafer reconstruction device, which includes: The first driving module 1 is used to drive the inspection machine to scan the grains in the wafer sequentially. The first driving module 1 controls the inspection machine via software, generating a grid-like scanning path based on the wafer size (e.g., 4 inches or 6 inches) and preset die standard dimensions (e.g., length W=500μm, width H=500μm). During scanning, the vision system acquires images of each die and uses image processing algorithms to identify the die status. The module's identification parameters (e.g., matching score threshold) can be preset; for example, a die is considered normal when the matching score is higher than 90%.

[0049] In addition, the first drive module 1 communicates with the detection platform 12 in real time to ensure the continuity and accuracy of the scanning path. If the scanning is interrupted (such as when a crack is encountered), the module will pause and trigger the calculation module to perform coordinate compensation.

[0050] Data acquisition module 2 is used to acquire the coordinate information of the current grain if the current grain is a normal grain; The data acquisition module 2 records the precise coordinates (X, Y) of the die in the global coordinate system of the mechanical platform and stores them in a dynamically generated wafer map data array. In addition, the module can also record supplementary data, such as image feature values ​​and recognition confidence levels, to support subsequent analysis. The coordinate information is stored in array form to ensure data consistency and traceability. The module supports real-time updates to adapt to dynamic changes during the scanning process.

[0051] Calculation module 3 is used to calculate the coordinate information of the next normal grain based on the coordinate information of the previous grain when the current grain is an abnormal grain. The calculation module 3 processes the coordinate information acquired by the data acquisition module 2 and supports multiple strategies, such as step reselection or local search (such as spiral search). If the coordinate verification fails, the module can increment the M value or start the search algorithm until a normal grain is located.

[0052] The spectrum generation module 4 is used to generate continuous wafer spectra based on coordinate information.

[0053] The spectrum generation module 4 integrates the coordinates of all normal wafers (including coordinates recovered through compensation) to generate a globally continuous wafer spectrum. The spectrum file contains the absolute coordinates, status identifier (normal / abnormal), and identification confidence level of each wafer. The spectrum format supports standard data exchange (such as CSV or JSON) for easy use in subsequent processes.

[0054] Furthermore, the device also includes a second drive module and a third drive module; The second driving module is used to drive the testing machine to move to the reference position corresponding to the calculated coordinate information of the next normal grain, that is, to control the precise positioning of the testing machine by the theoretical coordinates calculated by the calculation module 3. The third driving module is used to drive the inspection platform to identify the grains at the reference position. Specifically, it drives the inspection platform 12 to verify whether the grain at that position is a normal grain using an image recognition algorithm (such as template matching). If a normal grain is identified, the coordinate information is confirmed to be accurate, and the reference is updated to continue scanning. If an abnormal grain is identified, a reselection mechanism is triggered (such as adjusting the jump coefficient M or local search) to ensure the robustness of the coordinate calculation. This mechanism realizes an active sequential process of "calculation prediction + visual verification," overcoming the shortcomings of existing technologies that rely on manual positioning.

[0055] More preferably, the device further includes a fourth driving module and a fifth driving module. The fourth driving module is used to drive the inspection machine to test the performance parameters of each die in the wafer according to the continuous wafer pattern. The fifth driving module is used to drive the dicing machine to dice the wafer into individual chips according to the die pattern on the wafer pattern. Specifically, the fourth driving module locates the chip position based on the absolute coordinates in the pattern, drives the probe to electrically connect with the chip electrode, and integrates a source measurement unit (SMU) and optical equipment for performance measurement. The fifth driving module plans the dicing path based on the pattern with fused performance information, prioritizes the processing of qualified chip areas, and optimizes resource allocation. These modules work together to deeply bind geometric coordinates with electro-optical performance, generating a "yield map" that supports automated sorting and on-demand dicing, enhancing the value of engineering applications.

[0056] like Figure 4 As shown, Figure 4A schematic diagram of an embodiment of a fragmented wafer reconstruction system is shown, comprising: A fragmented wafer reconstruction device 11 is used to identify complete wafer spectra and coordinate the entire process through a central processing unit. The fragmented wafer reconstruction device receives user instructions through a terminal interface and generates control signals to drive the detection station 12 and the dicing station 13. The specific structure of the fragmented wafer reconstruction device 11 is as described above and will not be repeated here.

[0057] Inspection unit 12 is used to perform scanning and testing tasks; The testing equipment 12 is responsible for chip scanning, identification, and performance testing. During the scanning phase, the equipment moves the wafer via a precision mechanical platform, allowing each chip to enter the vision center sequentially. During the testing phase, the equipment integrates a probe card and a source measurement unit (SMU) to measure electrical parameters (such as forward voltage VF and reverse current IV) and optical parameters (such as wavelength WLD) of the chips.

[0058] For example, once the calculation module determines the coordinates of the next normal die, the inspection platform 12 quickly moves to that position and verifies the die status through image recognition. The test data is bound to the coordinates and directly updated to the wafer map.

[0059] The dicing machine 13 performs path planning based on the continuous wafer map generated by the fragmented wafer reconstruction equipment 11. Performance information (such as a yield map) from the map is used to optimize the dicing sequence and prioritize dicing qualified chip areas, skipping abnormally dense areas to save tool wear. The dicing process is monitored in real time (e.g., by a laser sensor). If an offset is detected (e.g., a new crack caused by stress), the machine pauses and requests the equipment to recalibrate the coordinates.

[0060] For example, a user uploads image data or scanning commands for the wafer under test via a user terminal. The first drive module 1 of the fragmented wafer reconstruction device 11 drives the inspection platform 12 to scan the grains in the wafer sequentially, and the data acquisition module 2 acquires the coordinate information of the current grain. If the current grain is an abnormal grain, the calculation module 3 calculates the theoretical coordinates of the next normal grain based on the coordinate information of the previous normal grain, and dynamically adjusts the coordinates based on the calculation results, wherein the jump coefficient M can be adaptively optimized based on historical crack data. At the same time, the second drive module drives the inspection platform 12 to move to the calculated theoretical coordinate position, and the third drive module identifies and verifies the grains at the reference position to ensure coordinate accuracy. Subsequently, the map generation module 4 integrates the coordinates of all normal grains (including coordinates recovered through compensation) to generate a globally continuous wafer map.

[0061] Furthermore, users can specify test or dicing parameters via the terminal. The fourth drive module drives the inspection station 12 to test the performance parameters of each die (such as forward voltage, reverse current, and wavelength) based on the continuous wafer pattern, and binds the data with coordinates to generate a yield report. The fifth drive module drives the dicing station 13 to plan the dicing path according to the yield map, prioritizing the processing of qualified chip areas and skipping abnormally dense areas to optimize resources.

[0062] In summary, this invention achieves an intelligent crack crossing mechanism through the synergy of algorithms and images, thereby reconstructing a logically complete and coordinate-continuous chip map on a physically incomplete wafer, realizing a leap from "passive interruption" to "active continuation", and completing an intelligent upgrade of the wafer test data processing flow.

[0063] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A method for reconstructing fragmented wafers, characterized in that, include: The drive inspection machine sequentially scans the grains in the wafer; If the current grain is a normal grain, then obtain the coordinate information of the current grain; If the current grain is an abnormal grain, the coordinate information of the next normal grain is calculated based on the coordinate information of the previous grain, and the calculated next normal grain is used as the current grain. A continuous wafer pattern is generated based on the coordinate information.

2. The fragmented wafer reconstruction method as described in claim 1, characterized in that, Also includes: Drive the detection machine to move to the reference position corresponding to the calculated coordinate information of the next normal grain; The detection machine is driven to identify the grains at the reference position in order to determine whether the grains at the reference position are normal grains; If the judgment is yes, it means that the coordinate information is accurate; If the result is "no", it means that the coordinate information is incorrect.

3. The fragmented wafer reconstruction method as described in claim 2, characterized in that, The step of calculating the coordinate information of the next normal grain based on the coordinate information of the previous grain includes: According to the formula Calculate the abscissa information of the next normal grain; According to the formula Calculate the ordinate information of the next normal grain; in, The x-coordinate represents the previous grain. Represents the ordinate of the previous grain. Indicates the standard length of a single grain. Indicates the standard width of a single grain. This indicates the preset number of abnormal grains to be skipped. The x-coordinate represents the next normal grain. The ordinate represents the next normal grain.

4. The fragmented wafer reconstruction method as described in claim 1, characterized in that, Also includes: The testing equipment is driven according to the wafer pattern to test the performance parameters of each grain in the wafer. The drive dicing machine cuts the wafer into individual chips according to the grain pattern on the wafer.

5. A fragmented wafer reconstruction device, characterized in that, include: The first drive module is used to drive the inspection machine to scan the grains in the wafer sequentially. The data acquisition module is used to acquire the coordinate information of the current grain if the current grain is a normal grain. The calculation module is used to calculate the coordinate information of the next normal grain based on the coordinate information of the previous grain when the current grain is an abnormal grain. The pattern generation module is used to generate continuous wafer patterns based on coordinate information.

6. The fragmented wafer reconstruction equipment as described in claim 5, characterized in that, Also includes: The second driving module is used to drive the detection machine to move to the reference position corresponding to the calculated coordinate information of the next normal grain; The third driving module is used to drive the testing machine to identify the grains at the reference position in order to determine whether the grains at the reference position are normal grains.

7. The fragmented wafer reconstruction equipment as described in claim 5, characterized in that, Also includes: The fourth driving module is used to drive the testing machine to test the performance parameters of each grain in the wafer according to the wafer pattern; The fifth drive module is used to drive the dicing machine to dice the wafer into individual chips according to the die pattern on the wafer.

8. A fragmented wafer reconstruction system, characterized in that, include: A fragmented wafer reconstruction apparatus according to any one of claims 5 to 7; The testing equipment is used to scan the grains in the wafer sequentially, identify the grains at the reference positions, and test the performance parameters of each grain in the wafer. A dicing machine for dicing a wafer into individual chips according to a die pattern on the wafer.

Images