Accelerator structure, method of generating accelerator structure, and apparatus therefor
By introducing CoW units into the InFO_SoW structure and employing multi-layer wiring and through-silicon via (TSV) design, the problem of insufficient chip integration efficiency in existing technologies is solved, achieving a high-efficiency accelerator structure that meets the large-scale integration requirements of accelerators and reduces power consumption.
CN116108900BActive Publication Date: 2026-06-02ANHUI CAMBRICON INFORMATION TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ANHUI CAMBRICON INFORMATION TECH CO LTD
- Filing Date
- 2021-11-05
- Publication Date
- 2026-06-02
Smart Images
Figure CN116108900B_ABST
Abstract
The application relates to an accelerator structure and an apparatus thereof, a method for generating the accelerator structure and a computer readable storage medium, a computer program product and a computer device thereof. The accelerator structure comprises: an operation layer provided with a plurality of chip pair wafer units, each of the chip pair wafer units comprising a first die group and a second die group; a module layer provided with a power module die group and an interface module die group; and a circuit layer arranged between the operation layer and the module layer. The power module die group provides power to the first die group and the second die group through the circuit layer, and the first die group and the second die group output a calculation result through the interface module die group via the circuit layer.
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