Display panel and its driving method, display device

Abstract

This invention discloses a display panel and its driving method and display device. The display panel includes a gate driving circuit, multiple gate lines, and multiple touch electrodes. The gate driving circuit provides scanning signals to the multiple gate lines. The multiple gate lines extend along a first direction and are arranged along a second direction. The multiple touch electrodes include first touch electrodes and second touch electrodes adjacent to each other along the second direction. Gate lines overlapping with the first touch electrodes are designated as first gate lines, and gate lines overlapping with the second touch electrodes are designated as second gate lines. In the scanning sequence of the multiple gate lines, the scanning sequence of at least one second gate line is located between the scanning sequences of at least two first gate lines. The display panel provided by this application can alleviate or eliminate horizontal stripe problems and improve the display uniformity of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to display panels and their driving methods and display devices. Background Technology

[0002] In LCD panels with integrated touch functionality, the common electrode is typically reused as the touch electrode. During the display driving phase, a common voltage is provided to the common electrode, and during the touch driving phase, touch driving signals are provided to each touch electrode to sense touch information.

[0003] In liquid crystal display panels, the common electrode is divided into multiple touch electrodes by slits. During the display driving stage, horizontal lines are prone to appear near the slits, affecting the display effect. Summary of the Invention

[0004] In view of this, this application provides a display panel and its driving method, and a display device, for mitigating or eliminating horizontal lines on the displayed screen.

[0005] According to one aspect of this application, a display panel is provided, including a gate driving circuit, a plurality of gate lines, and a plurality of touch electrodes; The gate driving circuit is used to provide scan signals to the plurality of gate lines; The plurality of gate lines extend along a first direction and are arranged along a second direction; The plurality of touch electrodes includes a first touch electrode and a second touch electrode that are adjacent to each other along the second direction, wherein the gate line that overlaps with the first touch electrode is the first gate line, and the gate line that overlaps with the second touch electrode is the second gate line. In the scanning timing of the plurality of gate lines, the scanning sequence of at least one of the second gate lines is located between the scanning sequences of at least two of the first gate lines; According to another aspect of this application, a driving method for a display panel is provided, the display panel including a gate driving circuit, multiple gate lines and multiple touch electrodes; The gate driving circuit is used to provide scan signals to the plurality of gate lines; The plurality of gate lines extend along a first direction and are arranged along a second direction; The plurality of touch electrodes includes a first touch electrode and a second touch electrode that are adjacent to each other along the second direction, wherein the gate line that overlaps with the first touch electrode is the first gate line, and the gate line that overlaps with the second touch electrode is the second gate line. In the driving method, the gate driving circuit provides a scan signal to the plurality of gate lines, and the scan sequence of at least one of the second gate lines is located between the scan sequences of at least two of the first gate lines; According to another aspect of this application, a display device is provided, including the display panel provided in this application.

[0006] In this application, by placing the scan signal of the second gate line overlapping with the second touch electrode into the scan timing of the first gate line overlapping with the first touch electrode, the voltage recovery time of the common voltage on the first touch electrode affected by the scan signal coupling is increased, thereby alleviating or eliminating the horizontal stripes on the display screen.

[0007] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of touch electrodes and gate lines in related technologies; Figure 2 for Figure 1 A schematic diagram of the scanning signal timing of the gate line in the diagram; Figure 3 This is a top view schematic diagram of a display panel provided in an embodiment of this application; Figure 4 A cross-sectional schematic diagram of a display panel provided in an embodiment of this application; Figure 5 A top view schematic diagram of another display panel provided in an embodiment of this application; Figure 6 for Figure 5 A schematic diagram of the scanning signal timing of the gate line in the diagram; Figure 7 A top view schematic diagram of another display panel provided in an embodiment of this application; Figure 8 This is a schematic diagram illustrating the connection relationship between a gate driving circuit and a gate line, provided in an embodiment of this application. Figure 9 for Figure 8 A schematic diagram showing the correspondence between gate lines and scan signals; Figure 10 for Figure 9 A schematic diagram of the scanning signal timing of the gate line in the diagram; Figure 11This is a schematic diagram showing the voltage changes in the conventional and edge regions of the touch electrodes in related technologies and embodiments of this application under disturbance. Figure 12 A schematic diagram illustrating the connection relationship between a gate driving circuit and a gate line, provided in an embodiment of this application. Figure 13 A schematic diagram illustrating the connection relationship between a gate driving circuit and a gate line, provided in an embodiment of this application. Figure 14 for Figure 13 A schematic diagram showing the connection relationship between the gate drive circuit and the clock signal line; Figure 15 for Figure 14 A timing diagram of the clock signal on the clock signal line and the signal output from the shift register unit; Figure 16 for Figure 15 The comparative example; Figure 17 A schematic diagram illustrating the connection relationship between a gate driving circuit and a gate line, provided in an embodiment of this application. Figure 18 for Figure 17 A timing diagram of the scan signals for the gate lines in the diagram; Figure 19 A schematic diagram illustrating the connection relationship between a gate driving circuit and a gate line, provided in an embodiment of this application. Figure 20 This is a schematic diagram showing multiple sets of touch electrode groups provided in an embodiment of this application; Figure 21 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0010] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0011] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0012] Unless otherwise specified, all letters used to represent quantities in this application are integers.

[0013] In related technologies, liquid crystal display panels with integrated touch functionality typically reuse a common electrode as a touch electrode. During the display driving phase, a common voltage is provided to each touch electrode constituting the common electrode, and during the touch driving phase, a touch driving signal is provided to each touch electrode individually. For example... Figure 1 and Figure 2 As shown, gate line 01 overlaps with touch electrode 02, and during the display driving phase, each gate line 01 sequentially receives a scan signal, such as... Figure 1 and Figure 2 In G1~Gn, due to the parasitic capacitance between gate line 01 and touch electrode 02, the rising edge of the scan signal (such as...) Figure 2 (as shown by the upward arrow in the image) and the falling edge (as shown by the downward arrow in the image) Figure 2 As shown by the down arrows in the diagram, both will cause a corresponding change in the common voltage on the touch electrode 02. For the gate line 01 corresponding to the same touch electrode 02, if the rising edge of one scan signal and the falling edge of another scan signal simultaneously affect the common voltage of the touch electrode, the effects can cancel each other out. Figure 2 The effects of the falling edge of scan signal G1 and the rising edge of scan signal G7 on the voltage of touch electrode 02 can cancel each other out. Similarly, the effects of the falling edge of scan signal Gn-6 and the rising edge of scan signal Gn on the voltage of touch electrode 02 can also cancel each other out. However, for gate lines located near the edge of touch electrode 02, the effects of the scan signals transmitted on their voltage on touch electrode 02 are usually not canceled out, causing a unidirectional trend change in the common voltage of touch electrode 02. For example, with... Figure 1The rising edges of scan signals G1~G6 received by the overlapping gate lines 01 in the upper edge region A of the touch electrode 02 will all cause an increase in the common voltage on the touch electrode 02, resulting in a change in the upward trend of the common voltage on the touch electrode 02. Figure 1 The falling edges of the scan signals Gn-5 to Gn received by the overlapping gate lines 01 in the lower edge region B of the touch electrode 02 will all cause a decrease in the common voltage on the touch electrode 02, resulting in a downward trend in the common voltage on the touch electrode 02. Figure 1 and Figure 2 Taking a 12-clock-signal cycle as an example, the upper edge region A and lower edge region B of touch electrode 02 each have 6 lines of scanning signals that cause a unidirectional trend change in the common voltage. In addition, because the time interval between the rising edge (or falling edge) of two adjacent scanning signals is small, the common voltage on touch electrode 02 has insufficient recovery ability after being disturbed. This results in abnormal clamping pressure between each pixel electrode and the common electrode (touch electrode 02) near the edge of touch electrode 02, causing horizontal lines on the display.

[0014] Based on this, this application provides a display panel and its driving method, as well as a display device, to alleviate or eliminate the problem of horizontal lines on the display.

[0015] The display panel provided in this application includes a gate driving circuit, multiple gate lines, and multiple touch electrodes. The gate driving circuit is used to provide scanning signals to the multiple gate lines. The multiple gate lines extend along a first direction and are arranged along a second direction. The multiple touch electrodes include first touch electrodes and second touch electrodes that are adjacent to each other along the second direction. The gate line that overlaps with the first touch electrode is the first gate line, and the gate line that overlaps with the second touch electrode is the second gate line. In the scanning timing of the multiple gate lines, the scanning sequence of at least one second gate line is located between the scanning sequences of at least two first gate lines.

[0016] The above-mentioned technical solution is the core inventive concept of this application, and is specifically described in the following embodiments.

[0017] In some embodiments of this application, such as Figures 3-6As shown, the display panel 100 includes an array substrate 1, an opposing substrate 2, and a liquid crystal layer 3 sandwiched between the array substrate 1 and the opposing substrate 2. The array substrate 1 includes multiple data lines 40 and multiple gate lines 10. The multiple data lines 40 extend along a second direction Y and are arranged along a first direction X. The multiple gate lines 10 extend along the first direction X and are arranged along the second direction Y. The data lines 40 and gate lines 10 are intersected to define multiple sub-pixels. Each sub-pixel includes a transistor 60 and a pixel electrode 50. The source S of the transistor 60 is connected to the data line 40, the drain D of the transistor 60 is connected to the pixel electrode 50, and the gate G of the transistor 60 is connected to the gate line 10. Both can be located in the same film layer. Under the control of the scan signal provided by the gate line 10, the data signal provided by the data line 40 can be written to the pixel electrode 50 through the transistor 60. The array substrate 1 also includes a common electrode 20. The electric field formed by the common electrode 20 and the pixel electrode 50 is used to control the liquid crystal layer 3 to achieve display. The common electrode 20 and the pixel electrode 50 can be arranged in the same layer or in different layers. Figure 4 Taking a common electrode 20 and pixel electrode 50 as an example, with the pixel electrode 50 located on the side of the common electrode 20 closer to the liquid crystal layer 3. The common electrode 20 may include multiple touch electrodes 20 arranged in an array. During the display driving stage, the gate line 10 provides a scan signal to the gate G of the transistor 60 to control the transistor 60 to conduct, so that the data line 40 writes data voltage to the pixel electrode 50 through the transistor 60, and at the same time provides a common voltage to each touch electrode 20 that makes up the common electrode 20. The electric field formed by the pixel electrode 50 and the common electrode 20 controls the rotation of liquid crystal molecules in the liquid crystal layer 3, thereby adjusting the transmittance of the corresponding sub-pixel to achieve display. Different clamping pressures between the pixel electrode 50 and the common electrode 20 control different transmittances of the corresponding sub-pixels. During the touch driving stage, touch driving signals are provided to each touch electrode 20 to sense touch information and obtain touch coordinates.

[0018] Unless otherwise specified, the terms "common electrode" and "touch electrode" are used to refer to the overall structure and individual substructures, respectively. That is, the whole consisting of all touch electrodes is called the common electrode, and the individual substructures contained in the common electrode are called touch electrodes.

[0019] The array substrate 1 also includes a gate driving circuit 30, which is used to provide scan signals to multiple gate lines 10.

[0020] In the display panel 100, touch electrodes 20 are arranged in an array along intersecting first direction X and second direction Y, where the first direction X can be a row direction and the second direction Y can be a column direction. Each touch electrode 20 can cover multiple rows and columns of sub-pixels. Touch electrodes 20 located in the same row overlap with the same group of gate lines 10, and touch electrodes 20 located in different rows overlap with different groups of gate lines 10. It should be noted that the touch electrodes 20 and the gate lines 10 are located on different layers, and the touch electrodes 20 and the gate lines 10 overlap in a direction perpendicular to the plane of the display panel.

[0021] The plurality of touch electrodes 20 includes a first touch electrode 21 and a second touch electrode 22 adjacent to each other along the second direction Y. A gate line 10 overlapping with the first touch electrode 21 is designated as a first gate line 11, and a gate line 10 overlapping with the second touch electrode 22 is designated as a second gate line 12. In some embodiments, the first gate line 11 overlaps with each touch electrode 20 in the row containing the first touch electrode 21, and the second gate line 12 overlaps with each touch electrode 20 in the row containing the second touch electrode 22. In the following embodiments, the first touch electrode 21 and the second touch electrode 22 are used as representatives of touch electrodes that distinguish different gate lines.

[0022] In the scanning timing of multiple gate lines 10, the scanning sequence of at least one second gate line 12 is located between the scanning sequences of at least two first gate lines 11. Combined with... Figure 5 and Figure 6The scan signals received by the two first gate lines 111 and 112 overlapping with the first touch electrode 21 are denoted as G111 and G112, respectively. The scan signal received by the second gate line 12 overlapping with the second touch electrode 22 is denoted as G12. The scan pulse of the scan signal G12 is delayed by 1H compared with the scan pulse of the scan signal G111, and the scan pulse of the scan signal G112 is delayed by 1H compared with the scan pulse of the scan signal G12. The scan sequence of the scan signal G12 is located between the scan sequences of the scan signals G111 and G112. As a result, the duration between the falling edge of the scan signal G111 of the first gate line 111 overlapping with the first touch electrode 21 and the falling edge of the scan signal G112 of the first gate line 112 is increased from the original 1H to 2H, where H is the delay duration between two adjacent scan pulses. In this application, by adjusting the driving order of the scanning signals of the first gate line and the second gate line, the scanning order of the second gate line is inserted into the scanning order of the first gate line. This increases the delay time between adjacent scanning signals of the first gate line, thereby increasing the common voltage recovery time of the touch electrode, improving the common voltage recovery capability of the touch electrode, and reducing or eliminating the display horizontal lines problem caused by abnormal clamping voltage between the pixel electrode and the common voltage. Furthermore, in this application, the timing of the scanning signal of the first gate line corresponding to the first touch electrode is adjusted using the scanning signal of the second gate line corresponding to the second touch electrode adjacent to the first touch electrode. Compared to adjusting the timing of the scanning signal of the first gate line using the scanning signal of the gate line at other positions, this reduces the occurrence of brightness differences caused by leakage current of the sub-pixel transistors.

[0023] It should be noted that the scanning order can be understood as the order of the start times of the scanning pulses of each scanning signal. One scanning signal is located between the scanning orders of the other two scanning signals, and it is not required that the scanning pulses of the three scanning signals do not overlap.

[0024] like Figure 7 As shown, the gate drive circuit 30 includes a plurality of shift register units 31 arranged along the second direction Y. The plurality of shift register units include a first shift register unit 311 and a second shift register unit 312. The first shift register unit 311 is connected to the first gate line 11 and is used to provide a scan signal to the first gate line 11. The second shift register unit 312 is connected to the second gate line 12 and is used to provide a scan signal to the second gate line 12. Along the second direction Y, at least one second shift register unit 312 is located between two first shift register units 311.

[0025] Multiple shift register units 31 arranged sequentially along the second direction Y can have a regular cascaded relationship and output scan signals sequentially according to the arrangement order of the shift register units. In the second direction Y, at least one level of second shift register unit 312 is located between two levels of first shift register units 311, so that the scan signal transmitted in at least one second gate line 12 is between the scan signals transmitted in two first gate lines 11 in terms of scanning order. In this application, by adjusting the connection relationship between the shift register units 31 in the gate driving circuit 30 and the first gate line 11 and the second gate line 12, the scanning order of the first gate line 11 and the second gate line 12 can be adjusted accordingly, thereby reducing the modification to the gate driving circuit.

[0026] In some embodiments of this application, such as Figure 8 As shown, along the second direction Y, multiple shift register units 31 are arranged sequentially, wherein the first shift register unit 311 and the second shift register unit 312 are arranged alternately. That is, multiple shift register units 31 are alternately connected to the first gate line 11 and the second gate line 12. Thus, the gate driving circuit alternately provides scanning signals to the first gate line 11 and the second gate line 12, thereby realizing the sequential and alternating scanning of each first gate line 11 corresponding to the first touch electrode 21 and each second gate line 12 corresponding to the second touch electrode 22.

[0027] Combination Figures 8-10 , Figure 9 The diagram illustrates the correspondence between the m-th group of gate lines overlapping with the first touch electrode and the received scan signal, as well as the correspondence between the (m+1)-th group of gate lines overlapping with the second touch electrode and the received scan signal. Figure 10 Timing diagrams of the scan signals received by the m-th gate line and the (m+1)-th gate line are provided.

[0028] The first touch electrode 21 and the second touch electrode 22 are arranged adjacent to each other along the second direction Y. The first touch electrode 21 overlaps with the m-th group of gate lines. The m-th group of gate lines includes the first to the nth first gate lines 11 arranged sequentially along the second direction Y, and are respectively denoted as m_1, m_2, ..., m_n. The second touch electrode 22 overlaps with the (m+1)-th group of gate lines. The (m+1)-th group of gate lines includes the first to the nth second gate lines 12 arranged sequentially along the second direction Y, and are respectively denoted as m+1_1, m+1_2, ..., m+1_n. The scan signals received by the first to nth gate lines 11 of the m-th group of gate lines are G(m_1)_1, G(m_2)_3, ..., G(m_n-1)_2n-3, G(m_n)_2n-1, respectively. The scan signals received by the first to nth gate lines 12 of the (m+1)-th group of gate lines are G(m+1)_1, G(m+1_2)_4, ..., G(m+1_n-1)_2n-2, G(m+1_n)_2n, respectively. The shift register units 31 of the gate drive circuit 30 are arranged sequentially according to G(m_1)_1, G(m+1_1)_2, G(m_2)_3, G(m+1_2)_4, ..., G(m_n-1)_2n-3, G(m+1_n-1)_2n-2, ... The scan signals G(m_n)_2n-1 and G(m+1_n)_2n are output sequentially according to their scan timing, so that each first gate line 11 and each second gate line 12 alternately receives the scan signal. For example, the scan pulses of the scan signals output sequentially by the gate driving circuit 30 are delayed by 1H. For the scan signal G(i)_j, i represents the row of the gate line, and j represents the relative order of the scan signals output by the gate driving circuit.

[0029] For example, the scan signal G(m+1_1)_2 received by the first second gate line m+1_1 is delayed by 1H compared to the scan signal G(m_1)_1 received by the first first gate line m_1, and the scan signal G(m_2)_3 received by the second first gate line m_2 is delayed by 1H compared to the scan signal G(m+1_1)_2 received by the first second gate line m+1_1. Thus, for the scan pulses of the scan signal G(m_1)_1 received by the first first gate line overlapping with the same touch electrode 20 and the scan pulses of the scan signal G(m_2)_3 received by the second first gate line m_2, the rising edges of the two are spaced 2H apart, and the falling edges of the two are spaced 2H apart.

[0030] When the first gate line 11 and the second gate line 12 alternately receive scan signals, for the scan signals received by each first gate line 11 overlapping with the first touch electrode 21, the delay between the scan pulses of two adjacent scan signals increases. This increases the recovery time of the common voltage on the first touch electrode 21 after being disturbed, thus improving the recovery capability of the common voltage on the first touch electrode 21. At the same time, it reduces the number of gate lines in the upper edge region A1 and lower edge region B1 of the first touch electrode 21 that cause unidirectional disturbances to the common voltage of the first touch electrode 21. Figure 9 and Figure 10 Taking a display panel containing 12 clock signal lines as an example, the clock pulses of the clock signals provided by the 12 clock signal lines shift sequentially within one clock cycle. The number of gate lines that cause unidirectional disturbance to the edge region A1 / B1 of the first touch electrode 21 is 3, compared to related technologies (see reference). Figure 1 and Figure 2 By scanning the gate lines sequentially, the number of gate lines causing horizontal lines is halved, effectively improving the display horizontal lines problem caused by disturbances in the common voltage on the first touch electrode 21. The same technical effect is achieved for the edge regions A2 / B2 of the second touch electrode 22.

[0031] Figure 11 The accompanying diagram illustrates voltage changes in the conventional and edge regions of the touch electrode under disturbance, based on related technologies and embodiments of this application. Figure 11 Parts (a) and (b) in the text refer to the related technologies. Figure 2 After the clock signal duty cycle is adjusted from 50% to less than 50%, the common voltage of the normal area and edge area of ​​the touch electrode is disturbed. Figure 11 Parts (c) and (d) in the embodiments of this application are used to represent... Figure 10The common voltage of the touch electrode in the normal and edge regions is disturbed after the duty cycle of the clock signal is adjusted from 50% to less than 50%. (a) and (c) correspond to the normal region, and (b) and (d) correspond to the edge region. In part (a), the falling edge of scan signal G1' is adjacent to the rising edges of scan signals G6' and G7', and the time interval between the rising edges of scan signals G6' and G7' is 1H. The common voltage on touch electrode 02 changes due to the disturbance of the rising edge of scan signal G6', as shown in Com1 in the figure, and also changes due to the disturbance of the falling edge of scan signal G1', as shown in Com2 in the figure. Because the time interval between the rising edges of scan signals G6' and G7' is short, the common voltage on touch electrode 02 is disturbed after... Unable to recover in time, for example at time T1', the common voltage on touch electrode 02 is still disturbed by the rising edge of scan signal G6', and at the same time, the common voltage on touch electrode 02 is also disturbed by the falling edge of scan signal G1', as shown in Com2 in the figure. However, in part (b), for example at time T2', the common voltage on touch electrode 02 is only affected by the falling edge of scan signal Gn'. That is, the disturbance conditions of the normal area of ​​touch electrode 02 (the area of ​​touch electrode other than edge areas A and B) and edge areas A / B are different, thus making it easy for horizontal lines to appear in the edge areas. Figure 11 In part (c), as the interval between adjacent scan signals G(m_3)_5' and G(m_4)_7' increases, for example to 2H, the disturbance to the common voltage of the touch electrode 20 caused by the rising edge of the scan signal G(m_3)_5', such as Com1 in part (c), has enough time to recover. For example, at time T1, the touch electrode 20 is only affected by the falling edge of the scan signal G(m_1)_1'. Thus, the disturbance situation of the regular area and the edge area of ​​the touch electrode 20 is similar, and the degree of change of the common voltage on the touch electrode 20 is similar or the same, thereby effectively improving the problem of horizontal lines and improving the display uniformity of the display area corresponding to the touch electrode.

[0032] In some embodiments of this application, the gate drive circuit may be configured as a dual-sided drive. Figure 12 and Figure 8 The difference lies in the fact that the gate drive circuits are respectively located at both ends of the gate line. For example... Figure 12 As shown, the shift register unit 31 located at the left end of the gate line 10 and the shift register unit 31 located at the right end of the gate line 10 are symmetrically arranged. The same gate line is connected to the corresponding shift register unit 31 from the left and right ends respectively, and the shift register units 31 connected to the same gate line respectively provide the same scan signal to the gate line. By adopting this bilateral driving method, the signal delay phenomenon caused by providing a scan signal from only one side is improved.

[0033] In some embodiments of this application, such as Figure 13 As shown, the gate driving circuit 30 includes a first gate driving circuit 301 and a second gate driving circuit 302, located at opposite ends of the gate line 10 along the first direction X. The first gate driving circuit 301 includes a plurality of first shift register unit groups 32 arranged along the second direction Y. Each first shift register unit group 32 includes a first shift register unit 311 and a second shift register unit 312 arranged along the second direction Y. That is, in the first gate driving circuit 301, the first shift register unit 311 and the second shift register unit 312 are alternately arranged along the second direction Y. The second gate driving circuit 302 includes a plurality of second shift register unit groups 33 arranged along the second direction Y. Each second shift register unit 33 includes a first shift register unit 311 and a second shift register unit 312 arranged along the second direction Y. That is, in the second gate driving circuit 302, the first shift register unit 311 and the second shift register unit 312 are alternately arranged along the second direction Y.

[0034] Continue to refer to Figure 13 Each first gate line 11 arranged along the second direction Y is sequentially and alternately connected to the first shift register unit 311 of each first shift register unit group 32 of the first gate driving circuit 301 and the first shift register unit 311 of each second shift register unit group 33 of the second gate driving circuit 302. For example, the first gate line m_1 is connected to the first shift register unit 311 of the first shift register unit group 32 of the first gate drive circuit 301; the second gate line m_2 is connected to the first shift register unit 311 of the second shift register unit group 33 of the second gate drive circuit 302; the third gate line m_3 is connected to the first shift register unit 311 of the next group of first shift register units 32 of the first gate drive circuit 301; the fourth gate line m_4 is connected to the first shift register unit 311 of the next group of second shift register units 33 of the second gate drive circuit 302; and the connection relationships between the remaining first gate lines and the shift register units 31 of the gate drive circuit 30 are similar. By setting the gate drive circuits at opposite ends of the gate lines and alternately driving the gate lines, the problem of large bezel size caused by setting the gate drive circuit on only one side can be improved.

[0035] Continue to refer to Figure 13Each second gate line 12 arranged along the second direction Y is sequentially and alternately connected to the second shift register unit 312 of each first shift register unit group 32 of the first gate driving circuit 301 and the second shift register unit 312 of each second shift register unit group 33 of the second gate driving circuit 302. For example, the first second gate line m+1_1 is connected to the second shift register unit 312 of the first shift register unit group 32 of the first gate drive circuit 301; the second second gate line m+1_2 is connected to the second shift register unit 312 of the second shift register unit group 33 of the second gate drive circuit 302; the third second gate line m+1_3 is connected to the second shift register unit 312 of the next group of first shift register unit groups 32 of the first gate drive circuit 301; the fourth second gate line m+1_4 is connected to the second shift register unit 312 of the next group of second shift register unit groups 33 of the second gate drive circuit 302; and the connection relationships between the remaining second gate lines and the shift register units 31 of the gate drive circuit 30 are similar. By setting the gate drive circuits at opposite ends of the gate lines and alternately driving the gate lines, the problem of large bezel size caused by setting the gate drive circuit on only one side can be improved.

[0036] Combination Figure 9 , Figure 10 and Figure 13By setting the timing of the output scan signals of the first shift register unit group 32 of the first gate driving circuit 301 and the second shift register unit group 33 of the second gate driving circuit 302, the first gate line 11 and the second gate line 12 can alternately receive scan signals during the scan timing. Specifically, the first shift register unit group 32 of the first gate driving circuit 301 and the second shift register unit group 33 of the second gate driving circuit 302 alternately output scan signals. Within each shift register unit group 32 / 33, the first shift register unit 311 and the second shift register unit 312 output scan signals sequentially. For example, the first shift register unit 311 and the second shift register unit of the first shift register unit group 32 of the first gate driving circuit 301 sequentially output scan signals G(m_1)_1 and G(m+1_1)_2, wherein scan signal G(m+1_1)_2 is delayed by 1H compared to scan signal G(m_1)_1. Then, the first shift register unit 311 and the second shift register unit 312 of the second shift register unit group 33 of the second gate driving circuit 302 sequentially output scan signals G(m_2)_3 and G(m+1_2)_4, wherein scan signal G(m_2)_3 is delayed by 1H compared to scan signal G(m+1_1)_2, and scan signal G(m+1_2)_4 is delayed by 1H compared to scan signal G(m_2)_3. Then, the next group of first shift register units of the first gate driving circuit 301... The first shift register unit 311 and the second shift register unit 312 of the storage unit group 32 sequentially output scan signals G(m_3)_5 and G(m+1_3)_6, wherein scan signal G(m_3)_5 is delayed by 1H compared to scan signal G(m+1_2)_4, and scan signal G(m+1_3)_6 is delayed by 1H compared to scan signal G(m_3)_5. Then, the first shift register unit 311 and the second shift register unit 312 of the next group of the second shift register unit group 33 of the second gate drive circuit 302 sequentially output scan signals G(m_4)_7 and G(m+1_4)_8, wherein scan signal G(m_4)_7 is delayed by 1H compared to scan signal G(m+1_3)_6, scan signal G(m+1_4)_8 is delayed by 1H compared to scan signal G(m_4)_7, and so on.

[0037] In related technologies, when gate driving circuits located at both ends of a gate line alternately drive the gate line, the gate driving circuit on the left side of the gate line is connected to the gate lines in odd-numbered rows, and the gate driving circuit on the right side of the gate line is connected to the gate lines in even-numbered rows, with odd and even rows driven alternately, for example, left 1, right 2, left 3, right 4, ... In this application, the first shift register group of the first gate driving circuit and the second shift register group of the second gate driving circuit are driven alternately, for example, left 1, left 2, right 3, right 4, left 5, left 6, right 7, right 8, ..., thereby realizing the alternating driving of each first gate line and each second gate line.

[0038] The display panel also includes clock signal lines, which are connected to the gate driving circuit and provide clock signals to the gate driving circuit. To enable the first shift register unit group 32 of the first gate driving circuit 301 and the second shift register unit 33 of the second gate driving circuit 302 to alternately drive the gate lines, the clock signal lines are matched with the first shift register unit group and the second shift register unit group in a grouped manner. For example, the first to the second P clock signal lines are divided into P groups. The first group includes the first clock signal line and the second clock signal line, the second group includes the third clock signal line and the fourth clock signal line, and so on, until the Pth group includes the second P-1 clock signal line and the second P clock signal line. The odd-numbered clock signal lines are connected to the first gate driving circuit 301, and the even-numbered clock signal lines are connected to the second gate driving circuit 302. The following explanation uses a display panel with 12 clock signal lines as an example.

[0039] Combination Figure 9 , Figure 10 , Figures 13-15The 12 clock signal lines are labeled CK1-CK12 and divided into 6 clock signal line groups. The clock signal output by each clock signal line includes multiple clock cycles. One clock cycle includes a high level and a low level, and the duration of one clock cycle is 12H. Within one clock cycle, the clock signals output by clock signal lines CK1 to CK12 are staggered by 1H. In the first gate drive circuit 301 on the left side of the gate line, every three first shift register unit groups 32 form a cycle, which is connected to the first group of clock signal lines, the third group of clock signal lines, and the fifth group of clock signal lines, respectively. That is, the first gate drive circuit 301 is connected to clock signal lines CK1, CK2, CK5, CK6, CK9, and CK10, respectively. The shift register units 311 in the three first shift register unit groups 32 in one cycle are labeled R1, R2, R5, R6, R9, and R10, respectively. In the second gate drive circuit 302 to the right of the gate line, every three second shift register units 33 form a cycle, connected to the second, fourth, and sixth clock signal lines respectively. That is, the second gate drive circuit 302 is connected to clock signal lines CK3, CK4, CK7, CK8, CK11, and CK12 respectively. The shift register units 312 in the three second shift register unit groups 33 of one cycle are denoted as R3, R4, R7, R8, R11, and R12 respectively. Here, "x" in Rx represents the sequence number of the connected clock signal line. For either the first gate drive circuit 301 or the second gate drive circuit 302, a clock signal is provided by 6 clock signal lines. According to the cascading relationship, the output signal of the shift register unit 31 of the (q-3)th stage serves as the input signal of the shift register unit 31 of the qth stage. In one cycle of the first gate drive circuit 301, the output signal of shift register unit R1 serves as the input signal of shift register unit R6, the output signal of shift register unit R2 serves as the input signal of shift register unit R9, and the output signal of shift register unit R5 serves as the input signal of shift register unit R10. In one cycle of the second gate drive circuit 302, the output signal of shift register unit R3 serves as the input signal of shift register unit R8, the output signal of shift register unit R4 serves as the input signal of shift register unit R11, and the output signal of shift register unit R7 serves as the input signal of shift register unit R12.

[0040] like Figure 16 As shown, the clock signals of the 12 clock signal lines are output sequentially with a 1H delay. The duty cycle of the clock signal is 50%, meaning that the high-level duration accounts for 50% of the total clock cycle. Figure 14In an embodiment where the gate drive circuit is connected to 12 clock signals, if the duty cycle of the clock signals is 50%, the input and output signals of several shift register units in the gate drive circuit will overlap, affecting the normal output of the shift register units. For example, in the first gate drive circuit, there is overlap between the input signal G_R1 received by shift register unit R6 and its output signal G_R6, as shown in the shaded area filled with diagonal lines. Similarly, there is overlap between the input signal G_R5 received by shift register unit R10 and its output signal G_R10, as shown in the shaded area filled with dots. The shift register units R8 and R12 in the second gate drive circuit have the same problem. Therefore, in this application, the duty cycle of the clock signals is set to be less than 50%. Figure 15 Taking a clock cycle of 12H and a high-level duration of 5H as an example, this approach can accommodate both normal cascading between shift register units and alternating driving between the first shift register unit group and the second shift register unit group.

[0041] In some embodiments of this application, the number of clock signal lines can be 8, divided into 4 clock signal line groups. The duration of one clock cycle can be 8H. Within one clock cycle, the 8 clock signal lines output clock pulses sequentially with a 1H delay. The first gate driving circuit is connected to the first group of clock signal lines and the third group of clock signal lines, respectively. Every two first shift register units form a cycle, and the shift register units are denoted as R1, R2, R5, and R6, respectively. The second gate driving circuit is connected to the second group of clock signal lines and the fourth group of clock signal lines, respectively. Every two second shift register units form a cycle, and the shift register units are denoted as R3, R4, R7, and R8, respectively. For any of the first gate driving circuit 301 and the second gate driving circuit 302... Firstly, it is provided with clock signals by four clock signal lines. According to the cascading relationship, the output signal of the shift register unit 31 of the (w-2)th stage serves as the input signal of the shift register unit 31 of the wth stage. In the first gate drive circuit, the output signal of the shift register unit R1 serves as the input signal of the shift register unit R5, and the output signal of the shift register unit R2 serves as the input signal of the shift register unit R6. In this configuration, the duty cycle of the clock signal can be 50%, or the duty cycle of the clock signal can be less than 50%. There will be no overlap between the input and output signals of each shift register unit. Thus, the implementation of this application can take into account both the normal cascading between each shift register unit and the alternating drive of the first shift register unit group and the second shift register unit group.

[0042] In some embodiments of this application, such as Figure 17As shown, the gate driving circuit 30 includes a plurality of shift register units 31 arranged along the second direction Y. The plurality of shift register units 31 include a first shift register unit 311 and a second shift register unit 312. The first shift register unit 311 is connected to the first gate line 11, and the second shift register unit 312 is connected to the second gate line 12. Along the second direction Y, the first shift register unit 311 and the second shift register unit 312 are arranged alternately. Figure 17 and Figure 8 One of the differences lies in the connection order of the shift register unit 31 and the gate line 10. (Continue to refer to...) Figure 17 Each first gate line 11 arranged along the second direction Y is sequentially connected to each first shift register unit 311 arranged along the second direction Y. Each second gate line 12 arranged in the opposite direction to the second direction Y is sequentially connected to each second shift register unit 312 arranged along the second direction Y. That is, the first gate line 11 and the first shift register unit 311 are connected in the same arrangement order, and the second gate line 12 and the second shift register unit 312 are connected in the opposite arrangement order. Thus, the connection lines between the first gate line 11 and the first shift register unit 311 are arranged sequentially along the second direction Y, and the connection lines between the second gate line 12 and the second shift register unit 312 are arranged sequentially in the opposite direction to the second direction Y. The two types of connection lines can be kept separate, reducing mutual interference between signals.

[0043] Continue to refer to Figure 17 The gate driving circuit 30 can be disposed at one end of the gate line 10 to drive the gate line 10 on one side. For example, the gate driving circuit 30 includes a gate driving circuit 30a located at the left end of the gate line 10, or the gate driving circuit 30 includes a gate driving circuit 30b located at the right end of the gate line. Optionally, the gate driving circuits 30 can be disposed at opposite ends of the gate line 10 to drive the gate line 10 on both sides. Figure 17 The diagram illustrates that gate drive circuits 30a and 30b are respectively provided at the left and right ends of the gate line 10.

[0044] Figure 18 To and Figure 17 The corresponding scan timing diagram, combined with Figure 17 and Figure 18Each first gate line 11 overlapping with the first touch electrode 21 receives scan signals sequentially from the first first gate line m_1 to the nth first gate line m_n. The second gate line 12 overlapping with the second touch electrode 22 receives scan signals sequentially in the reverse order from the nth second gate line m+1_n to the first second gate line m+1_1. Furthermore, each first gate line 11 and second gate line 12 receives scan signals alternately. This arrangement increases the time interval between the rising or falling edges of the scan pulses for each first gate line 11 and each second gate line 12, improving the recovery capability of the common voltage on the first and second touch electrodes, reducing horizontal lines, and simultaneously improving the display uniformity of the display area corresponding to each touch electrode.

[0045] In some embodiments of this application, such as Figure 19 As shown, and in combination Figure 9 and Figure 10 The gate driving circuit 30 includes a first gate driving circuit group 303 and a second gate driving circuit group 304. Along the first direction X, the first gate driving circuit group 303 and the second gate driving circuit group 304 are located at opposite ends of the gate line 10. The first gate driving circuit group 303 includes a plurality of first shift register units 311 arranged along the second direction Y. The first shift register units 311 are connected to the first gate line 11. The second gate driving circuit group 304 includes a plurality of second shift register units 312 arranged along the second direction Y. The second shift register units 312 are connected to the second gate line 12. The display panel also includes 2a clock signal lines, namely the first clock signal line CK1, the second clock signal line CK2, ..., the seconda clock signal line CK2a, where a is an integer greater than or equal to 2. Within one clock cycle, the clock pulses output from the first clock signal line CK1 to the seconda clock signal line CK2a are sequentially staggered. The odd-numbered clock signal lines are cyclically connected to each of the first shift register units 311 of the first gate drive circuit group 303. For example, the first clock signal line CK1, ..., the seconda clock signal line CK2a... The third clock signal line CK3, ..., the second a-1 clock signal line are sequentially and cyclically connected to each of the first shift register units 311 of the first gate driving circuit group 303. The even-numbered clock signal lines are sequentially and cyclically connected to each of the second shift register units 312 of the second gate driving circuit group 304. For example, the second clock signal line CK2, the fourth clock signal line CK4, ..., the second a clock signal line CK2a are sequentially and cyclically connected to each of the second shift register units 312 of the second gate driving circuit group 304. Thus, the first gate driving circuit group 303 and the second gate driving circuit 304 alternately output scan signals. The timing of the scan signals transmitted on each of the first gate lines 11 overlapping with the first touch electrode 21 and each of the second gate lines 12 overlapping with the second touch electrode 22 can be viewed. Figure 9 .use Figure 19 The connection method shown can divide the odd-numbered clock signal lines into one group and the even-numbered clock signal lines into another group. This ensures that the cascading relationship between the shift registers of the first gate drive circuit group and the second gate drive circuit group is regular and that the scan signal can be output normally. At the same time, it reduces the limitation on the clock signal duty cycle. The clock signal duty cycle can be 50% or less than 50%.

[0046] In the above embodiments, the driving method of the gate lines corresponding to the first touch electrode and the second touch electrode is presented. In some embodiments of this application, the touch electrode of the display panel may include a plurality of touch electrode groups arranged along the second direction, and the touch electrode group includes the first touch electrode and the second touch electrode.

[0047] like Figure 20 As shown, the display panel includes a plurality of touch electrodes 20 arranged in an array, and the plurality of touch electrodes 20 includes a plurality of touch electrode groups 200 arranged along the second direction Y. Figure 20 Taking two adjacent touch electrode groups 201 and 202 as examples, touch electrode group 200 includes a first touch electrode 21 and a second touch electrode 22. For the same touch electrode group 200, the connection method of the first gate line 11 overlapping with the first touch electrode 21 and the second gate line 12 overlapping with the second touch electrode 22 with the gate driving circuit, as well as the timing of the received scan signal, can be referred to Figures 3-19 In the corresponding implementations, for different touch electrode groups 200, such as adjacent touch electrode groups 201 and 202, the timing of the scan signal received by the gate line 10 corresponding to the touch electrode group 202 can immediately follow the timing of the scan signal received by the gate line 10 corresponding to the touch electrode 201. Thus, for the display area corresponding to each touch electrode group 200, the problem of horizontal lines on the display can be alleviated or eliminated, and the display uniformity of the corresponding display area can be improved.

[0048] Based on the same inventive concept, this application also provides a driving method for a display panel. The display panel includes a gate driving circuit, multiple gate lines, and multiple touch electrodes. The gate driving circuit provides scan signals to the multiple gate lines. The multiple gate lines extend along a first direction and are arranged along a second direction. The multiple touch electrodes include first touch electrodes and second touch electrodes adjacent to each other along the second direction. Gate lines overlapping with the first touch electrodes are called first gate lines, and gate lines overlapping with the second touch electrodes are called second gate lines. In the driving method, the gate driving circuit provides scan signals to the multiple gate lines, and the scanning sequence of at least one second gate line is located between the scanning sequences of at least two first gate lines. Specifically, the gate driving circuit alternately provides scan signals to the first gate lines and the second gate lines. Detailed descriptions and beneficial effects of this embodiment can be found in the foregoing content and will not be repeated here.

[0049] Based on the same inventive concept, this application also provides a display device, including the display panel in any embodiment of this application. For example... Figure 21 As shown, the display device 1000 provided in this application includes a display panel. The display devices in this application include, but are not limited to, wearable products, mobile phones, tablets, computers, televisions, vehicle display devices, and other display devices with display functions. Figure 21 Taking a mobile phone as an example. The display device of this application has the same technical effects as the display panel provided in this application, which will not be elaborated here.

[0050] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, Includes gate drive circuitry, multiple gate lines, and multiple touch electrodes; The gate driving circuit is used to provide scan signals to the plurality of gate lines; The plurality of gate lines extend along a first direction and are arranged along a second direction; The plurality of touch electrodes includes a first touch electrode and a second touch electrode that are adjacent to each other along the second direction, and the gate line that overlaps with the first touch electrode is the first gate line, and the gate line that overlaps with the second touch electrode is the second gate line. In the scanning timing of the plurality of gate lines, the scanning sequence of at least one of the second gate lines is located between the scanning sequences of at least two of the first gate lines.

2. The display panel according to claim 1, characterized in that, The gate driving circuit includes a plurality of shift register units arranged along the second direction. The plurality of shift register units include a first shift register unit and a second shift register unit. The first shift register unit is connected to the first gate line, and the second shift register unit is connected to the second gate line. Along the second direction, at least one stage of the second shift register unit is located between two first shift register units.

3. The display panel according to claim 2, characterized in that, Along the second direction, the first shift register unit and the second shift register unit are arranged alternately.

4. The display panel according to claim 3, characterized in that, The gate driving circuit includes a first gate driving circuit and a second gate driving circuit, and along the first direction, the first gate driving circuit and the second gate driving circuit are located at opposite ends of the gate line. The first gate driving circuit includes a plurality of first shift register units arranged along the second direction, and the first shift register unit group includes first shift register units and second shift register units arranged along the second direction; The second gate drive circuit includes a plurality of second shift register units arranged along the second direction, and the second shift register unit group includes the first shift register unit and the second shift register unit arranged along the second direction; Each of the first gate lines arranged along the second direction is sequentially and alternately connected to the first shift register unit of each of the first shift register unit groups of the first gate driving circuit and the first shift register unit of the second shift register unit group of the second gate driving circuit.

5. The display panel according to claim 4, characterized in that, Each of the second gate lines arranged along the second direction is sequentially and alternately connected to the second shift register unit of each of the first shift register unit groups of the first gate driving circuit and the second shift register unit of the second gate driving circuit.

6. The display panel according to claim 4, characterized in that, The first shift register group of the first gate driving circuit and the second shift register unit group of the second gate driving circuit alternately output the scan signal; In this configuration, the first shift register unit and the second shift register unit of the first shift register unit group output scan signals in sequence, and the first shift register unit and the second shift register unit of the second shift register unit group output scan signals in sequence.

7. The display panel according to claim 4, characterized in that, It also includes a clock signal line, which is connected to the gate driving circuit and provides a clock signal to the gate driving circuit. The duty cycle of the clock signal is less than or equal to 50%.

8. The display panel according to claim 3, characterized in that, Each of the first gate lines arranged along the second direction is sequentially connected to each of the first shift register cells arranged along the second direction; Each of the second gate lines arranged in a direction opposite to the second direction is sequentially connected to each of the second shift register cells arranged in the second direction.

9. The display panel according to claim 1, characterized in that, The gate driving circuit includes a first gate driving circuit group and a second gate driving circuit group. Along the first direction, the first gate driving circuit group and the second gate driving circuit group are respectively located at opposite ends of the gate line. The first gate drive circuit group includes a plurality of first shift register units arranged along the second direction, and the first shift register units are connected to the first gate line; The second gate drive circuit group includes a plurality of second shift register units arranged along the second direction, and the second shift register units are connected to the second gate line; The display panel also includes 2a clock signal lines, namely the first clock signal line, the second clock signal line, ..., the seconda clock signal line. Within one clock cycle, the clock signals output by the first clock signal line to the seconda clock signal line are staggered in sequence. The first clock signal line, the third clock signal line, ..., the seconda-1 clock signal line are sequentially and cyclically connected to each of the first shift register units of the first gate drive circuit group. The second clock signal line, the fourth clock signal line, ..., the seconda clock signal line are sequentially and cyclically connected to each of the second shift register units of the second gate drive circuit group; Where a is an integer greater than or equal to 2.

10. The display panel according to claim 1, characterized in that, The touch electrode includes a plurality of touch electrode groups arranged along the second direction, and the touch electrode group includes the first touch electrode and the second touch electrode.

11. A driving method for use in a display panel, characterized in that, The display panel includes a gate driving circuit, multiple gate lines, and multiple touch electrodes; The gate driving circuit is used to provide scan signals to the plurality of gate lines; The plurality of gate lines extend along a first direction and are arranged along a second direction; The plurality of touch electrodes includes a first touch electrode and a second touch electrode that are adjacent to each other along the second direction, wherein the gate line that overlaps with the first touch electrode is the first gate line, and the gate line that overlaps with the second touch electrode is the second gate line. In the driving method, the gate driving circuit provides a scan signal to the plurality of gate lines, and the scan sequence of at least one of the second gate lines is located between the scan sequences of at least two of the first gate lines.

12. The driving method according to claim 11, characterized in that, The gate drive circuit alternately provides scan signals to the first gate line and the second gate line.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-10.

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