Chip testing apparatus, system, method

Abstract

This disclosure provides a chip testing apparatus, system, and method. The apparatus includes: a first switching module for determining the test network to be tested among multiple test networks, wherein the multiple test networks are respectively connected to multiple first ports of a link switch, and the test unit of the chip under test is connected to a second port of the link switch; and a second switching module for controlling the interconnection between the first and second ports of the test network to be tested, and the disconnection between the first and second ports of other test networks, thereby realizing the interconnection between the test network to be tested and the test unit of the chip under test. This disclosure reduces the manpower required for network deployment in chip testing solutions, improves the efficiency, reusability, automation, and intelligence of network deployment in chip testing solutions.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a chip testing apparatus, system, and method. Background Technology

[0002] In the testing process of computing and storage device chips, specific tests are required on the chip's networking functions, performance, compatibility, and reliability at pre-silicon verification platforms, post-silicon verification platforms, and complete system product verification platforms. However, current chip testing systems typically employ manual methods for network deployment, which is labor-intensive and suffers from low efficiency, reusability, automation, and intelligence, failing to meet the complex requirements of chip testing systems. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a chip testing apparatus, system, and method to at least solve or alleviate the above-mentioned problems.

[0004] According to a first aspect of the present disclosure, a chip testing apparatus is provided, applied to a testing host computer. The apparatus includes: a first switching module, configured to determine a test network to be tested among multiple test networks, wherein the multiple test networks are respectively connected to multiple first ports of a link switch, and a test unit of a chip under test is connected to a second port of the link switch; and a second switching module, configured to control the interconnection between the first port and the second port connected to the test network to be tested, and the disconnection between the first port and the second port connected to other test networks, thereby realizing the interconnection between the test network to be tested and the test unit of the chip under test.

[0005] According to a second aspect of the present disclosure, a chip testing system is provided, comprising: a testing host computer, the testing host computer including the chip testing device described in the first aspect.

[0006] According to a third aspect of the present disclosure, a chip testing method is provided. The method includes: determining a test network to be tested among multiple test networks, wherein the multiple test networks are respectively connected to multiple first ports of a link switch, and a test unit of a chip under test is connected to a second port of the link switch; controlling the first port and the second port connected to the test network to be tested to interconnect, and disconnecting the first port and the second port connected to other test networks, thereby realizing the interconnection between the test network to be tested and the test unit of the chip under test.

[0007] According to the chip testing scheme provided in this disclosure, a test network to be tested is determined from multiple test networks. These multiple test networks are respectively connected to multiple first ports of a link switch, and the test unit of the chip under test is connected to a second port of the link switch. This disclosure achieves interconnection between the test network to be tested and the test unit of the chip under test by controlling the interconnection between the first and second ports of the test network to be tested, while disconnecting the first and second ports of other test networks. This disclosure reduces the manpower required for network deployment in chip testing schemes, improves the efficiency, reusability, automation, and intelligence of network deployment. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0009] Figure 1 This is a schematic diagram of a test host computer according to an embodiment of this disclosure;

[0010] Figure 2 This is a schematic diagram of a chip testing system according to another embodiment of the present disclosure;

[0011] Figure 3 This is a schematic diagram of an origin corrector according to another embodiment of the present disclosure;

[0012] Figure 4 This is a schematic diagram of a chip testing apparatus according to an embodiment of the present disclosure;

[0013] Figure 5 This is a schematic diagram of the test network link switching of a chip testing apparatus according to another embodiment of this disclosure;

[0014] Figure 6 This is a schematic diagram of a chip testing apparatus according to yet another embodiment of the present disclosure;

[0015] Figure 7 This is a schematic diagram of a chip testing apparatus according to another embodiment of the present disclosure;

[0016] Figure 8 This is a schematic diagram of the hard disk transport module of a chip testing apparatus according to another embodiment of the present disclosure;

[0017] Figure 9 This is a schematic diagram of the hard disk transport module of a chip testing apparatus according to another embodiment of the present disclosure;

[0018] Figure 10This is a schematic diagram of the hard disk transport module of a chip testing apparatus according to another embodiment of the present disclosure;

[0019] Figure 11 This is a flowchart of a chip testing method according to an embodiment of the present disclosure. Detailed Implementation

[0020] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0021] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0022] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0023] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0024] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information other than that necessary for basic functions will not affect the user's use of basic functions.

[0025] First, some of the nouns or terms that appear in the description of the embodiments of this disclosure are to be interpreted as follows.

[0026] SAS (Serial Attached SCSI): This is a hard drive interface that uses serial technology to achieve higher transmission speeds and improves internal space by shortening the connection cable.

[0027] SATA (Serial Advanced Technology Attachment): Serial ATA is a hard drive interface specification jointly proposed by Intel, IBM, Dell, APT, Maxtor, and Seagate.

[0028] PCIe (Peripheral Component Interconnect Express): A high-speed serial computer expansion bus standard, originally named "3GIO". It was proposed by Intel in 2001 to replace the older PCI, PCI-X and AGP bus standards.

[0029] CXL (Compute Express Link): A new type of high-speed interconnect technology designed to provide higher data throughput and lower latency to meet the needs of modern computing and storage systems.

[0030] Jammer Function: Primarily used to allow users to simulate electronic interference signals, it is crucial for testing and evaluating the anti-interference capabilities of electronic systems. This function helps identify and respond to potential electronic interference threats, ensuring stable system operation and information security.

[0031] Trainer Function: Primarily used for training and simulating various signal environments, helping users become familiar with and master signal processing techniques. By simulating different signal conditions, the Trainer function can help users improve their ability to cope with complex signal environments, whether in communications, radar, or other fields requiring signal processing.

[0032] DUT (Device Under Test): refers to the test unit on the chip under test in chip testing. DUT usually refers to the functional unit of the chip, such as memory, on-chip microcontroller, etc. In chip testing, a series of tests are performed on the DUT to verify whether its function is normal.

[0033] NVMe (NVM Express): Non-volatile memory host controller interface specification is a logical device interface specification.

[0034] EMU (Emulator): A pre-silicon simulator simulation and verification platform, such as the prototype HAPS100.

[0035] EVB (Evaluation Board): A verification and evaluation board, a common hardware test board.

[0036] CRB (Customer Reference Board): This is a product reference board provided by the design and development manufacturer to its customers. It is a form between the EVB verification and evaluation board and the productized complete platform. Its purpose is to accelerate the customer's reference design during product development.

[0037] The chip testing scheme provided by the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0038] Test System

[0039] The testing system includes a host computer 1, see [link / reference] Figure 1 The host computer 1 for testing may include a processor 11 and a memory 12. The memory 12 in the host computer 1 can be used as main memory (or simply main memory or RAM) to store instruction information and / or data information. For example, the memory 12 can store data provided by the processor 11, and can also be used to realize data exchange between the processor 11 and external storage devices (or auxiliary memory or external memory).

[0040] In some cases, the processor 11 needs to access the memory 12 via the interconnect bus to retrieve or modify the data in the memory 12.

[0041] In addition, the host computer 1 may also include storage devices, display devices, and input / output devices. Storage devices may be hard drives, optical discs, flash memory, or other devices used for information storage and retrieval, coupled to the interconnect bus via corresponding interfaces. Display devices may be coupled to the interconnect bus via a corresponding graphics card, used to display information based on display signals provided by the interconnect bus.

[0042] The test host computer 1 may also include communication devices, enabling it to communicate with networks or other devices in various ways. The communication devices may include one or more communication modules, and may include wireless communication modules adapted to specific wireless communication protocols. For example, the communication devices may include a WLAN module for implementing WiFi communication conforming to the IEEE 802.11 standard. The communication devices may include a WWAN module for implementing wireless wide area communication conforming to cellular or other wireless wide area protocols. The communication devices may also include communication modules using other protocols, such as Bluetooth modules, or other custom-type communication modules. The communication devices may also be ports for serial data transmission.

[0043] In this embodiment, the chip testing device 100 is applied to a test host computer 1. The processor of the test host computer 1 executes the operations of the various functional modules included in the chip testing device 100. The processor of the test host computer 1 determines the test network to be tested from multiple test networks. These multiple test networks are respectively connected to multiple first ports of a link switch, and the test unit of the chip under test is connected to a second port of the link switch. This embodiment achieves interconnection between the test network to be tested and the test unit of the chip under test by controlling the interconnection between the first and second ports of the test network to be tested, and disconnecting the first and second ports of other test networks. This embodiment reduces the manpower required for network deployment in chip testing schemes, improves the efficiency, reusability, automation, and intelligence of network deployment in chip testing schemes.

[0044] Figure 2 A schematic block diagram of a testing system is shown. The testing system also includes: a material receiving cabinet 21, a control station 22, a robotic arm 23, a networking cabinet 24, a switching and error correction cabinet 25, a testing cabinet 26, and the aforementioned testing host computer 1.

[0045] Incoming material cabinet 21 is used to store hard drives for various computing and storage business scenarios. These hard drives are stored in disk racks. Incoming material cabinet 21 is used to store hard drives required for different test batches. These hard drives include hard drives of different forms, such as solid-state drives and mechanical hard drives; they also include hard drives of different sizes, such as 2.5-inch and 3.5-inch hard drives; they also include hard drives with different interfaces, such as U.2, U.3, E1.S / L, and E3.S / L interface hard drives; and they also include hard drives with different protocols, such as SAS, SATA, NVMe, and CXL hard drives.

[0046] The rack of the disk enclosure is fixed to the rack rails with screws. This embodiment does not limit the specific structure of the disk enclosure and rack. This embodiment uses the U-number of the rack from top to bottom of the material receiving cabinet 21 as the vertical coordinate and the number of slots in the disk enclosure from left to right as the horizontal coordinate to determine the coordinate calibration points of the hard drives. Specifically, this embodiment stores the coordinate positioning points of each hard drive through a hard drive material database.

[0047] The incoming material cabinet 21 stores hard drives of various forms and interfaces required for different test batches. Adding or removing hard drives from the incoming material cabinet 21 will update the hard drive and its coordinate calibration point in the hard drive material database. Furthermore, the disk racks and structural components on the racks in the incoming material cabinet 21 can be replaced and maintained to better support the different hard drive requirements of different chips under test.

[0048] The control unit 22 connects to the robotic arm 23, which retrieves the hard drive from the receiving cabinet 21 and transports it to the network cabinet 24 for installation. Specifically, the robotic arm 23 is a 6-axis robotic arm that can rotate and extend without dead angles between the receiving cabinet 21 and the network cabinet 24. The robotic arm 23 can perform hard drive retrieval operations in the receiving cabinet 21 and hard drive installation operations in the network cabinet 24. The robotic arm 23's robotic hand can rotate, extend, and open and close its grippers to adapt to the needs of ejecting, pushing, clamping, and moving hard drives with different interface types.

[0049] The network cabinet 24 stores the hard drives transported by the robotic arm 23. The stored hard drives include various types and interfaces required for different test batches. These hard drives include different forms, such as solid-state drives (SSDs) and mechanical hard drives (HDDs); they also include different sizes, such as 2.5-inch and 3.5-inch hard drives; they include hard drives with different interfaces, such as U.2, U.3, E1.S / L, and E3.S / L interface hard drives; and they include hard drives with different protocols, such as SAS, SATA, NVMe, and CXL hard drives.

[0050] The rack of the network cabinet 24, which houses the hard drives, is secured to rack rails with screws. This embodiment does not limit the specific structure of the rack and the enclosure. This embodiment uses the number of U-shaped sections on the rack of the network cabinet 24 from top to bottom as the vertical coordinate and the number of slots in the enclosure from left to right as the horizontal coordinate to determine the coordinate calibration points of the hard drives. Specifically, this embodiment stores the coordinate positioning points of each hard drive using a hard drive network database.

[0051] The network cabinet 24 stores hard drives of various forms and interfaces required for different test batches. Adding or removing hard drives from the network cabinet 24 will update the hard drive and its coordinate calibration points in the hard drive networking database. Furthermore, the disk enclosures and structural components on the racks within the network cabinet 24 support replacement and maintenance to better support the different hard drive requirements of different chips under test.

[0052] The network cabinet 24 also includes a backplane connector, which includes a test port. The test port is connected to the device under test via a cable to enable the deployment of the test network.

[0053] In some embodiments, see Figure 3 An origin calibrator 221 is installed on the horizontal plane of the control unit 22 to calibrate the origin of the robotic arm 23's movement. For example, the origin calibrator 221 is an "L"-shaped ruler. The robotic arm 23 places one corner of the hard drive within this "L"-shaped ruler, thereby calibrating the origin of the robotic arm 23's movement. In addition to locating the hard drive based on the coordinate calibration points of the hard drive in the hard drive material database, this embodiment of the present disclosure also uses the origin calibrator 221 to calibrate the hard drive's position, thereby reducing positioning errors caused by the deformation of the disk cabinet components of the receiving cabinet and the networking cabinet under stress, and obtaining the hard drive's position more accurately.

[0054] In some embodiments, positioning stickers are affixed to the locations of the hard drives in the receiving cabinet 21 and the networking cabinet 24. The positioning stickers are usually reflective stickers so that they can be more easily captured to identify the location of the hard drives.

[0055] See Figure 2 A camera 231 is positioned near the end of the robotic arm 23, away from the robotic hand. The camera 231 captures a positioning sticker (not shown) attached to the location of the hard drive, allowing the robotic arm 23 to correct the hard drive's position based on the location of the positioning sticker. In addition to locating the hard drive based on its coordinate calibration points in the hard drive material database, this embodiment also uses the camera 231 to capture the positioning sticker to correct the hard drive's position, thereby reducing positioning errors caused by the deformation of the disk cabinet components in the receiving cabinet and network cabinet, and obtaining a more accurate hard drive position. This embodiment can also further correct the hard drive's position using an origin calibrator 211 based on the camera 231 capturing the positioning sticker, thus obtaining a more accurate hard drive position.

[0056] Specifically, the positioning sticker is illuminated by a supplementary light (not shown in the figure) to improve the accuracy of the camera 23 in capturing the positioning sticker, thereby assisting in the automatic and precise positioning and repositioning of the hard drive.

[0057] In some embodiments, the aforementioned host computer 1 can also be connected to a remote test machine via a communication device, enabling the test system of this embodiment to be remotely controlled.

[0058] In this embodiment, the test host computer 1 controls the robotic arm 23 to remove hard drives from the incoming material cabinet and install them into the network cabinet. The test host computer 1 controls the robotic arm 23 to automate the storage, retrieval, input, and movement of materials in the incoming material cabinet, thus achieving automated test deployment. The incoming material cabinet 21 and the network cabinet 24 can store hard drives of different shapes, sizes, and interfaces, thereby meeting the chip testing needs of different application scenarios corresponding to different test batches.

[0059] During the operation of the hard drive by the host computer 1 and the robotic arm 23, if deformation deviations, displacements, abnormal clamping postures, loosening, or drops occur in the hard drive material or disk cabinet structure, the robotic arm 23 controls the origin calibrator 211 of the machine platform 22 and uses a camera to capture the positioning sticker to assist in identifying the hard drive's location, achieving automatic and accurate positioning and repositioning of the hard drive's coordinates. The extension and retraction of the gripper structure of the robotic arm 23 allows for the ejection and pushing of the material hard drive in the disk cabinet, enabling operations such as hard drive insertion, removal, and disconnection, supporting automated reliability testing.

[0060] After the host computer 1 installs the hard drive into the network cabinet 24, it forms multiple test networks through the test ports of the backplane connector of the network cabinet 24. Each test network includes at least one test port.

[0061] The switching and error correction cabinet 25 includes a link switcher 251 and an analyzer 252.

[0062] The link switch 251 is at least one of a SAS link switch and a PCIe link switch. The SAS link switch is compatible with both the SAS and SATA protocols; the PCIe link switch is compatible with both the PCIe and CXL protocols.

[0063] Multiple test networks in the network cabinet 24 are connected to multiple ports of the link switch 251 via cables. The test unit (DUT) of the device under test chip is also connected to multiple ports of the link switch 251 via cables. The host computer 1 configures arbitrary pairwise interconnections between the multiple ports of the link switch 251.

[0064] The device under test (DUT) chip is housed in test cabinet 26, which also houses the necessary test platform. The test network and test platform are connected via a standard interface, supporting SAS, SATA, PCIe, and CXL protocols. Therefore, DUT chips from different test platforms during the R&D testing phase can be integrated and deployed within test cabinet 26. These different test platforms include: a pre-silicon EMU simulation prototype verification platform, a post-silicon EVB sample verification platform, and a CRB and complete system productization verification platform.

[0065] In this embodiment, multiple test networks are connected to multiple first ports of a link switch 251 via cables, and the test unit of the device under test (DUT) chip is connected to a second port of the link switch via a cable. The host computer 1 controls the link switch 251 to determine the test network to be tested among the multiple test networks. The host computer 1 controls the link switch 251 to interconnect the first and second ports of the test network to be tested, while disconnecting the first and second ports of other test networks, thereby achieving interconnection between the test network to be tested and the test unit of the DUT chip.

[0066] Therefore, in this embodiment, the test network of the device under test (DUT) chip test unit connected to the test cabinet 26 can be automatically switched by the test host computer 1. That is, the test host computer 1 can automatically switch any of the multiple test networks formed by the network cabinet 24 to connect to the DUT chip test unit. This embodiment achieves adaptive and automated switching of the test network that is compatible with the test environment without manual on-site intervention, operation, or repeated deployment.

[0067] In this embodiment, the transmitting port of the analyzer 252 is also connected to the third port of the link switch 251 via a cable, and the receiving port of the analyzer 252 is connected to the fourth port of the link switch 251. The host computer 1 controls the link switch 251 to disconnect the first port and the second port of the test network under test, controls the first port and the third port of the test network under test to interconnect, and controls the second port and the fourth port to interconnect. In this embodiment, the analyzer 252 is connected between the test network under test and the chip test unit of the device under test, thereby using the protocol packet capture function supported by the analyzer 252 to perform reliability tests such as capturing protocol messages during the test process, locating problems, and annotating errors.

[0068] The switch and error correction cabinet 25 includes an analyzer 252, which is at least one of a SAS analyzer and a PCIe analyzer. The SAS analyzer is compatible with both SAS and SATA protocols; the PCIe analyzer is compatible with both PCIe and CXL protocols.

[0069] The SAS analyzer has Jammer and Trainer functions; the PCIe analyzer has Jammer functions, and analyzer 252 uses the supported Jammer / Trainer functions to construct protocol error injection and support automated reliability testing.

[0070] It should be noted that this embodiment only describes the control and operation process between the host computer 1 and the receiving cabinet 21, control platform 22, robotic arm 23, networking cabinet 24, switching and error correction cabinet 25, and test cabinet 26 in the chip testing system. However, the chip testing system in this embodiment does not necessarily include the receiving cabinet 21, control platform 22, robotic arm 23, networking cabinet 24, switching and error correction cabinet 25, and test cabinet 26.

[0071] For example, the chip testing system in this embodiment may not include the receiving cabinet 21, control station 22, robotic arm 23, and networking cabinet 24. The testing host computer 1 only controls and operates the multiple test networks that have completed networking and the switching and error correction cabinets 25 and 26. Alternatively, the chip testing system in this embodiment may not include the receiving cabinet 21, control station 22, robotic arm 23, networking cabinet 24, and testing cabinet 26, but only controls and operates the multiple test networks that have completed networking and the switching and error correction cabinet 25, as well as the chip under test (DUT) not obtained through the testing cabinet 26. Furthermore, the chip testing system in this embodiment may not include the receiving cabinet 21, control station 22, robotic arm 23, networking cabinet 24, switching and error correction cabinet 25, and testing cabinet 26. The testing host computer 1 only controls and operates the multiple test networks that have completed networking and the DUT chip not obtained through the testing cabinet 26 through a control link switch.

[0072] Chip testing equipment

[0073] Figure 4 This is a schematic diagram of the internal structure of a chip testing apparatus 100 according to an embodiment of this disclosure. The chip testing apparatus 100 is used to test a host computer. Figure 4 As shown, the chip testing device 100 includes a first switching module 110 and a second switching module 130.

[0074] The first switching module 110 is used to determine the test network to be tested among multiple test networks.

[0075] Multiple test networks in the network cabinet 24 are connected to multiple first ports of the link switch 251, and the test unit of the chip of the device under test is connected to the second port of the link switch 251.

[0076] See Figure 5For example, multiple test networks may be categorized into three test networks: Test Network A, Test Network B, and Test Network C. This embodiment of the disclosure uses the example where each of Test Network A, Test Network B, and Test Network C includes two test ports. However, this embodiment of the disclosure does not limit the number of test ports included in the test network or the number of test networks.

[0077] Test ports a and b of test networks A, B, and C are respectively connected to multiple first ports of link switch 251. Specifically, test port a of test network A is connected to first port 1, and test port b of test network A is connected to first port 2; test port a of test network B is connected to first port 3, and test port b of test network B is connected to first port 4; test port a of test network C is connected to first port 5, and test port b of test network C is connected to first port 6.

[0078] It is worth noting that the serial numbers in First Port 1, First Port 2, First Port 3, First Port 4, First Port 5, and First Port 6 do not have any other meaning; they are only used to indicate that they are different first ports.

[0079] See Figure 5 The device under test (DUT) chip test unit includes two test ports. This embodiment does not limit the number of test ports included in the DUT chip test unit; this embodiment only illustrates the example of a DUT chip test unit including two test ports.

[0080] Test ports A and B of the device under test (DUT) chip test unit are connected to the second port 11 and the second port 12 of the link switch 251, respectively. The serial numbers in the second port 11 and the second port 12 do not have any other meaning; they are only used to indicate that they are different second ports.

[0081] It is worth noting that the embodiments disclosed herein do not limit whether the first port and the second port are the same or different; they can be the same port or different ports.

[0082] The first switching module 110 determines test network A as the test network to be tested.

[0083] The second switching module 130 controls the interconnection between the first port 1 and the second port 11 of test network A, and the interconnection between the first port 2 and the second port 12 of test network A. The first ports 3, 4, 5, and 6 of test network B and test network C are all disconnected from the second ports 11 and 12, realizing the interconnection between test network A and the test unit of the chip under test.

[0084] When it is necessary to switch the test network, the first switching module 110 determines test network B as the test network to be tested.

[0085] The second switching module 130 controls the disconnection between the first port 1 and the second port 11 of test network A, and the disconnection between the first port 2 and the second port 12 of test network A. The second switching module 130 also controls the interconnection between the first port 3 and the second port 11 of test network B, and the interconnection between the first port 4 and the second port 12 of test network B. The first ports 5 and 6 of test network C are also disconnected from the second ports 11 and 12, thus achieving interconnection between test network B and the test unit of the device under test (DUT) chip.

[0086] When it is necessary to switch the test network, the first switching module 110 determines the test network C as the test network to be tested.

[0087] The second switching module 130 controls the disconnection between the first port 3 and the second port 11 of test network B, and the disconnection between the first port 4 and the second port 12 of test network B. The second switching module 130 also controls the interconnection between the first port 5 and the second port 11 of test network C, and the interconnection between the first port 6 and the second port 12 of test network C. The first ports 1 and 2 of test network A are also disconnected from the second ports 11 and 12, thus achieving interconnection between test network C and the test unit of the device under test (DUT) chip.

[0088] It is worth noting that this disclosure embodiment tests multiple test networks, and is not limited to the order of test network A, test network B, and test network C mentioned above. This disclosure embodiment only needs to ensure that the first port and the second port of the link switch 251 accessed by the test network to be tested are interconnected, and the first port and the second port of the link switch 251 accessed by other test networks are disconnected, so as to realize the interconnection between the test network to be tested and the test unit of the chip under test.

[0089] Therefore, embodiments of this disclosure can automatically switch the test network connecting the test unit of the device under test (DUT) chip, that is, automatically switch any test network among multiple test networks to connect to the DUT chip test unit. Embodiments of this disclosure achieve adaptive and automated switching of test networks compatible with the test environment without manual on-site intervention, operation, or repeated deployment.

[0090] In some embodiments, see Figure 6 The transmit port of analyzer 252 is also connected to the third port of link switch 251 via a cable, and the receive port of analyzer 252 is connected to the fourth port of link switch 251.

[0091] The chip testing device also includes:

[0092] The third switching module 150 is used to control the disconnection between the first port and the second port of the test network under test, and to control the interconnection between the first port of the test network under test and the third port of the link switch, and the interconnection between the second port and the fourth port of the link switch.

[0093] In this embodiment, the analyzer 252 is connected between the test network to be tested and the chip test unit of the device under test. The analyzer 252 uses its protocol packet capture function to capture protocol messages during the test process, locate problems, and perform reliability tests such as anomaly annotation.

[0094] Specifically, still in Figure 5 The example provided will be used for illustration.

[0095] The two transmit ports (TX) of the analyzer 252 are connected to the third port 7 and the third port 8 of the link switch 251 via cables, and the two receive ports (RX) of the analyzer 252 are connected to the fourth port 9 and the fourth port 10 of the link switch 251.

[0096] The serial numbers in third port 7 and third port 8, and fourth port 9 and fourth port 10 have no other meaning; they are only used to indicate that they are different third and fourth ports.

[0097] In this embodiment of the present disclosure, it is not limited whether the first port, second port, third port, and fourth port of the link switch 251 are the same or different; they can be the same port or different ports.

[0098] The third switching module 150 disconnects the first port 1 and the second port 11 of test network A, and disconnects the first port 2 and the second port 12 of test network A. It also connects the first port 1 and the third port 7 of test network A, connects the first port 2 and the third port 8 of test network A, connects the fourth port 9 and the second port 11, and connects the fourth port 10 and the third port 12. This enables reliability testing, including capturing protocol messages, locating problems, and annotating errors, using the protocol packet capture function supported by analyzer 252.

[0099] In some embodiments, see Figure 7 The chip testing device also includes:

[0100] The hard drive delivery module 170 is used to control the robotic arm 23 to remove at least one hard drive from the receiving cabinet 21 and install the removed hard drive into the network cabinet 24.

[0101] Specifically, the robotic arm 23 is connected to the control unit 22. The robotic arm 23 removes the hard drive from the receiving cabinet 21 and transports the removed hard drive to the network cabinet 24 for installation. In this embodiment of the disclosure, the robotic arm 23 is controlled by the hard drive transport module 170 to realize the automated storage, retrieval, input, and transfer of materials in the receiving cabinet, thereby achieving automated testing and deployment.

[0102] In some embodiments, see Figure 8 The hard disk transport module 170 includes:

[0103] The first coordinate calibration unit 1701 is used to control the robotic arm 23 to take out the hard disk from the receiving cabinet 21 according to the coordinate calibration point of the receiving cabinet 21.

[0104] The second coordinate calibration unit 1702 is used to control the robotic arm 23 to install the hard drive into the network cabinet according to the coordinate calibration point of the network cabinet 24.

[0105] In this embodiment, the coordinate positioning points of each hard disk in the incoming material cabinet 21 and the network cabinet 24 are stored in the hard disk material database. This allows the first coordinate calibration unit 1701 and the second coordinate calibration unit 1702 to control the robotic arm 23 to perform retrieval and storage operations on the hard disks based on the coordinate calibration points. This enables the robotic arm 23 to accurately locate the position of the hard disks, achieving accurate automated storage, retrieval, input, and relocation of the hard disks, and realizing automated testing and deployment.

[0106] The coordinate calibration points of the incoming material cabinet 21 are stored in the hard disk material database, and the coordinate calibration points of the network cabinet 24 are stored in the hard disk network database.

[0107] The hard disk material database and the hard disk network database update the hard disks and their coordinate calibration points according to the changes of each hard disk in the incoming material cabinet 21 and the network cabinet 24, respectively.

[0108] In some embodiments, see Figure 9 The hard drive delivery module 170 also includes:

[0109] The origin correction unit 1703 is used to control the robotic arm 23 to correct the coordinate origin of the robotic arm 23's movement on the origin corrector 221 of the control platform 22.

[0110] For example, Figure 3 The origin calibrator 221 shown is an "L"-shaped ruler. In this embodiment, the origin calibrator 221 is further used to calibrate the position of the hard disk, thereby reducing the positioning error caused by the deformation of the disk cabinet mechanism of the incoming material cabinet 21 and the network cabinet 24 under force, and obtaining the position of the hard disk more accurately.

[0111] In some embodiments, see Figure 10The hard drive delivery module 170 also includes:

[0112] The positioning sticker recognition unit 1704 is used to control the robotic arm 23 to correct the position of the hard drive according to the position of the positioning sticker. The position of the positioning sticker is captured by the camera, and the positioning sticker is attached to the location of the hard drive.

[0113] A camera 231 is positioned near the end of the robotic arm 23, away from the robotic hand. Figure 2 As shown in the figure. In this embodiment, the positioning sticker recognition unit 1704 corrects the position of the hard drive based on the position of the positioning sticker captured by the camera 231, thereby reducing the positioning error caused by the deformation of the disk cabinet components of the receiving cabinet and the networking cabinet under force, and obtaining the position of the hard drive more accurately.

[0114] Chip testing methods

[0115] Figure 11 A flowchart illustrating a chip testing method according to an embodiment of this disclosure is shown. This chip testing method can be executed by the chip testing apparatus 100 in the above embodiments. Figure 11 As shown, the chip testing method includes the following steps:

[0116] Step 1101: Determine the test network to be tested from multiple test networks, wherein the multiple test networks are respectively connected to multiple first ports of the link switch, and the test unit of the chip of the device under test is connected to the second port of the link switch.

[0117] Step 1102: Control the interconnection between the first and second ports of the test network to be tested, and disconnect the first and second ports of other test networks to achieve interconnection between the test network to be tested and the test unit of the chip under test.

[0118] In this embodiment, a test network to be tested is determined from multiple test networks. These multiple test networks are respectively connected to multiple first ports of a link switch, and the test unit of the device under test (DUT) chip is connected to a second port of the link switch. This embodiment achieves interconnection between the test network to be tested and the test unit of the DUT chip by controlling the interconnection between the first and second ports of the test network to be tested, while disconnecting the first and second ports of other test networks. This embodiment reduces the manpower required for network deployment in chip testing solutions, improves the efficiency, reusability, automation, and intelligence of network deployment in chip testing solutions.

[0119] It should be noted that the details of the timestamp synchronization method have been described in detail in conjunction with the structural diagram in the timestamp synchronization device section of the above embodiments. For the specific process, please refer to the description in the aforementioned timestamp synchronization device embodiments, and will not be repeated here.

[0120] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0121] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0122] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0123] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A chip testing device, applied to a testing host computer, the device comprising: The first switching module is used to determine the test network to be tested among multiple test networks, wherein the multiple test networks are respectively connected to multiple first ports of the link switch, and the test unit of the chip of the device under test is connected to the second port of the link switch; The second switching module is used to control the interconnection between the first port and the second port of the test network to be tested, and to disconnect the first port and the second port of other test networks, thereby realizing the interconnection between the test network to be tested and the test unit of the chip of the device under test.

2. The apparatus according to claim 1, wherein, The device further includes: The hard drive delivery module is used to control the robotic arm to remove at least one hard drive from the receiving cabinet and install the removed hard drive into the network cabinet.

3. The apparatus according to claim 2, wherein, The hard disk transport module includes: The first coordinate calibration unit is used to control the robotic arm to take the hard disk out of the receiving cabinet according to the coordinate calibration point of the receiving cabinet; The second coordinate calibration unit is used to control the robotic arm to install the hard drive into the network cabinet based on the coordinate calibration points of the network cabinet.

4. The apparatus according to claim 3, wherein, The hard disk transport module also includes: The origin correction unit is used to control the robotic arm to correct the origin of the robotic arm's movement on the origin corrector of the control platform.

5. The apparatus according to claim 3 or 4, wherein the hard disk transport module further comprises: The positioning sticker recognition unit is used to control the robotic arm to correct the position of the hard drive according to the position of the positioning sticker, the position of which is captured by the camera, and the positioning sticker is attached to the location of the hard drive.

6. The apparatus according to claim 2, wherein, The receiving cabinet and the network cabinet are used to store the hard drives required for different test batches.

7. The apparatus according to claim 2, wherein, The robotic arm's hand is at least one of a rotating, extending, or opening / closing gripper.

8. The apparatus according to claim 1, wherein, The link switch is at least one of SAS link switch and PCIe link switch.

9. The apparatus according to claim 8, wherein, The SAS link switch is compatible with both SAS and SATA protocols; the PCIe link switch is compatible with both PCIe and CXL protocols.

10. The apparatus according to claim 1, wherein, The device further includes: The third switching module is used to control the disconnection between the first port and the second port of the test network to be tested, and to control the interconnection between the first port of the test network to be tested and the third port of the link switch, and the interconnection between the second port and the fourth port of the link switch, wherein the transmitting port of the analyzer is connected to the third port, and the receiving port of the analyzer is connected to the fourth port.

11. The apparatus according to claim 10, wherein the analyzer is at least one of a SAS analyzer and a PCIe analyzer.

12. The apparatus of claim 11, wherein the SAS analyzer is compatible with both the SAS and SATA protocols; and the PCIe analyzer is compatible with both the PCIe and CXL protocols.

13. The apparatus according to claim 12, wherein the SAS analyzer has Jammer and Trainer functions; and the PCIe analyzer has Jammer function.

14. The apparatus according to claim 9, wherein the test unit of the device under test chip is integrated and deployed in a test cabinet, the test cabinet carries a test platform, and the test network and the test platform are connected by a universal standard interface.

15. A chip testing system, comprising: The host computer for testing includes the chip testing device according to any one of claims 1-14.

16. A chip testing method, the method comprising: Among multiple test networks, the test network to be tested is determined, wherein the multiple test networks are respectively connected to multiple first ports of the link switch, and the test unit of the chip of the device under test is connected to the second port of the link switch; The system controls the interconnection between the first port and the second port of the test network to be tested, while disconnecting the first port and the second port of other test networks, thereby achieving interconnection between the test network to be tested and the test unit of the chip of the device under test.

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