Low-resource-consumption Turbo decoder and decoding method based on block and variable length

Abstract

This invention discloses a low-consumption Turbo decoder and decoding method based on block and variable length, aiming to solve the problems of excessive resource consumption and limited compatibility code length parameters of existing decoders. It includes: a rate matching module, a data storage module, a decoding control module, a forward metric calculation module, a backward metric calculation module, an external information calculation module, and a SISO control module. Its key feature is that it also includes an internal interleaving address calculation module, which includes two multipliers, a divider, a ROM storing the basic sequence S, a register storing the permutation pattern T, and a register storing the prime number sequence r. This module is used to generate row and column positions according to the order of data transmission. The row positions are mapped to the original row positions using the permutation pattern. The column positions are multiplied and divided to obtain the address of the prime number sequence S. The original column positions are obtained through a lookup table. The original row positions are then multiplied by the total number of columns and added back to the original column positions. Values ​​exceeding the information length are removed to obtain the interleaving address.

Description

Technical Field

[0001] This invention belongs to the field of error correction technology for wireless communication systems, specifically relating to a low-power Turbo decoder and decoding method that can be used in satellite communication. Background Technology

[0002] Turbo codes, proposed by Berrou et al. in 1993, are parallel concatenated convolutional codes (PCCC). Their core principle is to approximate the Shannon limit through an interleaver and iterative decoding. The iterative decoding of Turbo codes is robust to time-varying channels, making them suitable for applications where rapid satellite movement leads to Doppler frequency shifts and link switching. Their technological background is deeply coupled with the low latency, wide coverage, and complex channel characteristics of low-Earth orbit (LEO) satellite communication, making them a key technology choice for addressing challenges such as LEO link noise, fading, and terminal power limitations. Therefore, Turbo codes have been widely used in LEO satellite communication, and the design of high-throughput, low-resource-consumption Turbo decoders has received widespread attention in the industry.

[0003] While iterative decoding of Turbo codes approaches the Shannon limit, it faces three major engineering challenges, which directly led to the development of block-based decoding:

[0004] Long code decoding latency: Traditional Turbo decoding, such as Log-MAP, requires forward / backward recursion of the entire sequence. As the code length increases, the recursion chain lengthens, and the iteration latency increases sharply, which cannot meet the requirements of high-speed real-time transmission.

[0005] Storage overhead explodes: Full sequence recursion requires caching a large number of forward and backward metrics, resulting in excessive storage resource consumption under long code and a sharp increase in hardware implementation costs.

[0006] Serial iteration bottleneck: In the traditional structure, two soft-input soft-output (SISO) decoders exchange soft information serially. The increase in the number of iterations further amplifies the delay, making it difficult to improve throughput.

[0007] To address these issues, existing Turbo decoders generally employ a block-parallel decoding architecture. By increasing the number of decoders, decoding latency is reduced. The idea of ​​block decoding originated as early as the product code era. The hardware overhead of Viterbi decoding for long-constrained convolutional codes was too high. Researchers proposed state graph partitioning and modular architectures, using distributed computing to reduce hardware costs, which is the origin of the "architectural partitioning" idea in block decoding. Since the introduction of Turbo codes, their engineering implementation could not meet the needs of real-time communication scenarios, forcing the systematic development of block decoding schemes. In 1995, Hagenauer's team optimized the data block boundary state estimation and overlapping sub-block strategy. Jah-Ming Hsu and Chin-Liang Wang, in their 1998 paper "A parallel decoding scheme for turbo codes," proposed a parallel architecture of "overlapping sub-blocks + boundary state transfer."

[0008] Because the computation of forward and backward metrics follows the Markov chain property, the computation must wait for the previous value to complete before proceeding to the next. Therefore, the more clock cycles allocated to each value computation, the lower the decoder throughput. Compressing the computation clock for each value, while reducing the computation clock length and improving throughput, inevitably leads to increased critical path latency, reduced clock frequency, and almost no increase in throughput.

[0009] Patent document CN201611259880.X discloses "A Turbo Decoder and Decoding Method," which employs four-block decoding, dividing soft information into four parallel signals and using a parallel bidirectional iterative Max-Log-Map algorithm to improve the throughput and decoding latency of Turbo decoding and achieve parallel decoding of WCMDA. However, the design idea of ​​this block decoder is to divide the information data into several blocks, design the calculation of forward and backward metrics to be multi-stage to reduce path latency, and perform parallel decoding of several blocks. While increasing the clock frequency, it keeps the average number of accumulated metrics calculated per clock cycle unchanged to improve throughput. This trade-off of area for speed will lead to a multiple increase in resource consumption with the number of blocks, and there is unutilized waiting time between the calculation of adjacent metrics.

[0010] In addition, traditional Turbo code decoders rely on the interleaving length of the codeword information, and the parameters are often pre-stored in ROM due to the complexity of calculation, only to be read and used during decoding. This method also limits the decoder to compatibility with pre-stored parameters and prevents it from supporting codewords of other lengths. Summary of the Invention

[0011] The purpose of this invention is to address the shortcomings of the prior art by providing a low-power Turbo decoder and decoding method based on block and variable length, thereby reducing resource consumption, being compatible with all code length parameters under the 3GPP standard, and improving the adaptability of the Turbo decoder.

[0012] The technical approach to achieve the objective of this invention is as follows: A single SISO decoding unit (comprising a forward metric calculation module, a backward metric calculation module, an external information calculation module, and a SISO control module) is used to implement the decoding of two component decoders in a time-division manner. Each block of data to be decoded is divided into four sub-blocks, and its metric calculation and LLR calculation are controlled as a four-stage pipelined operation. The order of metric calculations is adjusted to eliminate waiting time. Parallel decoding of the four sub-blocks is achieved using a time-division method based on a single SISO decoding unit. Furthermore, by reconstructing the calculation of the interleaving sequence, a pipeline structure that is easy to implement in hardware is formed, achieving compatibility with all code length parameters of 3GPP Turbo codes. This scheme can achieve block-based parallel iterative decoding of Turbo codes based on a single SISO core decoding unit without significantly reducing decoder throughput, thereby greatly reducing decoder resource consumption while maintaining compatibility with all 3GPP Turbo code parameters.

[0013] Based on the above ideas, the technical solution of the present invention includes:

[0014] 1. A low-resource-consumption Turbo decoder based on block-based and variable-length decoding, comprising: a decoding rate matching module, a data storage module, a decoding control module, a forward metric calculation module, a backward metric calculation module, an external information calculation module, and a SISO control module, characterized in that:

[0015] It also includes an internal interleaving address calculation module, which includes two multipliers, one divider, and a ROM with a depth of (but not limited to) 8192 (the depth setting must be greater than the sum of the lengths of all basic sequences S) and a width of 8 to store the basic sequence S, a register storing the permutation pattern T, and a register storing the prime number sequence r. It is used to generate row positions and column positions according to the order of data transmission. The row positions are mapped to the original row positions through the permutation pattern. The column positions are multiplied and divided to obtain the address of the basic sequence S. The original column positions are obtained through a lookup table. The original row positions are multiplied by the total number of columns and then added to the column positions. Values ​​exceeding the information length are deleted to obtain the interleaving address.

[0016] Furthermore, the forward metric calculation module is used to calculate the forward metric value, including the branch metric gamma, through a four-level pipeline operation. The first level calculates the forward gamma, the second level calculates the sum of the forward metric value and gamma, the third level compares and selects the forward metric values, and the fourth level limits the forward metric value. At the same time, the mean of the input forward metric values ​​is calculated when performing the calculations in the first and second levels, and the mean of the forward metric values ​​is subtracted when making the selection in the third level to prevent data overflow.

[0017] Furthermore, the backward metric calculation module is used to calculate the backward metric value, including the branch metric gamma, through a four-level pipeline operation. The first level calculates the backward gamma, the second level calculates the sum of the backward metric value and gamma, the third level compares and selects the backward metric values, and the fourth level limits the backward metric value. At the same time, the mean of the input backward metric values ​​is calculated when performing the calculations in the first and second levels, and the mean of the backward metric values ​​is subtracted when making the selection in the third level to prevent data overflow.

[0018] Furthermore, the external information calculation module is used to calculate the external information and the log-likelihood ratio (LLR) required for iteration. That is, the external information calculation process is performed in a four-stage pipeline. The first three stages calculate the addition, comparison and selection of forward and backward metric values, and the fourth stage calculates the log-likelihood ratio (LLR) and external information.

[0019] Furthermore, the SISO control module includes an address control submodule and a storage submodule, which are respectively used to generate the data retrieval address for the calculated metric value and the address for storing the metric value, external information, and internal interleaving.

[0020] Furthermore, the forward metric calculation module, backward metric calculation module, external information calculation module, and SISO control module constitute a SISO decoding unit. Under the four-level pipelined operation calculation, the decoder completes the parallel decoding of the four sub-blocks of the data to be decoded by calling this single SISO decoding unit in a time-division manner.

[0021] 2. A method for decoding based on the aforementioned low-power Turbo decoder, characterized in that it includes:

[0022] (1) Calculate the parameters required for decoding and the inner interleaving address according to the 3GPP Turbo code standard and input parameters, and store them;

[0023] (2) The decoder performs rate matching on the received channel data information and stores the data;

[0024] (3) Calculate the initial values ​​of the backward metric values ​​of the two component codes based on the tail bit information in the channel data. And initialize the number of iterations to one;

[0025] (4) Iteratively decode the first component code in the Turbo code, that is, control the order of use of the information bits and the first parity bits after the rate matching is achieved by the SISO control module, and obtain the initial state of the metric value using (3). The forward and backward metric value calculation modules respectively complete the forward metric. Calculation of backward metric And the likelihood ratio information is calculated through the external information calculation module. External information Calculation;

[0026] (5) Iteratively decode the second component code in the Turbo code, that is, control the order of use of the information bits and the second parity bits after the de-rate matching through the SISO control module, and use the internal interleaving address obtained in (1) and the initial state of the metric value obtained in (3) to complete the forward metric through the forward and backward metric value calculation modules respectively. Calculation of backward metric And the likelihood ratio information is calculated through the external information calculation module. External information The calculation increments the iteration count by one;

[0027] (6) Determine if the number of iterations has reached the maximum value:

[0028] If the maximum value is reached, the likelihood ratio information LLR updated in the last iteration is retrieved from the output RAM and decoded for output.

[0029] Otherwise, return (4).

[0030] Compared with the prior art, the present invention has the following advantages:

[0031] Firstly, because the present invention contains an internal interleaving address calculation module in the decoder, it can calculate and store the internal interleaving information for any input code length parameter by calculating the original row position and the original column position of the input data in the two-dimensional interleaving matrix. This overcomes the deficiency of the present invention, which can only be compatible with a limited number of code length parameters, and makes the present invention compatible with all code length parameters under the 3GPP standard.

[0032] Secondly, by increasing the calculation process of the traditional forward and backward metric calculation module and external information calculation module to a four-stage pipeline operation, this invention reduces critical path delay and increases the upper limit of the decoder's stable operating clock frequency.

[0033] Third, this invention divides each block of data to be decoded into four sub-blocks. Based on the four-level pipelined operation of the calculation process of the forward and backward metric calculation module and the external information calculation module, the usage order of the information bit data and the first and second parity bit data is reasonably scheduled, which can eliminate the waiting time between calculating the forward and backward metric values. This allows the invention to achieve block-parallel iterative decoding of Turbo codes based on a single SISO core decoding module without reducing the decoder throughput, thereby significantly reducing the consumption of decoder hardware resources. Attached Figure Description

[0034] Figure 1 This is a structural diagram of the decoder of the present invention;

[0035] Figure 2 This is a schematic diagram of the internal interleaving address calculation module in the decoder of this invention;

[0036] Figure 3 This is a schematic diagram of the forward metric calculation module in the decoder of this invention;

[0037] Figure 4 This is a flowchart illustrating the implementation of the decoding method of this invention;

[0038] Figure 5 This is a diagram showing the order of information bit usage in the decoding method of this invention;

[0039] Figure 6 This is a simulation result diagram of the decoder of the present invention performing decoding. Detailed Implementation

[0040] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without creative effort should all fall within the protection scope of the present invention.

[0041] Example 1: Low-power Turbo decoder based on block and variable length

[0042] Reference Figure 1 This example includes: a rate matching module 1, a data storage module 2, an internal interleaving address calculation module 3, a decoding control module 4, a forward metric calculation module 5, a backward metric calculation module 6, an external information calculation module 7, and a SISO control module 8. Among them:

[0043] The rate matching module 1 includes a RAM with a depth of, but not limited to, 12000 and a width of 8. The depth of the RAM must be greater than twice the maximum code length. It is used to recover the punched bits of the input data and determine whether there are punched bits in the sequence number of the input data. If there are punched bits, it outputs 0 and stores the current input data into the RAM. If there are no punched bits, it outputs the stored data from the RAM in sequence. Its input port is the input port of the decoder.

[0044] The data storage module 2 includes two sets of storage units, each containing three RAMs. In this example, the quantization bit width is, but not limited to, 8, and the depth of each RAM is, but not limited to, 8192. The depth of the RAM must be greater than the maximum code length. It is used to store the channel data after recovering the punched bits and the data required for calculating the output metric value. The two sets of storage units are used alternately. When one set of storage units writes data, the other set of storage units reads data. Its input port is connected to the output port of the derate matching module 1.

[0045] The internal interleaving address calculation module 3, used to calculate the internal interleaving address, includes: two multipliers 31, a divider 32, a ROM memory 33 for storing the basic sequence S, a register 34 for storing the permutation pattern T, and a register 35 for storing the prime number sequence r. Figure 2 As shown.

[0046] The ROM memory 33 is used to store all basic sequences S corresponding to all code lengths within the 3GPP standard;

[0047] The preset register 34 is used to store all permutation patterns T corresponding to all code lengths within the 3GPP standard;

[0048] The preset register 35 is used to store the prime number sequence r corresponding to all code lengths in the 3GPP standard;

[0049] This internal interleaving address calculation module is used to generate row and column positions according to the order of data transmission, and obtain the original row position by mapping the row position through register 34.

[0050] The two multipliers 31 perform related multiplications of the original row position and the column position, respectively. The first multiplier multiplies the original row position in register 34 with the column number C, and the second multiplier multiplies the column position with the prime number r in register 35.

[0051] The divider 32 calculates the remainder of the result of the second multiplier divided by the prime number p-1, uses the result as an address to retrieve data from the ROM memory 33 to obtain the original column position, adds the original column position to the result of the first multiplier, and deletes values ​​that exceed the information length to obtain the interleaved address;

[0052] The decoding control module 4 includes a RAM with a depth of, but not limited to, 8192 and a width of 8. The depth of the RAM must be greater than the maximum code length. It is used to generate decoding parameters and control the input alternation storage, internal interleaving address calculation, backward metric initial value calculation, iteration number signal, decoding data storage and output. Its input port is the input port of the decoder, and its output port is the output port of the decoder and is connected to the input port of the internal interleaving address calculation module 3.

[0053] The forward metric calculation module 5 is used to calculate the forward metric value required for the log-likelihood ratio:

[0054] Reference Figure 3 The forward metric calculation module performs forward metric calculations through a four-stage pipeline operation. The first stage calculates the forward gamma, the second stage calculates the sum of the forward metric and gamma, the third stage compares and selects the forward metric, and the fourth stage limits the forward metric. Simultaneously, the mean of the input forward metric is calculated during the first and second stages of calculation, and this mean is subtracted during the selection in the third stage to prevent data overflow. Its input port is connected to the data storage module 2.

[0055] The backward metric calculation module 6 is used to calculate the backward metric required for the log-likelihood ratio through a four-stage pipeline operation. The first stage calculates the backward gamma, the second stage calculates the sum of the backward metric and gamma, the third stage compares and selects the backward metric, and the fourth stage limits the backward metric. At the same time, the mean of the input backward metric is calculated when performing the calculations in the first and second stages, and the mean of the backward metric is subtracted when making the selection in the third stage to prevent data overflow. Its input port is connected to the data storage module 2.

[0056] The external information calculation module 7 is used to calculate the external information and the log-likelihood ratio LLR required for iteration. The external information calculation process is performed in a four-stage pipeline. The first three stages calculate the addition, comparison and selection of forward and backward metric values, and the fourth stage calculates the log-likelihood ratio LLR and external information. Its input port is connected to the output port of the forward calculation module 5, the backward metric calculation module 6 and the SISO control module 8.

[0057] The SISO control module 8, whose input port is connected to the output ports of the internal interleaving calculation module 3 and the decoding control module 4, includes an address control submodule 81 and a storage submodule 82. The address control submodule 81 generates the data retrieval address for the calculated metric value. It treats the information data as four equal blocks, and every four time intervals, it serially generates addresses for retrieving the information bits and parity bits of each block in the order of the first to the fourth block. When calculating the forward metric value, it retrieves the data from the head; when calculating the backward metric value, it retrieves the data from the tail. The storage submodule 82 stores the metric value, external information, and internal interleaving address, including a forward metric value storage RAM, a backward metric value storage RAM, an external information ping-pong storage RAM, and an internal interleaving address ping-pong storage RAM. The depth of each RAM is set to 8192, which must be greater than the maximum code length. The widths are 8×13, 8×13, 10, and 13, respectively. The metric value is only stored for the first half of the time interval; for the second half, the metric value is sent to the external information calculation module to calculate the external information.

[0058] Example 2: Decoding method based on the low-power Turbo decoder described above

[0059] Reference Figure 4 The implementation steps of this example include the following:

[0060] Step 1: Calculate the parameters required for decoding and the inner interleaving address.

[0061] (1.1) Calculate the length H of the decoded information block:

[0062] The input includes parameters such as information bit length K, rate matching length, and maximum number of iterations. The decoding control module 4 generates the decoding information block length H based on the input parameters.

[0063] If the length K of the input parameter information bits is a multiple of 8, then the calculated information block length H = K.

[0064] Otherwise, H = K - mod(K, 8) + 8.

[0065] (1.2) Based on the information bit length K, the inner interleaving address calculation module 3 calculates the inner interleaving address according to the 3GPP standard:

[0066] (1.2.1) The internal interleaving calculation module 3 calculates the parameters required for interleaving based on the information bit length K, including the number of rows R of the interleaving matrix, the number of columns C of the interleaving matrix, and the prime number p.

[0067] if Then R=10, p=53, C=p;

[0068] Otherwise, first determine the number of rows R of the interleaving matrix as follows:

[0069] ;

[0070] Then select the matching criteria from the lookup table. The smallest prime number p;

[0071] Then, determine the number of columns C of the interleaving matrix based on the smallest prime number p:

[0072] ;

[0073] (1.2.2) Set the register to pre-store the permutation pattern T and the prime number sequence r, and set the ROM to store the basic sequence S;

[0074] (1.2.3) Generate the row position and column position according to the information transmission order, and obtain the original row position by mapping the row position through the permutation pattern. The column position and the prime number r are multiplied and divided by p-1 to obtain the address of the prime number sequence S. The original column position is obtained by looking up the table.

[0075] (1.2.4) Multiply the original row position by the total number of columns using a multiplier, add the original column position, delete values ​​that exceed the length K of the decoded information, and output and store the inner interleaving address.

[0076] Step 2: Restore and save the punch positions of the input data.

[0077] The punched position refers to the data location in the encoded data that was not transmitted. Recovering the punched position of the input data means assigning a value to this untransmitted data location, which includes:

[0078] (2.1) Determine if the sequence number of the input data has a punched position:

[0079] If it exists, output 0 and store the current input data in RAM;

[0080] If it does not exist, output the stored data from RAM in sequential order;

[0081] (2.2) Data storage module 2 stores the data output by solution rate matching module 1.

[0082] Step 3: Calculate the initial values ​​of the backward metric values ​​for the two component codes. And initialize the iteration count to 1.

[0083] (3.1) The decoding control module 4 inputs the tail bit information from the input data into the backward metric calculation module 6 to calculate the initial value of the backward metric of the two component codes. :

[0084] (3.1.1) Transmit the codeword vector according to time l of the first component code. Received codeword vector at time l Channel reliability measurement Calculate the branch metric at time l of the first component code. :

[0085] ;

[0086] in, s represents the state at the previous moment, and s represents the state at the current moment. ;

[0087] (3.1.2) Let According to branch metric right The backward initial value of the first component code is obtained through iterative calculation.

[0088] ,

[0089] in, For the set of encoding register states, , These are the l-times of the first component code. State backward metric, time l State backward metric.

[0090] (3.1.3) Transmit the codeword vector according to time l of the second component code. Received codeword vector at time l Channel reliability measurement Calculate the branch metric at time l of the second component code. :

[0091] ,

[0092] (3.1.4) Let According to branch metric right The backward initial value of the second component code is obtained through iterative calculation. :

[0093] ,

[0094] in, , For the set of encoding register states, , These are the l-times of the second component code. State backward metric, time l State backward metric;

[0095] (3.2) Set the initial iteration count of the decoding control module 4 to 1.

[0096] Step 4 controls the order of use of the information bits and the first parity bits after the puncture bit is recovered, and calculates the forward metric of the first component code in the 3GPP Turbo code. Backward metric Likelihood ratio information External information , in .

[0097] (4.1) The SISO control module 8 achieves precise control over the reading order of information bits and the first parity bit through segmented management of the data address and a bidirectional traversal strategy. The specific implementation is as follows:

[0098] Address Segmentation: Suppose the data address space with a decoded information block length H = 8N is divided into four consecutive address segments, namely:

[0099] Paragraph 1: ,

[0100] Paragraph 2: ,

[0101] Paragraph 3: ,

[0102] Paragraph 4: ,

[0103] Forward address generation: SISO control module 8 traverses each address segment in the order of segment 1, segment 2, segment 3, and segment 4, and generates a forward read address in each segment using an incremental method from the head to the tail, which is used for forward metric calculation.

[0104] Backward address generation: After completing the forward traversal, the SISO control module 8 traverses each address segment in the order of segment 1, segment 2, segment 3, and segment 4. However, within each segment, a backward read address is generated in a decreasing manner from the tail to the head for backward measurement calculation.

[0105] During the forward address generation and backward address generation processes, the traversal order of the four address segments remains consistent, with only the address traversal direction within each address segment being reversed. The reading order of the information bits and the first parity bit is directly controlled by the generation order of the forward and backward addresses, thereby achieving the ordered calculation of the Turbo code decoding metric.

[0106] (4.2) Forward metric calculation module 5 calculates the forward metric. The backward metric module 6 calculates the backward metric. :

[0107] (4.2.1) Transmit the codeword vector according to time l of the first component code. Received codeword vector at time l Channel reliability measurement Calculate the forward branch metric at time l of the first component code. :

[0108] ;

[0109] (4.2.2) Let the initial value of the forward metric of the first component code be... According to the forward branch metric right Perform iterative calculations up to the forward metric value at time K of the first component code. At time l+1, the first component code is obtained. State forward metric ):

[0110] ,

[0111] For time l State forward metric;

[0112] (4.2.3) Transmit the codeword vector according to time l of the first component code. Received codeword vector at time l and channel reliability measurement Calculate the backward branch metric at time l of the first component code. :

[0113]

[0114] in, ;

[0115] (4.2.4) Based on backward branching metric The initial value of the backward metric of the first component code obtained in (3.1.1) Iterative calculation up to time 0 of the first component code backward metric value At time l, the first component code is obtained. State backward metric

[0116] ,

[0117] in, For time l State backward metric;

[0118] (4.3) External information calculation module 7 calculates the forward metric value of the first component code. With backward metric Calculate the likelihood ratio information of the first component code. :

[0119] ;

[0120] in, , Let represent the set of transition states caused by bit 1 and the set of transition states caused by bit 0 at time l, respectively.

[0121] (4.4) Based on the likelihood ratio information of the first component code First component code, time l information bit data Second component code l-time out-of-time information Calculate the out-of-time information of the first component code l :

[0122] .

[0123] Step 5: Control the order of use of the information bits and the second parity bits after the puncture points are recovered, and calculate the forward metric of the second component code in the 3GPP Turbo code. Backward metric Likelihood ratio information External information And increment the iteration count by 1.

[0124] (5.1) The SISO control module 8 achieves precise control over the reading order of information bits and the second parity bit through segmented management of the data address and a bidirectional traversal strategy. The specific implementation is as follows:

[0125] Address Segmentation: Suppose the data address space with a decoded information block length H = 8N is divided into four consecutive address segments, namely:

[0126] First paragraph: ,

[0127] Second paragraph: ,

[0128] Third paragraph: ,

[0129] Fourth paragraph: ,

[0130] Forward address generation: The SISO control module iterates through each address segment in the order of the first segment, the second segment, the third segment, and the fourth segment. Within each address segment, it generates a forward read address for the second parity bit in an ascending manner from the head to the tail. The forward read address for the second parity bit is mapped through internal interleaving to obtain the forward read address for the information bit. These addresses are used to read the second parity bit and the information bit data to perform forward metric calculation.

[0131] Backward address generation: The SISO control module iterates through each address segment in the order of the first segment, the second segment, the third segment, and the fourth segment. Within each address segment, it generates a backward read address for the second parity bit in a descending manner from the tail to the head. The backward read address for the second parity bit is mapped by internal interleaving to obtain the backward read address for the information bit. These addresses are used to read the second parity bit and the information bit data to perform backward metric calculation.

[0132] (5.2) Forward metric calculation module 5 calculates the forward metric. The backward metric module 6 calculates the backward metric. ;

[0133] (5.2.1) Transmit the codeword vector according to time l of the second component code. Received codeword vector at time l Channel reliability measurement Calculate the forward branch metric at time l of the second component code. :

[0134] ,in ;

[0135] (5.2.2) Let the starting value of the forward metric of the second component code be... According to the forward branch metric right Iterative calculation up to time K of the second component code forward metric value The second component code is obtained at time l+1. State forward metric :

[0136] ,

[0137] in, For time l State forward metric;

[0138] (5.2.3) Transmit the codeword vector according to time l of the second component code. Received codeword vector at time l and channel reliability measurement Calculate the backward branch metric at time l of the second component code. :

[0139] ,in ;

[0140] (5.2.4) Based on backward branching metric The initial value of the backward metric of the second component code obtained in (3.1.2) Iterative calculation up to time 0 of the second component code backward metric value At time l, the second component code is obtained. State backward metric :

[0141] ,

[0142] in, For time l State backward metric;

[0143] (5.3) External information calculation module 7 calculates the forward metric value of the second component code. With backward metric Calculate the likelihood ratio information :

[0144] ,

[0145] in , Let represent the set of transition states caused by bit 1 and the set of transition states caused by bit 0 at time l, respectively.

[0146] (5.4) Based on the likelihood ratio information of the second component code Second component code, time l information bit data First component code l time-out information Calculate the out-of-time information of the second component code l. :

[0147] ;

[0148] (5.4) Decoding control module 4 increments the iteration count by 1.

[0149] Step 6: The decoder performs iterative decoding.

[0150] Determine if the number of iterations has reached the maximum value:

[0151] If the maximum value is reached, the likelihood ratio information LLR updated in the last iteration is retrieved from the output RAM and decoded for output.

[0152] Otherwise, return to step 4.

[0153] The effectiveness of this invention can be illustrated by the following simulation results.

[0154] 1. Simulation experimental conditions.

[0155] The software platform for the simulation experiment of this invention is Vivado 2018.3, and the selected FPGA model is xc7vx690tffg1761-2.

[0156] 2. Simulation Experiment Content

[0157] Simulation Experiment 1: Under the above conditions, the hardware resource consumption of the lookup table (LUT) and BRAM of the traditional decoder and the decoder of the present invention with a working clock of 200MHz was statistically analyzed. The results are shown in Table 1.

[0158] Table 1. Resource Consumption Comparison Table Between the Decoding Device of the Present Invention and Traditional Decoding Devices

[0159]

[0160] The statistical results in Table 1 show that, compared with traditional decoding devices, the resource consumption of the decoding device of the present invention is significantly reduced, with the overall LUT resource decreasing by 61% and the BRAM resource decreasing by 30%.

[0161] Simulation Experiment 2: Under the above conditions, a Turbo codeword with an information bit length of 168 and a maximum iteration count of 4 was selected and decoded using the decoder of this invention. The results are as follows: Figure 6 .

[0162] from Figure 6 As can be seen, at a clock frequency of 200MHz, the decoding time of this decoder is 7.12µs, and the throughput is 23Mbps, which is comparable to the throughput of traditional block decoders. This indicates that the present invention can significantly reduce the hardware resource consumption of the decoder without reducing decoding performance.

Claims

1. A low-resource-consumption Turbo decoder based on block-based and variable-length decoding, comprising: The module comprises a rate matching module, a data storage module, a decoding control module, a forward metric calculation module, a backward metric calculation module, an external information calculation module, and a SISO control module, characterized in that: It also includes an internal interleaving address calculation module, which includes two multipliers, one divider, a ROM storing the basic sequence S, a register storing the permutation pattern T, and a register storing the prime number sequence r. It is used to generate row positions and column positions according to the order of data transmission. The row positions are mapped to the original row positions through the permutation pattern. The column positions are multiplied and divided to obtain the address of the basic sequence S. The original column positions are obtained through a lookup table. The original row positions are multiplied by the total number of columns and then added to the original column positions. Values ​​exceeding the information length are deleted to obtain the interleaving address.

2. The decoder according to claim 1, characterized in that, The forward metric calculation module is used to calculate the forward metric value, including the branch metric gamma, through a four-level pipeline operation. The first level calculates the forward gamma, the second level calculates the sum of the forward metric value and gamma, the third level compares and selects the forward metric value, and the fourth level limits the forward metric value. At the same time, the mean of the input forward metric value is calculated when performing the calculations in the first and second levels, and the mean of the forward metric value is subtracted when making the selection in the third level to prevent data overflow.

3. The decoder according to claim 1, characterized in that, The backward metric calculation module is used to calculate the backward metric value, including the branch metric gamma, through a four-level pipeline operation. The first level calculates the backward gamma, the second level calculates the sum of the backward metric value and gamma, the third level compares and selects the backward metric value, and the fourth level limits the backward metric value. At the same time, the mean of the input backward metric value is calculated when performing the calculations in the first and second levels, and the mean of the backward metric value is subtracted when making the selection in the third level to prevent data overflow.

4. The decoder according to claim 1, characterized in that: The external information calculation module is used to calculate the external information required for iteration and the log-likelihood ratio (LLR), that is, the external information... The calculation process is performed in a four-stage pipeline. The first three stages calculate the sum and comparison of forward and backward metrics, and the fourth stage calculates the log-likelihood ratio (LLR) and extrinsic information. The SISO control module includes: The address control submodule is used to generate the data address for the calculated metric value. It treats the information data as four sub-blocks and generates the address for the information bit data and check bit data of each sub-block in the order of the first sub-block to the fourth sub-block every four time moments. The forward cumulative metric is taken from the head and the backward cumulative metric is taken from the tail. The storage submodule is used to store metric values, external information, and internal interleaving addresses. It includes forward metric value storage RAM, backward metric value storage RAM, external information ping-pong storage RAM, and internal interleaving address ping-pong storage RAM. Its metric values ​​only store the values ​​of the first half of the time step, and the metric values ​​are sent to the external information calculation module to calculate the external information in the second half of the time step.

5. The decoder according to claim 1, characterized in that: The forward metric calculation module, backward metric calculation module, external information calculation module, and SISO control module constitute a SISO decoding unit. Under four-level pipelined operation calculation, the decoder completes the parallel decoding of four sub-blocks of the data to be decoded by calling this single SISO decoding unit in a time-division manner.

6. A method for decoding based on a low-consumption Turbo decoder, characterized in that, include: (1) Calculate the parameters required for decoding and the inner interleaving address according to the 3GPP Turbo code standard and input parameters, and store them; (2) The decoder recovers the punched bits from the received channel data information and stores the data; (3) Calculate the initial values ​​of the backward metric values ​​of the two component codes based on the tail bit information in the channel data. And initialize the number of iterations to one; (4) Iteratively decode the first component code in the 3GPP Turbo code, that is, control the order of use of the information bits and the first check bits after the puncture bit is recovered through the SISO control module, and obtain the initial state of the measurement value using (3). The forward and backward measurement value calculation modules respectively complete the forward measurement. Calculation of backward metric And the likelihood ratio information is calculated through the external information calculation module. External information Calculation; (5) Iteratively decode the second component code in the 3GPP Turbo code, that is, control the order of use of the information bits and the second parity bits after the punctured bits are recovered through the SISO control module, and use the internal interleaving address obtained in (1) and the initial state of the metric value obtained in (3) to complete the forward metric through the forward and backward metric calculation modules respectively. Calculation of backward metric And the likelihood ratio information is calculated through the external information calculation module. External information The calculation increments the iteration count by one; (6) Determine if the number of iterations has reached the maximum value: If the maximum value is reached, the likelihood ratio information LLR updated in the last iteration is retrieved from the output RAM and decoded for output. Otherwise, return (4).

7. The method according to claim 6, characterized in that, Step (1) calculates the parameters and interleaving address required for decoding, and its implementation includes: (1a) The input includes parameters such as information bit length K, rate matching length, and maximum number of iterations. The decoding control module generates the information block length based on the input parameters. (1b) The internal interleaving calculation module calculates the required parameters based on the information bit length K, including the number of rows R, the prime number p, and the number of columns C; if Then R=10, p=53, C=p; Otherwise, first determine the number of rows R of the interleaving matrix as follows: ； Then select the matching criteria from the lookup table. The smallest prime number p; Then, determine the number of columns C of the interleaving matrix based on the smallest prime number p: ； (1c) Set the register to pre-store the permutation pattern T and the prime number sequence r, and set the ROM to store the basic sequence S; (1d) Generate the row position and column position according to the information transmission order, and obtain the original row position by mapping the row position through the permutation pattern. Obtain the address of the basic sequence S by multiplying the column position and prime number r through a multiplier and a p-1 divider, and obtain the original column position through a lookup table. (1e) Multiply the original row position by the total number of columns using a multiplier, add the original column position, delete values ​​that exceed the information length, and output and store the inner interleaving address.

8. The method according to claim 6, characterized in that, In step (3), the initial values ​​of the backward metric values ​​of the two component codes are calculated based on the tail bit information in the channel data. The formula is as follows: ； ； in, , , As a measure of channel reliability, , , , These are the transmitted codeword vector at time l, the received codeword vector at time l, and the codeword vector at time l, respectively, for the first component code. State backward metric, time l+1 State backward metric, , , , These are the transmitted codeword vector at time l, the received codeword vector at time l, and the codeword vector at time l, respectively, for the second component code. State backward metric, time l+1 State backward metric, s represents the state at the previous moment, and s represents the state at the current moment. This is the set of encoding register states.

9. The method according to claim 6, characterized in that, The order in which the information bits and the first check bits are used after the puncture is restored by the SISO control module in (4) is to control the address order used to retrieve the information bits and the first check bits. Its implementation includes: Address Segmentation: Assume the data address space of the decoded information block length H = 8N is divided into four consecutive address segments, namely segment 1 (address range...). Segment 2 (address range) Segment 3 (address range) Segment 4 (address range) ); Forward address generation: The SISO control module traverses each address segment in the order of segment 1, segment 2, segment 3, and segment 4, and generates a forward read address in each address segment in an ascending manner from the head to the tail. This address is used to read the information bits and the first parity bit data to perform forward metric calculation. Backward address generation: The SISO control module traverses each address segment in the order of segment 1, segment 2, segment 3, and segment 4, and generates a backward read address in each address segment in a descending order from the tail to the head. This address is used to read the information bits and the first parity bit data to perform backward metric calculation.

10. The method according to claim 6, characterized in that, The order in which the information bits and the second check bits are used after the puncture is restored by the SISO control module in (5) is to control the address order used to retrieve the information bits and the first check bits. Its implementation includes: Address Segmentation: Assume the data address space of the decoded information block length H = 8N is divided into four consecutive address segments, namely segment 1 (address range...). Segment 2 (address range) Segment 3 (address range) Segment 4 (address range) ); Forward address generation: The SISO control module traverses each address segment in the order of segment 1, segment 2, segment 3, and segment 4, and generates a forward read address for the second parity bit in each address segment in an ascending manner from the head to the tail. The forward read address for the second parity bit is mapped by internal interleaving to obtain the forward read address for the information bit, which is used to read the second parity bit and the information bit data to perform forward metric calculation. Backward address generation: The SISO control module traverses each address segment in the order of segment 1, segment 2, segment 3, and segment 4. Within each address segment, it generates a backward read address for the second parity bit in a descending order from the tail to the head. The backward read address for the second parity bit is mapped by internal interleaving to obtain the backward read address for the information bit. This address is used to read the second parity bit and the information bit data to perform backward metric calculation.

11. The method according to claim 9, characterized in that: During the forward address generation and backward address generation processes, the traversal order of the four address segments remains consistent, with only the address traversal direction within each address segment being reversed. The reading order of the information bits and the first parity bits is directly controlled by the generation order of the forward address and the backward address, so as to realize the ordered calculation of the Turbo code decoding metric.

12. The method according to claim 6, characterized in that, In step (4), the forward metric of the first component code in the 3GPP Turbo code is calculated. Backward metric Likelihood ratio information External information The formula is as follows: ； ； ； ； in, , , As a measure of channel reliability, , , , , , These are the transmitted codeword vector at time l, the received codeword vector at time l, and the codeword vector at time l+1, respectively, for the first component code. State forward metric, time l State forward metric, time l State backward metric, time l+1 State backward metric, , Let represent the set of transition states caused by bit 1 and the set of transition states caused by bit 0 at time l, respectively. s represents the state at the previous moment, and s represents the state at the current moment. For the set of encoding register states, This represents the information bit data at time l. This represents the external information calculated from the second component code at time l.

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