Low power system of high-speed optical module

Abstract

This invention relates to the field of optical communication technology, specifically a low-power system for a high-speed optical module. The system includes a transmitter and a receiver. The transmitter employs a driver chip with integrated equalization functions and a thin-film lithium niobate electro-optic modulation chip. The receiver uses a Retimer chip instead of a traditional Redriver. The Retimer chip performs signal reconstruction, clock data recovery, preprocessing before forward error correction, and bandwidth expansion. It incorporates an adaptive equalization algorithm to compensate for link insertion loss differences and supports protocol-transparent transmission. The system's power consumption is controlled below 15W, exhibiting strong compatibility and effectively solving the problems of insufficient receiver bandwidth and insertion loss compensation, meeting the low-power and high-reliability requirements of high-speed optical modules of 1.6Tbps and above.

Description

Technical Field

[0001] This invention relates to the field of optical communication technology, and more specifically to a low-power system for a high-speed optical module. Background Technology

[0002] With the rapid development of artificial intelligence technology, the transmission rate of optical modules has been doubling continuously. Currently, 1.6Tbps optical modules have become the mainstream demand in the market. They adopt an 8-channel design, with each channel achieving 200Gbps transmission and equipped with 106Gbaud PAM4 modulation signals. However, the increase in speed has brought serious power consumption problems. The 1.6T optical module based on a 3nm process digital signal processor consumes up to 24W, and the heat dissipation pressure is extremely high under standard OSFP packaging. At the switch side, when the panel is filled with 72 such optical modules, the total power consumption will reach 1728W, requiring extremely high airflow for air cooling. The resulting noise problem is significant, and even contact liquid cooling faces many challenges. To reduce power consumption, the industry has proposed a linear drive pluggable optical module solution, which reduces power consumption to 12W by eliminating the digital signal processor. However, the insertion loss of critical links in this solution seriously affects eye diagram quality and bit error rate indicators. Although subsequent linear receiver optical module solutions retain digital signal processor functionality at the transmitting end, the receiving end still uses the design of linearly driven pluggable optical modules, resulting in insufficient receiver performance, bandwidth that cannot meet the theoretical requirement of 75GHz, and difficulty in uniformly compensating for differences in link insertion loss between different ports. This leads to high deployment and maintenance costs and fails to meet the stable operation requirements of 1.6Tbps high-speed optical modules.

[0003] Based on the above problems, there is an urgent need for a low-power technology solution that can solve the problems of insufficient receiver bandwidth and link insertion loss compensation. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a low-power system for a high-speed optical module, comprising a transmitter and a receiver. The transmitter includes a driver chip with integrated equalization function, a thin-film lithium niobate electro-optic modulation chip, and a laser. The receiver includes a detector array, a transimpedance amplifier, and an output driver. The receiver output driver uses a Retimer chip instead of a traditional Redriver. The Retimer chip performs signal reconstruction, clock data recovery, preprocessing before forward error correction, and bandwidth expansion, increasing the equivalent bandwidth of the receiver to 75GHz and above. The Retimer chip embeds an adaptive equalization algorithm to automatically compensate for the differences in link insertion loss between different switch ports. The Retimer chip supports protocol-transparent transmission and can process and reconstruct the original signals emitted by digital signal processor optical modules and linearly driven pluggable optical modules into low bit error rate signals.

[0005] Preferably, the bandwidth of the driver chip is 90GHz to meet the signal transmission requirements corresponding to a baud rate of 106Gbaud, and the bandwidth of the thin-film lithium niobate electro-optic modulation chip is 80-110GHz to ensure the signal integrity at the transmitting end.

[0006] Further optimized, the adaptive equalization algorithm dynamically adjusts the equalization parameters by detecting link insertion loss data in real time, and can compensate for link insertion loss differences of 16dB and below.

[0007] Furthermore, the signal reconstruction function of the Retimer chip includes amplitude calibration, phase alignment, and noise suppression of the received signal to ensure that the bit error rate of the output signal meets the requirements of the optical communication system.

[0008] Further preferably, the preprocessing before forward error correction includes frame synchronization, symbol synchronization and channel estimation of the received signal, providing preprocessing support for possible subsequent forward error correction processing.

[0009] Furthermore, the system also includes an interconnection interface that does not require differentiation of signal source type, and achieves a 99.9% pass rate in compatibility tests with digital signal processor optical modules and linear drive pluggable optical modules.

[0010] Further optimized, the overall system power consumption is controlled within 15W, which is a significant power reduction compared to the traditional 1.6T digital signal processor optical module.

[0011] Furthermore, the Retimer chip's clock data recovery function supports clock extraction and data synchronization at a baud rate of 106 Gbaud, and the clock extraction accuracy meets the timing requirements of signal transmission.

[0012] In a further preferred embodiment, the combination of the detector array and transimpedance amplifier at the receiving end, in conjunction with the Retimer chip, enables signal gain adjustment and bandwidth matching of the entire link.

[0013] Furthermore, the system is suitable for optical modules in OSFP package form and can be adapted to both air cooling and contact liquid cooling heat dissipation scenarios without the need for additional adjustments to the core hardware structure.

[0014] The technical effects achieved by the above embodiments include: The core inventive technology of this invention lies in using a Retimer chip to replace the traditional Redriver for reconstructing the receiver link. Through signal reconstruction and clock data recovery, the equivalent bandwidth of the receiver is increased to over 75GHz, and an embedded adaptive equalization algorithm automatically compensates for link insertion loss differences. This technical solution effectively solves the main technical problems of insufficient receiver bandwidth and difficulty in insertion loss compensation in existing 1.6Tbps optical modules. While reducing system power consumption, it improves compatibility with different types of optical modules, ensuring the stability and reliability of high-speed data transmission. Attached Figure Description

[0015] Figure 1 This is a low-power system connection block diagram of a high-speed optical module according to this application; Figure 2 This is a diagram of the high-speed optical module signal transmission link architecture of this application; Figure 3 This is a comparison diagram of the internal structure of different schemes for the 8×200G high-speed optical module of this application. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0017] Please see Figures 1-3 The existing 1.6Tbps high-speed optical module receiver has a core bottleneck: the combined bandwidth of the transimpedance amplifier and output driver is only 56GHz, which is far lower than the 75GHz required for 106Gbaud PAM4 modulated signals. Furthermore, the link insertion loss difference between different switch ports reaches 16dB, which the existing Redriver technology cannot compensate for uniformly. At the same time, it lacks compatibility with different types of optical modules, affecting transmission stability.

[0018] Based on this, this embodiment provides a low-power system for a high-speed optical module, applicable to optical communication scenarios with speeds of 1.6Tbps and above. It includes a transmitter and a receiver. The transmitter includes a driver chip with integrated equalization function, a thin-film lithium niobate electro-optic modulation chip, and a laser. The receiver includes a detector array, a transimpedance amplifier, and an output driver. The output driver of the receiver uses a Retimer chip instead of a traditional Redriver. The Retimer chip performs signal reconstruction, clock data recovery, preprocessing before forward error correction, and bandwidth expansion, increasing the equivalent bandwidth of the receiver to 75GHz and above. The Retimer chip embeds an adaptive equalization algorithm to automatically compensate for differences in link insertion loss between different switch ports. The Retimer chip supports protocol-transparent transmission and can process and reconstruct the original signals emitted by digital signal processor optical modules and linearly driven pluggable optical modules into low bit error rate signals.

[0019] In this technical solution, the transmitting and receiving ends exchange data via a standard electrical signal interface. The transmitting end's driver chip integrates a pre-emphasis equalization circuit, which adjusts the high-frequency gain of the output signal to offset link loss. Its 90GHz bandwidth design is calculated based on the effective bandwidth requirement of the PAM4 modulated signal. The effective bandwidth of the PAM4 signal is approximately 0.7 times the baud rate, and 106Gbaud corresponds to an effective bandwidth of 75GHz. The 90GHz bandwidth provides sufficient redundancy to ensure signal integrity. The thin-film lithium niobate electro-optic modulation chip adopts a waveguide structure design with a bandwidth covering 80-110GHz, precisely matching the bandwidth characteristics of the driver chip's output signal, achieving efficient conversion from electrical to optical signals without significant distortion. The Retimer chip at the receiver is a core improved component, integrating a signal reconstruction unit, a clock data recovery unit, a pre-processing unit before forward error correction, and an adaptive equalization unit. The signal reconstruction unit uses a variable gain amplifier and phase adjustment circuit to perform amplitude calibration and phase alignment on the received distorted signal, while also incorporating a Chebyshev low-pass filter to suppress high-frequency noise. The clock data recovery unit employs a charge-pump phase-locked loop architecture, comparing the phase difference between the received signal and the local oscillator signal using a phase detector, and outputting an error signal to control the voltage-controlled oscillator to adjust the frequency, achieving accurate clock extraction at a 106 Gbaud baud rate. The pre-processing unit before forward error correction completes frame synchronization, symbol synchronization, and channel estimation, providing a foundation for subsequent error correction processing. The adaptive equalization unit dynamically adjusts the equalization coefficient by acquiring link insertion loss data in real time, compensating for insertion loss differences between different ports. The Retimer chip's protocol-transparent transmission characteristic is achieved through compatibility with the signal formats of digital signal processor optical modules and linearly driven pluggable optical modules. Regardless of the encoding method and level standard of the original signal, it is converted into a unified differential signal format after processing by the Retimer chip.

[0020] This technical solution effectively solves the problems of insufficient receiver bandwidth and insertion loss compensation, improves compatibility with different optical modules, ensures the stability of high-speed transmission, and controls system power consumption to meet the low power consumption requirements of optical communication equipment.

[0021] The existing 1.6Tbps optical module's transmitting end driver chip and electro-optic modulation chip have insufficient bandwidth compatibility, which can easily lead to signal distortion during conversion and transmission, affecting the integrity of the transmitting end signal.

[0022] Based on this, the bandwidth of the driver chip is 90GHz, which meets the signal transmission requirements corresponding to a baud rate of 106Gbaud, and the bandwidth of the thin-film lithium niobate electro-optic modulation chip is 80-110GHz, ensuring the integrity of the signal at the transmitting end.

[0023] In this technical solution, the driver chip uses a SiGe process and integrates a four-stage amplifier circuit and a two-stage pre-emphasis circuit. The four-stage amplifier circuit achieves step-by-step gain enhancement of the signal, while the two-stage pre-emphasis circuit provides additional gain compensation for high-frequency signals, ensuring that the high-frequency components of the output signal are not attenuated by link losses. Its 90GHz 3dB bandwidth is achieved by optimizing the gate length and bias voltage of the transistor. The gate length is controlled at 40nm, and the bias voltage is set at 1.5V, controlling static power consumption while ensuring bandwidth. The thin-film lithium niobate electro-optic modulation chip uses an X-cut lithium niobate substrate and is designed based on a Mach-Zehnder interferometer structure. By applying voltage to change the refractive index of the lithium niobate waveguide, amplitude modulation of the input electrical signal is achieved. Its bandwidth range of 80-110GHz is obtained by optimizing the width and length of the waveguide. The driver chip and the thin-film lithium niobate electro-optic modulator chip are connected via a microstrip line. The characteristic impedance of the microstrip line is matched to 65Ω to reduce signal reflection loss at the interface. The swing of the output signal of the driver chip is set to 4Vpp, which is precisely matched with the input sensitivity of the electro-optic modulator chip to ensure efficient conversion of electrical signals to optical signals. The entire transmission link does not require additional processing by a digital signal processor to output a high-quality optical signal that meets the 106Gbaud baud rate requirement.

[0024] This technical solution enables precise bandwidth matching between transmitting chips, suppresses signal distortion, ensures the quality of transmitting signals, and lays the foundation for high-speed data transmission.

[0025] The existing 1.6Tbps optical module receiver lacks accuracy and automation in link insertion loss difference compensation. The insertion loss difference between different switch ports can reach 16dB, and manual on-site parameter scanning leads to complex deployment and high maintenance costs.

[0026] Based on this, the adaptive equalization algorithm dynamically adjusts the equalization parameters by detecting link insertion loss data in real time, and can compensate for link insertion loss differences of 16dB and below.

[0027] In this technical solution, the adaptive equalization algorithm is integrated into the adaptive equalization unit of the Retimer chip. The chip's internal signal detection module collects link insertion loss data in real time, maintaining a sampling frequency consistent with the signal transmission rate—one insertion loss data acquisition is completed for every symbol transmitted, ensuring real-time data accuracy. Insertion loss data detection is achieved by measuring the difference between the received signal amplitude and a preset standard amplitude. The preset standard amplitude is calibrated based on the signal amplitude under lossless link conditions. When the detected insertion loss data exceeds the normal range, the algorithm automatically initiates a parameter adjustment process. The algorithm internally stores a mapping table between insertion loss values ​​and equalization coefficients. This mapping table, established using extensive link test data, covers the optimal equalization coefficients corresponding to different insertion loss values ​​within the 0-16dB range. When a specific insertion loss value is detected, the algorithm quickly looks up the mapping table and calls the corresponding equalization coefficient, adjusting the gain and bandwidth characteristics of the equalizer within the Retimer chip.

[0028] The equalizer employs an infinite impulse response filter architecture, with coefficient adjustment achieved through a digital control module. The adjustment response time is less than 10ns, ensuring rapid compensation during signal transmission. The 16dB insertion loss difference coverage is determined based on actual insertion loss test results of existing mainstream switch ports, covering over 99% of application scenarios. It achieves precise compensation for different insertion loss links without manual intervention, truly enabling plug-and-play functionality for optical modules.

[0029] This technical solution enables automatic and accurate compensation for link insertion loss differences, eliminating the need for manual debugging, reducing deployment and maintenance costs, and ensuring consistent signal transmission quality across different ports.

[0030] The signal reconstruction function of existing retimer chips lacks specific implementation details, resulting in the amplitude, phase and noise indicators of the reconstructed signal failing to meet the transmission requirements of high-speed optical modules, thus affecting the overall communication quality.

[0031] Based on this, the signal reconstruction function of the Retimer chip includes amplitude calibration, phase alignment and noise suppression of the received signal to ensure that the bit error rate of the output signal meets the requirements of the optical communication system.

[0032] In this technical solution, the amplitude calibration function is implemented through a variable gain amplifier inside the Retimer chip. The gain adjustment range of the variable gain amplifier is 0-20dB with a step size of 0.1dB. By detecting the difference between the peak amplitude of the received signal and the preset target amplitude, the amplifier gain is automatically adjusted to stabilize the output signal amplitude within the preset range. The preset target amplitude is set to 500mVpp based on the input sensitivity of the host receiving interface. The phase alignment function is implemented collaboratively by a phase detector and a phase adjustment circuit. The phase detector adopts a double-balanced mixer architecture, compares the phase difference between the received signal and the reference clock signal output by the clock data recovery unit, and outputs the corresponding error voltage. The phase adjustment circuit adjusts the signal transmission delay according to the error voltage to keep the phase of the received signal consistent with the reference clock signal, with a phase adjustment accuracy of up to 1ps. The noise suppression function is implemented through a two-stage filtering circuit. The first stage is an RC low-pass filter with a cutoff frequency set to 120GHz to filter high-frequency noise. The second stage is an adaptive noise canceller, which collects noise signals in the link and generates a canceller signal with the same amplitude but opposite phase as the noise, which is superimposed on the received signal to achieve noise suppression. The bit error rate (BER) of the reconstructed signal must meet the requirements of the optical communication system, i.e., the BER must be lower than 2e-4. This indicator is verified through testing under different link conditions to ensure communication reliability in high-speed transmission scenarios.

[0033] This technical solution clarifies the specific implementation method of signal reconstruction, effectively calibrates signal amplitude, aligns phase, suppresses noise, ensures a low bit error rate of the output signal, and improves the communication quality of high-speed optical modules.

[0034] The specific steps of the existing forward error correction preprocessing function are unclear, resulting in poor efficiency and effectiveness of subsequent forward error correction processing, and failing to effectively compensate for errors in link transmission.

[0035] Based on this, the preprocessing before forward error correction includes frame synchronization, symbol synchronization and channel estimation of the received signal, providing preprocessing support for possible subsequent forward error correction processing.

[0036] In this technical solution, frame synchronization is achieved by detecting the frame synchronization code in the received signal. The frame synchronization code uses an 8-bit fixed sequence 10101010. The frame synchronization module searches for this synchronization sequence in the received signal using a sliding window detection method. When three identical synchronization sequences are detected consecutively, the start position of the data frame is determined, and the end position of the data frame is marked. The frame length is set to 1024 bytes to ensure that data is processed frame by frame. Symbol synchronization is implemented based on a timing recovery algorithm. By extracting the zero-crossing information of the received signal, the phase and frequency of the sampling clock are adjusted so that the rising edge of the sampling clock is precisely aligned with the optimal sampling point of the symbol. The sampling clock frequency is set to 106 GHz to match the baud rate of 106 Gbaud. The accuracy of symbol synchronization is controlled within 5% of the symbol period to avoid inter-symbol interference. The channel estimation function is achieved by analyzing the pilot symbols in the received signal. The amplitude and phase of the pilot symbols are known. The channel estimation module calculates the channel response parameters by comparing the transmitted and received values ​​of the pilot symbols and using the least squares estimation algorithm. The channel response parameters include amplitude attenuation and phase offset. These parameters are transmitted to the subsequent forward error correction module to adjust the parameters of the error correction algorithm and improve the error correction effect.

[0037] This technical solution refines the specific steps of preprocessing before forward error correction, providing accurate frame structure, synchronous sampling, and channel information for subsequent error correction processing, thereby improving error correction efficiency and accuracy and ensuring the reliability of data transmission.

[0038] The existing high-speed optical module interconnection interface lacks compatibility with different types of optical modules. The signal formats emitted by digital signal processor optical modules and linearly driven pluggable optical modules are different, which makes interconnection difficult and increases the complexity of system integration.

[0039] Based on this, the system also includes an interconnection interface, which does not need to distinguish between signal source types, and the compatibility test pass rate with digital signal processor optical modules and linear drive pluggable optical modules reaches 99.9%.

[0040] In this technical solution, the optical module interconnect interface supports differential signal transmission. The physical layer design of the interface conforms to the OSFP package specification requirements. The pin definitions include data positive and negative terminals, clock positive and negative terminals, and power supply pins. The differential impedance matching of the data pins is 100Ω to ensure the integrity of signal transmission. The host receiving interface adopts a unified standard signal format. The differential signal swing is set to 500mVpp, and the timing parameters, including setup time and hold time, are set to 10ps and 5ps, respectively. Regardless of the original signal format emitted by the digital signal processor optical module or the linear drive pluggable optical module, it is converted to the unified standard signal format after reconstruction by the Retimer chip. The compatibility test pass rate of 99.9% is based on testing 1000 sets of digital signal processor optical modules and linear drive pluggable optical modules of different brands and batches. The test items include signal transmission rate, bit error rate, and interface stability. Only one test set experienced a brief signal interruption, meeting the system integration compatibility requirements.

[0041] This technical solution achieves high compatibility between the host receiving interface and different types of optical modules, reduces system integration complexity, and improves the versatility and applicability of optical modules.

[0042] The existing 1.6Tbps digital signal processor optical module has a power consumption of up to 24W, which leads to high heat dissipation pressure and prominent noise problems, and does not conform to the design trend of green energy saving.

[0043] Based on this, the overall power consumption of the system is controlled within 15W, which is a significant reduction in power consumption compared to the traditional 1.6T digital signal processor optical module.

[0044] In this technical solution, power consumption control is achieved through both hardware selection and circuit design optimization. The core component, the Retimer chip, uses a 3nm CMOS process, which is characterized by low power consumption. The typical power consumption of the chip is only 7W, far lower than the 17W or more power consumption of digital signal processors. The driver chip at the transmitting end adopts a low-power design, with static power consumption controlled at 1W and dynamic power consumption adjusted according to the signal transmission rate. At a baud rate of 106Gbaud, the dynamic power consumption is 2.2W. The thin-film lithium niobate electro-optic modulation chip consumes 1W, achieving low-power operation through optimization of driving voltage and operating current. The transimpedance amplifier at the receiving end uses a low-noise, low-power SiGe process, with a power consumption of 0.9W. The system's power management module employs dynamic voltage regulation technology, adjusting the supply voltage according to different operating scenarios. In high-speed transmission scenarios, the supply voltage is 1.8V, while in standby scenarios, the supply voltage drops to 1.2V, further reducing static power consumption. In addition, the circuit layout adopts a low-power wiring strategy to reduce the length and intersection of signal lines and reduce power loss during signal transmission. Through the above design, the power consumption of the entire system is stably controlled within 15W, meeting the low power consumption requirements.

[0045] This technical solution significantly reduces the power consumption of high-speed optical modules, alleviates the heat dissipation pressure on equipment, reduces noise generation, conforms to the trend of green energy saving, and improves the operational stability of equipment.

[0046] In this technical solution, the clock data recovery function consists of a phase-locked loop (PLL) circuit and a data synchronization module. The PLL circuit adopts a charge pump architecture, including a phase detector, a charge pump, a low-pass filter, and a voltage-controlled oscillator (VCO). The phase detector uses a dual-edge triggering design, enabling simultaneous detection of the rising and falling edges of the signal, improving phase detection accuracy. Its operating frequency range covers 90-110 GHz, adapting to signal transmission at a baud rate of 106 Gbaud. The charge pump's current source uses a mirrored current source design, with output current accuracy controlled within ±5%. The charging and discharging speed of the low-pass filter is controlled by adjusting the output current of the charge pump. The low-pass filter uses an RC active filter architecture with a cutoff frequency set to 1 MHz, effectively filtering high-frequency noise from the phase detector output and stabilizing the control voltage of the VCO. The VCO uses a ring oscillator architecture, consisting of 5 stages of inverters. The oscillation frequency changes linearly with the control voltage, with a voltage control range of 0.8-2.0V, corresponding to an oscillation frequency of 90-110 GHz. At a baud rate of 106 Gbaud, the oscillation frequency is locked at 106 GHz. The data synchronization module aligns the recovered clock signal with the received data, ensuring that each data symbol is accurately sampled on the rising edge of the clock. The clock extraction accuracy reaches a phase error of less than 5ps, meeting the timing requirements of signal transmission and ensuring the accuracy of data synchronization.

[0047] This technical solution achieves precise clock extraction and data synchronization at a baud rate of 106 Gbaud, ensuring the timing accuracy of signal transmission and improving the communication quality of high-speed optical modules.

[0048] The existing transimpedance amplifier and output driver combination at the receiver has insufficient bandwidth, and the gain and bandwidth matching between the two and the Retimer chip is poor, resulting in poor signal transmission quality throughout the receiver link.

[0049] Based on this, the combination of the transimpedance amplifier and detector array at the receiving end, with the cooperation of the Retimer chip, enables signal gain adjustment and bandwidth matching of the entire link.

[0050] In this technical solution, the transimpedance amplifier adopts a common-emitter-common-base amplification architecture, which can convert the weak current signal output by the photodetector into a voltage signal. Its transimpedance gain is set to 50dBΩ, and its bandwidth is 56GHz. This is achieved by optimizing the transistor's load resistance and bias current. The load resistance uses a high-resistance polysilicon resistor with a resistance of 1kΩ, and the bias current is set to 1mA, ensuring both gain and bandwidth. The output driver adopts a push-pull architecture, consisting of two complementary MOS transistors. The signal processed by the Retimer chip is amplified to the amplitude required by the host receiving interface. Its output swing can be adjusted between 400-800mVpp, and the bandwidth is increased to 75GHz. The input of the Retimer chip oversamples the analog signal output by the transimpedance amplifier through a high-precision clock recovery module (CDR) to generate a digitized instantaneous value sequence of the original signal. The phase-locked loop (PLL) synchronizes the clock edge of the original signal and extracts a low-jitter reference clock (RefCLK) to provide a reference for subsequent reconstruction. The reconstruction module, based on an adaptive finite impulse response (FIR) filter, performs feedforward equalization (FFE) and decision feedback equalization (DFE) on the sampled signal to eliminate high-frequency attenuation and inter-symbol interference. Simultaneously, it dynamically adjusts the filter coefficients to adapt to signal distortion under different channel conditions (such as temperature and impedance variations). The reconstructed signal is processed by a clock domain conversion module (CDC) and a multi-phase delay-locked loop (MMDLL) to realign the signal to the precise clock cycle of RefCLK. This process eliminates clock skew and jitter by adjusting the delay units of the signal transmission path bit by bit, ensuring that the setup time and hold time of the output signal meet system specifications. The Retimer chip supports a configurable protocol mapping engine to adapt the reconstructed signal to the target interface standard (such as PCIe, SerDes, or optical module interfaces). Asynchronous conversion between the input / output clock domains is achieved through a rate matching buffer while maintaining signal integrity.

[0051] This technical solution achieves reasonable gain allocation and precise bandwidth matching in the receiving link, improving the signal transmission quality of the entire receiving link and ensuring the reliability of high-speed data transmission.

[0052] Existing high-speed optical modules require adjustments to their core hardware structure for different heat dissipation scenarios, resulting in poor adaptability and failing to meet the needs of the two mainstream heat dissipation scenarios under OSFP packaging: air cooling and contact liquid cooling.

[0053] Based on this, the system is suitable for optical modules in OSFP package form and can be adapted to both air cooling and contact liquid cooling heat dissipation scenarios without additional adjustments to the core hardware structure.

[0054] In this technical solution, the system adopts a standard OSFP package with dimensions of 14.5mm × 22.6mm × 149.7mm, conforming to the packaging specifications of the optical module industry. The package shell is made of zinc-aluminum alloy, which has good thermal conductivity. The layout of core components fully considers heat dissipation paths. High-power components such as the retimer chip, driver chip, and transimpedance amplifier are concentrated in the central area of ​​the package. A thermal pad with a thermal conductivity of 12W / (m·K) is placed between this area and the package shell, which can quickly conduct the heat generated by the components to the shell. For air-cooling scenarios, ventilation slots are designed on both sides of the OSFP package. The width of the ventilation slots is 1.8mm and the spacing is 0.3mm, which facilitates air circulation and removes heat from the shell surface. Under air-cooling conditions with a wind speed of 5m / s, the maximum temperature inside the package can be controlled below 70℃. For contact liquid cooling scenarios, the bottom of the package is designed as a flat, heat-conducting surface with a surface roughness of less than 0.8μm, facilitating a tight fit with the cooling plate of the liquid cooling device. The coolant flow rate within the cooling plate is 1L / min, efficiently absorbing the heat transferred by the package. Under liquid cooling conditions, the maximum internal temperature of the package can be controlled below 50℃. The core hardware structure adopts a modular design, and the selection of components takes into account high-temperature resistance. The operating temperature range covers -40℃ to 105℃, allowing for adaptation to both heat dissipation scenarios without additional adjustments to the layout and connection relationships of the core hardware.

[0055] This technical solution enables OSFP-packaged optical modules to adapt to both air-cooled and contact liquid-cooled scenarios without adjusting the core hardware structure, thereby improving the versatility and environmental adaptability of the optical modules and reducing equipment deployment costs.

[0056] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A low-power system for a high-speed optical module, comprising a transmitter and a receiver, wherein the transmitter includes a driver chip with integrated equalization function, a thin-film lithium niobate electro-optic modulation chip, and a laser, and the receiver includes a detector array, a transimpedance amplifier, and an output driver, characterized in that, The output driver at the receiver uses a Retimer chip instead of a traditional Redriver. The Retimer chip performs signal reconstruction, clock data recovery, preprocessing before forward error correction, and bandwidth expansion, increasing the equivalent bandwidth of the receiver to 75GHz and above. The Retimer chip has an embedded adaptive equalization algorithm that automatically compensates for the differences in link insertion loss between different switch ports. The Retimer chip supports protocol-transparent transmission and can process the raw signals emitted by the digital signal processor optical module and the linearly driven pluggable optical module and reconstruct them into low bit error rate signals.

2. The low-power system of the high-speed optical module according to claim 1, characterized in that, The driver chip has a bandwidth of 90GHz, which meets the signal transmission requirements corresponding to a baud rate of 106Gbaud. The thin-film lithium niobate electro-optic modulation chip has a bandwidth of 80-110GHz, ensuring the integrity of the transmitting signal.

3. The low-power system of the high-speed optical module according to claim 1, characterized in that, The adaptive equalization algorithm dynamically adjusts the equalization parameters by detecting link insertion loss data in real time, and can compensate for link insertion loss differences of 16dB and below.

4. The low-power system of the high-speed optical module according to claim 1, characterized in that, The signal reconstruction function of the retimer chip includes amplitude calibration, phase alignment, and noise suppression of the received signal to ensure that the bit error rate of the output signal meets the requirements of the optical communication system.

5. The low-power system of the high-speed optical module according to claim 1, characterized in that, Preprocessing before forward error correction includes frame synchronization, symbol synchronization, and channel estimation of the received signal, providing preprocessing support for possible subsequent forward error correction processing.

6. The low-power system of the high-speed optical module according to claim 1, characterized in that, The system also includes an interconnect interface that does not require differentiation of signal source type, and the compatibility test pass rate with digital signal processor optical modules and linear drive pluggable optical modules reaches 99.9%.

7. The low-power system of the high-speed optical module according to claim 1, characterized in that, The overall power consumption of the system is controlled within 15W, which is a significant reduction in power consumption compared to the traditional 1.6T digital signal processor optical module.

8. The low-power system of the high-speed optical module according to claim 1, characterized in that, The Retimer chip's clock data recovery function supports clock extraction and data synchronization at a baud rate of 106 Gbaud, and the clock extraction accuracy meets the timing requirements of signal transmission.

9. The low-power system of the high-speed optical module according to claim 1, characterized in that, The combination of the transimpedance amplifier and detector array at the receiving end, in conjunction with the Retimer chip, enables signal gain adjustment and bandwidth matching of the entire link.

10. The low-power system of the high-speed optical module according to claim 1, characterized in that, The system is suitable for optical modules in OSFP package and can be adapted to both air cooling and contact liquid cooling scenarios without the need for additional adjustments to the core hardware structure.

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