Data check code generation method, central processing unit, computer device and medium
By dividing the data into two parts, which are processed separately by the CRC calculation component and the cryptographic extension component, and generating and merging the check codes, the resource waste and speed limitation caused by processing by a single component are solved, and faster check code generation is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PHYTIUM TECH CO LTD
- Filing Date
- 2026-02-27
- Publication Date
- 2026-06-02
AI Technical Summary
In existing technologies, a single component is used to process data and generate cyclic redundancy check codes, which fails to fully utilize the performance of the central processing unit, resulting in wasted resources and limited check code generation speed.
The target data is divided into first data and second data by a loading storage unit, and processed by the CRC calculation component and the cryptographic extension component respectively to generate the first check code and the second check code, and then merged to generate the target check code.
By making full use of the central processing unit's resources, the speed of checksum generation is improved, the verification efficiency during data transmission is increased, and the requirement for rapid data verification is met.
Smart Images
Figure CN122137533A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing technology, and more specifically, to a data check code generation method, a central processing unit, a computer device, and a medium. Background Technology
[0002] Data communication transmission mainly refers to the process of securely and accurately transmitting data from the sending end to the receiving end through a transmission medium (such as network cable or optical fiber) according to an agreed protocol. Data communication plays an important role in network communication, storage devices, file transfer, and other fields. Cyclic redundancy check (CRC) is one of the most commonly used error detection techniques in data communication.
[0003] In related technologies, data is acquired and processed sequentially by a single component in the central processing unit to generate a cyclic redundancy check code.
[0004] However, in related technologies, using a single component to process data cannot fully utilize the performance of the central processing unit, resulting in a waste of central processing unit resources and limiting the generation speed of cyclic redundancy check codes. Summary of the Invention
[0005] The purpose of this application is to address the shortcomings of the prior art by providing a data verification code generation method, a central processing unit, a computer device, and a medium, so as to solve the aforementioned technical problems existing in the related art.
[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a data checksum generation method applied to a central processing unit (CPU), the CPU comprising: a loading storage unit, a cyclic redundancy check (CRC) calculation component, and a cryptographic extension component; the method comprising: The target data is obtained using the loading storage unit, and the target data is the data to be used to generate a verification code. The loading storage unit uses the data processing capabilities of the CRC calculation component and the cryptographic extension component to divide the target data into first data and second data. The first data and the second data are processed using the CRC calculation component and the cryptographic extension component respectively to obtain the first check code and the second check code; The first check code and the second check code are merged using the CRC calculation component and the cryptographic extension component to obtain the target check code corresponding to the target data.
[0007] Optionally, dividing the target data into first data and second data based on the data processing capabilities of the CRC calculation component and the cryptographic extension component includes: Based on the instruction runtime of the CRC calculation component and the cryptographic extension component, the target data is divided into initial first data and initial second data. Based on the amount of data processed in a single operation by the CRC calculation component and the cryptographic extension component, the initial first data and the initial second data are adjusted to obtain the first data and the second data.
[0008] Optionally, dividing the target data into initial first data and initial second data based on the instruction runtime of the CRC calculation component and the cryptographic extension component includes: The first clock cycle required by the CRC calculation component is determined based on the first number of required instructions of the CRC calculation component. The second clock cycle required by the cryptographic extension component is determined based on the second number of demand instructions for the cryptographic extension component; wherein, the first number of demand instructions and the second number of demand instructions are respectively the number of running instructions required by the CRC calculation component and the cryptographic extension component to process the same amount of data; The division ratio is determined based on the first clock cycle and the second clock cycle; According to the division ratio, the target data is divided into the initial first data and the initial second data.
[0009] Optionally, the step of using the CRC calculation component and the cryptographic extension component to process the first data and the second data respectively to obtain the first check code and the second check code includes: The first data is processed using the CRC instructions in the CRC calculation component to obtain the first checksum; and the second data is processed using the cryptographic instructions in the cryptographic extension component to obtain the second checksum.
[0010] Optionally, processing the second data using cryptographic instructions from the cryptographic extension component to obtain the second verification code includes: The second data is divided into a first sub-data and a second sub-data; The first sub-data and the second sub-data are processed using cryptographic instructions in the cryptographic extension component to obtain the second verification code.
[0011] Optionally, the step of using cryptographic instructions from the cryptographic extension component to process the first sub-data and the second sub-data respectively to obtain the second verification code includes: The first sub-data and the second sub-data are processed by using the polynomial multiplication instruction and the triple XOR instruction in the cryptographic extension component to obtain the third check code and the fourth check code. The third check code and the fourth check code are merged to obtain the second check code.
[0012] Optionally, the step of processing the first data using CRC instructions in the CRC calculation component to obtain the first checksum; and processing the second data using cryptographic instructions in the cryptographic extension component to obtain the second checksum, includes: Based on the delay of the CRC instruction in the CRC calculation component and the delay of the cryptographic instruction in the cryptographic extension component, the CRC instruction in the CRC calculation component and the cryptographic instruction in the cryptographic extension component are cross-arranged to obtain the cross-arranged instruction; The first data is processed using the CRC instruction in the cross-arranged instructions to obtain the first check code; and the second data is processed using the cryptographic instructions in the cross-arranged instructions to obtain the second check code. In the cross-arranged instructions, CRC instructions and cryptographic instructions run in parallel.
[0013] Secondly, embodiments of this application also provide a central processing unit, including: a loading storage unit, a cyclic redundancy check (CRC) calculation component, and a cryptographic extension component; the loading storage unit is connected to the CRC calculation component and the cryptographic extension component respectively; The loading storage unit is used to perform the steps performed by the loading storage unit in any of the methods described in the first aspect above; the CRC calculation component is used to perform the steps performed by the CRC calculation component in any of the methods described in the first aspect above; the cryptographic extension component is used to perform the steps performed by the cryptographic extension component in any of the methods described in the first aspect above.
[0014] Thirdly, embodiments of this application also provide a computer device, which includes at least the central processing unit described in the second aspect above.
[0015] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when read and executed, implements the method described in any of the first aspects above.
[0016] The beneficial effects of this application are as follows: This application provides a data checksum generation method, which includes: acquiring target data using a loading storage unit, the target data being the data for which a checksum is to be generated; dividing the target data into first data and second data using the loading storage unit based on the data processing capabilities of a CRC calculation component and a cryptographic extension component; processing the first data and the second data respectively using the CRC calculation component and the cryptographic extension component to obtain a first checksum and a second checksum; and merging the first checksum and the second checksum using the CRC calculation component and the cryptographic extension component to obtain the target checksum corresponding to the target data. Dividing the target data and processing the first and second data using the CRC calculation component and the cryptographic extension component respectively fully utilizes the performance of the central processing unit (CPU), avoids wasting CPU resources, and improves the speed of target checksum generation. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A schematic diagram of the system framework on which the data verification code generation method provided in this application is based; Figure 2 A flowchart illustrating a data verification code generation method provided in this application embodiment. Figure 1 ; Figure 3 This is a schematic diagram illustrating data transmission between computers, provided as an embodiment of this application. Figure 4 A flowchart illustrating a data verification code generation method provided in this application embodiment. Figure 2 ; Figure 5 A flowchart illustrating a data verification code generation method provided in this application embodiment. Figure 3 ; Figure 6 This application provides a schematic diagram of a data segmentation processing framework. Figure 7 A flowchart illustrating a data verification code generation method provided in this application embodiment. Figure 4 ; Figure 8 This application provides a schematic diagram of the instruction processing method in a CRC calculation component and a cryptographic extension component according to an embodiment of the present application. Figure 9 A flowchart illustrating a data verification code generation method provided in this application embodiment. Figure 5 ; Figure 10 A flowchart illustrating a data verification code generation method provided in this application embodiment. Figure 6 ; Figure 11 A schematic diagram illustrating a related technology and a comparison process for generating a checksum in this application, provided for an embodiment of this application; Figure 12 This is a schematic diagram of the structure of a data verification code generation device provided in an embodiment of this application; Figure 13 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.
[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0021] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0022] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0023] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.
[0024] Figure 1 A schematic diagram of the system framework upon which the data verification code generation method of this application is based is provided, as shown below. Figure 1 As shown, the system framework includes at least two computers. The following explanation uses two computers as an example. One computer is the data sender, and the other computer is the data receiver. The two computers are connected through a computer network, which can be any network that can connect two computers, such as a local area network or a wide area network.
[0025] like Figure 1 As shown, a computer includes an operating system, which is the most basic system software that controls and manages the hardware and software resources of the entire computer system. A computer also includes a hardware platform, which is the computer hardware system that includes computing resources, network resources, and storage resources. For example... Figure 1 As shown, the hardware platform may include multiple CPUs (Central Processing Units), memory, disks, network interface cards, and other components. The CPU includes: a Load-Store Unit (LSU), a CRC (Cyclic Redundancy Check) calculation component, and cryptographic extensions (CRYPTO), etc.
[0026] The CPU executes program instructions stored in memory. It can retrieve and write target data from memory by loading storage units, and process the target data using CRC calculation components and cryptographic extension components to calculate the target checksum. It can also verify whether errors occurred during transmission based on the received target data and checksum. Memory, also known as a storage module, is used to store encoded programs, data to be transmitted, and checksums. It can be a cache, DRAM (Dynamic Random Access Memory), or non-volatile memory such as an SSD (Solid State Drive). The network interface card (NIC), also known as a network communication module, enables data transmission between the central processing units (CPUs) of one computer and the CPUs of another computer.
[0027] by Figure 1 Taking the illustrated application scenario as an example, the computer (data sender) processes the data to be sent. The CPU uses an LSU to read the target data from memory and divides the read target data into two parts. One part of the data is processed by the CRC calculation component to generate the first data, and the other part of the data is processed by the cryptographic extension component to generate the second data. Then, the CPU processes the generated first and second data to generate the target checksum and writes the target checksum back into memory. Afterward, the computer (data sender) sends the target data and target checksum to another computer (data receiver) through a computer network. The computer (data receiver) processes the received target data in a similar manner and generates a new target checksum. By comparing the received target checksum with the new target checksum, it determines whether an error occurred during the transmission of the target data.
[0028] This application provides a data checksum generation method, applied to a central processing unit (CPU). The CPU includes a loading memory unit, a CRC calculation component, and a cryptographic extension component. The following explains the data checksum generation method provided by this application.
[0029] Figure 2 A flowchart illustrating a data verification code generation method provided in this application embodiment. Figure 1 ,like Figure 2 As shown, the method includes: S101. Obtain the target data by loading the storage unit.
[0030] The target data is the data for which a verification code is to be generated.
[0031] In some implementations, a load storage unit is used to read the target data from memory. After reading the target data, a prefetch operation is added. Specifically, the load storage unit reads a preset number of bytes of target data from memory each time; for example, the preset number of bytes could be 1024 bytes.
[0032] S102. Using the data processing capabilities of the CRC calculation component and the cryptographic extension component, the loading storage unit divides the target data into first data and second data.
[0033] The first data is the data to be processed by the CRC calculation component, and the second data is the data to be processed by the cryptographic extension component.
[0034] In practical applications, it is confirmed whether the central processing units of both the computer (data sender) and the computer (data receiver) have CRC calculation components and cryptographic extension components. After confirming that CRC calculation components and cryptographic extension components are present, the process described in S102 is executed.
[0035] It should be noted that the data processing capabilities of the CRC calculation component and the cryptographic extension component are used to characterize their data processing speeds. Specifically, when partitioning the target data, components with faster processing speeds can be partitioned with more data, while components with slower processing speeds can be partitioned with less data. This ensures that the processing times of the CRC calculation component and the cryptographic extension component are roughly the same, thereby improving processing efficiency.
[0036] S103. Using a CRC calculation component and a cryptographic extension component, the first data and the second data are processed respectively to obtain the first check code and the second check code.
[0037] In some implementations, a CRC calculation component is used to process the first data to obtain a first checksum; and a cryptographic extension component is used to process the second data to obtain a second checksum. The CRC calculation component and the cryptographic extension component can be performed simultaneously to improve processing speed.
[0038] S104. Using a CRC calculation component and a cryptographic extension component, the first check code and the second check code are merged to obtain the target check code corresponding to the target data.
[0039] The method employs a CRC calculation component and a cryptographic extension component to calculate the first and second check codes respectively, and then combines the first and second check codes to obtain the target check code corresponding to the target data, significantly improving the calculation efficiency of the target check code. The target check code is a Redundant Cyclic Check Sequence (CRC) code.
[0040] Figure 3 This is a schematic diagram illustrating data transmission between computers, provided as an embodiment of this application. Figure 3 As shown, in some implementations, a computer (data sender) sends target data and a target checksum to a computer (data receiver) via a computer network; the computer (data receiver) receives the target data and target checksum sent by the computer (data sender), and uses the received target data to generate a new target checksum using a similar processing procedure. By comparing the generated new target checksum with the received target checksum, it is determined whether an error occurred during the transmission of the target data.
[0041] In practical applications, either the computer (data sending end) or the central processing unit in the computer (data sending end) can execute the above processes S101 to S104.
[0042] In summary, this application provides a data checksum generation method, which includes: acquiring target data using a loading storage unit, the target data being the data for which a checksum is to be generated; dividing the target data into first data and second data using the loading storage unit based on the data processing capabilities of a CRC calculation component and a cryptographic extension component; processing the first data and the second data respectively using the CRC calculation component and the cryptographic extension component to obtain a first checksum and a second checksum; and merging the first checksum and the second checksum using the CRC calculation component and the cryptographic extension component to obtain the target checksum corresponding to the target data. Dividing the target data and processing the first and second data using the CRC calculation component and the cryptographic extension component respectively fully utilizes the performance of the central processing unit (CPU), avoids wasting CPU resources, and improves the speed of target checksum generation.
[0043] Moreover, it can improve the efficiency of data verification during storage, compression, and transmission, meeting the requirements for rapid data verification in data transmission scenarios.
[0044] This application provides a data checksum generation method applicable to various storage and communication systems with high requirements for data reliability and checksum generation speed. This method can be applied to scenarios such as high-speed networks, data storage, and file compression. It improves the efficiency of data verification during storage, compression, and transmission. It fully utilizes CPU resources to meet the requirements for rapid data verification in data transmission scenarios.
[0045] In 32-bit Castagnoli checksum generation, the CPU reads data from memory much faster than it processes the data; therefore, the data processing speed determines the checksum generation speed. Current technologies use only a single component for data processing, failing to fully utilize the CPU's capabilities.
[0046] This application splits the input target data into two parts according to a certain ratio: first data and second data. A cryptographic extension component and a CRC calculation component are used to process these two parts of data respectively. Then, the first and second checksums obtained after processing the data are merged to generate the target checksum. During data processing, the cryptographic extension component and the CRC calculation component can process the data simultaneously, making this data processing method faster than using a single component, resulting in a faster checksum generation speed.
[0047] Optionally, Figure 4 A flowchart illustrating a data verification code generation method provided in this application embodiment. Figure 2 ,like Figure 4 As shown, the process in S103 above, which divides the target data into first data and second data based on the data processing capabilities of the CRC calculation component and the cryptographic extension component, may include: S201. Based on the instruction runtime of the CRC calculation component and the cryptographic extension component, the target data is divided into initial first data and initial second data.
[0048] In some implementations, the target data is divided into initial first data and initial second data based on the instruction runtime required by the CRC calculation component and the cryptographic extension component when processing the same byte data.
[0049] In practical applications, less data can be allocated to components with longer instruction runtimes, while more data can be allocated to components with shorter instruction runtimes, so that the processing time of the CRC calculation component and the cryptographic extension component is roughly the same.
[0050] For example, if the instruction runtime of the CRC calculation component is shorter than that of the cryptographic extension component, then the amount of initial first data is greater than the amount of initial second data.
[0051] S202. Adjust the initial first data and initial second data according to the amount of data processed by the CRC calculation component and the cryptographic extension component in a single operation to obtain the first data and the second data.
[0052] In this embodiment of the application, based on the amount of data processed in a single operation by the CRC calculation component and the cryptographic extension component, the initial first data is adjusted to a multiple of the amount of data processed in a single operation by the CRC calculation component, and the initial second data is adjusted to a multiple of the amount of data processed in a single operation by the cryptographic extension component, thus obtaining the first data and the second data.
[0053] Optionally, Figure 5 A flowchart illustrating a data verification code generation method provided in this application embodiment. Figure 3 ,like Figure 5 As shown, the process in S201 above, which divides the target data into initial first data and initial second data based on the instruction runtime of the CRC calculation component and the cryptographic extension component, may include: S301. Determine the first clock cycle required by the CRC calculation component based on the first number of required instructions for the CRC calculation component.
[0054] In some implementations, the number of instructions that the CRC calculation component needs to run for each preset number of bytes is determined, i.e., the first required instruction number; a first clock cycle is determined based on the first required instruction number, and the CRC calculation component needs one first clock cycle to run one instruction.
[0055] The preset number of bytes is a multiple of the amount of data processed by the CRC calculation component in a single operation.
[0056] For example, the CRC calculation component processes 8 bytes of data at a time. The preset number of bytes can be 16 bytes. The CRC calculation component needs to run two instructions to process 16 bytes. That is, the first required instruction number is 2, which requires 2 clock cycles, or 2 first clock cycles.
[0057] S302. Determine the second clock cycle required by the cryptographic extension component based on the number of second requirement instructions for the cryptographic extension component.
[0058] The first and second requirement instructions are respectively the number of execution instructions required for the CRC calculation component and the cryptographic extension component to process the same amount of data.
[0059] In some implementations, the number of instructions that the cryptographic extension component needs to run for each preset number of bytes is determined, i.e., the second required instruction number; a second clock cycle is determined based on the second required instruction number, and the cryptographic extension component needs one second clock cycle to run one instruction.
[0060] The preset number of bytes represents the amount of data processed in a single operation by the cryptographic extension component.
[0061] For example, the cryptographic extension component processes 16 bytes of data at a time. The preset number of bytes can be 16 bytes. The cryptographic extension component needs to run three instructions to process 16 bytes. That is, the first requirement is 3 instructions, which requires 3 clock cycles, and the second requirement is 3 clock cycles.
[0062] S303. Determine the division ratio based on the first clock cycle and the second clock cycle.
[0063] In some implementations, the number of the first clock cycles and the number of the second clock cycles determine the division ratio. A smaller number of clock cycles corresponds to a larger division ratio.
[0064] For example, if the number of clock cycles in the first clock cycle is 2 and the number of clock cycles in the second clock cycle is 3, then the data partitioning ratio between the CRC calculation component and the cryptographic extension component is 3:2.
[0065] S304. According to the division ratio, the target data is divided into initial first data and initial second data.
[0066] In this embodiment of the application, if the number of first clock cycles is less than the number of second clock cycles, then the amount of initial first data corresponding to the CRC calculation component is greater than the amount of initial second data corresponding to the cryptographic extension component.
[0067] In addition, the initial first data and the initial second data are adjusted according to the amount of data processed in a single operation by the CRC calculation component and the cryptographic extension component. For example, the target data of 1024 bytes is divided into the first data of 608 bytes and the second data of 416 bytes.
[0068] Figure 6 This is a schematic diagram of a data segmentation processing framework provided in an embodiment of this application, such as... Figure 6 As shown, the data to be processed is segmented, with each segment being 1024 bytes. The first segment, from 0 to 1023 bytes, is further divided into 608-byte and 416-byte segments, and processed to obtain a 32-bit checksum. The second segment, from 1024 to 2047 bytes, is also divided into 608-byte and 416-byte segments, and combined with the 32-bit checksum from the first segment, to obtain a 32-bit checksum for the second segment. This process continues until all data in the data to be processed is segmented and processed, resulting in the checksum for the final data. The target data can be any of these segments.
[0069] Optionally, the process in S103 above, which uses a CRC calculation component and a cryptographic extension component to process the first data and the second data respectively to obtain the first check code and the second check code, may include: The first data is processed using CRC instructions in the CRC calculation component to obtain the first check code; and the second data is processed using cryptographic instructions in the cryptographic extension component to obtain the second check code.
[0070] The CRC instruction can be CRC32CX (32-bit Castagnoli polynomial cyclic redundancy check). Cryptographic instructions include polynomial multiplication instructions and triple XOR instructions. The polynomial multiplication instructions include PMULL2 and PMULL instructions, and the triple XOR instruction is EOR3. In this embodiment, when processing data using cryptographic extension components, a triple XOR instruction is used instead of two XOR instructions, which reduces the number of instructions.
[0071] In some implementations, the first data is processed using the CRC32CX instruction in the CRC calculation component to obtain the first check code; and the second data is processed using the polynomial multiplication instruction and the triple XOR instruction in the cryptographic extension component to obtain the second check code.
[0072] In this embodiment, when combining the cryptographic extension component and the CRC calculation component for data processing, the data needs to be segmented and prefetched to improve data access speed, taking into account the specific CPU configuration. Based on this, the segmented data needs to be split according to a certain ratio, considering the number of components in the CPU, instruction execution performance, and algorithms, so that the clock cycle ratio required by the cryptographic extension component and the CRC calculation component is 1:1. Then, the instructions in the cryptographic extension component and the CRC calculation component are used respectively to process the first data and the second data to generate the first checksum and the second checksum.
[0073] Optionally, Figure 7 A flowchart illustrating a data verification code generation method provided in this application embodiment. Figure 4 ,like Figure 7 As shown, the above-mentioned processing of the second data using cryptographic instructions in the cryptographic extension component to obtain the second verification code includes: S401. Divide the second data into the first sub-data and the second sub-data.
[0074] In some implementations, the second data is divided equally into a first sub-data and a second sub-data.
[0075] S402. Using cryptographic instructions in the cryptographic extension component, process the first sub-data and the second sub-data respectively to obtain the second verification code.
[0076] In this embodiment of the application, cryptographic instructions in the cryptographic extension component are used to process the first sub-data and the second sub-data in parallel to obtain the second verification code.
[0077] Figure 8 This application provides a schematic diagram of the instruction processing method in a CRC calculation component and a cryptographic extension component, as shown in the embodiments. Figure 8As shown, in some implementations, the CRC32CX calculation instruction in the CRC calculation component is used to process the first data in the target data, namely 608 bytes of data. The CRC32CX is used to process the data sequentially to obtain a 32-bit first check code.
[0078] like Figure 8 As shown, when processing the 416-byte second data using the cryptographic extension component, the second data is first divided into a first sub-data and a second sub-data, each 208 bytes long. The first and second sub-data are processed using the PMULL2 instruction, the PMULL instruction, and the triple XOR instruction (EOR3 instruction) respectively, resulting in two 128-bit checksums. These two 128-bit checksums are then combined to generate a 128-bit second checksum.
[0079] like Figure 8 As shown, the 32-bit first check code and the 128-bit second check code are combined to obtain the 32-bit target check code.
[0080] Optionally, Figure 9 A flowchart illustrating a data verification code generation method provided in this application embodiment. Figure 5 ,like Figure 9 As shown, the process in S402 above, which uses cryptographic instructions from the cryptographic extension component to process the first sub-data and the second sub-data respectively to obtain the second check code, may include: S501. Using the polynomial multiplication instruction and the triple XOR instruction in the cryptographic extension component, the first sub-data and the second sub-data are processed respectively to obtain the third check code and the fourth check code.
[0081] Among them, the polynomial multiplication instructions include: PMULL2 instruction and PMULL instruction; the triple XOR instruction is EOR3 instruction.
[0082] S502. The third check code and the fourth check code are merged to obtain the second check code.
[0083] In this embodiment, the PMULL2, PMULL, and EOR3 instructions in the cryptographic extension components are used to process the first sub-data and the second sub-data respectively to obtain the third check code and the fourth check code; the third check code and the fourth check code are then combined to obtain the second check code.
[0084] It is worth noting that on some CPUs, the cryptographic extension supports the PMULL instruction and the PMULL2 instruction with a latency of 3. These instructions divide the second data into two parts, the first sub-data and the second sub-data, and process them separately, thus eliminating data hazards between the PMULL instruction and the PMULL2 instruction.
[0085] Optionally, Figure 10 A flowchart illustrating a data verification code generation method provided in this application embodiment. Figure 6 ,like Figure 10 As shown, the process of processing the first data using CRC instructions in the CRC calculation component to obtain the first checksum, and processing the second data using cryptographic instructions in the cryptographic extension component to obtain the second checksum, can include: S601. Based on the delay of the CRC instruction in the CRC calculation component and the delay of the cryptographic instruction in the cryptographic extension component, the CRC instruction in the CRC calculation component and the cryptographic instruction in the cryptographic extension component are cross-arranged to obtain the cross-arranged instruction.
[0086] In this process, the CRC instructions in the CRC calculation component and the cryptographic instructions in the cryptographic extension component are cross-arranged, and it is necessary to ensure that there are no data hazards between the cross-arranged instructions.
[0087] In this embodiment, the cryptographic instructions include: PMULL2 instruction, PMULL instruction, and EOR3 instruction. Using a triple XOR instruction to perform the XOR operation when calculating the second checksum using the cryptographic extension component can reduce the number of XOR instructions.
[0088] It should be noted that the throughput and latency of each instruction in the CPU are shown in Table 1. Based on the throughput and latency of each instruction, the assembly code for generating the target checksum is cross-arranged to ensure no pipeline stalls.
[0089] Table 1
[0090] S602. The first data is processed using the CRC instruction in the cross-arranged instructions to obtain the first check code; and the second data is processed using the cryptographic instruction in the cross-arranged instructions to obtain the second check code.
[0091] In the cross-arranged instructions, CRC instructions and cryptographic instructions run in parallel.
[0092] In the embodiments of this application, when the CRC instruction is combined with the PMULL2 instruction, the PMULL instruction, and the EOR3 instruction, based on... Figure 8When the shown arrangement is interleaved, the CRC instruction runs in parallel with the PMULL2, PMULL, and EOR3 instructions. Furthermore, during code execution, there are no pipeline pauses caused by data dependencies between instructions. This fully utilizes CPU resources and maximizes CPU performance.
[0093] In summary, this application provides a data checksum generation method. Cyclic Redundancy Check (CRC) is widely used in network communication, data storage, and data compression scenarios. It verifies whether errors occur during data transmission by generating checksums. In this application, the target data is divided according to a specific ratio based on the number of CPU components and instruction characteristics. Different components process the divided data separately, and the checksums generated by the two methods are combined. This method fully utilizes the components in the CPU (Central Processing Unit) to quickly generate the target checksum. When calculating the CRC checksum using the cryptographic extension component, a triple XOR instruction is used instead of an XOR instruction, reducing the number of XOR instructions. In the assembly code implementation of the checksum generation process, the instructions in the cryptographic extension component and the CRC calculation component are interleaved, considering the throughput and latency of each instruction. This method reduces pipeline stalls, fully utilizes CPU resources, and maximizes CPU performance.
[0094] Furthermore, this application can perform error detection on transmission problems caused by signal interference, clock jitter, physical connection issues, etc., ensuring data integrity. It has the advantages of high error detection rate, ability to detect a variety of common errors, and high detection efficiency.
[0095] Optionally, Figure 11 A related technology and a schematic diagram of the comparison process for generating a checksum in this application are provided for embodiments of this application, as shown in the figure. Figure 11 As shown, existing technologies suffer from inefficiency in CRC checksum generation, failing to fully utilize CPU components. During CRC checksum generation, a CPU unit first rapidly loads data from memory, then processes it. However, the data loading speed outpaces the data processing speed, thus limiting the generation of the CRC checksum. For example... Figure 11 As shown, existing technologies use only a single CPU component to calculate the checksum when processing data with a CPU.
[0096] In this embodiment, when processing data using the CPU, the target data is divided according to the number of cryptographic extension components and CRC calculation components in the CPU, combined with the corresponding algorithm. In the application scenario provided in this application, 1024 bytes of data are divided into 608 bytes and 416 bytes of data in a 3:2 ratio, resulting in data 1 (first data) and data 2 (first data). Then, the CRC32C calculation instruction in the CRC component and the polynomial multiplication and XOR instructions in the cryptographic extension component are used to calculate the checksum for data 1 and data 2 respectively. Finally, the data are merged to obtain the target checksum, as shown below. Figure 11 As shown, in the process of calculating the CRC checksum using the cryptographic extension component, the triple XOR instruction EOR3 is used instead of the XOR instruction, thereby reducing the number of XOR instructions. In the assembly code implementation of the target checksum generation process, the instructions in the cryptographic extension component and the instructions in the CRC calculation component are interleaved, taking into account the throughput and latency of each instruction used. This method can reduce pipeline stalls, make full use of CPU resources, maximize CPU performance, and improve the processing speed and checksum generation speed.
[0097] It should be noted that in the 32-bit Castagnoli checksum generation method, the CPU reads data from memory much faster than it processes the data, so the speed of data processing determines the speed of checksum generation.
[0098] In this embodiment, when processing data using the CPU, the target data is divided according to the number of cryptographic extension components and CRC calculation components, combined with the corresponding algorithm. In the application scenario provided in this application, 1024 bytes of data are divided into 608 bytes and 416 bytes of data in a 3:2 ratio. This ensures that the number of clock cycles used by the cryptographic extension components and CRC calculation components when processing data is the same. Figure 11 As shown, both the CRC calculation component and the cryptographic extension component are used to calculate the checksum. Furthermore, when using the cryptographic extension component for checksum calculation, a triple XOR instruction is used instead of a standard XOR instruction, reducing the number of instructions required. In the assembly code implementation of the target checksum generation process, the instructions in the cryptographic extension component and the CRC calculation component are interleaved, taking into account the throughput and latency of each instruction used. This approach reduces pipeline stalls, fully utilizes CPU resources, and maximizes CPU performance.
[0099] The following describes the data check code generation apparatus, computer equipment, and storage medium used to execute the data check code generation method provided in this application. For the specific implementation process and technical effects, please refer to the relevant content of the data check code generation method above, which will not be repeated below.
[0100] Figure 12 This is a schematic diagram of a data checksum generation device provided in an embodiment of this application. The device is applied to a central processing unit (CPU), which includes: a loading memory unit, a cyclic redundancy check (CRC) calculation component, and a cryptographic extension component. Figure 12 As shown, the device includes: The acquisition module 101 is used to acquire target data using the loading storage unit, wherein the target data is data to be generated as a verification code; The partitioning module 102 is used to partition the target data into first data and second data using the loading storage unit based on the data processing capabilities of the CRC calculation component and the cryptographic extension component. Processing module 103 is used to process the first data and the second data respectively using the CRC calculation component and the cryptographic extension component to obtain the first check code and the second check code. The merging module 104 is used to merge the first check code and the second check code using the CRC calculation component and the cryptographic extension component to obtain the target check code corresponding to the target data.
[0101] Optionally, the partitioning module 102 is specifically used to partition the target data into initial first data and initial second data according to the instruction runtime of the CRC calculation component and the cryptographic extension component; and to adjust the initial first data and the initial second data according to the amount of data processed by the CRC calculation component and the cryptographic extension component in a single operation to obtain the first data and the second data.
[0102] Optionally, the partitioning module 102 is specifically configured to: determine the first clock cycle required by the CRC calculation component based on the first number of required instructions of the CRC calculation component; determine the second clock cycle required by the cryptographic extension component based on the second number of required instructions of the cryptographic extension component; wherein the first number of required instructions and the second number of required instructions are respectively the number of running instructions required by the CRC calculation component and the cryptographic extension component to process the same amount of data; determine the partitioning ratio based on the first clock cycle and the second clock cycle; and partition the target data into the initial first data and the initial second data according to the partitioning ratio.
[0103] Optionally, the processing module 103 is specifically used to process the first data using CRC instructions in the CRC calculation component to obtain the first check code; and to process the second data using cryptographic instructions in the cryptographic extension component to obtain the second check code.
[0104] Optionally, the processing module 103 is specifically used to divide the second data into a first sub-data and a second sub-data; and to process the first sub-data and the second sub-data respectively using cryptographic instructions in the cryptographic extension component to obtain the second verification code.
[0105] Optionally, the processing module 103 is specifically used to process the first sub-data and the second sub-data respectively using the polynomial multiplication instruction and the triple XOR instruction in the cryptographic extension component to obtain the third check code and the fourth check code; and to merge the third check code and the fourth check code to obtain the second check code.
[0106] Optionally, the processing module 103 is specifically configured to, based on the delay of the CRC instruction in the CRC calculation component and the delay of the cryptographic instruction in the cryptographic extension component, cross-arrange the CRC instruction in the CRC calculation component and the cryptographic instruction in the cryptographic extension component to obtain cross-arranged instructions; process the first data using the CRC instruction in the cross-arranged instructions to obtain the first checksum; and process the second data using the cryptographic instruction in the cross-arranged instructions to obtain the second checksum; wherein the CRC instruction and the cryptographic instruction in the cross-arranged instructions run in parallel.
[0107] The above-described device is used to execute the method provided in the foregoing embodiments, and its implementation principle and technical effect are similar, so they will not be described again here.
[0108] These modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more digital signal processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a system-on-a-chip (SOC).
[0109] Figure 13 This application provides a schematic diagram of the structure of a computer device, as shown in the embodiment of the present application. Figure 13As shown, the computer device includes: processor 201 and memory 202.
[0110] The memory 202 is used to store programs, and the processor 201 calls the programs stored in the memory 202 to execute the above method embodiments. The specific implementation and technical effects are similar, and will not be described in detail here.
[0111] Optionally, this application also provides a program product, such as a computer-readable storage medium, including a program that, when executed by a processor, performs the above-described method embodiments.
[0112] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0113] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0114] Furthermore, the functional units in the various embodiments of this application can be integrated into a single loading and storage unit, or each unit can exist physically separately, or two or more units can be integrated into a single unit. The integrated units described above can be implemented in hardware or in a combination of hardware and software functional units.
[0115] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0116] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method for generating a data verification code, characterized in that, Applied to a central processing unit, the central processing unit includes: a load memory unit, a cyclic redundancy check (CRC) calculation component, and a cryptographic extension component; the method includes: The target data is obtained using the loading storage unit, and the target data is the data to be used to generate a verification code. The loading storage unit uses the data processing capabilities of the CRC calculation component and the cryptographic extension component to divide the target data into first data and second data. The first data and the second data are processed using the CRC calculation component and the cryptographic extension component respectively to obtain the first check code and the second check code; The first check code and the second check code are merged using the CRC calculation component and the cryptographic extension component to obtain the target check code corresponding to the target data.
2. The method according to claim 1, characterized in that, The step of dividing the target data into first data and second data based on the data processing capabilities of the CRC calculation component and the cryptographic extension component includes: Based on the instruction runtime of the CRC calculation component and the cryptographic extension component, the target data is divided into initial first data and initial second data. Based on the amount of data processed in a single operation by the CRC calculation component and the cryptographic extension component, the initial first data and the initial second data are adjusted to obtain the first data and the second data.
3. The method according to claim 2, characterized in that, The step of dividing the target data into initial first data and initial second data based on the instruction runtime of the CRC calculation component and the cryptographic extension component includes: The first clock cycle required by the CRC calculation component is determined based on the first number of required instructions of the CRC calculation component. The second clock cycle required by the cryptographic extension component is determined based on the second number of demand instructions for the cryptographic extension component; wherein, the first number of demand instructions and the second number of demand instructions are respectively the number of running instructions required by the CRC calculation component and the cryptographic extension component to process the same amount of data; The division ratio is determined based on the first clock cycle and the second clock cycle; According to the division ratio, the target data is divided into the initial first data and the initial second data.
4. The method according to claim 1, characterized in that, The step of using the CRC calculation component and the cryptographic extension component to process the first data and the second data respectively to obtain the first check code and the second check code includes: The first data is processed using the CRC instructions in the CRC calculation component to obtain the first checksum; and the second data is processed using the cryptographic instructions in the cryptographic extension component to obtain the second checksum.
5. The method according to claim 4, characterized in that, The step of processing the second data using cryptographic instructions from the cryptographic extension component to obtain the second verification code includes: The second data is divided into a first sub-data and a second sub-data; The first sub-data and the second sub-data are processed using cryptographic instructions in the cryptographic extension component to obtain the second verification code.
6. The method according to claim 5, characterized in that, The step of processing the first sub-data and the second sub-data respectively using cryptographic instructions from the cryptographic extension component to obtain the second verification code includes: The first sub-data and the second sub-data are processed by using the polynomial multiplication instruction and the triple XOR instruction in the cryptographic extension component to obtain the third check code and the fourth check code. The third check code and the fourth check code are merged to obtain the second check code.
7. The method according to claim 4, characterized in that, The first data is processed using the CRC instruction in the CRC calculation component to obtain the first checksum; The second data is processed using cryptographic instructions from the cryptographic extension component to obtain the second verification code, including: Based on the delay of the CRC instruction in the CRC calculation component and the delay of the cryptographic instruction in the cryptographic extension component, the CRC instruction in the CRC calculation component and the cryptographic instruction in the cryptographic extension component are cross-arranged to obtain the cross-arranged instruction; The first data is processed using the CRC instruction in the cross-arranged instructions to obtain the first check code; and the second data is processed using the cryptographic instructions in the cross-arranged instructions to obtain the second check code. In the cross-arranged instructions, CRC instructions and cryptographic instructions run in parallel.
8. A central processing unit, characterized in that, include: The system includes a loading storage unit, a cyclic redundancy check (CRC) calculation component, and a cryptographic extension component; the loading storage unit is connected to both the CRC calculation component and the cryptographic extension component. The loading storage unit is used to perform the steps performed by the loading storage unit in the method of any one of claims 1-7; the CRC calculation component is used to perform the steps performed by the CRC calculation component in the method of any one of claims 1-7; the cryptographic extension component is used to perform the steps performed by the cryptographic extension component in the method of any one of claims 1-7.
9. A computer device, characterized in that, At least including: The central processing unit as described in claim 8.
10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when read and executed, implements the method described in any one of claims 1-7.