Circuit board and method for manufacturing the same

Abstract

This application discloses a circuit board and a method for manufacturing the same. The method includes: providing a substrate, the substrate including a substrate layer stacked along the thickness direction and a first conductor layer disposed on one side of the substrate layer; forming a first dielectric layer on the surface of the first conductor layer away from the substrate layer; patterning the first dielectric layer by irradiating it with a laser, so that a portion of the first conductor layer is exposed from the first dielectric layer; and etching the first conductor layer to form a first circuit layer.

Description

Technical Field

[0001] This application relates to the field of printed circuit boards, and more particularly to a circuit board and a method for manufacturing the same. Background Technology

[0002] In circuit board production, the circuit fabrication process includes: drilling different types of holes mechanically or with lasers, performing shadow processing, pressing dry film, projecting the designed circuit pattern onto the dry film using an ultraviolet light source through film, causing a chemical change so that the pattern exposed after exposure can be removed using a developer in the subsequent development process, and finally etching out the circuit pattern and removing the dry film to complete the circuit fabrication.

[0003] The above process has the following problems: (1) When making fine lines from film, burrs often occur; (2) Whether the exposure equipment is properly maintained and whether the exposure equipment is calibrated will affect the exposure quality, and thus affect the quality of the line production; (3) Insufficient development may cause inconsistent line widths or incomplete patterns, which may lead to short circuits or produce fragmented or jagged line edges, resulting in poor lines; while overdevelopment may cause the lines to become narrower and affect their conductivity. Summary of the Invention

[0004] In view of this, this application provides a circuit board and a method for manufacturing the same that can solve the above-mentioned technical problems.

[0005] A method for manufacturing a circuit board, comprising:

[0006] A substrate is provided, the substrate comprising a substrate layer stacked along the thickness direction and a first conductor layer disposed on one side of the substrate layer;

[0007] A first dielectric layer is formed on the surface of the first conductor layer opposite to the substrate layer;

[0008] The first dielectric layer is patterned by irradiating it with a laser, so that a portion of the first conductor layer is exposed from the first dielectric layer.

[0009] The first conductor layer is etched to form the first circuit layer.

[0010] In some embodiments, the step of “patterning the first dielectric layer by irradiating it with a laser” includes: forming a pattern on the first dielectric layer by irradiating it with a laser, wherein, during laser irradiation, the spot size used for the edge contour of the pattern is smaller than the spot size used for the non-edge regions of the pattern.

[0011] In some embodiments, the method further includes: forming a through-hole on the substrate, the through-hole penetrating the substrate layer and the first conductor layer; forming a first metal layer on the surface of the first conductor layer, the first metal layer covering the surface of the first conductor layer away from the substrate layer and partially exposing the through-hole on the surface of the first conductor layer.

[0012] In some implementations, after the step of "etching the first conductor layer to form the first circuit layer", the method further includes:

[0013] A first cover film is formed on the surface of the first dielectric layer away from the first conductor layer. The first cover film includes a first adhesive layer and a first protective layer. The first protective layer covers the surface of the first adhesive layer away from the first dielectric layer. The first adhesive layer and the first protective layer are provided with a first window. The first window penetrates the first protective layer and the first adhesive layer.

[0014] A first groove is formed on the surface of the first dielectric layer away from the first metal layer, a portion of the first metal layer is exposed in the first groove, a plurality of first grooves are spaced apart, and the first window is connected to the first groove.

[0015] A first coating is formed in the first groove, the first coating covering the surface of the first metal layer away from the first conductor layer;

[0016] The first electronic component is installed inside the first window.

[0017] In some embodiments, the substrate further includes a second conductor layer disposed on the other side of the substrate opposite to the first conductor layer, and the via also penetrates the second conductor layer;

[0018] The method for manufacturing the circuit board also includes:

[0019] A second metal layer is formed on the surface of the second conductor layer, the second metal layer covering the surface of the second conductor layer away from the substrate layer and partially exposing the vias on the surface of the second conductor layer;

[0020] A second dielectric layer is formed on the surface of the second conductor layer opposite to the substrate layer;

[0021] The second dielectric layer is patterned by irradiating it with a laser.

[0022] The second conductor layer is etched to form the second circuit layer.

[0023] In some embodiments, after the step of "etching the second conductor layer to form the second circuit layer", the method further includes:

[0024] A second cover film is formed on the surface of the second dielectric layer away from the second conductor layer. The second cover film includes a second adhesive layer and a second protective layer. The second protective layer covers the surface of the second adhesive layer away from the second dielectric layer. The second adhesive layer and the second protective layer are provided with a second opening. The second opening penetrates the second protective layer and the second adhesive layer.

[0025] A second groove is formed on the surface of the second dielectric layer away from the second metal layer, a portion of the second metal layer is exposed in the second groove, a plurality of second grooves are spaced apart, and the second window is connected to the plurality of second grooves;

[0026] A first plating layer is formed in the second groove, the first plating layer covering the surface of the second metal layer away from the second conductor layer;

[0027] Electronic components are installed within the second window.

[0028] In some embodiments, the thickness of the first coating is less than the thickness of the second dielectric layer.

[0029] This application also provides a circuit board, which includes an inner circuit board substrate, a first conductive connector, a first electronic component, and a bottom filler. The inner circuit board substrate includes a first dielectric layer, a first metal layer, a first conductor layer, and a substrate layer stacked sequentially. The first dielectric layer has a first groove, and a portion of the first metal layer is exposed in the first groove. A plurality of first grooves are spaced apart. The first conductive connector is disposed in the first groove and is electrically connected to the first metal layer. The first electronic component is electrically connected to the inner circuit board substrate through the first conductive connector. The bottom filler covers the inner circuit board substrate and the surface of the first conductive connector exposed on the first electronic component.

[0030] In some embodiments, the inner circuit board further includes a second conductor layer, a second metal layer, and a second dielectric layer stacked sequentially. The second dielectric layer covers the surface of the second metal layer away from the second conductor layer. The second dielectric layer has a second groove, and a portion of the second metal layer is exposed in the second groove. A plurality of second grooves are spaced apart. A first plating layer is provided at the bottom of the second groove. The thickness of the first plating layer is less than the thickness of the second dielectric layer. The second electronic component is electrically connected to the first plating layer through a second conductive connector.

[0031] In some embodiments, the circuit board further includes a first cover film covering the surface of the first dielectric layer away from the first conductor layer. The first cover film includes a first adhesive layer and a first protective layer. The first protective layer covers the surface of the first adhesive layer away from the first dielectric layer. The first adhesive layer and the first protective layer are provided with a first opening. The first opening penetrates the first protective layer and the first adhesive layer. The first groove is exposed in the first opening.

[0032] This application uses laser to pattern a dielectric layer, and then etches the exposed conductor layer from the dielectric layer to achieve image transfer and circuit fabrication. Compared with the traditional method of fabricating circuits through dry film exposure and development, the method provided in this application produces circuits of excellent quality, without producing defects such as burrs, line edges, broken lines, or short circuits. It is also unaffected by factors such as whether the equipment is calibrated or properly maintained, and is especially suitable for fabricating fine lines. Attached Figure Description

[0033] Figure 1 This is a cross-sectional schematic diagram of a substrate provided in one embodiment of the present application, on which a first metal layer and a second metal layer are formed.

[0034] Figure 2 In order to be in Figure 1 A cross-sectional diagram showing the formation of a first dielectric layer and a second dielectric layer based on the structure shown.

[0035] Figure 3 In order to be in Figure 2 A cross-sectional diagram showing the formation of the first opening based on the structure shown.

[0036] Figure 4 In order to be in Figure 3 A cross-sectional diagram showing the formation of the first and second circuit layers based on the structure shown.

[0037] Figure 5 In order to be in Figure 4 A cross-sectional diagram showing the formation of a first adhesive layer, a second adhesive layer, a first covering layer, a second covering layer, a first window, and a second window based on the structure shown.

[0038] Figure 6 In order to be in Figure 5 A cross-sectional diagram showing the formation of the first and second grooves based on the structure shown.

[0039] Figure 7 In order to be in Figure 6 A cross-sectional schematic diagram showing the formation of a protective layer and solder pads based on the structure shown.

[0040] Figure 8 In order to be in Figure 7 A cross-sectional schematic diagram of an electronic component mounted on the structure shown.

[0041] Explanation of main component symbols

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[0044] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0045] To better understand the above-mentioned objectives, features, and advantages of the embodiments of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the features in the embodiments of this application can be combined with each other.

[0046] The following description sets forth numerous specific details to provide a thorough understanding of the embodiments of the present invention. The described embodiments are only a part of, and not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the embodiments of the present invention.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of the invention pertain. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the invention.

[0048] Please see Figures 1 to 8 One embodiment of this application provides a method for manufacturing a circuit board 100, comprising the following steps:

[0049] Step S1: Please refer to Figure 1 A substrate 10 is provided, the substrate 10 including a substrate layer 11 and a conductor layer 12 disposed on at least one side of the substrate layer 11. In this embodiment, the substrate 10 includes a substrate layer 11 and a first conductor layer 121 and a second conductor layer 122 located on opposite sides of the substrate layer 11.

[0050] Through-hole 14 and first blind hole 15 are formed on substrate 10. Through-hole 14 penetrates first conductor layer 121, substrate layer 11 and second conductor layer 122. First blind hole 15 penetrates second conductor layer 122 and substrate layer 11. Part of first conductor layer 121 is exposed from the bottom of first blind hole 15.

[0051] A first metal layer 131 is formed on the surface of the first conductor layer 121 facing away from the substrate layer 11. The first metal layer 131 covers the surface of the first conductor layer 121 facing away from the substrate layer 11 and partially exposes the via 14 on the surface of the first conductor layer 121. A second metal layer 132 is formed on the surface of the second conductor layer 122 facing away from the substrate layer 11. The second metal layer 132 covers the surface of the first blind via 15 exposed on the surface of the second conductor layer 122 and partially exposes the via 14 on the surface of the second conductor layer 122. A conductive structure 16 is formed within the first blind via 15, and the conductive structure 16 is electrically connected to the first conductor layer 121, the second conductor layer 122, and the second metal layer 132. In this embodiment, the first metal layer 131 and the second metal layer 132 are connected within the via 14.

[0052] The substrate layer 11 can be made of at least one of polyimide (PI), polyethylene terephthalate (PET), and prepregs containing glass fiber and epoxy resin. In this embodiment, the substrate layer 11 is made of PI. This application does not impose any special limitations on the material of the substrate layer 11. The conductor layer 12 has electrical conductivity, and the material of the conductor layer 12 can be made of at least one of copper, silver, aluminum, etc. In this embodiment, the conductor layer 12 is made of copper. This application does not impose any special limitations on the material of the conductor layer 12.

[0053] Step S2: Please refer to Figure 2 A first dielectric layer 21 is formed on the surface of the first metal layer 131 opposite to the surface of the first conductor layer 121, and a second dielectric layer 22 is formed on the surface of the second metal layer 132 opposite to the surface of the second conductor layer 122. The first dielectric layer 21 covers the surface of the first metal layer 131 opposite to the surface of the first conductor layer 121 and also covers the surface of the first metal layer 131 exposed in the via 14. The second dielectric layer 22 covers the surface of the second metal layer 132 opposite to the surface of the second conductor layer 122 and also covers the surface of the second metal layer 132 exposed in the via 14.

[0054] In this embodiment, the first dielectric layer 21 and the second dielectric layer 22 are connected within the via 14 and fill the via 14. The first dielectric layer 21 and the second dielectric layer 22 can be made of materials such as polyimide (PI). The thickness of the first dielectric layer 21 can be 2–5 μm, and the thickness of the second dielectric layer 22 can be 2–5 μm. This is just an example, and this application does not impose any special limitations on the thickness of the first dielectric layer 21 and the second dielectric layer 22.

[0055] Step S3: Please refer to Figure 3The first dielectric layer 21 and the second dielectric layer 22 are patterned by laser etching. A first opening 23 is formed by laser processing on the surface of the first dielectric layer 21 facing away from the first metal layer 131, exposing a portion of the first metal layer 131 through the first opening 23. A first opening 23 is also formed by laser processing on the surface of the second dielectric layer 22 facing away from the second metal layer 132, exposing a portion of the first metal layer 131 and a portion of the conductive structure 16 through the first opening 23.

[0056] In this embodiment, the laser spot size is adjusted according to the laser processing path. Specifically, when the first dielectric layer 21 and the second dielectric layer 22 are irradiated with a laser to form a pattern, the laser spot used for the edge contour of the pattern is smaller than the laser spot used for the non-edge areas of the pattern. Using a smaller laser spot for irradiation at the edge contour of the pattern ensures processing accuracy and that the circuit pattern remains accurate and undistorted. Using a larger laser spot for irradiation in the non-edge areas of the pattern ensures the accuracy and efficiency of the laser engraving. In this application, "edge contour of the pattern" refers to the edge area of ​​the pattern, and "non-edge area of ​​the pattern" refers to the remaining area of ​​the pattern excluding the edge area.

[0057] Step S4: Please refer to Figure 4 Through the first opening 23, the first metal layer 131 and the first conductor layer 121 are etched with a chemical solution to form a first circuit layer 31 on the surface of the substrate layer 11 opposite to the second conductor layer 122. The first circuit layer 31 includes a first gap 32, and a portion of the substrate layer 11 is exposed from the bottom of the first gap 32. Through the first opening 23, the second metal layer 132 and the second conductor layer 122 are etched with a chemical solution to form a second circuit layer 33 on the surface of the substrate layer 11 opposite to the first conductor layer 121. The second circuit layer 33 includes a second gap 34, and a portion of the substrate layer 11 is exposed from the bottom of the second gap 34.

[0058] This application uses laser etching instead of traditional dry film etching to first pattern the first dielectric layer 21 and the second dielectric layer 22, and then uses a chemical etching solution to etch the first metal layer 131, the second metal layer 132, the first conductor layer 121, and the second conductor layer 122 to form a circuit layer. The areas of the first metal layer 131 and the second metal layer 132 covered by the first dielectric layer 21 and the second dielectric layer 22 are not etched by the chemical etching solution.

[0059] Furthermore, within the circuit layer, the linewidth and spacing of each line are controlled by laser, unaffected by external forces, resulting in high circuit yield and eliminating issues such as broken lines, fragmented or jagged lines, or short circuits. The circuit fabrication process eliminates the need for organic materials like dry film and developing / stripping solutions, and is unaffected by equipment factors such as whether the exposure machine is calibrated or properly maintained. It also avoids defects in the etched circuitry due to development quality issues.

[0060] Step S5: Please refer to Figure 5 A first cover film is formed on the surface of the first dielectric layer 21. The first cover film includes a first adhesive layer 41 and a first protective layer 43. The first adhesive layer 41 fills the first gap 32 and covers the surface of the first dielectric layer 21 facing away from the first metal layer 131. The first protective layer 43 covers the surface of the first adhesive layer 41 facing away from the first dielectric layer 21. A second cover film is formed on the surface of the second dielectric layer 22. The second cover film includes a second adhesive layer 42 and a second protective layer 44. The second adhesive layer 42 fills the second gap 34 and covers the surface of the second dielectric layer 22 facing away from the second metal layer 132. The second protective layer 44 covers the surface of the second adhesive layer 42 facing away from the second dielectric layer 22. The first adhesive layer 41 and the first protective layer 43 have a pre-opened first window 45 that penetrates the first protective layer 43 and the first adhesive layer 41, with a portion of the first dielectric layer 21 exposed from the bottom of the first window 45. The second adhesive layer 42 and the second protective layer 44 have a pre-drilled second opening 46 that penetrates the second protective layer 44 and the second adhesive layer 42, with a portion of the second dielectric layer 22 exposed from the bottom of the second opening 46. The first protective layer 43 and the second protective layer 44 protect the circuit layer area where electronic components 80 are not installed, preventing the circuit in this area from external contamination or influence.

[0061] Step S6: Please refer to Figure 6 Laser ablation exposes the first dielectric layer 21 in the first window 45 to form a first groove 51, with multiple first grooves 51 spaced apart. The first groove 51 penetrates the first dielectric layer 21, and a portion of the first metal layer 131 is exposed from the bottom of the first groove 51. Laser ablation exposes the second dielectric layer 22 in the second window 46 to form a second groove 52, with multiple second grooves 52 spaced apart. The second groove 52 penetrates the second dielectric layer 22, and a portion of the second metal layer 132 and a portion of the conductive structure 16 are exposed from the bottom of the second groove 52. This forms the inner layer circuit board 60.

[0062] Step S7: Please refer to Figure 7 A first coating 61 is formed in the first groove 51, covering the surface of the first metal layer 131 facing away from the first conductor layer 121. A first plating layer 62 is formed in the second groove 52, covering the surface of the second metal layer 132 facing away from the second conductor layer 122 and the surface of a portion of the conductive structure 16 facing away from the second metal layer 132.

[0063] The first coating 61 is formed using an organic solderability preservative (OSP) process, and the material of the organic solderability preservative can be triazine indene or imidazole organic crystalline base. The first plating layer 62 is formed using an electroless nickel immersion gold (ENEPIG) or electroless nickel immersion gold (ENIG) process.

[0064] In some other embodiments, a first plating layer 62 is formed in the first groove 51, covering the surface of the first metal layer 131 facing away from the first conductor layer 121. A first plating layer 62 is also formed in the second groove 52, covering the surface of the second metal layer 132 facing away from the second conductor layer 122 and a portion of the conductive structure 16 facing away from the second metal layer 132. That is, a first plating layer 62 is formed in both the first groove 51 and the second groove 52.

[0065] In this embodiment, the thickness of the first plating layer 62 is less than the thickness of the second dielectric layer 22, so that the second groove 52 is sufficient to accommodate the second conductive connector 72 in subsequent processes, preventing the solder from overflowing from the second groove 52 and forming a welding bridge during the welding of the second conductive connector 72.

[0066] Step S8: Please refer to Figure 8 A first conductive connector 71 is welded within the first groove 51. During the welding process, the first coating 61 is removed, exposing the first metal layer 131 exposed at the bottom of the first groove 51. The first conductive connector 71 is formed on the surface of the first metal layer 131 facing away from the first conductor layer 121. A first electronic component 81 is installed within the first opening 45, and the first electronic component 81 is electrically connected to the first metal layer 131 through the first conductive connector 71. Alternatively, a second conductive connector 72 can be formed on the surface of the first plating layer 62 facing away from the second metal layer 132 or the conductive structure 16. The second electronic component 82 is then installed within the second opening 46, and the second electronic component 82 is electrically connected to the first plating layer 62 through the second conductive connector 72.

[0067] In this embodiment, the first window 45 is filled with a bottom filler 90, which covers the substrate layer 11, the first conductor layer 121, the first metal layer 131, the first dielectric layer 21, the first conductive connector 71, and the first electronic component 81 exposed on the surface of the first window 45. This method helps to enhance the connection stability between the first electronic component 81 and the inner circuit board 60, and the first window 45 can fully accommodate the bottom filler 90, thereby preventing the bottom filler 90 from overflowing.

[0068] Please see Figure 8This application also provides a circuit board 100, which includes an inner circuit board 60, a first conductive connector 71, a first electronic component 81, and a bottom filler 90. The inner circuit board 60 includes a first dielectric layer 21, a first metal layer 131, a first conductor layer 121, and a substrate layer 11 stacked sequentially. The first dielectric layer 21 has a first groove 51, and a portion of the first metal layer 131 is exposed in the first groove 51. Multiple first grooves 51 are spaced apart. The first conductive connector 71 is disposed in the first groove 51 and is electrically connected to the first metal layer 131. The first electronic component 81 is electrically connected to the inner circuit board 60 through the first conductive connector 71. The bottom filler 90 covers the inner circuit board 60 and the surface of the first conductive connector 71 exposed on the first electronic component 81.

[0069] In some embodiments, the circuit board 100 further includes a first cover film covering the surface of the first dielectric layer 21 away from the first conductor layer 121. The first cover film includes a first adhesive layer 41 and a first protective layer 43. The first protective layer 43 covers the surface of the first adhesive layer 41 away from the first dielectric layer 21. The first adhesive layer 41 and the first protective layer 43 are provided with a first opening 45. The first opening 45 penetrates the first protective layer 43 and the first adhesive layer 41. A first groove 51 is exposed in the first opening 45.

[0070] In some embodiments, the inner circuit board 60 further includes a second conductor layer 122, a second metal layer 132, and a second dielectric layer 22 stacked sequentially. The second dielectric layer 22 covers the surface of the second metal layer 132 facing away from the second conductor layer 122. The second dielectric layer 22 has a second groove 52, with a portion of the second metal layer 132 exposed in the second groove 52. Multiple second grooves 52 are spaced apart. A first plating layer 62 is provided at the bottom of the second groove 52. The thickness of the first plating layer 62 is less than the thickness of the second dielectric layer 22, so that the second groove 52 can accommodate solder and prevent solder from overflowing the second groove 52 and forming solder bridges. The second electronic component 82 is electrically connected to the first plating layer 62 through a second conductive connector 72.

[0071] In some embodiments, the circuit board 100 further includes a second cover film covering the surface of the second dielectric layer 22 away from the second conductor layer 122. The second cover film includes a second adhesive layer 42 and a second protective layer 44 covering the surface of the second adhesive layer 42 away from the second dielectric layer 22. The second adhesive layer 42 and the second protective layer 44 are provided with a second opening 46, which penetrates the second protective layer 44 and the second adhesive layer 42. A second groove 52 is exposed in the second opening 46.

[0072] In some embodiments, the first dielectric layer 21 and the second dielectric layer 22 comprise polyimide (PI). The thickness of the first dielectric layer 21 and the second dielectric layer 22 can be 2–5 μm.

[0073] In some embodiments, the first conductive connector 71 and the second conductive connector 72 may be solder paste or solder balls, etc. The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A method for manufacturing a circuit board, characterized in that, include: A substrate is provided, the substrate comprising a substrate layer stacked along the thickness direction and a first conductor layer disposed on one side of the substrate layer; A first dielectric layer is formed on the surface of the first conductor layer opposite to the substrate layer; The first dielectric layer is patterned by irradiating it with a laser, so that a portion of the first conductor layer is exposed from the first dielectric layer. The first conductor layer is etched to form the first circuit layer.

2. The method for manufacturing a circuit board as described in claim 1, characterized in that, The step of "patterning the first dielectric layer by irradiating it with a laser" includes: forming a pattern on the first dielectric layer by irradiating it with a laser, wherein, during laser irradiation, the spot size used for the edge contour of the pattern is smaller than the spot size used for the non-edge region of the pattern.

3. The method for manufacturing a circuit board as described in claim 1, characterized in that, Also includes: A via is formed on the substrate, the via penetrating the substrate layer and the first conductor layer, and a first metal layer is formed on the surface of the first conductor layer, the first metal layer covering the surface of the first conductor layer away from the substrate layer and partially exposing the via on the surface of the first conductor layer.

4. The method for manufacturing a circuit board as described in claim 3, characterized in that, Following the step of "etching the first conductor layer to form the first circuit layer", the method further includes: A first cover film is formed on the surface of the first dielectric layer away from the first conductor layer. The first cover film includes a first adhesive layer and a first protective layer. The first protective layer covers the surface of the first adhesive layer away from the first dielectric layer. The first adhesive layer and the first protective layer are provided with a first window. The first window penetrates the first protective layer and the first adhesive layer. A first groove is formed on the surface of the first dielectric layer away from the first metal layer, a portion of the first metal layer is exposed in the first groove, a plurality of first grooves are spaced apart, and the first window is connected to the first groove. A first coating is formed in the first groove, the first coating covering the surface of the first metal layer away from the first conductor layer; The first electronic component is installed inside the first window.

5. The method for manufacturing a circuit board as described in claim 3, characterized in that, The substrate further includes a second conductor layer, which is disposed on the other side of the substrate opposite to the first conductor layer, and the through-hole also penetrates the second conductor layer; The method for manufacturing the circuit board also includes: A second metal layer is formed on the surface of the second conductor layer, the second metal layer covering the surface of the second conductor layer away from the substrate layer and partially exposing the vias on the surface of the second conductor layer; A second dielectric layer is formed on the surface of the second conductor layer opposite to the substrate layer; The second dielectric layer is patterned by irradiating it with a laser. The second conductor layer is etched to form the second circuit layer.

6. The method for manufacturing a circuit board as described in claim 5, characterized in that, Following the step of "etching the second conductor layer to form the second circuit layer", the method further includes: A second cover film is formed on the surface of the second dielectric layer away from the second conductor layer. The second cover film includes a second adhesive layer and a second protective layer. The second protective layer covers the surface of the second adhesive layer away from the second dielectric layer. The second adhesive layer and the second protective layer are provided with a second opening. The second opening penetrates the second protective layer and the second adhesive layer. A second groove is formed on the surface of the second dielectric layer away from the second metal layer, a portion of the second metal layer is exposed in the second groove, a plurality of second grooves are spaced apart, and the second window is connected to the plurality of second grooves; A first plating layer is formed in the second groove, the first plating layer covering the surface of the second metal layer away from the second conductor layer; Electronic components are installed within the second window.

7. The method for manufacturing a circuit board as described in claim 6, characterized in that, The thickness of the first coating layer is less than the thickness of the second dielectric layer.

8. A circuit board, characterized in that, include: An inner circuit board includes a first dielectric layer, a first metal layer, a first conductor layer and a substrate layer stacked sequentially. The first dielectric layer is provided with a first groove, a portion of the first metal layer is exposed in the first groove, and a plurality of the first grooves are spaced apart. A first conductive connector is disposed in the first groove and is electrically connected to the first metal layer. A first electronic component, which is electrically connected to the inner circuit board via the first conductive connector; The bottom filler covers the inner circuit board and the first conductive connector, which are exposed on the surface of the first electronic component.

9. The circuit board as described in claim 8, characterized in that, The inner circuit board further includes a second conductor layer, a second metal layer, and a second dielectric layer stacked sequentially. The second dielectric layer covers the surface of the second metal layer away from the second conductor layer. The second dielectric layer has a second groove, and a portion of the second metal layer is exposed in the second groove. Multiple second grooves are spaced apart. A first plating layer is provided at the bottom of the second groove. The thickness of the first plating layer is less than the thickness of the second dielectric layer. The second electronic component is electrically connected to the first plating layer through a second conductive connector.

10. The circuit board as described in claim 8, characterized in that, The circuit board further includes a first cover film, which covers the surface of the first dielectric layer away from the first conductor layer. The first cover film includes a first adhesive layer and a first protective layer. The first protective layer covers the surface of the first adhesive layer away from the first dielectric layer. The first adhesive layer and the first protective layer are provided with a first opening, which penetrates the first protective layer and the first adhesive layer. The first groove is exposed in the first opening.

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