Semiconductor devices and their fabrication methods, memory systems

Abstract

This disclosure provides a semiconductor device and a method for fabricating the same, as well as a memory system. The semiconductor device includes a first electrode and a first insulating layer. The first electrode extends along a first direction and includes a first end face, a second end face, and a sidewall. The first end face and the second end face are disposed opposite to each other in the first direction, and the sidewall connects the first end face and the second end face. The first insulating layer surrounds at least a portion of the sidewall of a first end face of the first electrode and is located on the side of the first end face opposite to the second end face.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a memory system, and a method for fabricating a semiconductor device. Background Technology

[0002] Semiconductor devices can be used in memory, such as Dynamic Random Access Memory (DRAM). DRAM is widely used in electronic devices such as computers and mobile phones due to its simple structure, large capacity, high density, low power consumption, and high speed. However, with the development of technology nodes, the improvement of the electrical performance of semiconductor devices and the reduction of manufacturing complexity have encountered bottlenecks. Summary of the Invention

[0003] In a first aspect, some embodiments of this disclosure provide a semiconductor device. The semiconductor device includes a first electrode and a first insulating layer. The first electrode extends along a first direction and includes a first end face, a second end face, and a sidewall. The first end face and the second end face are disposed opposite to each other in the first direction, and the sidewall connects the first end face and the second end face. The first insulating layer surrounds at least a portion of the sidewall of a first end face of the first electrode and is located on the side of the first end face opposite to the second end face.

[0004] In an exemplary embodiment, the dimension of the first electrode in the first direction is greater than 950 nm.

[0005] In an exemplary embodiment, the ratio of the dimension of the first electrode in the first direction to the dimension of the first electrode in the direction intersecting the first direction is greater than 33.

[0006] In an exemplary embodiment, a plurality of first electrodes are arranged at intervals; a portion of the first insulating layer is located on the side of the first end face of each first electrode that faces away from the second end face.

[0007] In an exemplary embodiment, the first insulating layer contacts at least a portion of the sidewall of the first end and contacts the first end face.

[0008] In an exemplary embodiment, the first insulating layer includes a first extension and a second extension. The first extension surrounds at least a portion of the sidewall of the first end face; the second extension is located on the side of the first end face facing away from the second end face; wherein the surfaces of the first extension and the second extension facing away from the first end face in a first direction are coplanar.

[0009] In an exemplary embodiment, the material of the first insulating layer includes at least one of the following: silicon nitride, silicon carbonitride, and silicon boronitride.

[0010] In an exemplary embodiment, the semiconductor device further includes a second electrode and a capacitor dielectric layer. A portion of the second electrode is located on one side of the first electrode in a direction intersecting the first direction, and a portion of the second electrode is located on opposite sides of the first insulating layer in the first direction; a portion of the capacitor dielectric layer is located between the first electrode and the second electrode.

[0011] In an exemplary embodiment, the semiconductor device further includes a second insulating layer. The second insulating layer is spaced apart from the first insulating layer in a first direction and surrounds at least a portion of the sidewall of the first electrode; wherein a portion of the second electrode is located on opposite sides of the second insulating layer in the first direction.

[0012] In an exemplary embodiment, a portion of the capacitor dielectric layer and a portion of the second electrode pass through the first insulating layer and the second insulating layer along a first direction.

[0013] In an exemplary embodiment, the semiconductor device further includes a semiconductor body. The semiconductor body extends along a first direction. The semiconductor device is located on one side of the first electrode in the first direction and away from the first end face.

[0014] In an exemplary embodiment, the semiconductor device further includes a gate structure and a gate dielectric layer. The gate structure is located on at least one side of the semiconductor body in a direction intersecting the first direction; the gate dielectric layer is located between the semiconductor body and the gate structure.

[0015] In an exemplary embodiment, the semiconductor device further includes a connection structure. The connection structure extends along a first direction and is connected to a second end face and a semiconductor body.

[0016] Secondly, some embodiments of this disclosure provide a memory system. The memory system includes a memory and a controller, the memory including semiconductor devices as mentioned in any of the embodiments described above. The controller is coupled to the memory and is used to control the memory to store data.

[0017] Thirdly, some embodiments of this disclosure provide a method for fabricating a semiconductor device. The method for fabricating this semiconductor device includes:

[0018] A hole is formed through the first sacrificial layer and the stacked structure along a first direction, wherein the first sacrificial layer is located on one side of the stacked structure in the first direction; a first electrode is formed in the hole; the first sacrificial layer is removed, wherein the end of the first electrode protrudes from the stacked structure; and a first insulating layer is formed around at least a portion of the sidewall of the end.

[0019] In an exemplary embodiment, forming a first insulating layer around at least a portion of the sidewall of the end comprises: forming an initial first insulating layer on one side of the laminated structure and the end in a first direction; forming a first opening through the initial first insulating layer to obtain the first insulating layer, wherein a portion of the first insulating layer is located on one side of the end in the first direction.

[0020] In an exemplary embodiment, the stacked structure includes a second sacrificial layer and an initial second insulating layer alternately disposed in a first direction, with a first opening exposing the second sacrificial layer; wherein the preparation method further includes: forming a second opening penetrating the initial second insulating layer to obtain a second insulating layer; and removing the second sacrificial layer via the first opening and / or the second opening.

[0021] In an exemplary embodiment, the first insulating layer and the second insulating layer are made of the same material, and at least a portion of the first sacrificial layer, the second sacrificial layer, and the first insulating layer are made of different materials.

[0022] In an exemplary embodiment, the preparation method further includes: forming a capacitor dielectric layer on one side of the first electrode in the direction intersecting with the first direction and on opposite sides of the first insulating layer in the first direction; and forming a second electrode on the side of the capacitor dielectric layer away from the first electrode and the first insulating layer.

[0023] In an exemplary embodiment, after removing the first sacrificial layer, the preparation method further includes forming a third sacrificial layer on one side of the second sacrificial layer in the first direction, and making the end protrude beyond the third sacrificial layer. For example, the material of the third sacrificial layer is the same as the material of the second sacrificial layer.

[0024] In an exemplary embodiment, the preparation method further includes:

[0025] A semiconductor body extending along a first direction is formed, wherein a stacked structure is formed on one side of the semiconductor body in the first direction; a gate structure is formed on at least one side of the semiconductor body in a direction intersecting the first direction; and a gate dielectric layer is formed between the gate structure and the semiconductor body. Attached Figure Description

[0026] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0027] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0028] Figure 2 This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure, taken on another plane;

[0029] Figure 3This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0030] Figures 4A to 4P This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this disclosure during the fabrication process;

[0031] Figure 5 This is a schematic block diagram of a system with a memory system provided in the embodiments of this disclosure; and

[0032] Figure 6A and Figure 6B This is a schematic block diagram of a memory system provided in an embodiment of this disclosure. Detailed Implementation

[0033] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this disclosure, the first electrode discussed herein may also be referred to as the second electrode, and vice versa.

[0035] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0036] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0037] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0038] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0039] Furthermore, when the term “connection” or “linkage” is used in this disclosure, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0040] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] This disclosure provides a semiconductor device through some embodiments. Figure 1 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Figure 2 This is a schematic cross-sectional view of the semiconductor device provided in this embodiment of the disclosure, taken on another plane. For example, Figure 2 It can be along Figure 1 The diagram shows a cross-section of the plane containing line AA.

[0042] It should be noted that the D1 direction (corresponding to the first direction), the D2 direction, and the D3 direction in the following figures illustrate the spatial relationships of the components in the semiconductor device. For example, the D1 direction may be the extension direction of the first electrode, and the D2 and D3 directions may be two directions that intersect (e.g., are perpendicular) to each other on planes that intersect (e.g., are perpendicular) to the aforementioned extension directions. The same concepts will be used throughout this disclosure to describe the spatial relationships of the components in the semiconductor device.

[0043] like Figure 1As shown, the semiconductor device 100 may include a first electrode 110 and a first insulating layer 120. The first electrode 110 may include a first end face 111, a second end face 112, and a sidewall 113. The first end face 111 and the second end face 112 are disposed opposite each other in the D1 direction, and the sidewall 113 connects the first end face 111 and the second end face 112. The first insulating layer 120 may surround at least a portion of the sidewall of the first end face 114 of the first electrode 110 and is located on the side of the first end face 111 opposite to the second end face 112. Having a first insulating layer 120 partially located on the side of the first end face 111 opposite to the second end face 112 also helps to improve the support performance of the first electrode 110. Especially for the first electrode 110 with a large size in the D1 direction, the first insulating layer 120 can improve the structural stability of the first electrode 110, thereby improving the yield of the semiconductor device 100.

[0044] In some embodiments, the first electrode 110 may be a columnar structure. Optionally, the columnar structure may have an angle. For example, the first electrode 110 may be a cylindrical structure with an angle. The first end face 111 and the second end face 112 may be generally circular. The sidewall 113 may be generally cylindrical. The first electrode 110 may serve as one plate of a capacitor C. Such a capacitor C may be referred to as a columnar capacitor.

[0045] In some embodiments, the first end portion 114 of the first electrode 110 may be a portion of the first electrode 110 including a first end face 111 and a portion of a sidewall 113. The sidewall of the first end portion 114 may surround the first end face 111 and its dimension in the D1 direction is smaller than the dimension of the sidewall 113 of the first electrode 110 in the D1 direction. The second end portion 115 of the first electrode 110 may be a portion of the first electrode 110 including a second end face 112 and a portion of a sidewall 113. The sidewall of the second end portion 115 may surround the second end face 112 and its dimension in the D1 direction is smaller than the dimension of the sidewall 113 of the first electrode 110 in the D1 direction.

[0046] In some embodiments, the dimension of the first electrode 110 in the D1 direction may be greater than 950 nm. For example, the dimension of the first electrode 110 in the D1 direction may be between 1100 nm and 1200 nm. Specifically, the dimension of the first electrode 110 in the D1 direction may be 1000 nm, 1050 nm, 1100 nm, 1150 nm, and 1200 nm, etc. The dimension of the first electrode 110 in the D1 direction is related to the charge storage capacity of the capacitor C. For example, when the first electrode 110 has a predetermined area in a plane perpendicular to the D1 direction, the larger the dimension of the first electrode 110 in the D1 direction, the stronger the charge storage capacity of the capacitor C.

[0047] In some embodiments, the ratio of the dimension of the first electrode 110 in the D1 direction to the dimension of the first electrode 110 in a direction intersecting the D1 direction (e.g., the D2 or D3 direction) is greater than 33. For example, this ratio may be greater than 40. For instance, this ratio may be 35, 40, 45, and 50, etc. A large ratio for the first electrode 110 places higher demands on the performance of the etching equipment. In the semiconductor device 100, since a first insulating layer 120, partially located on the side of the first end face 111 facing away from the second end face 112, is formed after the formation of the first electrode 110, the performance requirements of the etching equipment can be reduced, which helps to save costs.

[0048] In some embodiments, the material of the first electrode 110 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, doped semiconductors (e.g., doped polycrystalline silicon), or any other suitable conductive material. For example, the first electrode 110 may be made of a single material (e.g., titanium nitride).

[0049] In some implementations, such as Figure 2 As shown, a plurality of first electrodes 110 are arranged at intervals. For example, viewed from the D1 direction, the plurality of first electrodes 110 are arranged in an array. Adjacent first electrodes 110 in the D2 direction are spaced apart. Adjacent first electrodes 110 in the D3 direction are spaced apart.

[0050] In some embodiments, the first insulating layer 120 may extend along both the D2 and D3 directions. The dimensions of the first insulating layer 120 in the D2 and D3 directions may be larger than its dimensions in the D1 direction. For example, the first insulating layer 120 may be a layered structure having thickness in the D1 direction. Furthermore, the dimensions of the first insulating layer 120 in the D1 direction may be smaller than the dimensions of the first electrode 110 in the D1 direction.

[0051] In some embodiments, the first insulating layer 120 may include a first extension 121 and a second extension 122. The first extension 121 may surround at least a portion of the sidewall of the first end face 114. The second extension 122 may be located on the side of the first end face 111 opposite to the second end face 112. The surfaces of the first extension 121 and the second extension 122 are coplanar opposite to the first end face 111 in the D1 direction. For example, when the semiconductor device 100 is in Figure 1 In the shown placement position, the upper surface of the first extension 121 is higher than the first end face 111, and the lower surface of the first extension 121 is lower than the first end face 111. The second extension 122 is located above the first end face 111. The upper surfaces of the first extension 121 and the second extension 122 are approximately flush.

[0052] It should be noted that the first extension 121 and the second extension 122 are for further illustrating the positional relationship between the various parts of the first insulating layer 120 and the first electrode 110. In some practical applications, the first extension 121 and the second extension 122 may be an integral structure, with no interface between them.

[0053] In some embodiments, the first insulating layer 120 contacts at least a portion of the sidewall of the first end 114 and contacts the first end face 111. For example, the first extension 121 may contact at least a portion of the sidewall of the first end 114, and the second extension 122 may contact the first end face 111.

[0054] In some embodiments, when multiple first electrodes 110 are arranged at intervals, a portion of the first insulating layer 120 (e.g., the second extension 122) may be located on the side of the first end face 111 of each first electrode 110 that faces away from the second end face 112 (e.g., in contact).

[0055] In some implementations, such as Figure 1 and Figure 2 As shown, viewed from the D1 direction, the first insulating layer 120 may have one or more first cutouts 123. For example, the first cutouts 123 may be generally circular, elliptical, rectangular, or other irregular shapes. A single first cutout 123 may be located between adjacent first electrodes 110. For example, viewed from the D1 direction, four first electrodes 110 may surround a first cutout 123. When the first cutout 123 exposes the first electrodes 110, the first insulating layer 120 (e.g., the first extension 121) may surround a portion of the sidewall of the first end portion 114. When the first cutout 123 does not expose the first electrodes 110 (e.g., the first cutout has a smaller size in a plane perpendicular to the D1 direction), the first insulating layer 120 (e.g., the first extension 121) may surround the entire sidewall of the first end portion 114 (not shown).

[0056] It should be noted that the first cutout 123 is for further illustrating the morphology of the first insulating layer 120, and does not indicate that the first insulating layer 120 is empty at the location of the first cutout 123. In some practical applications, the capacitor dielectric layer 141, the second electrode 142, and the conductive layer 143 are located at the location of the first cutout 123. The capacitor dielectric layer 141, the second electrode 142, and the conductive layer 143 will be described in detail below.

[0057] In some embodiments, the material of the first insulating layer 120 may include one or more of silicon nitride, silicon carbonitride, silicon boronitride, and any other suitable insulating material.

[0058] In some implementations, such as Figure 1As shown, the semiconductor device 100 may further include a second insulating layer 131. The second insulating layer 131 is spaced apart from the first insulating layer 120 in the D1 direction. The second insulating layer 131 may extend along the D2 and D3 directions. The dimensions of the second insulating layer 131 in the D2 and D3 directions may be larger than its dimensions in the D1 direction. For example, the second insulating layer 131 may be a layered structure with a substantially uniform thickness in the D1 direction. Furthermore, the dimensions of the second insulating layer 131 in the D1 direction may be smaller than the dimensions of the first electrode 110 in the D1 direction.

[0059] In some embodiments, viewed from the D1 direction, the second insulating layer 131 may have one or more second cutouts 132. For example, the second cutouts 132 may be generally circular, elliptical, rectangular, or other irregular shapes. A single second cutout 132 may be located between adjacent first electrodes 110. As an example, viewed from the D1 direction, the projection of the first cutout 123 may substantially overlap with the projection of the second cutout 132. When the second cutout 132 exposes the first electrode 110, the second insulating layer 131 may surround a portion of the sidewall of the middle portion of the first electrode 110. When the second cutout 132 does not expose the first electrode 110 (e.g., the second cutout has a smaller size in a plane perpendicular to the D1 direction), the second insulating layer 131 may surround the entire sidewall of the middle portion of the first electrode 110.

[0060] It should be noted that, similarly, the second cutout 132 is for further illustrating the morphology of the second insulating layer 131, and does not indicate that the second insulating layer 131 is empty at the location of the second cutout 132. In some practical applications, the capacitor dielectric layer 141, the second electrode 142, and the conductive layer 143 are located at the location of the second cutout 132.

[0061] In some embodiments, the number of second insulating layers 131 may be one or more. When the number of second insulating layers 131 is multiple (not shown), the multiple second insulating layers 131 may be spaced apart in the D1 direction. For example, the multiple second insulating layers 131 may be arranged substantially parallel. The spacing between adjacent second insulating layers 131 may be the same or different. The dimensions of each second insulating layer 131 and the first insulating layer 120 in the D1 direction may be the same or different from each other. Increasing the number of second insulating layers 131 can further improve the structural stability of the first electrode 110.

[0062] In some embodiments, the material of the second insulating layer 131 may include one or more of silicon nitride, silicon carbonitride, silicon boronitride, and any other suitable insulating material.

[0063] In some implementations, such as Figure 1As shown, the semiconductor device 100 may further include a third insulating layer 133. The third insulating layer 133 and (e.g., the closest) second insulating layer 131 have a spacing distance in the D1 direction. For example, when the semiconductor device 100 is in Figure 1 In the shown placement, the lower surface of the third insulating layer 133 is substantially flush with the second end face 112. Furthermore, the third insulating layer 133 may extend along both the D2 and D3 directions. The dimensions of the third insulating layer 133 in the D2 and D3 directions may be larger than its dimension in the D1 direction. For example, the third insulating layer 133 may be a layered structure with a substantially uniform thickness in the D1 direction. The dimension of the third insulating layer 133 in the D1 direction may be smaller than the dimension of the first electrode 110 in the D1 direction.

[0064] In some embodiments, the third insulating layer 133 may surround the entire sidewall of the second end portion 115 of the first electrode 110. The third insulating layer 133 not only provides support for the first electrode 110, but also serves as an etching stop layer during the formation of the capacitor C.

[0065] In some embodiments, the material of the third insulating layer 133 may include one or more of silicon nitride, silicon carbonitride, silicon boronitride, and any other suitable insulating material.

[0066] In some implementations, such as Figure 1 As shown, the semiconductor device 100 may further include a capacitor dielectric layer 141 and a second electrode 142. A portion of the capacitor dielectric layer 141 may be located on one side of the first electrode 110 in the direction intersecting the D1 direction, and a portion of the capacitor dielectric layer 141 may be located on opposite sides of the first insulating layer 120 in the D1 direction. Optionally, a portion of the capacitor dielectric layer 141 may also be located on opposite sides of the second insulating layer 131 in the D1 direction, and a portion of the capacitor dielectric layer 141 may also be located on the side of the third insulating layer 133 facing the second insulating layer 131. The second electrode 142 may be located on the side of the capacitor dielectric layer 141 away from the first electrode 110 and the first insulating layer 120. Optionally, the second electrode 142 may be located on the side of the capacitor dielectric layer 141 away from the second insulating layer 131 and the third insulating layer 133. For example, the first electrode 110 may be in contact with the capacitor dielectric layer 141. In other words, a portion of the second electrode 142 may be located on one side of the first electrode 110 in the direction intersecting with the D1 direction, and a portion of the second electrode 142 may be located on opposite sides of the first insulating layer 120 in the D1 direction. A portion of the capacitor dielectric layer 141 may be located between the first electrode 110 and the second electrode 142. The second electrode 142 may have a layered structure. The second electrode 142 may serve as the other plate of the capacitor C.

[0067] In some embodiments, when multiple first electrodes 110 are arranged at intervals, the capacitor dielectric layers 141 corresponding to each first electrode 110 can be connected to each other and can be a single structure. The second electrodes 142 corresponding to each first electrode 110 can also be connected to each other and can be a single structure.

[0068] In some embodiments, the material of the capacitor dielectric layer 141 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating materials. High dielectric constant materials may include, but are not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide, etc. The material of the second electrode 142 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, doped semiconductors, or any other suitable conductive materials. For example, the material of the second electrode 142 may be titanium nitride.

[0069] In some implementations, such as Figure 1 As shown, the semiconductor device 100 may further include a conductive layer 143. The conductive layer 143 may be located on the side of the second electrode 142 opposite to the capacitor dielectric layer 141. The conductive layer 143 may be used to provide a relatively flat surface perpendicular to the D1 direction. For example, the material of the conductive layer 143 may include germanium-silicon.

[0070] In some embodiments, a portion of the capacitor dielectric layer 141 and a portion of the second electrode 142 may pass through the first insulating layer 120 and the second insulating layer 131 along the D1 direction. For example, when the first insulating layer 120 has a first cutout 123 and the second insulating layer 131 has a second cutout 132, a portion of the capacitor dielectric layer 141 and a portion of the second electrode 142 may pass through the first insulating layer 120 and the second insulating layer 131 at the locations of the first cutout 123 and the second cutout 132. Optionally, the conductive layer 143 may also pass through the first insulating layer 120 and the second insulating layer 131 along the D1 direction at the locations of the first cutout 123 and the second cutout 132.

[0071] In some implementations, such as Figure 1 As shown, the semiconductor device 100 may further include a semiconductor body 151. The semiconductor body 151 may extend along the D1 direction and may be located on one side of the first electrode 110 in the D1 direction and away from the first end face 111. For example, the size of the semiconductor body 151 in the D1 direction may be larger than its size in the D2 direction and may be larger than its size in the D3 direction. The semiconductor body 151 may generally be a columnar structure (e.g., a quadrangular prism) extending along the D1 direction. For example, the semiconductor body 151 may serve as the channel and active region of the transistor T.

[0072] In some embodiments, the material of the semiconductor body 151 may include silicon, germanium, silicon germanium, silicon carbide, gallium nitride, or any other suitable semiconductor material. For example, the material of the semiconductor body 151 may be silicon (e.g., single-crystal silicon).

[0073] In some embodiments, a plurality of semiconductor bodies 151 may be arranged at intervals. For example, viewed from the D1 direction, a plurality of semiconductor bodies 151 are arranged in an array. Adjacent semiconductor bodies 151 in the D2 direction are spaced apart. Adjacent semiconductor bodies 151 in the D3 direction are also spaced apart. For example, the ends of each semiconductor body 151 in a row arranged in the D2 direction that are away from the first electrode 110 are connected to each other.

[0074] In some implementations, such as Figure 1 As shown, the semiconductor device 100 may further include a gate structure 152. The gate structure 152 may be located on one side of the semiconductor body 151 in a direction intersecting the D1 direction. The dimension of the gate structure 152 in the D1 direction may be smaller than the dimension of the semiconductor body 151 in the D1 direction. In some examples, the gate structure 152 may be located on one side of the semiconductor body 151 in the D2 direction. In other examples, the gate structure 152 may be located on opposite sides of the semiconductor body 151 in the D2 direction. In still other examples, the gate structure 152 may be located on opposite sides of the semiconductor body 151 in both the D2 and D3 directions. Furthermore, the gate structure 152 may extend along the D3 direction. For example, the gate structure 152 may be connected to a row of semiconductor bodies 151 arranged along the D3 direction.

[0075] In some embodiments, when the gate structure 152 is located on one side of the semiconductor body 151 in the D2 direction, such as Figure 1 As shown, the gate structure 152 has a rectangular shape in the plane perpendicular to the D3 direction. The size of this rectangle in the D1 direction can be larger than its size in the D2 direction.

[0076] In some embodiments, the material of the gate structure 152 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. For example, the material of the gate structure 152 may include tungsten and titanium nitride.

[0077] In some implementations, such as Figure 1As shown, the semiconductor device 100 may further include a gate dielectric layer 153. The gate dielectric layer 153 may be located between the gate structure 152 and the semiconductor body 151. The gate dielectric layer 153 may be in contact with both the gate structure 152 and the semiconductor body 151. The material of the gate dielectric layer 153 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating material. High dielectric constant materials may include, but are not limited to, alumina, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide, etc. For example, the material of the gate dielectric layer 153 may be silicon oxide.

[0078] The semiconductor body 151, the gate dielectric layer 153, and the gate structure 152 can constitute a transistor T. The two ends of the semiconductor body 151 respectively serve as the two active regions of the transistor T. For example, when the semiconductor device 100 is in... Figure 1 In the illustrated placement, the upper end of the semiconductor body 151 can be the source of the transistor T, and the lower end of the semiconductor body 151 can be the drain of the transistor T. Integrating the channel and active region of the transistor T in the vertical direction helps to save on the planar area of ​​the transistor T.

[0079] In some implementations, such as Figure 1 As shown, when the gate structure 152 is located on one side of the semiconductor body 151 in the D2 direction, the semiconductor device 100 may further include a first isolation structure 154. The first isolation structure 154 may extend along the D3 direction and may be located between adjacent rows (arranged in the D3 direction) of semiconductor bodies 151. The gate structure 152 and the gate dielectric layer 153 may be located between the first isolation structure 154 and the semiconductor body 151. A row of semiconductor bodies 151, the gate structure 152, and the gate dielectric layer 153 are arranged in a mirror-symmetric manner with respect to the first isolation structure 154.

[0080] In some embodiments, the material of the first insulating structure 154 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the first insulating structure 154 may include silicon oxide.

[0081] In some implementations, such as Figure 1 As shown, when the gate structure 152 is located on one side of the semiconductor body 151 in the D2 direction, the semiconductor device 100 may further include a second isolation structure 155. The second isolation structure 155 may extend along the D3 direction and may be located between adjacent rows (arranged in the D3 direction) of semiconductor bodies 151. The first isolation structure 154 and the second isolation structure 155 are alternately arranged in the D2 direction. The material of the second isolation structure 155 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material.

[0082] In some embodiments, the second isolation structure 155 may include an air gap. This air gap can shield adjacent transistors T.

[0083] In other embodiments, the second isolation structure 155 may be replaced by a conductive structure and a dielectric layer (not shown). The conductive structure may extend along the D3 direction and may be located between adjacent columns (arranged in the D3 direction) of semiconductor bodies 151. The dielectric layer may be located between the conductive structure and the semiconductor bodies 151. For example, the dielectric layer is in contact with both the conductive structure and the semiconductor bodies. The material of the conductive structure may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, doped semiconductors, or any other suitable conductive material. The material of the dielectric layer may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating materials. High dielectric constant materials may include, but are not limited to, alumina, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide, etc.

[0084] During operation of the semiconductor device 100, the conductive structure can shield adjacent transistors T, thereby reducing mutual interference between adjacent transistors T. For example, during operation of the semiconductor device 100, the conductive structure can be configured to apply a ground voltage or a negative voltage. The dielectric layer can electrically isolate the conductive structure and the semiconductor body 151.

[0085] In some implementations, such as Figure 1 As shown, the semiconductor device 100 may further include a bit line structure 171. The bit line structure 171 may be located on the side of the semiconductor body 151 facing away from the first electrode 110 in the D1 direction and may extend along the D2 direction. The bit line structure 171 may be connected (e.g., contacted) to a row of semiconductor bodies 151 arranged in the D2 direction (e.g., the interconnected portions of the ends of each semiconductor body 151 in the row). Furthermore, a plurality of bit line structures 171 may be spaced apart in the D3 direction. The material of the bit line structure 171 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, metal silicide, or any other suitable conductive material.

[0086] In some implementations, such as Figure 1 As shown, the semiconductor device 100 may further include a connection structure 161. The connection structure 161 may extend along the D1 direction and may be connected to the second end face 112 and the semiconductor body 151. For example, the connection structure 161 may be generally columnar. One of the two end faces of the connection structure 161 disposed opposite each other in the D1 direction contacts the second end face 112 of the first electrode 110, and the other contacts the end face of the semiconductor body 151 that is away from the bit line structure 171 in the D1 direction.

[0087] Connection structure 161 can be used to connect capacitor C and transistor T. Specifically, the first electrode 110 of capacitor C can be electrically connected to, for example, the source of transistor T through connection structure 161. Capacitor C and transistor T can constitute a memory cell, for example, a DRAM memory cell. Capacitor C can be used to implement data storage, and transistor T can act as a switch to access the data in capacitor C.

[0088] In some implementations, such as Figure 1 As shown, the connection structure 161 may include a first connection portion 1611, a metal silicide layer 1612, and a second connection portion 1613 sequentially connected along the D1 direction. For example, the first connection portion 1611 contacts the metal silicide layer 1612 and the semiconductor body 151. The metal silicide layer 1612 contacts the first connection portion 1611 and the second connection portion 1613. The second connection portion 1613 contacts the second end face 112. The material of the first connection portion 1611 may include a doped semiconductor, such as doped polysilicon. The material of the metal silicide layer 1612 may include one or more of titanium silicon, cobalt silicon, nickel silicon, platinum silicon, or other metal silicide materials. The material of the second connection portion 1613 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. The connection structure 161, constructed from the above-described composite material, can be used to form an ohmic contact to reduce the contact resistance between the first electrode 110 and the semiconductor body 151.

[0089] In some embodiments, the semiconductor device 100 may further include a peripheral circuit structure (not shown). The peripheral circuit structure may be located on the side of the semiconductor body 151 opposite to the first electrode 110 in the D1 direction. Alternatively, the peripheral circuit structure may be located on the side of the first electrode 110 opposite to the semiconductor body 151 in the D1 direction. In other words, the semiconductor body 151 (or transistor T), the first electrode 110 (or capacitor C), and the peripheral circuit structure may be stacked in the D1 direction.

[0090] In some implementations, the peripheral circuitry may include any suitable digital, analog, and / or mixed-signal peripheral circuitry for controlling the operation of the memory cell array. For example, this peripheral circuitry may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0091] This disclosure also provides a method for fabricating a semiconductor device in some embodiments. Figure 3 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure. Figure 3 As shown, the semiconductor device fabrication method 200 (hereinafter referred to as fabrication method 200) may include the following steps.

[0092] S210, forming a hole that penetrates the first sacrificial layer and the stacked structure along a first direction, wherein the first sacrificial layer is located on one side of the stacked structure in the first direction.

[0093] S220, forming the first electrode in the hole.

[0094] S230, Remove the first sacrificial layer, wherein the end of the first electrode protrudes from the stacked structure.

[0095] S240, forming a first insulating layer around at least a portion of the sidewall at the end.

[0096] In the fabrication method 200 provided in this embodiment, the first insulating layer is formed after the first electrode is formed. The step of etching the first insulating layer can be omitted during the formation of the first electrode, reducing the difficulty of etching the stacked structure. In other words, while maintaining a preset (e.g., maximized) etching capability for the stacked structure, it helps to increase the size of the first electrode in the first direction.

[0097] Figures 4A to 4P This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this disclosure during the fabrication process. Specifically, Figure 4A The intermediate structure following the formation of the patterned first sacrificial layer is shown. Figure 4B The intermediate structure after the formation of the hole is shown. Figure 4C The intermediate structure after the deposition of conductive material is shown. Figure 4D The intermediate structure after the formation of the first electrode is shown. Figure 4E The intermediate structure after the formation of the covering layer is shown. Figure 4F The intermediate structure after removing the overlay and the first mask layer is shown. Figure 4G The intermediate structure after removing the first sacrificial layer is shown. Figure 4H The intermediate structure following the deposition of sacrificial material is shown. Figure 4I The intermediate structure after the formation of the third sacrificial layer is shown. Figure 4J The intermediate structure after the formation of the initial first insulating layer is shown. Figure 4K The intermediate structure following the formation of the patterned second and third mask layers is shown. Figure 4L The intermediate structure after the formation of the first opening is shown. Figure 4M The intermediate structure after removing part of the second sacrificial layer is shown. Figure 4N The intermediate structure after the formation of the second opening is shown. Figure 4OThe intermediate structure after removing another portion of the second sacrificial layer is shown. Figure 4P The semiconductor device after the capacitor is formed is shown.

[0098] It should be noted that the "intermediate structure" referred to in this disclosure can be a structure formed during the fabrication of a semiconductor device. Furthermore, to clearly illustrate the components related to steps S210 to S240 described above, Figures 4B to 4O The semiconductor body, gate structure, and gate dielectric layer, among other related components, are omitted from the diagram.

[0099] The following is combined Figures 4A to 4P The preparation method 200, which includes steps S210 to S240, will be described by way of example.

[0100] Preparation method 200 begins with step S210. For example... Figure 4A As shown, for example, the stacked structure 381 may be a composite layered structure extending along the D2 and D3 directions and having a thickness in the D1 direction. The first sacrificial layer 382 may be formed on one side (e.g., the surface) of the stacked structure 381 in the D1 direction by an oxidation process or a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0101] In some embodiments, the stacked structure 381 may include second sacrificial layers 384-1 and 384-2 and an initial second insulating layer 331' alternately disposed in the D1 direction. For example, the second sacrificial layer 384-1, the initial second insulating layer 331', and the second sacrificial layer 384-2 are alternately disposed in the D1 direction. The second sacrificial layers 384-1, 384-2, and the initial second insulating layer 331' may be formed by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, the size of the initial second insulating layer 331' in the D1 direction may be smaller than the size of each of the second sacrificial layers 384-1 and 384-2 in the D1 direction.

[0102] It should be noted that, Figure 4A The illustrated stacked structure 381, having two second sacrificial layers 384-1 and 384-2 and one initial second insulating layer 331', is merely an example. In other examples, the stacked structure 381 may have a greater number (e.g., greater than 2) of second sacrificial layers and a greater number (e.g., greater than 1) of initial second insulating layers. This disclosure does not impose specific limitations on the number of second sacrificial layers and initial second insulating layers included in the stacked structure. Furthermore, the surface of the second sacrificial layer in the D1 direction may serve as the outer surface of the stacked structure in the D1 direction.

[0103] In some embodiments, the materials of the second sacrificial layers 384-1 and 384-2 may be different from the material of the initial second insulating layer 331', such that the second sacrificial layers 384-1 and 384-2 and the initial second insulating layer 331' have different etching selectivity ratios relative to the same etching material.

[0104] In some embodiments, the material of the second sacrificial layers 384-1 and 384-2 may include one or more of silicon oxide, boron silicon oxide, phosphorus silicon oxide, boron phosphorus silicon oxide, or any other suitable removable material. The materials of the various second sacrificial layers 384-1 and 384-2 may be the same or different, and this disclosure does not limit this. The material of the initial second insulating layer 331' may include one or more of silicon nitride, boron silicon nitride, silicon carbonitride, or any other suitable material.

[0105] In some embodiments, the first sacrificial layer 382 may be a layered structure extending along the D2 and D3 directions and having a thickness in the D1 direction. In some examples, the first sacrificial layer 382 may be a composite layered structure. The first sacrificial layer 382 may include a first sublayer 3821 and a second sublayer 3822. The first sublayer 3821 and the second sublayer 3822 may be formed sequentially on the side of the stacked structure 381 away from it along the D1 direction. The first sublayer 3821 may be in contact with the second sacrificial layer 384-2 in the stacked structure 381. The dimension of the first sublayer 3821 in the D1 direction may be larger than the dimension of the second sublayer 3822 in the D1 direction. For example, the material of the first sublayer 3821 may include silicon. The material of the second sublayer 3822 may include silicon oxide. In other examples, the first sacrificial layer 382 may be composed of a single material, and this disclosure does not specifically limit this.

[0106] In some embodiments, at least a portion of the first sacrificial layer 382 is made of a different material than the second sacrificial layers 384-1 and 384-2 in the laminated structure 381. When the first sacrificial layer 382 may be a composite layered structure, the portion of the first sacrificial layer 382 that contacts the second sacrificial layer 384-2 (e.g., the first sublayer 3821) is made of a different material than the second sacrificial layer 384-2.

[0107] In step S210, as Figure 4A and Figure 4BAs shown, the pattern for forming the hole 385 can be transferred to the first sacrificial layer 382 using the first mask layer 383. For example, the first mask layer 383 can be a hard mask or photoresist. Next, the patterned first sacrificial layer 382 can be used to form the hole 385 penetrating the stacked structure 381 (e.g., the second sacrificial layer 384-2, the initial second insulating layer 331', and the second sacrificial layer 384-1) along the D1 direction by an etching process (e.g., dry etching and / or wet etching). If at least a portion of the first sacrificial layer 382 is made of a different material than the second sacrificial layer 384-2 in the stacked structure 381, at least a portion of the first sacrificial layer 382 can act as an etching mask during the formation of the hole 385. Optionally, at least a portion of the first mask layer 383 can be removed after the patterned first sacrificial layer 382 is formed.

[0108] After the above-described process, the hole 385 can penetrate the first sacrificial layer 382 and the stacked structure 381 along the D1 direction. The depth of the hole 385 can be determined based at least on the dimensions of the stacked structure 381 and the first sacrificial layer 382 in the D1 direction. Furthermore, the number of holes 385 can be multiple. Multiple holes 385 can be arranged at intervals.

[0109] In some embodiments, the preparation method 200 may further include the following steps prior to performing the step of forming the hole 385.

[0110] For example, refer again Figure 4A A semiconductor body 351 extending along the D1 direction can be formed. A stacked structure 381 can be formed on one side of the semiconductor body 351 in the D1 direction. Further, a gate structure 352 can be formed on at least one side of the semiconductor body 351 in a direction intersecting the D1 direction (e.g., one side in the D2 direction). Further, a gate dielectric layer 353 can be formed between the gate structure 352 and the semiconductor body 351. The semiconductor body 351, the gate structure 352, and the gate dielectric layer 353 can be formed by any process method known in the art, and the above-described components have been described in detail above; further details are omitted here.

[0111] For example, such as Figure 4AAs shown, an initial isolation layer (not shown) can be formed on one side of the semiconductor body 351 in the D1 direction using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The initial isolation layer may cover the end face of the semiconductor body 351 in the D1 direction. For example, the initial isolation layer (not shown) may be a layered structure extending along the D2 and D3 directions and having a thickness in the D1 direction. Further, a connection structure 361 can be formed through the initial isolation layer to the semiconductor body 351, resulting in an isolation layer 362. The material of the isolation layer 362 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material.

[0112] For example, such as Figure 4A As shown, an initial third insulating layer 333' can be formed on the side of the interconnect structure 361 facing away from the semiconductor body 351 in the D1 direction using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The stacked structure 381 can also form the initial third insulating layer 333' on the side facing away from the interconnect structure 361 in the D1 direction. For example, the second sacrificial layer 384-1 in the stacked structure 381 is in contact with the initial third insulating layer 333'. The material of the initial third insulating layer 333' can include one or more of silicon nitride, silicon carbonitride, silicon boron nitride, and any other suitable insulating material. For example, the material of the initial third insulating layer 333' can be the same as the material of the initial second insulating layer 331'. When the initial third insulating layer 333' is formed, such as... Figure 4B As shown, during the formation of hole 385, hole 385 can penetrate the initial third insulating layer 333' to the connecting structure 361, and thus obtain the third insulating layer 333.

[0113] Preparation method 200 proceeds to step S220. For example... Figure 4B and Figure 4C As shown, thin film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to achieve thin film deposition in... Figure 4B The top side of the intermediate structure shown is deposited with conductive material 386. This conductive material 386 can fill the holes 385. Further, as Figure 4C and Figure 4D As shown, the portion of conductive material 386 outside the hole 385 can be removed, and the conductive material 386 retained in the hole 385 can be the first electrode 310. It should be noted that the term "top side" in this disclosure refers to the side located at the top of each intermediate structure when it is in the placement position shown in the corresponding figures.

[0114] In some implementations, such as Figure 4D and Figure 4E As shown, it can be achieved through spin coating process. Figure 4DA capping layer 387 is formed on the top side of the intermediate structure shown. The capping layer 387 can be used to provide a flat surface perpendicular to the D1 direction. The material of the capping layer 387 may include organic carbon. Furthermore, it can be further processed using a chemical mechanical polishing (CMP) process. Figure 4E The intermediate structure shown is planarized, for example by removing the cover layer 387 and the first mask layer 383 until the second sublayer 3822 in the first sacrificial layer 382 and the end face of the first electrode 310 are exposed.

[0115] Preparation method 200 is executed up to step 230. For example... Figure 4F and Figure 4G As shown, the first sacrificial layer 382 can be removed by etching (e.g., wet etching) to expose the end of the first electrode 310. Thus, the end of the first electrode 310 protrudes from the stacked structure 381.

[0116] In some implementations, such as Figure 4H and Figure 4I As shown, the fabrication method 200 may further include forming a third sacrificial layer 389 on one side of the second sacrificial layer 384-2 in the stacked structure 381 in the D1 direction, and causing the end of the first electrode 310 to protrude beyond the third sacrificial layer 389. For example, as... Figure 4G and Figure 4H As shown, thin film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to achieve thin film deposition in... Figure 4G The top side of the intermediate structure shown is deposited with sacrificial material 388. This sacrificial material 388 may cover the end of the first electrode 310 that protrudes from the stacked structure 381. For example, the sacrificial material 388 may be the same material as the second sacrificial layer 384-2 (e.g., silicon oxide). Further, as... Figure 4H and Figure 4I As shown, a portion of the sacrificial material 388 can be removed by etching (e.g., wet etching and / or dry etching) to expose the end of the first electrode 310 again, and the remaining sacrificial material 388 can serve as a third sacrificial layer 389. In other words, the end of the first electrode 310 that is exposed again can protrude from the third sacrificial layer 389.

[0117] It should be noted that the purpose of forming the third sacrificial layer 389 is to reduce the size of the exposed end of the first electrode 310 in the D1 direction, so as to meet the requirements of the first insulating layer 320 to be formed subsequently (see reference). Figure 4L The design requirements for the thickness (e.g., dimensions in the D1 direction) of the first sacrificial layer 382. In some embodiments, the step of forming the third sacrificial layer 389 can be omitted by reasonably designing the thickness (e.g., dimensions in the D1 direction) of the first sacrificial layer 382.

[0118] Preparation method 200 proceeds to step S240. For example... Figures 4I to 4L As shown, a first insulating layer 320 may be formed around at least a portion of the sidewall of the end of the first electrode 310. For example, the first insulating layer 320 and the initial second insulating layer 331' may be made of the same material.

[0119] In some implementations, such as Figure 4I and Figure 4J As shown, an initial first insulating layer 320' can be formed on one side of the end of the stacked structure 381 and the first electrode 310 in the D1 direction using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Further, as... Figure 4K and Figure 4L As shown, the pattern used to form the first opening 392 can be transferred from the second mask layer 390 to the third mask layer 391 and then to the initial first insulating layer 320', thereby forming the first opening 392 penetrating the initial first insulating layer 320'. After the first opening 392 is formed, the initial first insulating layer 320' is converted back to the first insulating layer 320. For example, the second mask layer 390 can be a photoresist. The third mask layer 391 can be a hard mask.

[0120] In some embodiments, the first opening 392, viewed from the D1 direction, may be generally circular, elliptical, rectangular, or other irregular in shape. A single first opening 392 may be located between adjacent first electrodes 310. As an example, the first opening 392 may expose a portion of the first electrode 310, such that the first insulating layer 320 may surround a portion of the sidewall of the end of the first electrode 310. As another example, the first opening 392 may not expose the first electrode 310, such that the first insulating layer 320 may surround the entire sidewall of the end of the first electrode 310. Furthermore, since the initial first insulating layer 320' is formed on one side of the end of the first electrode 310 in the D1 direction, after the first opening 392 is formed, a portion of the first insulating layer 320 may be located on one side of the end of the first electrode 310 in the D1 direction. For example, the first insulating layer 320 may be made of a different material than the second sacrificial layers 384-1, 384-2.

[0121] It should be noted that, such as Figure 4J As shown, after the initial first insulating layer 320' is formed, it can be planarized by a CMP process, for example, making the surface of the retained initial first insulating layer coplanar with the end face of the first electrode 310 (not shown). In this way, after the first opening is formed, the converted first insulating layer can surround at least a portion of the sidewall of the end of the first electrode, but is not located on the side of the end of the first electrode in the D1 direction.

[0122] In some implementations, such as Figures 4M to 4OAs shown, the preparation method 200 may further include the step of removing the second sacrificial layers 384-1 and 384-2. For example, as... Figure 4L and Figure 4M As shown, the first opening 392 exposes the second sacrificial layer 384-2. The second sacrificial layer 384-2 can be removed by an etching process (e.g., wet etching) via the first opening 392. Optionally, during the removal of the second sacrificial layer 384-2, the third sacrificial layer 389 can also be removed. Further, as... Figure 4M and Figure 4N As shown, a second opening 393 penetrating the initial second insulating layer 331' can be formed by an etching process (e.g., dry etching). The third opening 393 can expose the second sacrificial layer 384-1. The initial second insulating layer 331' after the formation of the second opening 393 is transformed into the second insulating layer 331. Similarly, depending on the size of the second opening 393 in a plane perpendicular to the D1 direction, the second insulating layer 331 can surround at least a portion of the sidewall of the first electrode 310. Further, as... Figure 4N and Figure 4O As shown, the second sacrificial layer 384-1 can be removed by an etching process (e.g., wet etching) via the first opening 392 and the second opening 393. For example, the third insulating layer 333 can serve as an etching stop layer for removing the second sacrificial layer 384-1.

[0123] It should be noted that when the number of second sacrificial layers is greater than 2 and the number of initial second insulating layers is greater than 1, the steps of forming a second opening through the initial second insulating layer and removing the second sacrificial layer can be performed alternately.

[0124] In the above steps, such as Figure 4O As shown, after removing the second sacrificial layers 384-1 and 384-2, the first insulating layer 320, the second insulating layer 331, and the third insulating layer 333 can support the first electrode 310.

[0125] In some implementations, such as Figure 4P As shown, the preparation method 200 may further include the step of forming a capacitor C. For example, as... Figure 4O and Figure 4PAs shown, a capacitor dielectric layer 341 can be formed on one side of the first electrode 310 in the direction intersecting the D1 direction and on opposite sides of the first insulating layer 320 in the D1 direction using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Optionally, the capacitor dielectric layer 341 can also be formed on opposite sides of the second insulating layer 331 in the D1 direction and / or on the side of the third insulating layer 333 in the D1 direction away from the isolation layer 362. Further, a second electrode 342 can be formed on the side of the capacitor dielectric layer 341 away from the first electrode 310 and the first insulating layer 320 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Optionally, the second electrode 342 can also be formed on the side of the capacitor dielectric layer 341 away from the second insulating layer 331 and / or the third insulating layer 333. The first electrode 310, the capacitor dielectric layer 341, and the second electrode 342 can be used to constitute a capacitor C.

[0126] In some implementations, such as Figure 4J As shown, the fabrication method 200 may further include the step of forming a bit line structure 371. Exemplarily, the bit line structure 371 may be formed on the surfaces of the interconnected ends of a row of semiconductor bodies 351. Thus, the bit line structure 371 may extend along the D2 direction and may be connected to a row of semiconductor bodies 351 arranged along the D2 direction.

[0127] In some embodiments, the fabrication method 200 may further include the step of connecting a peripheral circuit structure (not shown). For example, the peripheral circuit structure may be bonded to the side of the semiconductor body 351 opposite to the capacitor C in the D1 direction. The peripheral circuit structure may be fabricated in parallel with the intermediate structure of the semiconductor device described above, thereby improving fabrication efficiency. Alternatively, the peripheral circuit structure may also be bonded to the side of the capacitor C opposite to the semiconductor body 351 in the D1 direction.

[0128] This disclosure also provides a memory system. Figure 5 This is a schematic block diagram of a system with a memory system provided in an embodiment of this disclosure. Figure 6A and Figure 6B This is a schematic block diagram of a memory system provided in an embodiment of this disclosure.

[0129] like Figure 5 As shown, system 40 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 41 located therein). Figure 5As shown, system 40 may include a host 44 and a memory system 41, the memory system 41 having one or more memories 42 and a controller 43. The host 44 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 44 may be configured to send or receive data to and from the memory 42.

[0130] Memory 42 may include, for example, the semiconductor devices described in any embodiment of this disclosure. According to some embodiments, controller 43 is coupled to memory 42 and host 44 and is configured to control memory 42. Controller 43 can manage data stored in memory 42 and communicate with host 44. In some embodiments, controller 43 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 43 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. Controller 43 may be configured to control the operation of memory 42, such as read, erase, and program operations. Controller 43 may also be configured to manage various functions related to data stored in or to be stored in memory 42, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 43 is further configured to process error correction codes (ECCs) related to data read from or written to memory 42. Controller 43 may also perform any other appropriate functions, such as formatting memory 42. Controller 43 may communicate with external devices (e.g., host 44) according to a specific communication protocol. For example, controller 43 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0131] The controller 43 and one or more memories 42 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 41 can be implemented and packaged into different types of end electronic products. Figure 6AIn one example shown, the controller 43 and a single memory 42 may be integrated into a memory card 45. The memory card 45 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 45 may further include a connector for connecting the memory card 45 to a host computer (e.g., Figure 5 The host 44) is coupled to the memory card connector 46. In such a way... Figure 6B In another example shown, the controller 43 and multiple memories 42 may be integrated into the SSD 47. The SSD 47 may further include a connection between the SSD 47 and the host (e.g., Figure 5 The SSD connector 48 is coupled to the host 44. In some embodiments, the storage capacity and / or operating speed of the SSD 47 is higher than that of the memory card 45.

[0132] The above description is merely an illustration of the embodiments of this disclosure and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this disclosure.

Claims

1. A semiconductor device, comprising: A first electrode extends along a first direction and includes a first end face, a second end face, and a sidewall. The first end face and the second end face are disposed opposite each other in the first direction, and the sidewall connects the first end face and the second end face. A first insulating layer surrounds at least a portion of the sidewall of the first end of the first electrode and is located on the side of the first end face opposite to the second end face.

2. The semiconductor device according to claim 1, wherein, The dimension of the first electrode in the first direction is greater than 950 nm.

3. The semiconductor device according to claim 1, wherein, The ratio of the dimension of the first electrode in the first direction to the dimension of the first electrode in the direction intersecting the first direction is greater than 33.

4. The semiconductor device according to claim 1, wherein, Multiple first electrodes are arranged at intervals; a portion of the first insulating layer is located on the side of the first end face of each first electrode opposite to the second end face.

5. The semiconductor device according to claim 1, wherein, The first insulating layer contacts at least a portion of the sidewall of the first end and contacts the first end face.

6. The semiconductor device according to claim 1, wherein, The first insulating layer includes: A first extension, surrounding at least a portion of the sidewall of the first end; and The second extension is located on the side of the first end face that is opposite to the second end face; Wherein, the surfaces of the first extension and the second extension are coplanar in the first direction away from the first end face.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The material of the first insulating layer includes at least one of the following: silicon nitride, silicon carbonitride, and silicon boronitride.

8. The semiconductor device according to any one of claims 1 to 4, further comprising: The second electrode is partially located on one side of the first electrode in the direction intersecting the first direction, and partially located on opposite sides of the first insulating layer in the first direction. as well as The capacitor dielectric layer is partially located between the first electrode and the second electrode.

9. The semiconductor device according to claim 8, further comprising: A second insulating layer is spaced apart from the first insulating layer in the first direction and surrounds at least a portion of the sidewall of the first electrode; In this configuration, a portion of the second electrode is located on opposite sides of the second insulating layer in the first direction.

10. The semiconductor device according to claim 9, wherein, Part of the capacitor dielectric layer and part of the second electrode pass through the first insulating layer and the second insulating layer along the first direction.

11. The semiconductor device according to claim 1, wherein, Also includes: The semiconductor body extends along the first direction and is located on the side of the first electrode in the first direction and away from the first end face.

12. The semiconductor device according to claim 11, wherein, Also includes: A gate structure is located on at least one side of the semiconductor body in a direction intersecting the first direction; as well as A gate dielectric layer is located between the semiconductor body and the gate structure.

13. The semiconductor device according to claim 11, further comprising: A connection structure extends along the first direction and is connected to the second end face and the semiconductor body.

14. A memory system, comprising: The memory includes the semiconductor device as described in any one of claims 1 to 13; as well as A controller, coupled to the memory, is used to control the memory to store data.

15. A method for fabricating a semiconductor device, comprising: A hole is formed that penetrates the first sacrificial layer and the stacked structure along a first direction, wherein the first sacrificial layer is located on one side of the stacked structure in the first direction; A first electrode is formed in the hole; Remove the first sacrificial layer, wherein the end of the first electrode protrudes from the stacked structure; and A first insulating layer is formed around at least a portion of the sidewall of the end.

16. The preparation method according to claim 15, wherein, The first insulating layer forming at least a portion of the sidewall surrounding the end comprises: An initial first insulating layer is formed on one side of the stacked structure and the end in the first direction; and A first opening is formed through the initial first insulating layer to obtain the first insulating layer, wherein the retained portion of the first insulating layer is located on one side of the end in the first direction.

17. The preparation method according to claim 16, wherein, The laminated structure includes a second sacrificial layer and an initial second insulating layer alternately disposed in the first direction, and the first opening exposes the second sacrificial layer; The preparation method further includes: A second opening is formed through the initial second insulating layer to obtain the second insulating layer; and The second sacrificial layer is removed through the first opening and / or the second opening.

18. The preparation method according to claim 17, wherein, The first insulating layer and the second insulating layer are made of the same material, and at least a portion of the first sacrificial layer, the second sacrificial layer, and the first insulating layer are made of different materials.

19. The preparation method according to claim 17, further comprising: A capacitor dielectric layer is formed on one side of the first electrode in the direction intersecting the first direction and on the opposite sides of the first insulating layer in the first direction. as well as A second electrode is formed on the side of the capacitor dielectric layer opposite to the first electrode and the first insulating layer.

20. The preparation method according to claim 17, wherein after removing the first sacrificial layer, the preparation method further comprises: A third sacrificial layer is formed on one side of the second sacrificial layer in the first direction, and the end protrudes from the third sacrificial layer.

21. The preparation method according to claim 20, wherein, The material of the third sacrificial layer is the same as that of the second sacrificial layer.

22. The preparation method according to claim 15, further comprising: A semiconductor body extending along the first direction is formed, wherein the stacked structure is formed on one side of the semiconductor body in the first direction; A gate structure is formed on at least one side of the semiconductor body in a direction intersecting the first direction; and A gate dielectric layer is formed between the gate structure and the semiconductor body.

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