Semiconductor devices and manufacturing methods thereof

Abstract

A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a word line layer. The substrate includes a plurality of fins and a plurality of first trenches, each of the first trenches being located between two fins. The first dielectric layer is located in the first trenches. The second dielectric layer is located in the first trenches, wherein at least the bottom of the second dielectric layer is surrounded by the first dielectric layer, and the upper portion of the second dielectric layer protrudes outward from the top surface of the first dielectric layer. The word line layer covers the second dielectric layer, the first dielectric layer, and the substrate. Such a semiconductor device reduces signal interference, lowers the electric field, and improves switching speed.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] In the operation of existing dynamic random access memory (DRAM), when the word line material at the bottom of the shallow trench insulation (STI) trench is close to the silicon substrate, the word line material in the trench can interfere with the adjacent silicon signal. Summary of the Invention

[0003] According to some embodiments of the present invention, a semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a word line layer. The substrate includes a plurality of fins and a plurality of first trenches, wherein each of the first trenches is located between two fins. The first dielectric layer is located in the first trenches. The second dielectric layer is located in the first trenches, wherein at least the bottom of the second dielectric layer is surrounded by the first dielectric layer, and the upper portion of the second dielectric layer protrudes outward from the top surface of the first dielectric layer. The word line layer covers the second dielectric layer, the first dielectric layer, and the substrate.

[0004] In some implementations, the character line layer extends into the first trench and surrounds the upper part of the second dielectric layer.

[0005] In some implementations, the top surface of the second dielectric layer is lower than the top surface of the fin.

[0006] In some embodiments, the semiconductor device further includes a third dielectric layer located above the fin, the top surface of the first dielectric layer, and the top of the second dielectric layer.

[0007] In some embodiments, the first dielectric layer is made of an oxide, the second dielectric layer is made of a nitride, and the word line layer is made of titanium nitride.

[0008] In some embodiments, a first distance from the top surface of the second dielectric layer to the bottom surface of the first trench is greater than a second distance from the top surface of the first dielectric layer to the bottom surface of the first trench.

[0009] In some embodiments, the substrate further includes a protrusion on an active region of the substrate and two second trenches respectively adjacent to two opposite sides of the protrusion, the protrusion having at least one recess, and the first dielectric layer, the second dielectric layer and the character line layer being located in the two second trenches, and the vertical distance between the bottom surface of the recess and the top surface of the second dielectric layer being in the range of 5 nanometers to 25 nanometers.

[0010] In some embodiments, the first dielectric layer is also located on the top surface of the protrusion.

[0011] In some embodiments, the top surface of the second dielectric layer is lower than the bottom surface of the recess of the protrusion.

[0012] In some embodiments, the semiconductor device further includes a third dielectric layer located in the second trench, between the second dielectric layer and the word line layer, and between the first dielectric layer and the word line layer.

[0013] According to some embodiments of the present invention, a semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a word line layer. The substrate includes a plurality of fins, a plurality of first trenches, a protrusion, and two second trenches, wherein each of the first trenches is located between two fins, the protrusion is located on an active region of the substrate, the two second trenches are respectively adjacent to two opposite sides of the protrusion, and the protrusion has at least one recess. The first dielectric layer is located in the first trenches and the two second trenches. The second dielectric layer is located in the first trenches and the two second trenches, wherein the vertical distance between the bottom surface of the recess and the top surface of the second dielectric layer is in the range of 5 nanometers to 25 nanometers. The word line layer covers the second dielectric layer, the first dielectric layer, and the substrate.

[0014] In some embodiments, the first dielectric layer is made of an oxide, the second dielectric layer is made of a nitride, and the word line layer is made of titanium nitride.

[0015] In some embodiments, the first dielectric layer is also located on the top surface of the protrusion.

[0016] In some embodiments, the top surface of the second dielectric layer is lower than the bottom surface of the recess of the protrusion.

[0017] In some embodiments, the semiconductor device further includes a third dielectric layer located in the second trench, between the second dielectric layer and the word line layer, and between the first dielectric layer and the word line layer.

[0018] According to some embodiments of the present invention, a method of manufacturing a semiconductor device includes forming an anti-reflective coating on a carbon layer on a semiconductor structure, wherein the semiconductor structure includes a substrate, a first dielectric layer on the substrate, and a second dielectric layer in the first dielectric layer, the carbon layer being located on the first dielectric layer; patterning the carbon layer using the anti-reflective coating as a mask to form a plurality of openings, wherein the first dielectric layer is exposed through the openings in the carbon layer; removing the anti-reflective coating; etching a protrusion of the first dielectric layer, the second dielectric layer, and the substrate using the carbon layer as a mask, such that the top surface of the second dielectric layer is exposed through the opening in the first dielectric layer, and the protrusion has at least one recess, wherein the vertical distance between the bottom surface of the recess and the top surface of the second dielectric layer is in the range of 5 nanometers to 25 nanometers; and forming a word line layer to cover the second dielectric layer, the first dielectric layer, and the substrate.

[0019] In some embodiments, etching the first dielectric layer, the second dielectric layer, and the protrusions of the substrate includes controlling the etching selectivity between the first dielectric layer and the second dielectric layer, and the etching selectivity between the second dielectric layer and the substrate.

[0020] In some embodiments, the method further includes forming a third dielectric layer on the surface of the first dielectric layer, the second dielectric layer, and the recess, such that the third dielectric layer is located between the second dielectric layer and the word line layer and between the first dielectric layer and the word line layer.

[0021] In some embodiments, the third dielectric layer is formed by an oxidation process that includes atomic layer deposition and on-site vapor generation techniques.

[0022] In some embodiments, the substrate further includes a plurality of fins and a plurality of first trenches, each of the first trenches being located between two fins, a first dielectric layer and a second dielectric layer being located in the first trench, and etching of the first dielectric layer, the second dielectric layer and the protrusion of the substrate is performed such that at least the bottom of the second dielectric layer in the first trench is surrounded by the first dielectric layer, and the upper portion of the second dielectric layer protrudes outward from the top surface of the first dielectric layer.

[0023] In the above embodiments of the present invention, since the upper part of the second dielectric layer protrudes outward from the top surface of the first dielectric layer, the height of the second dielectric layer is increased, and the distance between the word line layer and the silicon substrate is increased. The increased height of the second dielectric layer located in the second trench reduces the horizontal distance between the word line layer and the silicon region (i.e., the sidewall of the substrate). Such a semiconductor device reduces signal interference, lowers the electric field, and improves switching speed. Controlling the etch selectivity between the first and second dielectric layers and between the second dielectric layer and the substrate allows the height of the second dielectric layer to be increased. The vertical distance between the bottom surface of the recess and the top surface of the second dielectric layer, ranging from 5 nanometers to 25 nanometers, can be more easily manufactured to improve yield. Attached Figure Description

[0024] When accompanied by Figure 1 When reading this document, the best understanding of the invention can be obtained from the embodiments described below. Note that, according to standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation.

[0025] Figure 1 A top view of a semiconductor device according to an embodiment of the present invention is shown.

[0026] Figure 2 Illustration as follows Figure 1 The semiconductor device is shown in cross-section along line 2-2.

[0027] Figure 3 Illustration as follows Figure 1 The semiconductor device is shown in cross-section along line 3-3.

[0028] Figure 4 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0029] Figures 5-9 Illustration as follows Figure 3 A cross-sectional view of a semiconductor device at an intermediate stage of the manufacturing process. Detailed Implementation

[0030] The following description of embodiments provides numerous different implementations, or examples, for carrying out various features of the provided object. Specific examples of elements and arrangements are described below to simplify the subject matter. Of course, these examples are merely illustrative and are not intended to be limiting. Furthermore, element symbols and / or letters may be repeated in various examples. This repetition is for simplicity and clarity purposes and does not in itself specify the relationship between the various embodiments and / or configurations discussed.

[0031] Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for descriptive purposes to describe the relationship between one element or feature and another, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the apparatus in use or operation other than those shown in the accompanying drawings. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0032] Figure 1 A top view of a semiconductor device 100 according to an embodiment of the present invention is shown. Figure 2 Illustration as follows Figure 1 A cross-sectional view of the semiconductor device 100 along line 2-2. (See figure) Figure 1 and Figure 2 As shown, the semiconductor device 100 can be a dynamic random access memory (DRAM) and includes a plurality of active regions 120 and a plurality of word lines 110 spanning the active regions 120. The semiconductor device 100 includes a substrate 130, a first dielectric layer 140, a second dielectric layer 150, and a word line layer 160 (i.e., Figure 1 The character line layer 110 is a plurality of fins 132 and a plurality of first trenches 134, each of the first trenches 134 being located between two fins 132. In some embodiments, the substrate 130 may be made of silicon. A first dielectric layer 140 is located in the first trenches 134. A second dielectric layer 150 is located in the first trenches 134, and at least the bottom of the second dielectric layer 150 is surrounded by the first dielectric layer 140. Furthermore, the upper portion of the second dielectric layer 150 protrudes outward from the top surface of the first dielectric layer 140. A character line layer 160 covers the second dielectric layer 150, the first dielectric layer 140, and the substrate 130.

[0033] like Figure 2As shown, the character line layer 160 extends into the first trench 134 and surrounds the upper portion of the second dielectric layer 150. The material of the character line layer 160 may include titanium nitride. The top surface of the second dielectric layer 150 is lower than the top surface of the fin 132. A first distance D1 from the top surface of the second dielectric layer 150 to the bottom surface of the first trench 134 is greater than a second distance D2 from the top surface of the first dielectric layer 140 to the bottom surface of the first trench 134.

[0034] Specifically, since the upper part of the second dielectric layer 150 protrudes outward from the top surface of the first dielectric layer 140, the height of the second dielectric layer 150 is increased and the distance between the word line layer 160 and the silicon substrate 130 is increased, signal interference is reduced, the electric field is reduced, and the switching speed is improved.

[0035] Furthermore, the semiconductor device 100 may also include a third dielectric layer 170. The third dielectric layer 170 is located above the fin 132, on the top surface of the first dielectric layer 140, and above the second dielectric layer 150. The material of the first dielectric layer 140 is different from the material of the second dielectric layer 150. For example, the material of the first dielectric layer 140 may contain oxides, and the material of the second dielectric layer 150 may contain nitrides. Furthermore, the material of the third dielectric layer 170 may contain oxides.

[0036] Figure 3 Illustration as follows Figure 1 A cross-sectional view of the semiconductor device 100 along line 3-3. (See figure) Figure 1 and Figure 3 As shown, substrate 130 includes a protrusion 136 and two second trenches 138. The protrusion 136 is located on the active region 120 of substrate 130, and the two second trenches 138 are respectively adjacent to two opposite sides of the protrusion 136. Furthermore, the protrusion 136 has at least one recess 137. A first dielectric layer 140 is located in the two second trenches 138. A second dielectric layer 150 is located in the two second trenches 138. The vertical distance D3 between the bottom surface of the recess 137 and the top surface of the second dielectric layer 150 is in the range of 5 nanometers to 25 nanometers. A character line layer 160 covers the second dielectric layer 150.

[0037] Specifically, the height of the second dielectric layer 150 located in the second trench 138 is increased to reduce the horizontal distance between the word line layer 160 and the silicon region (i.e., the sidewall of the substrate 130). This reduces signal interference, lowers the electric field, and improves switching speed. Furthermore, the thickness of the word line layer 160 maintains the drain-source current (IDS).

[0038] In some embodiments, a first dielectric layer 140 is disposed on the top surface of the protrusion 136. The top surface of the second dielectric layer 150 is lower than the bottom surface of the recess 137 of the protrusion 136 by a vertical distance D3 from 5 nanometers to 25 nanometers. Furthermore, a third dielectric layer 170 is located in the second trench 138. The third dielectric layer 170 is located between the second dielectric layer 150 and the word line layer 160, and between the first dielectric layer 140 and the word line layer 160. In other words, the third dielectric layer 170 is located on the sidewall of the opening 142 of the first dielectric layer 140.

[0039] Figure 4 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. The method for manufacturing a semiconductor device includes the following steps. In block 410, an anti-reflective coating is formed on a carbon layer on a semiconductor structure, wherein the semiconductor structure includes a substrate, a first dielectric layer on the substrate, and a second dielectric layer in the first dielectric layer, and the carbon layer is located on the first dielectric layer. Then, in block 420, the carbon layer is patterned using the anti-reflective coating as a mask to form a plurality of openings, wherein the first dielectric layer is exposed through the openings in the carbon layer. Next, in block 430, the anti-reflective coating is removed. Subsequently, in block 440, the first dielectric layer, the second dielectric layer, and a protrusion of the substrate are etched using the carbon layer as a mask, such that the top surface of the second dielectric layer is exposed through the opening in the first dielectric layer, and the protrusion has at least one recess, wherein the vertical distance between the bottom surface of the recess and the top surface of the second dielectric layer is in the range of 5 nanometers to 25 nanometers. Subsequently, in box 450, a character line layer is formed to cover the second dielectric layer, the first dielectric layer, and the substrate.

[0040] The aforementioned blocks 410 to 450 may include multiple more detailed steps. The method of manufacturing a semiconductor device may also include other steps between blocks 410 and 450, or other steps before and after block 410. In the following description, the aforementioned blocks 410 to 450 will be explained in detail.

[0041] Figures 5-9 Illustration as follows Figure 3 A cross-sectional view of the semiconductor device 100 at an intermediate stage of the manufacturing process. (See figure) Figure 5 As described above, an anti-reflective coating 180 is formed on a carbon layer 190 on a semiconductor structure 102. The semiconductor structure 102 includes a substrate 130, a first dielectric layer 140 on the substrate 130, and a second dielectric layer 150 within the first dielectric layer 140. Furthermore, the anti-reflective coating 180 is located on the first dielectric layer 140 and is patterned to expose multiple portions of the carbon layer 190.

[0042] like Figure 6As shown, the carbon layer 190 is patterned using an anti-reflective coating 180 to form a plurality of openings 192. Following this, Figure 5 The anti-reflective coating 180 was removed.

[0043] like Figure 7 As shown, the first dielectric layer 140, the second dielectric layer 150, and the protrusion 136 of the substrate 130 are etched using a carbon layer 190 as a mask. In the etching process, the etching selectivity between the first dielectric layer 140 and the second dielectric layer 150, and the etching selectivity between the second dielectric layer 150 and the substrate 130, are controlled to selectively etch the first dielectric layer 140 and the substrate 130 relative to the second dielectric layer 150, allowing the height of the second dielectric layer 150 to be adjusted. Therefore, the top surface of the second dielectric layer 150 is exposed through the opening 142 of the first dielectric layer 140, and the protrusion 136 has at least one recess 137, with the vertical distance D3 between the bottom surface of the recess 137 and the top surface of the second dielectric layer 150 ranging from 5 nanometers to 25 nanometers. Figure 7 After the structure is formed, the carbon layer 190 is removed from the first dielectric layer 140.

[0044] like Figure 8 As shown, a third dielectric layer 170 is formed on the surfaces of the first dielectric layer 140, the second dielectric layer 150, and the recess 137. In other words, the third dielectric layer 170 is also located on the sidewall of the opening 142. The third dielectric layer 170 can be formed by an oxidation process, for example, including atomic layer deposition (ALD) and on-site vapor generation technology (ISSF).

[0045] like Figure 9 As shown, after the third dielectric layer 170 is formed, a character line layer 160 is formed to cover the second dielectric layer 150, the first dielectric layer 140, and the substrate 130. Figure 9 After the character line layer 160 is formed, it is etched to remove portions of the character line layer 160, and thus a result can be obtained as shown. Figure 3 The semiconductor device 100. At this time, it is also possible to obtain... Figure 2 Another section of the structure.

[0046] In short, because the upper part of the second dielectric layer protrudes outward from the top surface of the first dielectric layer, the height of the second dielectric layer is increased, and the distance between the word line layer and the silicon substrate is increased. The increased height of the second dielectric layer located in the second trench reduces the horizontal distance between the word line layer and the silicon region (i.e., the sidewall of the substrate). Such a semiconductor device reduces signal interference, lowers the electric field, and improves switching speed. Controlling the etch selectivity between the first and second dielectric layers, as well as the etch selectivity between the second dielectric layer and the substrate, allows for an increase in the height of the second dielectric layer. The vertical distance between the bottom surface of the recess and the top surface of the second dielectric layer, ranging from 5 nanometers to 25 nanometers, can be more easily fabricated to improve yield.

[0047] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of the invention. Those skilled in the art will understand that they can readily use this invention as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them without departing from the spirit and scope of the invention.

[0048] [Symbol Explanation] 100: Semiconductor devices 102: Semiconductor Structure 110: Character Line 120: Active Zone 130: Substrate 132: Fins 134: First trench 136: convex part 137: Recessed area 138: Second trench 140: First dielectric layer 142: Opening 150: Second dielectric layer 160: Character Line Layer 170: Third dielectric layer 180: Anti-reflective coating 190: Carbon layer 192: Opening 410, 420, 430, 440, 450: Boxes 2-2, 3-3: Lines D1, D2, D3: Distance.

Claims

1. A semiconductor device, characterized in that, Include: A substrate includes a plurality of fins and a plurality of first grooves, wherein each of the plurality of first grooves is located between two of the plurality of fins; A first dielectric layer is located in the plurality of first trenches; A second dielectric layer is located in the plurality of first trenches, wherein at least the bottom of the second dielectric layer is surrounded by the first dielectric layer, and the upper part of the second dielectric layer protrudes outward from the top surface of the first dielectric layer; as well as A character line layer covers the second dielectric layer, the first dielectric layer, and the substrate.

2. The semiconductor device according to claim 1, characterized in that, The character line layer extends into the plurality of first trenches and surrounds the upper portion of the second dielectric layer.

3. The semiconductor device according to claim 1, characterized in that, The top surface of the second dielectric layer is lower than the top surface of the fin.

4. The semiconductor device according to claim 1, characterized in that, Also includes: A third dielectric layer is located on top of the plurality of fins, on the top surface of the first dielectric layer, and on top of the second dielectric layer.

5. The semiconductor device according to claim 1, characterized in that, The first dielectric layer is made of an oxide, the second dielectric layer is made of a nitride, and the character line layer is made of titanium nitride.

6. The semiconductor device according to claim 1, characterized in that, The first distance from the top surface of the second dielectric layer to the bottom surface of the first trench is greater than the second distance from the top surface of the first dielectric layer to the bottom surface of the first trench.

7. The semiconductor device according to claim 1, characterized in that, The substrate further includes a protrusion on the active region of the substrate and two second trenches respectively adjacent to two opposite sides of the protrusion. The protrusion has at least one recess, and the first dielectric layer, the second dielectric layer and the character line layer are also located in the two second trenches. The vertical distance between the bottom surface of the recess and the top surface of the second dielectric layer is in the range of 5 nanometers to 25 nanometers.

8. The semiconductor device according to claim 7, characterized in that, The first dielectric layer is also located on the top surface of the protrusion.

9. The semiconductor device according to claim 7, characterized in that, The top surface of the second dielectric layer is lower than the bottom surface of the recess of the protrusion.

10. The semiconductor device according to claim 7, characterized in that, Also includes: The third dielectric layer is located in the two second trenches, between the second dielectric layer and the character line layer, and between the first dielectric layer and the character line layer.

11. A semiconductor device, characterized in that, Include: A substrate includes a plurality of fins, a plurality of first grooves, a protrusion, and two second grooves, wherein each of the plurality of first grooves is located between two of the plurality of fins, the protrusion is located on an active region of the substrate, the two second grooves are respectively adjacent to two opposite sides of the protrusion, and the protrusion has at least one recess. A first dielectric layer is located in the plurality of first trenches and the two second trenches; A second dielectric layer is located in the plurality of first trenches and the two second trenches, wherein the vertical distance between the bottom surface of the recess and the top surface of the second dielectric layer is in the range of 5 nanometers to 25 nanometers. as well as A character line layer covers the second dielectric layer, the first dielectric layer, and the substrate.

12. The semiconductor device according to claim 11, characterized in that, The first dielectric layer is made of an oxide, the second dielectric layer is made of a nitride, and the character line layer is made of titanium nitride.

13. The semiconductor device according to claim 11, characterized in that, The first dielectric layer is also located on the top surface of the protrusion.

14. The semiconductor device according to claim 11, characterized in that, The top surface of the second dielectric layer is lower than the bottom surface of the recess of the protrusion.

15. The semiconductor device according to claim 11, characterized in that, Also includes: The third dielectric layer is located in the two second trenches, between the second dielectric layer and the character line layer, and between the first dielectric layer and the character line layer.

16. A method for manufacturing a semiconductor device, characterized in that, Include: An anti-reflective coating is formed on a carbon layer on a semiconductor structure, wherein the semiconductor structure includes a substrate, a first dielectric layer on the substrate, and a second dielectric layer in the first dielectric layer, and the carbon layer is located on the first dielectric layer; The carbon layer is patterned using the anti-reflective coating as a mask to form a plurality of openings, wherein the first dielectric layer is exposed through the plurality of openings in the carbon layer; Remove the anti-reflective coating; The carbon layer is used as a mask to etch the first dielectric layer, the second dielectric layer, and the protrusion of the substrate, such that the top surface of the second dielectric layer is exposed through the opening of the first dielectric layer, and the protrusion has at least one recess, wherein the vertical distance between the bottom surface of the recess and the top surface of the second dielectric layer is in the range of 5 nanometers to 25 nanometers. as well as A character line layer is formed to cover the second dielectric layer, the first dielectric layer, and the substrate.

17. The method according to claim 16, characterized in that, Etching the first dielectric layer, the second dielectric layer, and the protrusion of the substrate includes controlling the etching selectivity between the first dielectric layer and the second dielectric layer, and the etching selectivity between the second dielectric layer and the substrate.

18. The method according to claim 16, characterized in that, Also includes: A third dielectric layer is formed on the surfaces of the first dielectric layer, the second dielectric layer, and the recess, such that the third dielectric layer is located between the second dielectric layer and the character line layer and between the first dielectric layer and the character line layer.

19. The method according to claim 18, characterized in that, The third dielectric layer is formed by an oxidation process that includes atomic layer deposition and on-site vapor generation technology.

20. The method according to claim 16, characterized in that, The substrate further includes a plurality of fins and a plurality of first trenches, each of the plurality of first trenches being located between two of the plurality of fins, a first dielectric layer and a second dielectric layer being located in the plurality of first trenches, and etching the first dielectric layer, the second dielectric layer and the protrusions of the substrate is performed such that at least the bottom of the second dielectric layer in the plurality of first trenches is surrounded by the first dielectric layer, and the upper portion of the second dielectric layer protrudes outward from the top surface of the first dielectric layer.

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