Semiconductor device and data storage system including the same

Abstract

A semiconductor device and a data storage system including the semiconductor device are disclosed. The semiconductor device includes: a plate; gate electrodes stacked in a vertical direction and extending to different lengths, each gate electrode including a pad region; an interlayer insulating layer disposed alternately with the gate electrodes; a contact plug extending through the pad region; a dummy vertical structure extending through the gate electrodes and the interlayer insulating layer in a second region and spaced apart from the contact plug; and a contact insulating structure disposed alternately with the interlayer insulating layer and surrounding the contact plug. The pad region includes a first pad region penetrated by a first contact plug among the contact plugs. The dummy vertical structure includes a first dummy vertical structure adjacent to the first contact plug. The contact insulating structure includes a first contact insulating structure contacting the first contact plug and the first dummy vertical structure in the first pad region.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and data storage systems including such semiconductor devices. Background Technology

[0002] Semiconductor devices capable of storing large amounts of data are desired in data storage systems. Therefore, methods for increasing the data storage capacity of semiconductor devices have been investigated. For example, to improve the integration density of semiconductor devices, semiconductor devices comprising memory cells arranged in three dimensions rather than two dimensions have been proposed. Summary of the Invention

[0003] The exemplary implementations of this disclosure provide a semiconductor device with improved reliability and a data storage system including the semiconductor device.

[0004] According to an example implementation of this disclosure, a semiconductor device includes: a first semiconductor structure including a substrate, circuit devices on the substrate, and circuit interconnects on the circuit devices; and a second semiconductor structure disposed on the first semiconductor structure and having a first region and a second region, wherein the second semiconductor structure includes: a plate layer; gate electrodes stacked on the plate layer in a vertical direction perpendicular to the upper surface of the plate layer and spaced apart from each other, extending to different lengths in the second region in a first direction intersecting the vertical direction, each gate electrode including a pad region, the upper surface of the pad region being exposed upward; an interlayer insulating layer disposed alternately with the gate electrodes; a channel structure penetrating the gate electrodes and the interlayer insulating layer in the first region and extending in a vertical direction; and a contact plug in the second region. A pad region penetrating each gate electrode extends vertically and electrically connects the gate electrode to at least one of the circuit interconnects, respectively; a dummy vertical structure penetrates the gate electrode and the interlayer insulation layer in the second region, extends vertically and is spaced apart from the contact plug in a horizontal direction intersecting the vertical direction; a contact insulation structure is alternately disposed below each pad region and surrounding the contact plug with the interlayer insulation layer, wherein the pad region of each gate electrode includes a first pad region penetrated by a first contact plug in the contact plug, wherein the dummy vertical structure includes a first dummy vertical structure adjacent to the first contact plug, and wherein the contact insulation structure includes a first contact insulation structure below the first pad region that contacts the first contact plug and the first dummy vertical structure.

[0005] According to an example implementation of this disclosure, a semiconductor device includes: a stacked pattern having a memory cell array region and a stepped region; a stacked structure extending from the memory cell array region to the stepped region on the stacked pattern, wherein the stacked structure includes an interlayer insulating layer and a gate electrode alternately disposed in a vertical direction, the gate electrode including a gate contact pad arranged in a stepped shape on the stepped region; a channel structure penetrating the stacked structure in the memory cell array region and extending in a vertical direction; a first contact plug penetrating the gate electrode and the interlayer insulating layer in the stepped region; a first dummy vertical structure penetrating the gate electrode and the interlayer insulating layer in the stepped region and adjacent to the first contact plug; and a first contact insulating structure, adjacent to the interlayer insulating layer. Insulating layers are alternately disposed and surrounding a first contact plug; and a first dummy insulating structure is alternately disposed and surrounding a first dummy vertical structure with interlayer insulating layers, wherein the first contact insulating structure is spaced apart from the first dummy insulating structure, wherein each first dummy insulating structure includes a first dummy insulating pattern surrounding a first portion of the first dummy vertical structure, a second dummy insulating pattern surrounding a second portion extending from the first portion of the first dummy vertical structure, and a dummy insulating pad surrounding the first dummy insulating pattern and the second dummy insulating pattern, wherein the first dummy insulating pattern includes a first insulating material, and wherein the second dummy insulating pattern includes a second insulating material different from the first insulating material.

[0006] According to an example implementation of this disclosure, a data storage system includes: a semiconductor memory device, comprising a first semiconductor structure including circuit devices and circuit interconnects electrically connected to the circuit devices, a second semiconductor structure disposed on a surface of the first semiconductor structure and including a first region and a second region, and an input / output pad electrically connected to the circuit devices; and a controller electrically connected to the semiconductor memory device via the input / output pad and controlling the semiconductor memory device, wherein the second semiconductor structure includes: a plate; gate electrodes stacked on the plate in a vertical direction perpendicular to the upper surface of the plate and spaced apart from each other, extending to different lengths in a first direction intersecting the vertical direction on the second region, each gate electrode including a pad region, the upper surface of the pad region being exposed on top; an interlayer insulating layer disposed alternately with the gate electrodes; a channel structure penetrating the gate electrodes and the interlayer insulating layer in the first region and extending in a vertical direction; and a contact plug penetrating the second region. A pad region extending vertically through each gate electrode extends and electrically connects the gate electrode to at least one of the circuit interconnects, respectively; a dummy vertical structure extending vertically through the gate electrode and interlayer insulation layer in a second region and spaced apart from the contact plug in a horizontal direction intersecting the vertical direction; and a contact insulation structure alternately disposed below each pad region and surrounding the contact plug with the interlayer insulation layer, wherein each gate electrode pad region includes a first pad region penetrated by a first contact plug in the contact plug, wherein the dummy vertical structure includes a first dummy vertical structure adjacent to the first contact plug, and wherein each contact insulation structure includes a first contact insulation pattern contacting the first contact plug and a first portion of the first dummy vertical structure below the first pad region, and a second contact insulation pattern contacting a second portion of the first dummy vertical structure, the second portion of the first dummy vertical structure being connected to the first portion of the first dummy vertical structure. Attached Figure Description

[0007] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1A This is a plan view illustrating a semiconductor device in an example implementation of this disclosure;

[0009] Figure 1B This illustrates a semiconductor device along an example implementation of the present disclosure. Figure 1A A cross-sectional view taken from line I-I' in the diagram;

[0010] Figure 1C This illustrates a semiconductor device along an example implementation of the present disclosure. Figure 1A A cross-sectional view taken from line II-II' in the diagram;

[0011] Figure 1DThis illustrates a semiconductor device along an example implementation of the present disclosure. Figure 1A A cross-sectional view taken from line III-III' in the diagram;

[0012] Figure 2 It is shown Figure 1B A magnified view of region C of the semiconductor device;

[0013] Figure 3 It is shown Figure 1A A magnified view of region A of the semiconductor device in the image;

[0014] Figure 4 This illustrates a semiconductor device along an example implementation of the present disclosure. Figure 3 A cross-sectional view taken by line A-A' in the diagram;

[0015] Figure 5 It is shown Figure 1A An enlarged view of region B of the semiconductor device in the image;

[0016] Figure 6A This illustrates a semiconductor device along an example implementation of the present disclosure. Figure 5 A cross-sectional view taken by line B-B' in the diagram;

[0017] Figure 6B This illustrates a semiconductor device along another example implementation of this disclosure. Figure 5 A cross-sectional view taken by line B-B' in the diagram;

[0018] Figure 7 This illustrates another example implementation according to this disclosure. Figure 1A An enlarged view of region B of the semiconductor device in the image;

[0019] Figures 8 to 10 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary implementation of the present disclosure;

[0020] Figures 11A to 18B This is about a method of manufacturing a semiconductor device according to an example implementation of the present disclosure. Figure 1A The graph of region B;

[0021] Figure 19 This illustrates a semiconductor device along an example implementation of the present disclosure. Figure 1A The cross-sectional view taken by line I-I' in the diagram; and

[0022] Figure 20 This is a diagram illustrating a data storage system including semiconductor devices in an example implementation of this disclosure. Detailed Implementation

[0023] The implementation of this disclosure will be described below with reference to the accompanying drawings.

[0024] Figure 1A This is a plan view illustrating the semiconductor device in the example implementation. Figure 1B This illustrates the semiconductor device along the example implementation. Figure 1A The cross-sectional view taken from line I-I' in the diagram. Figure 1C This illustrates the semiconductor device along the example implementation. Figure 1A The cross-sectional view taken from line II-II' in the diagram. Figure 1D This illustrates the semiconductor device along the example implementation. Figure 1A The cross-sectional view taken from line III-III' in the diagram.

[0025] Reference Figure 1A , Figure 1B , Figure 1C and Figure 1D The semiconductor device 100 may include a peripheral circuit region (PERI) and a memory cell region (CELL). The PERI is a first semiconductor structure including a substrate 201, and the CELL is a second semiconductor structure including a substrate 101. The CELL may be disposed on the PERI. In another example, the CELL may be disposed below the PERI.

[0026] The peripheral circuit area (PERI) may include a substrate 201, an impurity region 205 in the substrate 201, a device isolation layer 210, circuit devices 220 disposed on the substrate 201, a peripheral insulating layer 290, circuit contact plugs 270, and circuit interconnects 280.

[0027] The substrate 201 may have an upper surface extending in a first direction (X direction) and a second direction (Y direction). The substrate 201 may have an active region defined by a device isolation layer 210. An impurity region 205, including impurities, may be disposed within a portion of the active region. The substrate 201 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0028] The circuit device 220 may include a planar transistor. Each circuit device 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. On both sides of the circuit gate electrode 225, impurity regions 205 may be disposed in the substrate 201 as source / drain regions.

[0029] The peripheral insulating layer 290 can be disposed on the circuit device 220 on the substrate 201. The peripheral insulating layer 290 may include multiple insulating layers formed in different processes. The peripheral insulating layer 290 may be formed of an insulating material.

[0030] Circuit contact plug 270 and circuit interconnect 280 can form a circuit interconnect structure electrically connected to circuit device 220 and impurity region 205. Circuit contact plug 270 can have a cylindrical shape, and circuit interconnect 280 can have a line shape. Electrical signals can be applied to circuit device 220 through circuit contact plug 270 and circuit interconnect 280. In areas not shown, circuit contact plug 270 can also be connected to circuit gate electrode 225. Circuit interconnect 280 can be connected to circuit contact plug 270, can have a line shape, and can be configured as multiple layers. Circuit contact plug 270 and circuit interconnect 280 can include conductive materials, such as tungsten (W), copper (Cu), aluminum (Al), and each of circuit contact plug 270 and circuit interconnect 280 can further include a diffusion barrier. In the example implementation, the number of layers of circuit contact plug 270 and circuit interconnect 280 can vary.

[0031] The memory cell region CELL may include a first region R1 and a second region R2. The memory cell region CELL may include a source structure SS including a plate layer 101, a gate electrode 130 stacked on the source structure SS and included in the gate structure GS, an interlayer insulating layer 120 alternately stacked with the gate electrode 130 and included in the gate structure GS, a channel structure CH configured to penetrate the gate structure GS in the first region R1, an isolation region MS (also referred to as an isolation structure in this disclosure) extending through the gate structure GS, an auxiliary isolation region US configured to penetrate the gate electrode 130 in the upper portion, a contact plug 170 connected to the gate electrode 130 and extending vertically in the second region R2, and a dummy vertical structure 175 configured to penetrate the gate structure GS and disposed around the contact plug 170. In the example, the memory cell region CELL may further include a horizontal insulating layer 110 disposed below the gate electrode 130 in the second region R2, a substrate insulating layer 121 configured to penetrate the plate layer 101, pillars 180 on the channel structure CH and the contact plug 170, and first to third cell region insulating layers 192, 194 and 196 covering the gate electrode 130.

[0032] In the memory cell region CELL, in the first region R1, gate electrodes 130 can be stacked vertically and a channel structure CH can be configured, and memory cells can be disposed in the first region R1. In the second region R2, gate electrodes 130 can extend to different lengths and can form a gate pad region GP, ​​and the second region R2 can be configured to electrically connect the memory cells to the peripheral circuit region PERI. The second region R2 can be disposed at least at at least one end of the first region R1 in at least one direction (e.g., in the first direction (X direction)). In the example implementation, the first region R1 can be referred to as the memory cell array region, and the second region R2 can be referred to as the stepped region.

[0033] The source structure SS may include a plate layer 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104 stacked sequentially in the first region R1. However, in the example implementation, the number of conductive layers included in the source structure SS may vary. In the example implementation, the source structure SS may be referred to as a stacked pattern.

[0034] The plate layer 101 may have a plate shape and may serve as at least a portion of the common source line of the semiconductor device 100. The plate layer 101 may have an upper surface extending in a first direction (X direction) and a second direction (Y direction). The plate layer 101 may include a conductive material. For example, the plate layer 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. The plate layer 101 may further include impurities. The plate layer 101 may be provided as a polycrystalline semiconductor layer (such as a polycrystalline silicon layer) or an epitaxial layer.

[0035] A first horizontal conductive layer 102 and a second horizontal conductive layer 104 may be sequentially stacked on the upper surface of the plate layer 101 in the first region R1. The first horizontal conductive layer 102 may not extend into the second region R2, while the second horizontal conductive layer 104 may extend into the second region R2. The first horizontal conductive layer 102 may be used as part of the common source line of the semiconductor device 100, for example, it may be used together with the plate layer 101 as a common source line. Figure 1D As shown, the first horizontal conductive layer 102 can be directly connected to the channel layer 140 around the channel layer 140. The second horizontal conductive layer 104 can contact the plate layer 101 in a portion of the second region R2 where the first horizontal conductive layer 102 and the horizontal insulating layer 110 are not disposed.

[0036] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may comprise semiconductor materials, such as polysilicon. In this case, at least the first horizontal conductive layer 102 may be a layer doped with impurities of the same conductivity type as the plate layer 101, and the second horizontal conductive layer 104 may be a doped layer or a layer comprising impurities diffused from the first horizontal conductive layer 102. However, the material of the second horizontal conductive layer 104 is not limited to semiconductor materials and may also be replaced with an insulating layer.

[0037] A horizontal insulating layer 110 may be disposed at the same level as the first horizontal conductive layer 102 on the plate layer 101 in at least a portion of the second region R2. The horizontal insulating layer 110 may comprise a first horizontal insulating layer 111 and a second horizontal insulating layer 112 alternately stacked on the second region R2 of the plate layer 101. The horizontal insulating layer 110 may be a layer remaining after a portion of it has been replaced with the first horizontal conductive layer 102 during the process of manufacturing the semiconductor device 100.

[0038] The horizontal insulating layer 110 may include silicon oxide, silicon nitride, silicon carbide, or silicon nitride. The first horizontal insulating layer 111 and the second horizontal insulating layer 112 may include different insulating materials. For example, the first horizontal insulating layer 111 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 may be formed of a different material than the interlayer insulating layer 120.

[0039] The substrate insulating layer 121 may be configured to penetrate the plate layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 within a portion of the second region R2. The substrate insulating layer 121 may be further disposed within the first region R1, for example, in a region where a through path extending from the memory cell region (CELL) to the peripheral circuit region (PERI) is formed. The upper surface of the substrate insulating layer 121 may be coplanar with the upper surface of the second horizontal conductive layer 104. The substrate insulating layer 121 may comprise an insulating material, such as silicon oxide, silicon nitride, silicon carbide, or silicon nitride.

[0040] Gate electrodes 130 may be vertically stacked and spaced apart on layer 101, and may be included in the gate structure GS together with interlayer insulating layer 120. The gate structure GS may include a first stacked structure GS1, a second stacked structure GS2, and a third stacked structure GS3, which are vertically stacked. However, in the example implementation, the number of stacked structures included in the gate structure GS may vary. For example, the gate structure GS may include four or more stacked structures, or it may include a single stacked structure or two stacked structures. The number of gate electrodes 130 included in the first stacked structure GS1, the number of gate electrodes 130 included in the second stacked structure GS2, and the number of gate electrodes 130 included in the third stacked structure GS3 may be the same as or different from each other.

[0041] The gate electrode 130 may include a lower gate electrode 130L forming the gate of a ground select transistor, a memory gate electrode 130M included in a plurality of memory cells, and an upper gate electrode 130U forming the gate of a string select transistor. The number of memory gate electrodes 130M included in the memory cells may be determined depending on the capacity of the semiconductor device 100. In an example implementation, each of the number of upper gate electrodes 130U and the number of lower gate electrodes 130L may be one to four or more, and the upper gate electrodes 130U and the lower gate electrodes 130L may have the same or different structures as the memory gate electrode 130M. In an example implementation, the gate electrode 130 may further include a gate electrode 130 disposed adjacent to the upper gate electrode 130U and / or the lower gate electrode 130L and included in an erase transistor used in an erase operation utilizing the gate-induced drain leakage (GIDL) phenomenon. Furthermore, a portion of the gate electrode 130 (e.g., the memory gate electrode 130M adjacent to the upper gate electrode 130U or the lower gate electrode 130L) may be a dummy gate electrode.

[0042] like Figure 1A As shown, the gate electrodes 130 can be isolated from each other in the second direction (Y direction) by isolation regions MS extending continuously in the first region R1 and the second region R2. Between a pair of isolation regions MS, the gate electrodes 130 can form a memory block, but the scope of the memory block is not limited thereto. A portion of the gate electrodes 130 (e.g., memory gate electrode 130M) can each form a layer in a memory block.

[0043] The gate electrodes 130 may be stacked vertically spaced apart from each other on the first region R1, may extend from the first region R1 to the second region R2 at different lengths, and may form a stepped structure in the gate pad region GP. The gate pad region GP may be defined as the region of the gate electrode 130 including the gate pad connected to the contact plug 170.

[0044] like Figure 1BAs shown, the gate electrode 130 can have a gate pad region GP that has been removed to a predetermined depth from the top of one of the first to third stacked structures GS1, GS2, and GS3. The gate pad regions GP can be configured not to overlap each other in a third direction (Z direction) which is vertical. The gate electrodes 130 included in the second stacked structures GS2 and the third stacked structures GS3 on the gate pad region GP of the first stacked structure GS1 can extend horizontally. In the example implementation, the gate pad regions GP can be arranged from the first region R1 in the first direction (X direction) in the order of the third stacked structure GS3, the second stacked structure GS2, and the first stacked structure GS1. As shown, only one gate pad region GP can be arranged in each of the first stacked structures GS1, the second stacked structure GS2, and the third stacked structure GS3, or multiple gate pad regions GP can be arranged in each of the first stacked structures GS1, the second stacked structure GS2, and the third stacked structure GS3. However, the arrangement shape, arrangement order, and depth of the gate pad regions GP in the example implementation can vary. In the example, the gate electrode 130 may not be arranged on the gate pad region GP.

[0045] The gate electrode 130 can be formed in each gate pad region GP with a first stepped structure and a second stepped structure in an asymmetrical shape along a first direction (X direction). The first stepped structure can be a stepped structure that is relatively adjacent to the first region R1 and decreases horizontally along the first direction (X direction), and the second stepped structure can be a stepped structure that is relatively far away from the first region R1 and increases horizontally along the first direction (X direction). For example, in the second region R2, the slope of the first stepped structure in each gate pad region GP can be less than the slope of the second stepped structure. However, in some example implementations, the first stepped structure and the second stepped structure can have symmetrical shapes.

[0046] In the first stepped structure, the gate electrode 130 can be connected to the contact plug 170. In the second stepped structure, the gate electrode 130 can form a dummy region that is not connected to the contact plug 170. In the example implementation, the specific shape of the stepped structure and the number of gate electrodes 130 forming each stepped structure are not limited to... Figure 1B The example shown. In some example implementations, the gate electrode 130 may also be configured to have a stepped structure in the second direction (Y direction). The gate electrode 130 may include a contact region (not shown) connected to the contact plug 170. The contact region may be an area of ​​the gate electrode layer not covered by other gate electrodes in a stacked structure, and may be defined as the area of ​​the gate pad that contacts the contact plug 170 in each stacked structure GS in which the second region R2 is set.

[0047] The gate electrode 130 may include a metallic material, such as tungsten (W). In an example implementation, the gate electrode 130 may include polysilicon or a metal silicide material. In an example implementation, the gate electrode 130 may further include a diffusion barrier, for example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0048] Interlayer insulating layers 120 may be disposed between gate electrodes 130. Similar to gate electrodes 130, interlayer insulating layers 120 may also be spaced apart from each other in the vertical direction and extend on the upper surface of the plate layer 101 in a first direction (X direction). In each of the first stack structure GS1, the second stack structure GS2, and the third stack structure GS3, the thickness of the interlayer insulating layer 120 may be different. In the example, at least a portion of the interlayer insulating layer 120 may have a different thickness than other portions. Furthermore, the number of interlayer insulating layers 120 may differ from the example shown. Interlayer insulating layers 120 may comprise insulating materials such as silicon oxide or silicon nitride.

[0049] Each channel structure CH can form a string of memory cells and can be spaced apart from each other in rows and columns on the board 101 in the first region R1. The channel structure CH can be arranged in a grid pattern in the XY plane or in a zigzag pattern in one direction. The channel structure CH can have a column shape and can have inclined side surfaces such that the cross-section of the channel structure CH along the third direction (Z direction) has a width that decreases toward the board 101 depending on the aspect ratio. In the example implementation, at least a portion of the channel structure CH located at the end of the first region R1 can be a dummy channel structure.

[0050] Reference Figure 1DEach channel structure CH may include a first channel portion CH1, a second channel portion CH2, and a third channel portion CH3 stacked in a third direction (Z direction). The first channel portion CH1, the second channel portion CH2, and the third channel portion CH3 may penetrate the first stacked structure GS1, the second stacked structure GS2, and the third stacked structure GS3 of the gate structure GS, respectively. The channel structure CH may have the form where the first channel portion CH1, the second channel portion CH2 above the first channel portion CH1, and the third channel portion CH3 above the second channel portion CH2 are connected to each other. The first channel portion CH1, the second channel portion CH2, and the third channel portion CH3 may have a form where the width of the upper surface of the lower channel portion disposed in the connection region or on the interface surface is greater than the width of the lower surface of the upper channel portion disposed in the upper channel portion. The channel structure CH may have a curved portion due to the width difference at the interface surface between the first channel portion CH1, the second channel portion CH2, and the third channel portion CH3. However, in the example implementation, the number of channel portions stacked in the third direction (Z direction) of the channel structure CH can vary. The first channel portion CH1 can further penetrate a portion of the source structure SS, and the lower end of the first channel portion CH1 can be located in the plate 101.

[0051] Each channel structure CH may include a channel layer 140, a gate dielectric layer 145, a channel filling insulating layer 147, and a channel pad 149 disposed in a channel via. The channel layer 140, the gate dielectric layer 145, and the channel filling insulating layer 147 may be interconnected among the first channel portion CH1, the second channel portion CH2, and the third channel portion CH3.

[0052] The channel layer 140 may be formed in a cup shape surrounding a channel-filling insulating layer 147, but in the example implementation, the channel layer 140 may also have a cylindrical or prism-shaped column shape without the channel-filling insulating layer 147. The channel layer 140 may be connected at its lower portion to a first horizontal conductive layer 102. The channel layer 140 may include a semiconductor material, such as polycrystalline silicon or monocrystalline silicon.

[0053] A gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not specifically shown, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a barrier layer stacked sequentially from the channel layer 140. The tunneling layer can tunnel charge into the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), or combinations thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The barrier layer may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), a high-k dielectric material, or combinations thereof. In an example implementation, at least a portion of the gate dielectric layer 145 may extend horizontally along the gate electrode 130.

[0054] The channel pad 149 may be disposed only on the upper end of the upper third channel portion CH3. The channel pad 149 may include, for example, doped polysilicon.

[0055] The isolation region MS can penetrate at least a portion of the gate electrode 130 and can extend in a first direction (X direction). For example... Figure 1A As shown, isolation zones MS can be arranged parallel to each other. A portion of an isolation zone MS can extend along the first zone R1 and the second zone R2 as a complete region, while another portion can extend only to a part of the second zone R2, or it can be intermittently arranged within the first zone R1 and the second zone R2. However, in the example implementation, the arrangement and number of isolation zones MS are not limited to... Figure 1A The example shown.

[0056] The isolation region MS can penetrate the gate electrode 130 stacked on the plate 101, and can further penetrate the first horizontal conductive layer 102 and the second horizontal conductive layer 104 below the gate electrode 130, and can be connected to the plate 101. The isolation region MS can have a shape in which its width decreases toward the plate 101 due to a high aspect ratio. For example, the side surface of the isolation region MS can have a substantially constant slope, such that the width can decrease continuously or coherently, and can have no curved portions on the side surface.

[0057] In the isolation region MS, a first isolation insulating layer 105 may be provided. The first isolation insulating layer 105 may include, for example, silicon oxide, silicon nitride, or silicon nitride.

[0058] Reference Figure 1A and Figure 1DThe auxiliary isolation region US can extend in the first direction (X direction) between adjacent isolation regions MS. The auxiliary isolation region US can be located in a portion of the second region R2 and the first region R1. The auxiliary isolation region US can penetrate a portion of the gate electrode 130, including the uppermost upper gate electrode 130U of the gate electrode 130. The auxiliary isolation region US can, for example, isolate three gate electrodes 130 from each other in the second direction (Y direction). However, in the example implementation, the number of gate electrodes 130 isolated by the auxiliary isolation region US can vary.

[0059] A second isolation insulating layer 103 may be provided in the auxiliary isolation region US. The second isolation insulating layer 103 may include, for example, silicon oxide, silicon nitride, or silicon nitride.

[0060] Contact plug 170 can be connected to the gate pad region GP of gate electrode 130 in the second region R2. Contact plug 170 can penetrate at least a portion of cell region insulating layers 192, 194, and 196, and can be connected to each gate pad region GP whose upper surface of gate electrode 130 is exposed. Contact plug 170 can penetrate the gate electrode 130 above and below the gate pad region GP, ​​and can penetrate the second horizontal conductive layer 104, the horizontal insulating layer 110, and the plate layer 101, and can be connected to the circuit interconnect 280 in the peripheral circuit region PERI. Contact plug 170 can be spaced apart from the gate electrode 130 above and below the gate pad region GP by contact insulating structure 160. Contact plug 170 can be spaced apart from plate layer 101, horizontal insulating layer 110, and second horizontal conductive layer 104 by substrate insulating layer 121.

[0061] Contact plugs 170 may have a shape corresponding to the channel structure CH. Each contact plug 170 may include first to third contact portions MC1, MC2, and MC3 stacked from the bottom. The first contact portion MC1, the second contact portion MC2, and the third contact portion MC3 may penetrate the first stacked structure GS1, the second stacked structure GS2, and the third stacked structure GS3 of the gate structure GS, respectively. The first contact portion MC1 may further penetrate the substrate insulating layer 121. The first to third contact portions MC1, MC2, and MC3 may have a cylindrical shape in which their width decreases towards the substrate 201 due to the aspect ratio. Each of the first to third contact portions MC1, MC2, and MC3 may have a substantially constant slope. The first contact portion MC1 may further include a landing region whose width is expanded below the substrate insulating layer 121. However, in some example implementations, the first contact portion MC1 may not include a landing region.

[0062] The first contact portion MC1, the second contact portion MC2, and the third contact portion MC3 may have a shape in which the width of the upper surface of the contact portion disposed at the lower part in the interconnect region or on the interface surface is greater than the width of the lower surface of the contact portion disposed at the upper part. Therefore, similar to the channel structure CH, the contact plug 170 may have a curved portion due to the width difference at the interface surface between the first contact portion MC1, the second contact portion MC2, and the third contact portion MC3.

[0063] The level of the interface surface between the first contact portion MC1 and the second contact portion MC2 can be the same as the level of the interface surface between the first channel portion CH1 and the second channel portion CH2. In the example, the level of the upper surface of the first contact portion MC1 can be the same as the level of the upper surface of the first channel portion CH1, and the level of the upper surface of the second contact portion MC2 can be the same as the level of the upper surface of the second channel portion CH2.

[0064] The contact plug 170 may include a conductive material, such as at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In some example implementations, the contact plug 170 may include a barrier layer extending along a side surface and a bottom surface, or may have an air gap therein.

[0065] Contact insulation structure 160 may be configured to surround the side surface of each contact plug 170 above and below the gate pad region GP. In some implementations, contact insulation structure 160 may be disposed above the corresponding gate pad region GP. In some implementations, contact insulation structure 160 may be disposed both above and below the corresponding gate pad region GP. In some implementations, contact insulation structure 160 may be disposed below the corresponding gate pad region GP. In this disclosure, contact insulation structure 160 disposed above and / or below the corresponding gate pad region GP may also be described as disposed in the corresponding gate pad region GP. Contact insulation structures 160 may be spaced apart from each other in a third direction (Z direction) around each contact plug 170. Contact insulation structure 160 may extend horizontally from the side surface of each contact plug 170. Contact insulation structures 160 may be disposed at substantially the same level as the gate electrode 130. Contact insulation structure 160 may include an insulating material, such as silicon oxide, silicon nitride, or silicon nitride.

[0066] The contact insulation structure 160 may include a first contact insulation structure 160a and a second contact insulation structure 160b different from the first contact insulation structure 160a. In an example, the first contact insulation structure 160a may surround a first contact plug 170a. The second contact insulation structure 160b may surround a second contact plug 170b and a second dummy vertical structure 175b.

[0067] The contact plug 170 may include a first contact plug 170a and a second contact plug 170b. The first contact plug 170a may be a contact plug surrounded by a first contact insulation structure 160a, and the second contact plug 170b may be a contact plug surrounded by a second contact insulation structure 160b.

[0068] Reference Figure 1A , Figure 1B and Figure 1C The dummy vertical structures 175 can be spaced apart from each other in rows and columns within the second region R2. The dummy vertical structures 175 can be configured to surround each contact plug 170. For example, as... Figure 1A As shown, when viewed in a plane, four dummy vertical structures 175 may surround each contact plug 170. In the example, at least one of the four dummy vertical structures 175 may share the second contact insulation structure 160b with the second contact plug 170b.

[0069] like Figure 1C As shown, the dummy vertical structures 175 can be regularly arranged in regions of the contact plugs 170 spaced apart from each other along a first direction (X direction). However, in the example implementation, the arrangement shape of the dummy vertical structures 175 can vary. When viewed in a plane, the dummy vertical structures 175 can have a circular shape, an elliptical shape, or a similar shape.

[0070] The dummy vertical structure 175 may have a shape corresponding to the contact plug 170. Each dummy vertical structure 175 may include first to third dummy extensions IC1, IC2, and IC3 stacked from the bottom. The first to third dummy extensions IC1, IC2, and IC3 may penetrate the gate structure GS. The lower surface of the first dummy extension IC1 may be buried in the board layer 101. The first to third dummy extensions IC1, IC2, and IC3 may have a cylindrical shape in which their width decreases towards the board layer 101 due to the aspect ratio.

[0071] The first to third dummy extensions IC1, IC2, and IC3 may have a shape in which the width of the upper surface of the dummy extension disposed at the lower part in the connection area or on the interface surface is greater than the width of the lower surface of the dummy extension disposed at the upper part. Therefore, similar to the contact plug 170, the dummy vertical structure 175 may also have a curved portion due to the width difference at the interface surface between the first to third dummy extensions IC1, IC2, and IC3.

[0072] The dummy vertical structure 175 may have the same or different structure as the channel structure CH. When the dummy vertical structure 175 is formed together with the channel structure CH, the dummy vertical structure 175 may have the same structure as the channel structure CH. The diameter or maximum width of the dummy vertical structure 175 may be greater than the diameter of the channel structure CH, but its example implementation is not limited to this.

[0073] When the dummy vertical structure 175 is formed using a portion of the process for forming the contact plug 170, the dummy vertical structure 175 may have a structure different from the channel structure CH. The dummy vertical structure 175 does not include a conductive layer and may include an insulating material. For example, the dummy vertical structure 175 may include silicon oxide, silicon nitride, or silicon nitride.

[0074] Unlike the channel structure in semiconductor device 100, the dummy vertical structure 175 may not be electrically connected to the upper interconnect structure and may not form a memory cell string.

[0075] The dummy vertical structure 175 may include a first dummy vertical structure 175a and a second dummy vertical structure 175b. The dummy vertical structure 175 that is adjacent to the first contact plug 170a and surrounded by the dummy insulating structure 150 may be the "first dummy vertical structure 175a", and the dummy vertical structure 175 that is adjacent to the second contact plug 170b and shares the second contact insulating structure 160b with the second contact plug 170b may be the "second dummy vertical structure 175b".

[0076] The dummy insulation structures 150 may be spaced apart from each other in the third direction (Z direction) around each first dummy vertical structure 175a. The dummy insulation structures 150 may be alternately arranged with the interlayer insulation layer 120 and positioned at substantially the same level as each gate electrode 130. Each dummy insulation structure 150 may be positioned at the same level as the first contact insulation structure 160a and the second contact insulation structure 160b.

[0077] Pillar 180 can form a cell interconnect structure electrically connected to memory cells in the memory cell area CELL. Pillar 180 can be connected to the channel structure CH and contact plug 170, and can be electrically connected to the channel structure CH and gate electrode 130. Pillar 180 can be in the form of a plug, but its example implementation is not limited to this, and can also be in the form of a wire. In the example implementation, the number of plugs and interconnects included in the cell interconnect structure can vary. Pillar 180 can include metals, such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0078] The first to third unit region insulating layers 192, 194, and 196 can be configured to cover the gate electrode 130 and the interlayer insulating layer 120 in the first stacked structure GS1, the second stacked structure GS2, and the third stacked structure GS3, respectively. The first to third unit region insulating layers 192, 194, and 196 can be disposed at the top of the first stacked structure GS1, the second stacked structure GS2, and the third stacked structure GS3. Each of the first unit region insulating layers 192, 194, and 196 can be formed of an insulating material, and multiple insulating layers can be formed. When the first unit region insulating layers 192, 194, and 196 comprise the same material as the interlayer insulating layer 120, the interface surface with the interlayer insulating layer 120 can be indistinguishable. In the example implementation, the first unit region insulating layers 192, 194, and 196, as well as the interlayer insulating layer 120, can be collectively referred to as the interlayer insulating layer.

[0079] In the example implementation, the first direction (X direction) and the second direction (Y direction) can be perpendicular to each other. The first direction (X direction) and the second direction (Y direction) can be perpendicular to a third direction (Z direction). The horizontal direction can indicate the first direction (X direction) and the second direction (Y direction), or a direction at an angle relative to the first direction or the second direction, and the vertical direction can indicate a third direction (Z direction). The horizontal direction, the first direction, and the second direction can all be horizontal.

[0080] Figure 2 It is shown Figure 1B An enlarged view of region C of the semiconductor device.

[0081] Reference Figure 2 The contact plug 170 can be connected to the first gate electrode portion 130a of the gate electrode 130 via the gate pad region GP. (Refer to...) Figure 2 The described contact plug 170 can also be applied to Figure 1A The first contact plug 170a and the second contact plug 170b are referenced. Figure 2 The described contact insulation structure 160 can also be applied to Figure 1B The first contact insulation structure 160a and the second contact insulation structure 160b are in the middle.

[0082] The contact plug 170 may have a form that expands in the horizontal direction toward the first gate electrode portion 130a. In an example, the contact plug 170 may include a vertical extension 170V and a horizontal extension 170H, the vertical extension 170V penetrating the gate electrode 130 and the interlayer insulating layer 120 and extending in the third direction (Z direction), and the horizontal extension 170H expanding in the horizontal direction from the vertical extension 170V and contacting the gate pad region GP.

[0083] Each gate electrode 130 may include a gate pad region GP and a gate stack region GN, the gate stack region GN being the area other than the gate pad region GP. The gate pad region GP may be a region of the gate electrode layer that is not covered by other gate electrodes due to the stepped structure. The gate stack region GN may be another region of the gate electrode layer that is covered by other gate electrodes. The gate pad region GP may contact the horizontal extension 170H of the contact plug 170.

[0084] Each gate electrode 130 may include a first gate electrode portion 130a corresponding to the gate pad region GP and a second gate electrode portion 130b corresponding to the gate stack region GN. In the example implementation, the first gate electrode portion 130a may be referred to as a gate contact pad, and the second gate electrode portion 130b may be referred to as a gate stack structure.

[0085] The contact insulation structure 160 may be alternately disposed with the interlayer insulation layer 120, and may be disposed at the same level as the second gate electrode portion 130b of the gate electrode 130 below the gate pad region GP. The contact insulation structure 160 may be disposed between the gate stack region GN and the vertical extension portion 170V. The contact insulation structure 160 may overlap with the horizontal extension portion 170H of the contact plug 170 in the third direction (Z direction). The contact plug 170 may be electrically isolated from the second gate electrode portion 130b below the gate pad region GP by means of the contact insulation structure 160.

[0086] Each contact insulation structure 160 may include a contact insulation pattern 164 surrounding a side surface of a contact plug 170 and a contact insulation pad 162 surrounding an outer surface of the contact insulation pattern 164. The contact insulation pad 162 may contact a second gate electrode portion 130b of the gate electrode 130. The contact insulation pattern 164 may include a first insulating material, and the contact insulation pad 162 may include a second insulating material different from the first insulating material. For example, the contact insulation pattern 164 may include silicon nitride, and the contact insulation pad 162 may include silicon oxide.

[0087] Figure 3 It is shown Figure 1A An enlarged view of region A of the semiconductor device. Figure 4 This illustrates the semiconductor device along the example implementation. Figure 3 The cross-sectional view taken by line A-A' in the diagram. Figure 3 It shows the setting with Figure 2 A plan view of the first contact plug 170a, the first contact insulation structure 160a, the first dummy vertical structure 175a, and the dummy insulation structure 150 at the same level as the second gate electrode portion 130b.

[0088] Reference Figure 3 and Figure 4 Region A of the semiconductor device 100 may include a first contact plug 170a disposed between isolation regions MS, a first dummy vertical structure 175a adjacent to the first contact plug 170a, and a gate contact region (e.g., Figure 1B The lower part of the gate pad region (GP) surrounds the first contact plug 170a and is spaced apart from each other in the third direction (Z direction) by a first contact insulation structure 160a, and dummy insulation structures 150 surround the first dummy vertical structure 175a and are spaced apart from each other in the third direction (Z direction).

[0089] The isolation regions MS can extend in a first direction (X direction) and can be spaced apart from each other in a second direction (Y direction). For example, the isolation regions MS can include a first isolation region extending in the first direction (X direction) and a second isolation region spaced apart from the first isolation region in the second direction (Y direction). The first contact plug 170a can be disposed between the first isolation region and the second isolation region.

[0090] The first contact insulation structure 160a may surround the vertically extending portion of the first contact plug 170a (e.g., Figure 2 The first contact plug 170a has a vertical extension 170V and may be spaced apart from each other in the third direction (Z direction). The first contact insulation structure 160a may be alternately disposed with the interlayer insulation layer 120 in the third direction (Z direction). Each first contact insulation structure 160a may include a 1-1 contact insulation pattern 164a surrounding the vertical extension 170V of the first contact plug 170a and a first contact insulation pad 162a surrounding the 1-1 contact insulation pattern 164a. In an example, the 1-1 contact insulation pattern 164a may include a first insulating material, and the first contact insulation pad 162a may include a second insulating material different from the first insulating material. For example, the 1-1 contact insulation pattern 164a may include silicon nitride, and the first contact insulation pad 162a may include at least one of silicon oxide, silicon carbide, and silicon oxide nitride.

[0091] The first dummy vertical structure 175a can be disposed adjacent to the first contact plug 170a and can surround the first contact plug 170a. The first dummy vertical structure 175a can include four dummy structures surrounding the first contact plug 170a. In the example, the first dummy vertical structure 175a can include dummy vertical structure 1751a, dummy vertical structure 1752a, dummy vertical structure 1753a, and dummy vertical structure 1754a. In the example, when viewed in a plane, dummy vertical structure 1751a can be disposed on the upper left side of the first contact plug 170a, dummy vertical structure 1752a can be disposed on the upper right side of the first contact plug 170a, dummy vertical structure 1753a can be disposed on the lower left side of the first contact plug 170a, and dummy vertical structure 1754a can be disposed on the lower right side of the first contact plug 170a. In the example, when viewed in a plane, the dummy vertical structures 1-1 and 1-2 can contact the first isolation zone located above the first contact plug 170a in the isolation zone MS. When viewed in a plane, the dummy vertical structures 1-3 and 1-4 can contact the second isolation zone located below the first contact plug 170a in the isolation zone MS.

[0092] Each first dummy vertical structure 175a may include a first portion Sa adjacent to the first contact plug 170a, a second portion Sb extending from and connected to the first portion Sa, and a third portion Sc connecting the second portions Sb to each other and contacting the isolation region MS. The first portion Sa of the first dummy vertical structure 175a may be closer to the first contact plug 170a than the second portion Sb of the first dummy vertical structure 175a. The third portion Sc of each first dummy vertical structure 175a may be a side surface exposed through the gate electrode 130.

[0093] When viewed in a plane, the spacing between the first contact plug 170a and the first dummy vertical structure 175a can be the same. For example, when viewed in a plane, the distances between the first contact plug 170a and the dummy vertical structure 1751a, the first contact plug 170a and the dummy vertical structure 1752a, the first contact plug 170a and the dummy vertical structure 1753a, and the first contact plug 170a and the dummy vertical structure 1754a can be the same. However, the exemplary implementation is not limited to this. For example, the spacing between the first contact plug 170a and the first dummy vertical structure 175a can be different.

[0094] Each first dummy vertical structure 175a may be surrounded by a dummy insulating structure 150. In the example, the dummy insulating structures 150 may surround dummy vertical structures 1-1 1751a, 1-2 1752a, 1-3 1753a, and 1-4 1754a respectively, and may be spaced apart from each other in the third direction (Z direction). For example, the dummy insulating structures 150 may be alternately arranged with the interlayer insulating layer 120 and may surround dummy vertical structure 1751a. In the example, the dummy insulating structures 150 may be arranged at the same level as the gate electrode 130 and the first contact insulating structure 160a.

[0095] The dummy insulating structures 150 surrounding the 1-1 dummy vertical structure 1751a can be spaced apart from each other in the third direction (Z direction) and can be spaced apart in the horizontal direction from the dummy insulating structure 150 surrounding the 1-2 dummy vertical structure 1752a. The dummy insulating structure 150 can be spaced apart in the horizontal direction from the first contact insulating structure 160a. In the example, when viewed in a plane, the gate electrode 130 can be disposed between the dummy insulating structure 150 and the first contact insulating structure 160a.

[0096] The dummy insulation structure 150 may include a first dummy insulation pattern 154 surrounding a first portion Sa of each first dummy vertical structure 175a, a second dummy insulation pattern 156 surrounding a second portion Sb of each first dummy vertical structure 175a, and a dummy insulation pad 152 surrounding the first dummy insulation pattern 154 and the second dummy insulation pattern 156. For example, the dummy insulation structure 150 surrounding the 1-1 dummy vertical structure 1751a may include a first dummy insulation pattern 154 in contact with the first portion Sa of the 1-1 dummy vertical structure 1751a, a second dummy insulation pattern 156 in contact with the second portion Sb of the 1-1 dummy vertical structure 1751a, and a dummy insulation pad 152 surrounding the first dummy insulation pattern 154 and the second dummy insulation pattern 156. The first dummy insulation pattern 154 may correspond to the surface profile of the first portion Sa, and the second dummy insulation pattern 156 may correspond to the surface profile of the second portion Sb. When viewed in a plane, the second dummy insulating pattern 156 may be disposed between the first dummy insulating pattern 154 and the isolation region MS. In the example, the first dummy insulating pattern 154 may be disposed closer to the first contact plug 170a than the second dummy insulating pattern 156. When viewed in a plane, the second dummy insulating pattern 156 of each of the 1-1 dummy vertical structures 1751a and 1-2 dummy vertical structures 1752a may be disposed between the first dummy insulating pattern 154 of each of the 1-1 dummy vertical structures 1751a and 1-2 dummy vertical structures 1752a and the first isolation region disposed above the first contact plug 170a in the isolation region MS. When viewed in a plane, the second dummy insulation pattern 156 of each of the dummy vertical structures 1-3 1753a and 1-4 1754a can be disposed between the first dummy insulation pattern 154 of each of the dummy vertical structures 1-3 1753a and 1-4 1754a and the second isolation zone disposed on the lower side of the first contact plug 170a in the isolation zone MS.

[0097] The first dummy insulating pattern 154 of the dummy vertical structure 1751a (1-1) can be arranged side-by-side with the first dummy insulating pattern 154 of the dummy vertical structure 1752a (1-2) in the first direction (X direction). The second dummy insulating pattern 156 of the dummy vertical structure 1751a (1-1) can be arranged side-by-side with the second dummy insulating pattern 156 of the dummy vertical structure 1752a (1-2) in the first direction (X direction). The first dummy insulating pattern 154 of the dummy vertical structure 1753a (1-3) can be arranged side-by-side with the first dummy insulating pattern 154 of the dummy vertical structure 1754a (1-4) in the first direction (X direction). The second dummy insulating pattern 156 of the dummy vertical structure 1753a (1-3) can be arranged side-by-side with the second dummy insulating pattern 156 of the dummy vertical structure 1754a (1-4) in the first direction (X direction).

[0098] The first dummy insulating pattern 154 may include a first insulating material, and the second dummy insulating pattern 156 may include a second insulating material different from the first insulating material. For example, the first dummy insulating pattern 154 may include silicon nitride, and the second dummy insulating pattern 156 may include silicon oxide.

[0099] Figure 5 It is shown Figure 1A An enlarged view of region B of the semiconductor device. Figure 6A This illustrates the semiconductor device along the example implementation. Figure 5 The cross-sectional view taken by line B-B' in the diagram. Figure 6B This illustrates a semiconductor device implemented according to another example. Figure 5 The cross-sectional view taken by line B-B' in the diagram. Figure 5 It shows the setting with Figure 2 A plan view of the second contact plug 170b, the first dummy vertical structure 175a and the second dummy vertical structure 175b, the dummy insulating structure 150 and the second contact insulating structure 160b, which are at the same level as the second gate electrode portion 130b.

[0100] Reference Figure 5 and Figure 6A Region B of the semiconductor device 100 may include a second contact plug 170b disposed between isolation regions MS, a first dummy vertical structure 175a and a second dummy vertical structure 175b adjacent to the second contact plug 170b, and a gate contact region of the second contact plug 170b (e.g., Figure 1B The lower portion of the gate pad region (GP) surrounds the second contact plug 170b and the second dummy vertical structure 175b and is spaced apart from each other in the third direction (Z direction) by a second contact insulating structure 160b, and surrounds each first dummy vertical structure 175a and is spaced apart from each other in the third direction (Z direction).

[0101] The second contact plug 170b can be disposed between the isolation zones MS. The first dummy vertical structure 175a and the second dummy vertical structure 175b can be disposed adjacent to and surrounding the second contact plug 170b. In the example, one second dummy vertical structure 175b and three first dummy vertical structures 175a can surround the second contact plug 170b. For example, the second dummy vertical structure 175b, 1-2 dummy vertical structures 1752a, 1-3 dummy vertical structures 1753a, and 1-4 dummy vertical structures 1754a can surround the second contact plug 170b. The second dummy vertical structure 175b can be located on the upper left side of the second contact plug 170b, the dummy vertical structure 1752a can be located on the upper right side of the second contact plug 170b, the dummy vertical structure 1753a can be located on the lower left side of the second contact plug 170b, and the dummy vertical structure 1754a can be located on the lower right side of the second contact plug 170b. However, the example implementation is not limited to this; the second dummy vertical structure 175b can be located on the upper right side of the second contact plug 170b, or it can be located on the lower left or lower right side of the second contact plug 170b.

[0102] When viewed in a plane, the second dummy vertical structure 175b and the 1-2 dummy vertical structure 1752a can contact the first isolation area located above the second contact plug 170b in the isolation area MS. When viewed in a plane, the 1-3 dummy vertical structure 1753a and the 1-4 dummy vertical structure 1754a can contact the second isolation area located below the second contact plug 170b in the isolation area MS.

[0103] The second dummy vertical structure 175b may include a first portion Sa adjacent to the second contact plug 170b, a second portion Sb extending from and connected to the first portion Sa, and a third portion Sc connecting the second portion Sb and contacting the isolation region MS. In the example, the first portion Sa of the second dummy vertical structure 175b may be closer to the second contact plug 170b than the second portion Sb of the second dummy vertical structure 175b.

[0104] The second contact plug 170b and the second dummy vertical structure 175b may share the second contact insulation structure 160b. Each second contact insulation structure 160b may be connected to the vertical extension of the second contact plug 170b (e.g., Figure 2The second contact insulation structure 160b contacts the second contact plug 170b and the second dummy vertical structure 175b, and may be spaced apart from each other in the third direction (Z direction). The second contact insulation structure 160b may be alternately disposed with the interlayer insulation layer 120 in the third direction (Z direction). Each second contact insulation structure 160b may contact the second contact plug 170b and the second dummy vertical structure 175b below the gate pad region GP.

[0105] Each second contact insulation structure 160b may include a 2-1 contact insulation pattern 164b that contacts the vertical extension 170V of the second contact plug 170b and the first portion Sa of the second dummy vertical structure 175b, a 2-2 contact insulation pattern 166b that extends from the 2-1 contact insulation pattern 164b and contacts the second portion Sb of the second dummy vertical structure 175b, and a second contact insulation pad 162b surrounding the 2-1 contact insulation pattern 164b and the 2-2 contact insulation pattern 166b.

[0106] 2-1 The contact insulation pattern 164b can be arranged along the surface contour of the outer surface of the second contact plug 170b and the outer surface of the first portion Sa of the second dummy vertical structure 175b. 2-2 The contact insulation pattern 166b can be arranged along the surface contour of the outer surface of the second portion Sb of the second dummy vertical structure 175b. When viewed in a plane, the 2-2 contact insulation pattern 166b can be positioned between the 2-1 contact insulation pattern 164b and the isolation area MS.

[0107] 2-1 Contact insulation pattern 164b may include a first insulating material, 2-2 contact insulation pattern 166b may include a second insulating material different from the first insulating material, and the second contact insulation pad 162b may include a third insulating material. For example, 2-1 contact insulation pattern 164b may include silicon nitride, 2-2 contact insulation pattern 166b may include silicon oxide, and the second contact insulation pad 162b may include at least one of silicon oxide, silicon carbide, and silicon oxide nitride.

[0108] The dummy vertical structures 1-2, 1-3, 1-4, and 1-5 can be surrounded by the dummy insulating structure 150. The dummy insulating structure 150 disposed in region B of the semiconductor device 100 can correspond to the dummy insulating structure 150 disposed in region A of the semiconductor device 100.

[0109] The second contact insulation structure 160b may be spaced apart from the dummy insulation structure 150 in the horizontal direction. When viewed in a plane, the gate electrode 130 (e.g., Figure 2The second gate electrode portion 130b can be disposed between the second contact insulation structure 160b and the dummy insulation structure 150.

[0110] In the example, when viewed on a plane, the spacing between the second contact plug 170b and the second dummy vertical structure 175b can be smaller than the spacing between the second contact plug 170b and each of the first dummy vertical structures 175a. For example, the spacing between the second contact plug 170b and the second dummy vertical structure 175b can be smaller than the spacing between the second contact plug 170b and the 1-2 dummy vertical structures 1752a.

[0111] Reference Figure 6A Each second gate electrode portion 130b may have a first height H1 in the third direction (Z direction). Correspondingly, a second contact insulation structure 160b disposed at the same level as the second gate electrode portion 130b may have the same thickness in the third direction (Z direction).

[0112] Reference Figure 6B The second gate electrode portion 130b' may include a 2-1 gate electrode portion 130b_1 having a first height H1 in the third direction (Z direction) and a 2-2 gate electrode portion 130b_2 having a second height H2 greater than the first height H1. Correspondingly, the thickness of the second contact insulation structure 160b disposed at the same level as the 2-1 gate electrode portion 130b_1 may be less than the thickness of the second contact insulation structure 160b disposed at the same level as the 2-2 gate electrode portion 130b_2.

[0113] In an example implementation, the semiconductor device 100 may include a first contact plug 170a and a second contact plug 170b, a first dummy vertical structure 175a surrounding the first contact plug 170a, a second dummy vertical structure 175b adjacent to the second contact plug 170b, a first contact insulating structure 160a surrounding the first contact plug 170a, a second contact insulating structure 160b contacting the second contact plug 170b and the second dummy vertical structure 175b, and a dummy insulating structure 150 surrounding the first dummy vertical structure 175a. However, the example implementation is not limited to this. For example, the semiconductor device 100 may include the first contact plug 170a, the first dummy vertical structure 175a, the first contact insulating structure 160a surrounding the first contact plug 170a, and the dummy insulating structure 150 surrounding the first dummy vertical structure 175a, but does not include... Figure 1A and Figure 5 The second contact plug 170b is shown.

[0114] Figure 7 This illustrates an implementation based on another example. Figure 1AAn enlarged view of region B of the semiconductor device.

[0115] Apart from Figure 7 Apart from the second dummy vertical structure 175b' shown and the second contact insulation structure 160b' that contacts the second dummy vertical structure 175b' and the second contact plug 170b, no other contact insulation structure will be provided. Figure 5 The components shown are identical or corresponding components, and are described repeatedly.

[0116] Reference Figure 7 Region B of semiconductor device 100a may include a second contact plug 170b disposed between isolation regions MS, a first dummy vertical structure 175a and a second dummy vertical structure 175b' adjacent to the second contact plug 170b, and a gate contact region of the second contact plug 170b (e.g., Figure 1B The lower part of the gate pad region GP in the middle surrounds the second contact plug 170b and the second dummy vertical structure 175b' and is spaced apart from each other in the third direction (Z direction) by the second contact insulation structure 160b', and the dummy insulation structures 150 surround the first dummy vertical structure 175a and are spaced apart from each other in the third direction (Z direction).

[0117] The first dummy vertical structure 175a and the second dummy vertical structure 175b' can be disposed adjacent to and around the second contact plug 170b. In the example, the two second dummy vertical structures 175b' and the two first dummy vertical structures 175a can surround the second contact plug 170b. The second dummy vertical structure 175b' can include a 2-1 dummy vertical structure 1751b and a 2-2 dummy vertical structure 1752b spaced apart from the 2-1 dummy vertical structure 1751b in the horizontal direction. For example, the 2-1 dummy vertical structure 1751b and the 2-2 dummy vertical structure 1752b can be spaced apart from each other in a first direction (X direction).

[0118] Virtual vertical structures 1751b (2-1), 1752b (2-2), 1753a (1-3), and 1754a (1-4) can surround the second contact plug 170b. Virtual vertical structure 1751b (2-1) can be positioned on the upper left side of the second contact plug 170b, virtual vertical structure 1752b (2-2) can be positioned on the upper right side of the second contact plug 170b, virtual vertical structure 1753a (1-3) can be positioned on the lower left side of the second contact plug 170b, and virtual vertical structure 1754a (1-4) can be positioned on the lower right side of the second contact plug 170b. However, the example implementation is not limited to this. For example, virtual vertical structure 1751b (2-1) can be positioned on the upper right side of the second contact plug 170b, and virtual vertical structure 1752b (2-2) can be positioned on the lower right side of the second contact plug 170b. In this case, the dummy vertical structure 1753a (1-3) can be set on the upper left side of the second contact plug 170b, and the dummy vertical structure 1754a (1-4) can be set on the lower left side of the second contact plug 170b.

[0119] When viewed in a plane, the 2-1 dummy vertical structure 1751b and 2-2 dummy vertical structure 1752b can contact the first isolation area located above the second contact plug 170b in the isolation area MS. When viewed in a plane, the 1-3 dummy vertical structure 1753a and 1-4 dummy vertical structure 1754a can contact the second isolation area located below the first contact plug 170a in the isolation area MS.

[0120] 2-1 The dummy vertical structure 1751b and 2-2 the dummy vertical structure 1752b may include a first portion Sa adjacent to the second contact plug 170b, a second portion Sb extending from and connected to the first portion Sa, and a third portion Sc connecting the second portions Sb to each other and contacting the isolation region MS. In the example, the first portion Sa of the second dummy vertical structure 175b' may be closer to the second contact plug 170b than the second portion Sb of the second dummy vertical structure 175b'.

[0121] The second contact insulation structure 160b' can be connected to the interlayer insulation layer (e.g., Figure 1B The interlayer insulation layer 120 is alternately disposed with respect to the vertical extension portion of the second contact plug 170b (e.g., Figure 2The second contact insulation structure 160b' can contact the second contact plug 170b, the second dummy vertical structure 1751b, and the second dummy vertical structure 1752b, and can be spaced apart from each other in the third direction (Z direction). The second contact insulation structure 160b' can contact the second contact plug 170b, the second dummy vertical structure 1751b, and the second dummy vertical structure 1752b. The second contact plug 170b, the second dummy vertical structure 1751b, and the second dummy vertical structure 1752b can share the second contact insulation structure 160b'.

[0122] Each second contact insulation structure 160b' may include a vertically extending portion of the second contact plug 170b (e.g., Figure 2 The vertical extension portion 170V), the first portion Sa of the 2-1 dummy vertical structure 1751b and the first portion Sa of the 2-2 dummy vertical structure 1752b, the 2-1 contact insulation pattern 164b' which contacts the second portion Sb of the 2-1 dummy vertical structure 1751b, the 2-3 contact insulation pattern 168b' which contacts the second portion Sb of the 2-2 dummy vertical structure 1752b, and the second contact insulation pad 162b' surrounding the 2-1 contact insulation pattern 164b', the 2-2 contact insulation pattern 166b' and the 2-3 contact insulation pattern 168b'.

[0123] 2-1 Contact insulation pattern 164b' may be set along the surface contours of the outer surface of the second contact plug 170b, the outer surface of the first portion Sa of the 2-1 dummy vertical structure 1751b, and the outer surface of the first portion Sa of the 2-2 dummy vertical structure 1752b. 2-2 Contact insulation pattern 166b' may extend from the side surface of 2-1 contact insulation pattern 164b' and may be set along the surface contour of the outer surface of the second portion Sb of the 2-1 dummy vertical structure 1751b. 2-3 Contact insulation pattern 168b' may extend from the side surface of 2-1 contact insulation pattern 164b' and may be set along the surface contour of the outer surface of the second portion Sb of the 2-2 dummy vertical structure 1752b. 2-2 Contact insulation pattern 166b' and 2-3 Contact insulation pattern 168b' may be disposed between 2-1 contact insulation pattern 164b' and the isolation region MS. The 2-2 contact insulation pattern 166b' and the 2-3 contact insulation pattern 168b' may be spaced apart from each other in the first direction (X direction).

[0124] The 2-1 contact insulation pattern 164b' may include a first insulating material, and the 2-2 contact insulation patterns 166b' and 2-3 contact insulation patterns 168b' may include a second insulating material different from the first insulating material. The second contact insulation pad 162b' may include a third insulating material. For example, the 2-1 contact insulation pattern 164b' may include silicon nitride, the 2-2 contact insulation patterns 166b' and 2-3 contact insulation patterns 168b' may include silicon oxide, and the second contact insulation pad 162b' may include at least one of silicon oxide, silicon carbide, and silicon oxide nitride.

[0125] Each of the dummy vertical structures 1-3 1753a and 1-4 1754a can be surrounded by a dummy insulating structure 150. The dummy insulating structure 150 disposed in region B of the semiconductor device 100a can correspond to the structure disposed in… Figure 5 The dummy insulating structure 150 in region B of semiconductor device 100.

[0126] The second contact insulation structure 160b' may be spaced apart from the dummy insulation structure 150 in the horizontal direction. When viewed in a plane, the gate electrode 130 (e.g., Figure 2 The second gate electrode portion 130b can be disposed between the second contact insulation structure 160b' and the dummy insulation structure 150.

[0127] In the example, when viewed on a plane, the spacing between the second contact plug 170b and the 2-1 dummy vertical structure 1751b can be smaller than the spacing between the second contact plug 170b and the 1-3 dummy vertical structure 1753a (and the 1-4 dummy vertical structure 1754a).

[0128] In another example implementation, the second dummy vertical structure 175b' may include dummy vertical structures 1751b and 1752b as shown in Figure 2-1, but the second dummy vertical structure 175b' may include three dummy vertical structures. In this case, the second dummy vertical structure 175b' may include dummy vertical structure 2-1, dummy vertical structure 2-2, and dummy vertical structure 2-3. Dummy vertical structure 2-1 may be located on the upper left side of the second contact plug 170b, dummy vertical structure 2-2 may be located on the upper right side of the second contact plug 170b, and dummy vertical structure 2-3 may be located on the lower left side of the second contact plug 170b. Each second contact insulation structure 160b' may contact the second contact plug 170b and the three dummy vertical structures 2-1, 2-2, and 2-3 included in the second dummy vertical structure 175b'.

[0129] In an example implementation, semiconductor device 100a may include a first contact plug 170a and a second contact plug 170b, a first dummy vertical structure 175a surrounding the first contact plug 170a, a second dummy vertical structure 175b' adjacent to the second contact plug 170b, a first contact insulating structure 160a surrounding the first contact plug 170a, a second contact insulating structure 160b' in contact with the second contact plug 170b and the second dummy vertical structure 175b', and a dummy insulating structure 150 surrounding the first dummy vertical structure 175a.

[0130] Figures 8 to 10 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example implementation. Figures 8 to 10 Each showed Figure 1A The cross section of the semiconductor device along line IV-IV'.

[0131] Reference Figure 8 Circuit devices 220, circuit interconnection structures, and peripheral region insulating layers 290, including those in the peripheral circuit region PERI, can be formed on the substrate 201.

[0132] A device isolation layer 210 can be formed in substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 can be sequentially formed on substrate 201. The device isolation layer 210 can be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 can be formed of silicon oxide, and the circuit gate electrode 225 can be formed of at least one of polysilicon and metal silicide layers, but the exemplary implementation is not limited to these. Subsequently, spacer layers 224 can be formed on both sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225, and impurity regions 205 can be formed in substrate 201 on both sides of the circuit gate dielectric layer 222 and the circuit gate electrode 225. In the exemplary implementation, the spacer layers 224 can be formed as multiple layers. The impurity regions 205 can be formed by performing an ion implantation process.

[0133] In the circuit interconnect structure, the circuit contact plug 270 can be formed by partially forming a peripheral insulating layer 290, removing a portion of the peripheral insulating layer 290 by etching, and filling with conductive material. The circuit interconnect 280 can be formed, for example, by depositing conductive material and patterning the conductive material.

[0134] The peripheral region insulating layer 290 can be formed as multiple insulating layers. In each of the processes used to form the circuit interconnect structure, a corresponding portion of the peripheral region insulating layer 290 can be formed. Therefore, a peripheral circuit region (PERI) can be formed.

[0135] On the peripheral circuit area PERI, a board layer 101, a horizontal insulating layer 110, a second horizontal conductive layer 104 and a substrate insulating layer 121 provided in the memory cell area CELL can be formed, and a module structure MSS and first to third vertical sacrificial layers 119a, 119b and 119c can be formed.

[0136] The plate layer 101 can be formed on the peripheral region insulating layer 290. The plate layer 101 can be formed of, for example, polysilicon, and can be formed by a CVD process. The polysilicon included in the plate layer 101 may include impurities.

[0137] When forming the plate 101, the landing pad 291 can be formed together on the uppermost circuit interconnect 280. The landing pad 291 can be formed in which a contact plug 170 is disposed (see...). Figure 1B In the lower region of the circuit interconnect 280. First, before forming the board 101, a portion of the peripheral region insulation layer 290 can be removed from the uppermost circuit interconnect 280 to form an opening. When forming the board 101, the opening can be filled with the material included in the board 101 to form a landing pad 291. The opening can be formed, for example, with a grounding path for connecting the board 101 to the circuit interconnect structure.

[0138] The first horizontal insulating layer 111 and the second horizontal insulating layer 112, included in the horizontal insulating layer 110, can be alternately stacked on the board layer 101. A portion of the horizontal insulating layer 110 may be replaced by a subsequent process. Figure 1B The first horizontal conductive layer 102 is a layer in the middle. The first horizontal insulating layer 111 may include a material different from that of the second horizontal insulating layer 112. For example, the first horizontal insulating layer 111 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 may be formed of the same material as the subsequent sacrificial insulating layer 118P. A portion of the horizontal insulating layer 110, for example, a portion of the second region R2, may be removed by a patterning process.

[0139] The second horizontal conductive layer 104 can be formed on the horizontal insulating layer 110 and can contact the plate layer 101 in the area where the horizontal insulating layer 110 has been removed.

[0140] A substrate insulating layer 121 can be formed to penetrate the board layer 101 in a portion of the region including the area where the contact plug 170 is disposed. The substrate insulating layer 121 can be formed by removing a portion of the board layer 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104, and filling with an insulating material. After filling with the insulating material, a planarization process can be further performed using a chemical mechanical polishing (CMP) process. Therefore, the upper surface of the substrate insulating layer 121 can be substantially coplanar with the upper surface of the second horizontal conductive layer 104.

[0141] Subsequently, the first stacking structure GS1 can be set up (see...) Figure 1B The first mode structure MSa is formed by alternately stacking sacrificial insulating layers 118P and interlayer insulating layers 120 on the second horizontal conductive layer 104 and the substrate insulating layer 121.

[0142] The sacrificial insulating layer 118P may be at least partially replaced by the gate electrode 130 through a subsequent process (see...). Figure 1B The interlayer insulating layer 118P can be formed of a material different from that of the interlayer insulating layer 120, and can be formed of a material that is selectively etched relative to the interlayer insulating layer 120 under specific etch conditions. For example, the interlayer insulating layer 120 can be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118P can be formed of a material different from that of the interlayer insulating layer 120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In the example implementation, the number and thickness of the interlayer insulating layer 120 and the sacrificial insulating layer 118P can differ from the example shown.

[0143] The gate pad region GP can be formed by repeating photolithography and etching processes on the sacrificial insulating layer 118P and the interlayer insulating layer 120. The gate pad region GP can be formed in the second region R2, and can be configured such that the upper sacrificial insulating layer 118P may include a region extending shorter than the lower sacrificial insulating layer 118P. An asymmetric stepped structure can be formed in the gate pad region GP, ​​allowing the upper surfaces and ends of the multiple sacrificial insulating layers 118P to be exposed upwards. The sacrificial insulating layers 118P can be further formed on the stepped structure of the gate pad region GP, ​​allowing the uppermost sacrificial insulating layer 118P in each region to have a relatively large thickness.

[0144] Subsequently, a first unit region insulating layer 192 can be formed covering the sacrificial insulating layer 118P and the interlayer insulating layer 120 in the first mode structure MSa. This can be achieved in conjunction with... Figure 1B The first channel structure CH and contact plug 170 in the middle and Figure 1C A first vertical sacrificial layer 119a is formed at the location corresponding to the dummy vertical structure 175. The first vertical sacrificial layer 119a can be formed by forming a hole to penetrate the first mold structure MSa, depositing sacrificial layer material in the hole, and performing a planarization process. The first vertical sacrificial layer 119a may include, for example, carbon or a carbon-based material, but its exemplary implementation is not limited to this.

[0145] The second mold structure MSb, the second vertical sacrificial layer 119b, the third mold structure MSc, and the third vertical sacrificial layer 119c can be formed on the first mold structure MSa in the same manner as the first mold structure MSa and the first vertical sacrificial layer 119a. The second vertical sacrificial layer 119b can be formed to connect to the first vertical sacrificial layer 119a, and the third vertical sacrificial layer 119c can be formed to connect to the second vertical sacrificial layer 119b. In this process, the first to third vertical sacrificial layers 119a, 119b, and 119c formed in the second region R2 can be formed to have a width similar to their width in the first region R1, and can be formed to have a width smaller than the width of the contact plug 170 and the width of the dummy vertical structure 175.

[0146] Reference Figure 9 It can form the channel structure CH of the through-mode structure MSS, and can form the first pore OH.

[0147] A mask layer can be formed that exposes only the first region R1. The channel structure CH can be formed by forming a lower channel via removing the first to third vertical sacrificial layers 119a, 119b and 119c from the first region R1, and sequentially depositing at least a portion of the gate dielectric layer 145, the channel layer 140, the channel filling insulating layer 147 and the channel pad 149 in the lower channel via.

[0148] The gate dielectric layer 145 can be formed to have a uniform thickness using an ALD or CVD process. In this process, the gate dielectric layer 145 can be formed wholly or partially, and a portion extending perpendicular to the plate layer 101 along the channel structure CH can be formed in this process. The channel layer 140 can be formed on the gate dielectric layer 145 in a lower channel via. The channel-filling insulating layer 147 can be formed to fill the lower channel via and can be an insulating material. The channel pad 149 can be formed of a conductive material (e.g., polysilicon).

[0149] The first pore OH can be formed by selectively removing the first to third vertical sacrificial layers 119a, 119b and 119c from the second region R2 and further removing the exposed landing pad 291.

[0150] First, a mask layer can be formed to expose the first to third vertical sacrificial layers 119a, 119b, and 119c in the second region R2, allowing selective removal of the first to third vertical sacrificial layers 119a, 119b, and 119c exposed through the mask layer. When the mask layer is formed with an opening larger than the upper surface of the third vertical sacrificial layer 119c, the first aperture OH can be... Figure 9The diagram shows an increased width at its upper end. The circuit interconnect 280 can be exposed through the bottom surface of the first hole OH. In some example implementations, the landing pad 291 may not be removed in this process and can be removed in a subsequent process.

[0151] Reference Figure 10 After the first hole OH expands in the horizontal direction, a first preliminary insulating pad 192P, a first preliminary insulating pattern 194P, and a vertical sacrificial layer 190P can be formed in the first hole OH.

[0152] The first hole OH can be enlarged in the horizontal direction by removing a portion of the sacrificial insulation layer 118P and the interlayer insulation layer 120 exposed via the first hole OH. During this process, the sacrificial insulation layer 118P can be removed relatively longer in the horizontal direction than the interlayer insulation layer 120. Subsequently, the sacrificial insulation layer 118P can be further removed around the first hole OH to form a tunnel portion.

[0153] A first preliminary insulating liner 192P can be formed by depositing insulating material in the first hole OH and the tunnel portion. The first preliminary insulating liner 192P can be conformally deposited on the inner sidewall of the tunnel portion. A first preliminary insulating pattern 194P can fill the tunnel portion on the first preliminary insulating liner 192P and can be formed on the sidewall of the first hole OH. A vertical sacrificial layer 190P can fill the first hole OH between the sidewalls of the first hole OH. The vertical sacrificial layer 190P can include a material different from the material of the first preliminary insulating pattern 194P and can include, for example, carbon (C).

[0154] Reference Figure 10 In region D, during the process of horizontally expanding the first hole OH by removing a portion of the sacrificial insulating layer 118P and interlayer insulating layer 120 exposed via the first hole OH, the first holes OH spaced apart in the horizontal direction can be connected to each other by tunnel portions. The distance between the central axes of the first holes OH connected by tunnel portions extending in the third direction (Z direction) can be less than the distance between the central axes of the first holes OH spaced apart in the horizontal direction extending in the third direction (Z direction).

[0155] The first hole OH connected through the tunnel section can share the first preliminary insulating pad 192P and the first preliminary insulating pattern 194P, and the vertical sacrificial layers 190P extending in the third direction (Z direction) can be spaced apart from each other in the horizontal direction.

[0156] Figures 11A to 18B This is a diagram illustrating a method for manufacturing a semiconductor device according to an example implementation.

[0157] Figure 11A, Figure 12A , Figure 13A , Figure 14 , Figure 15A , Figure 16A , Figure 17A and Figure 18A These are shown in the formation Figure 10 A plan view of the process following the process of the first hole of the common first preliminary insulating pad 192P and the first preliminary insulating pattern 194P, and the first holes spaced apart from each other in the horizontal direction, and is related to... Figure 5 The corresponding floor plan.

[0158] Figure 11B , Figure 12B , Figure 13B , Figure 15B , Figure 16B , Figure 17B and Figure 18B yes Figure 11A , Figure 12A , Figure 13A , Figure 15A , Figure 16A , Figure 17A and Figure 18A A cross-sectional view of the semiconductor device along line B-B', and is in line with... Figure 6A The corresponding cross-sectional view.

[0159] Reference Figure 11A and Figure 11B , Figure 10 The first hole OH of the shared first preliminary insulating pad 192P and first preliminary insulating pattern 194P can be referred to as the first contact hole CPH and the first dummy hole DH1. The first preliminary insulating pad 192P in the first contact hole CPH and the first dummy hole DH1 can be referred to as the second preliminary contact insulating pad 162P, and the first preliminary insulating pattern 194P can be referred to as the second preliminary contact insulating pattern 164P. The vertical sacrificial layer 190P in the first contact hole CPH can be referred to as the first contact vertical sacrificial layer 195P. The vertical sacrificial layer 190P in the first dummy hole DH1 can be referred to as the first dummy sacrificial layer 190a. Figure 10The first dummy holes OH, spaced apart from each other, can be referred to as the second dummy hole DH2, the third dummy hole DH3, and the fourth dummy hole DH4. The first preliminary insulating pad 192P and the first preliminary insulating pattern 194P formed in the first dummy holes OH, spaced apart from each other, can be referred to as the preliminary dummy insulating pad 152P and the first preliminary dummy insulating pattern 154P in the second dummy hole DH2, the third dummy hole DH3, and the fourth dummy hole DH4, respectively. The second dummy sacrificial layer 190b in the second dummy hole DH2, the third dummy sacrificial layer 190c in the third dummy hole DH3, and the fourth dummy sacrificial layer 190d in the fourth dummy hole DH4 can correspond to the vertical sacrificial layer 190P in the first dummy holes OH1, spaced apart from each other.

[0160] The first contact hole CPH can correspond to Figure 5 The second contact plug 170b in the first dummy hole DH1 can correspond to Figure 5 The second dummy vertical structure 175b, the second dummy hole DH2, the third dummy hole DH3, and the fourth dummy hole DH4 can correspond to Figure 5 The virtual vertical structures 1-2 (1752a), 1-3 (1753a), and 1-4 (1754a) are listed.

[0161] Because the first contact hole CPH is set such that the distance between it and the first dummy hole DH1 is less than the distance between it and the second dummy holes DH2, the third dummy hole DH3, and the fourth dummy hole DH4, therefore Figure 10 The first contact hole OH can be connected in a process that expands horizontally, and can share the second initial contact insulating pad 162P and the second initial contact insulating pattern 164P. Therefore, the first contact hole CPH and the first dummy hole DH1 can be physically connected to each other.

[0162] The second dummy hole DH2, the third dummy hole DH3, and the fourth dummy hole DH4 can be spaced apart from each other in the horizontal direction. The preliminary dummy insulating pad 152P and the first preliminary dummy insulating pattern 154P, respectively disposed in the tunnel portions of the second dummy hole DH2, the third dummy hole DH3, and the fourth dummy hole DH4, can also be spaced apart from each other in the horizontal direction. The second preliminary contact insulating pad 162P and the preliminary dummy insulating pad 152P can be spaced apart from each other in the horizontal direction. The sacrificial insulating layer 118P can be formed between the preliminary dummy insulating pad 152P and the second preliminary contact insulating pad 162P.

[0163] Reference Figure 12A and Figure 12BThe first opening OPN1 can be formed by removing the first dummy sacrificial layer 190a in the first dummy via DH1, the second dummy sacrificial layer 190b in the second dummy via DH2, the third dummy sacrificial layer 190c in the third dummy via DH3, and the fourth dummy sacrificial layer 190d in the fourth dummy via DH4. The first dummy sacrificial layer 190a to the fourth dummy sacrificial layer 190d can be removed by a wet etching process.

[0164] Reference Figure 13A and Figure 13B The preliminary dummy vertical structures 175a_P and 175b_P can be formed by filling the first opening OPN1 with insulating material. The first preliminary dummy vertical structure 175a_P can be formed into a dummy vertical structure surrounded by the preliminary dummy insulating pad 152P and the first preliminary dummy insulating pattern 154P by filling the second dummy hole DH2, the third dummy hole DH3 and the fourth dummy hole DH4 with insulating material. The first preliminary dummy vertical structure 175a_P may include 1-2 preliminary dummy vertical structures 1752a_P formed in the second dummy hole DH2, 1-3 preliminary dummy vertical structures 1753a_P formed in the third dummy hole DH3, and 1-4 preliminary dummy vertical structures 1754a_P formed in the fourth dummy hole DH4.

[0165] The second preliminary dummy vertical structure 175b_P can be formed as a dummy vertical structure surrounded by the second preliminary contact insulating pad 162P and the second preliminary contact insulating pattern 164P by filling the first dummy hole DH1 with insulating material.

[0166] Reference Figure 13A and Figure 14 By removing portions that extend in the first direction (X direction) and overlap with a portion of the sacrificial insulation layer 118P, a portion of the 1-2 preliminary dummy vertical structures 1752a_P, a portion of the first preliminary dummy insulation pattern 154P surrounding the 1-2 preliminary dummy vertical structures 1752a_P, a portion of the preliminary dummy insulation pad 152P surrounding the first preliminary dummy insulation pattern 154P, a portion of the second preliminary dummy vertical structure 175b_P, a portion of the second preliminary contact insulation pattern 164P surrounding the second preliminary dummy vertical structure 175b_P, and a portion of the second preliminary contact insulation pad 162P surrounding the second preliminary contact insulation pattern 164P, an isolation region MS (e.g., a first isolation region) can be formed on the upper side of the first contact vertical sacrificial layer 195P when viewed in a plane.

[0167] By removing portions that extend in the first direction (X direction) and overlap with a portion of the sacrificial insulation layer 118P, portions of the 1-3 preliminary dummy vertical structures 1753a_P and 1-4 preliminary dummy vertical structures 1754a_P, a portion of the first preliminary dummy insulation pattern 154P surrounding the 1-3 preliminary dummy vertical structures 1753a_P and 1-4 preliminary dummy vertical structures 1754a_P, and a portion of the preliminary dummy insulation pad 152P surrounding the first preliminary dummy insulation pattern 154P, an isolation region MS (e.g., a second isolation region) can be formed on the underside of the first contact vertical sacrificial layer 195P when viewed in a plane.

[0168] As the isolation region MS is formed, a portion of the first preliminary dummy vertical structure 175a_P can be removed to form the first dummy vertical structure 175a, and a portion of the second preliminary dummy vertical structure 175b_P can be removed to form the second dummy vertical structure 175b.

[0169] As the isolation zone MS is formed, the second preliminary virtual vertical structure 175b_P can be formed into the second virtual vertical structure 175b, the 1-2 preliminary virtual vertical structure 1752a_P can be formed into the 1-2 virtual vertical structure 1752a, the 1-3 preliminary virtual vertical structure 1753a_P can be formed into the 1-3 virtual vertical structure 1753a, and the 1-4 preliminary virtual vertical structure 1754a_P can be formed into the 1-4 virtual vertical structure 1754a.

[0170] Reference Figure 13A and Figure 14 When viewed on a plane, the maximum width of each of the first preliminary dummy vertical structure 175a_P and the second preliminary dummy vertical structure 175b_P can have a first dimension Ra.

[0171] When viewed in a plane, the maximum width of each of the first dummy vertical structure 175a and the second dummy vertical structure 175b can have a second dimension Rb that is smaller than the first dimension Ra. The second dimension Rb can be greater than half of the first dimension Ra.

[0172] The first preliminary dummy insulation pattern 154P and the preliminary dummy insulation pad 152P can be partially cut off and can be formed as the first dummy insulation pattern 154a'' and the dummy insulation pad 152 surrounding the first dummy vertical structure 175a, respectively.

[0173] The second initial contact insulation pattern 164P and the second initial contact insulation pad 162P can be partially cut off and can be formed as the second contact insulation pattern 164b'' and the second contact insulation pad 162b surrounding the second dummy vertical structure 175b, respectively.

[0174] Reference Figure 15A and Figure 15B The first dummy insulating pattern 154a'', located between the first dummy vertical structure 175a and the dummy insulating pad 152, can have its first width W1 removed. Similarly, the second contact insulating pattern 164b'', formed between the second dummy vertical structure 175b and the second contact insulating pad 162b, can have its first width W1 removed, thereby forming a second opening OPN2. The first dummy insulating pattern 154a'' and the second contact insulating pattern 164b can be exposed through the second opening OPN2.

[0175] The sacrificial insulation layer 118'' between the dummy insulating pad 152 and the second contact insulating pad 162b can be removed by removing the first width W1, thereby forming a third opening OPN3 through which the sacrificial insulation layer 118 can be exposed.

[0176] Through the Figure 14 The pull-back or etching process, which involves etching a first width W1 in the horizontal direction onto the side surfaces of the first dummy insulating pattern 154a'', the second contact insulating pattern 164b'', and the sacrificial insulating layer 118P exposed through the isolation region MS, can form a second opening OPN2 and a third opening OPN3. The etching degree of the side surfaces of the first dummy insulating pattern 154a'', the second contact insulating pattern 164b'', and the sacrificial insulating layer 118P can be controlled by controlling the pull-back process time. The first width W1 can be less than... Figure 13A Half of the first dimension Ra in the middle.

[0177] By pulling back the side surfaces of the first dummy insulation pattern 154a'' and the side surfaces of the sacrificial insulation layer 118P exposed via the isolation zone MS, a portion of the first dummy vertical structure 175a and a portion of the dummy insulation pad 152 can be exposed through the second opening OPN2 and the third opening OPN3.

[0178] By pulling back the side surfaces of the second contact insulation pattern 164b'' exposed via the isolation zone MS and the side surfaces of the sacrificial insulation layer 118P, a portion of the second dummy vertical structure 175b and a portion of the second contact insulation pad 162b can be exposed via the second opening OPN2 and the third opening OPN3.

[0179] Reference Figure 16A and Figure 16B An insulating pattern 166P can be formed in the second opening OPN2 and the third opening OPN3.

[0180] Because the width of each second opening OPN2 is relatively smaller than the width of each third opening OPN3, the insulating pattern 166P can fill the second openings OPN2 and can be conformally formed along the inner sidewall of the third openings OPN3. The insulating pattern 166P can be silicon oxide.

[0181] Reference Figure 17A and Figure 17B A planarization process can be performed to expose the side surfaces of the first dummy vertical structure 175a and the second dummy vertical structure 175b. The fourth opening OPN4 can be formed by removing the insulating pattern 166P formed between the dummy insulating pad 152 and the second contact insulating pad 162b. The insulating pattern 166P can be disposed on the side surface of the 2-1 contact insulating pattern 164b and can be formed as a 2-2 contact insulating pattern 166b, thereby preventing the 2-1 contact insulating pattern 164b from being exposed. Therefore, a second contact insulating structure 160b including the 2-1 contact insulating pattern 164b, the 2-2 contact insulating pattern 166b, and the second contact insulating pad 162b can be formed.

[0182] The insulating pattern 166P can be disposed on the side surface of the first dummy insulating pattern 154 and can be formed as the second dummy insulating pattern 156, thereby preventing the side surface of the first dummy insulating pattern 154 from being exposed. Therefore, a dummy insulating structure 150 including the first dummy insulating pattern 154, the second dummy insulating pattern 156, and the dummy insulating pad 152 can be formed.

[0183] Reference Figure 18A and Figure 18B The fifth opening OPN5 can be formed by removing the sacrificial insulating layer 118, and the sixth opening OPN6 can be formed by removing the first contact vertical sacrificial layer 195P. In the process of removing the sacrificial insulating layer 118, the 2-1 contact insulating pattern 164b can be bypassed by the 2-2 contact insulating pattern 166b without being removed, and the first dummy insulating pattern 154 can be bypassed by the second dummy insulating pattern 156 without being removed. Therefore, in the process of removing the sacrificial insulating layer 118 and replacing these layers with conductive material, the 2-1 contact insulating pattern 164b can surround the side surface of the second contact plug 170b and the side surface of the second dummy vertical structure 175b, thereby preventing the second contact plug 170b and the second dummy vertical structure 175b from conducting electricity through the conductive material.

[0184] Subsequently, refer to Figure 1B and Figure 5Conductive material can be formed in the fifth opening OPN5 to form the gate electrode 130, and conductive material can be formed in the sixth opening OPN6 to form the second contact plug 170b. By forming a pillar 180 connected to the upper end of the contact plug 170 and the channel structure CH, the semiconductor device 100 can be manufactured.

[0185] Figure 19 This illustrates the semiconductor device along the example implementation. Figure 1A The cross-sectional view taken from line I-I' in the diagram.

[0186] Reference Figure 19 The semiconductor device 100' may include a memory cell structure S1 and a peripheral circuit structure S2 that are bonded to each other by a wafer bonding method.

[0187] The above reference Figure 1B The description of the peripheral circuit region PERI can be applied to the peripheral circuit structure S2. The peripheral circuit structure S2 may further include a second bonding path 295 and a second bonding metal layer 298 as bonding structures, as well as a second bonding insulating layer 299. The second bonding path 295 can be connected to the uppermost circuit interconnect 280. At least a portion of the second bonding metal layer 298 can be connected to the second bonding path 295. The second bonding metal layer 298 can be connected to the first bonding metal layer 198 of the memory cell structure S1. The second bonding metal layer 298, together with the first bonding metal layer 198, can provide an electrical connection path for bonding the memory cell structure S1 and the peripheral circuit structure S2. In another example, a portion of the second bonding metal layer 298 may not be connected to the lower circuit interconnect 280 and may be configured solely for bonding.

[0188] The second bonding path 295 and the second bonding metal layer 298 may include a conductive material, such as copper (Cu). A second bonding insulating layer 299 may be disposed around the second bonding metal layer 298. The second bonding insulating layer 299 may also serve as a diffusion barrier for the second bonding metal layer 298 and may include at least one of, for example, SiN, SiON, SiCN, SiOC, SiOCN, and SiO.

[0189] In the absence of further description of the memory cell structure S1, the above reference can be applied. Figure 1B The memory cell structure S1 may further include a substrate insulating layer 122, cell interconnects 185, and a first bonding path 195, a first bonding metal layer 198, and a first bonding insulating layer 199 as bonding structures. In the example, the memory cell structure S1 may further include a passivation layer 106 on the upper surface of the cover plate layer 101 and the upper surface of the substrate insulating layer 122.

[0190] The substrate insulating layer 122 can be disposed above the gate structure GS, between the plate layer 101 and the gate structure GS on the first region R1, and at the same level as the plate layer 101 on the second region R2. The channel structure CH can penetrate the gate structure GS and the substrate insulating layer 122 in the first region R1, and can extend into the plate layer 101.

[0191] The substrate insulating layer 122 can be disposed on the first region R1 below the board layer 101, extending from the first region R1 to the second region R2, and can be disposed on the second region R2 at the same level as the board layer 101.

[0192] The cell interconnect 185 can be connected to the post 180. However, in the example implementation, the number and arrangement of the plugs and interconnects included in the cell interconnect structure can vary. The cell interconnect 185 can be formed of a conductive material and can include at least one of, for example, tungsten (W), aluminum (Al), and copper (Cu).

[0193] The first bonding path 195 and the first bonding metal layer 198 can be disposed below the bottommost cell interconnect 185. The first bonding path 195 can connect the cell interconnect 185 to the first bonding metal layer 198, and the first bonding metal layer 198 can be bonded to the second bonding metal layer 298 of the peripheral circuit structure S2. The first bonding insulating layer 199 can be bonded to the second bonding insulating layer 299 of the peripheral circuit structure S2. The first bonding path 195 and the first bonding metal layer 198 can include a conductive material, such as copper (Cu). The first bonding insulating layer 199 can include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0194] The memory cell structure S1 and the peripheral circuit structure S2 can be joined together by a bonding between the first bonding metal layer 198 and the second bonding metal layer 298, and by a bonding between the first bonding insulating layer 199 and the second bonding insulating layer 299. The bonding between the first bonding metal layer 198 and the second bonding metal layer 298 can be, for example, a copper (Cu)-copper (Cu) bonding, and the bonding between the first bonding insulating layer 199 and the second bonding insulating layer 299 can be, for example, a dielectric-dielectric bonding, such as a SiCN-SiCN bonding. The memory cell structure S1 and the peripheral circuit structure S2 can also be joined together by a hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

[0195] Passivation layer 106 may be disposed on the upper surface of plate layer 101 and may protect semiconductor device 100'. Passivation layer 106 may include at least one insulating material selected from silicon oxide, silicon nitride, and silicon carbide. Substrate insulating layer 122 may be broadly disposed in the first region R1 and the second region R2 to cover the upper end of contact plug 170. However, in the example implementation, the arrangement of substrate insulating layer 122 may vary within the range of electrical isolation between contact plug 170 and plate layer 101.

[0196] Figure 20 This is a diagram illustrating a data storage system including semiconductor devices according to an example implementation.

[0197] Reference Figure 20 The data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be implemented as a solid-state drive (SSD) device including one or more semiconductor devices 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0198] Semiconductor device 1100 can be implemented as a non-volatile memory device, such as, for example, reference to Figures 1A to 1D The NAND flash memory device described in the foregoing example implementation. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In the example implementation, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F may be implemented as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuit 1130. The second structure 1100S may be implemented as a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR disposed between the bit line BL and the common source line CSL.

[0199] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and multiple memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In the example implementation, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 can vary.

[0200] In the example implementation, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Lower gate lines LL1 and LL2 may be configured as gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be configured as the gate electrode of memory cell transistor MCT, and upper gate lines UL1 and UL2 may be configured as gate electrodes of upper transistors UT1 and UT2, respectively.

[0201] In the example implementation, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series with each other. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series with each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation that utilizes the GIDL phenomenon to erase data stored in the memory cell transistor MCT.

[0202] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second interconnect 1125 extending from the first structure 1100F to the second structure 1100S.

[0203] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 via an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0204] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In an example implementation, the data storage system 1000 may include multiple semiconductor devices 1100, in which case the controller 1200 can control the multiple semiconductor devices 1100.

[0205] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include controller interface 1221 for handling communication with semiconductor device 1100. Through controller interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be sent. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0206] According to the aforementioned example implementation, the semiconductor device and the data storage system including the semiconductor device may include a contact plug, a dummy vertical structure adjacent to the contact plug, and a contact insulation structure shared by the contact plug and the dummy vertical structure. The contact insulation structure may include a first contact insulation pattern that contacts a portion of the contact plug and the dummy vertical structure, and a second contact insulation pattern that contacts another portion of the dummy vertical structure. Therefore, by preventing the first contact insulation pattern from being removed during the manufacturing process through the second contact insulation pattern of the contact insulation structure shared by the contact plug and the dummy vertical structure, a semiconductor device and a data storage system including the semiconductor device with improved reliability can be provided.

[0207] While this disclosure contains numerous specific implementation details, these details should not be construed as limiting the scope of any claims that may be made. Certain features described in this disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from a combination may be removed from that combination, and the combination may be for sub-combinations or variations thereof.

[0208] This application claims priority to Korean Patent Application No. 10-2024-0176364, filed on December 2, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A first semiconductor structure includes a substrate, circuit devices on the substrate, and circuit interconnects on the circuit devices; as well as A second semiconductor structure, on top of the first semiconductor structure, has a first region and a second region. The second semiconductor structure includes: Plate layer; Gate electrodes are stacked and spaced apart from each other on the plate in a direction perpendicular to the upper surface of the plate, the gate electrodes extending to different lengths in the second region in a first direction intersecting the vertical direction, each gate electrode including a pad region, the upper surface of the pad region being exposed; An interlayer insulating layer is alternately disposed with the gate electrode; A channel structure extends through the gate electrode and the interlayer insulating layer in the first region, the channel structure extending in the vertical direction; A contact plug extends through the pad region of each of the gate electrodes in the second region, the contact plug extending in the vertical direction, the contact plug electrically connecting the gate electrode to at least one corresponding circuit interconnect in the circuit interconnect; A dummy vertical structure extends through the gate electrode and the interlayer insulating layer in the second region, the dummy vertical structure extending in the vertical direction and spaced apart from the contact plug in the horizontal direction; and A contact insulating structure, alternately disposed with the interlayer insulating layer, is provided in the corresponding pad region of the gate electrode, and the contact insulating structure surrounds the contact plug. Wherein, each of the gate electrodes includes a first pad region, and a first contact plug of the contact plug extends through the first pad region. The dummy vertical structure includes a first dummy vertical structure adjacent to the first contact plug, and The contact insulation structure includes a first contact insulation structure that contacts the first contact plug and the first dummy vertical structure, and the first contact insulation structure is located in the first pad area.

2. The semiconductor device according to claim 1, in, Each of the first contact insulation structures includes: The first contact insulation pattern contacts the first contact plug and the first portion of the first dummy vertical structure; A second contact insulating pattern surrounds a second portion of the first dummy vertical structure, the second portion of the first dummy vertical structure being connected to the first portion of the first dummy vertical structure; and A contact insulating pad covers the outer surface of both the first and second contact insulating patterns. Wherein, the first contact insulation pattern includes a first insulating material, and The second contact insulation pattern includes a second insulation material that is different from the first insulation material.

3. The semiconductor device according to claim 2, in, The first contact insulation pattern has a first area that contacts the first portion of the first dummy vertical structure. Each of the second contact insulation patterns has a second region that contacts a corresponding second portion in the second portion of the first dummy vertical structure, and The second region is smaller than the first region.

4. The semiconductor device according to claim 1, in, The dummy vertical structure includes a second dummy vertical structure adjacent to the first contact plug, the second dummy vertical structure being spaced apart from the first dummy vertical structure in the horizontal direction. The second semiconductor structure includes dummy insulating structures alternately disposed with the interlayer insulating layer, the dummy insulating structures surrounding the second dummy vertical structure, and... The dummy insulation structure is spaced apart from the first contact insulation structure in the horizontal direction.

5. The semiconductor device according to claim 4, in, The first contact plug and the first dummy vertical structure are spaced apart from each other by a first distance along the horizontal direction, and The first contact plug and the second dummy vertical structure are spaced apart from each other by a second distance along the horizontal direction, and the second distance is greater than the first distance.

6. The semiconductor device according to claim 4, wherein, The gate electrode is located between the first contact insulation structure and the dummy insulation structure.

7. The semiconductor device according to claim 4, wherein, Each of the aforementioned dummy insulation structures includes: The first dummy insulating pattern surrounds the third part of the second dummy vertical structure; A second dummy insulating pattern surrounds a fourth portion of the second dummy vertical structure, the fourth portion of the second dummy vertical structure being connected to the third portion of the second dummy vertical structure; and A dummy insulating pad is provided around the first dummy insulating pattern and the second dummy insulating pattern.

8. The semiconductor device according to claim 1, comprising: A first isolation structure extends through the gate electrode and extends in the first direction; as well as A second isolation structure extends through the gate electrode, and the second isolation structure is spaced apart from the first isolation structure in a second direction intersecting the vertical direction and the first direction. Wherein, the first contact plug is located between the first isolation structure and the second isolation structure, and The first dummy vertical structure is in contact with the first isolation structure.

9. The semiconductor device according to claim 1, in, The dummy vertical structure includes a second dummy vertical structure adjacent to the first contact plug, the second dummy vertical structure being spaced apart from the first dummy vertical structure in the first direction, and The first contact insulation structure is in contact with the second dummy vertical structure.

10. The semiconductor device according to claim 9, in, Each of the first contact insulation structures includes: The first contact insulation pattern contacts the first contact plug, the first part of the first dummy vertical structure, and the third part of the second dummy vertical structure. A second contact insulating pattern surrounds a second portion of the first dummy vertical structure, the second portion of the first dummy vertical structure being connected to the first portion of the first dummy vertical structure; A third contact insulating pattern surrounds a fourth portion of the second dummy vertical structure, the fourth portion of the second dummy vertical structure being connected to the third portion of the second dummy vertical structure; and A contact insulating pad covers the outer surfaces of the first contact insulating pattern, the second contact insulating pattern, and the third contact insulating pattern. Wherein, the first contact insulation pattern includes a first insulating material, and The second contact insulation pattern and the third contact insulation pattern include a second insulation material that is different from the first insulation material.

11. The semiconductor device according to claim 1, in, The illusory vertical structure includes insulating material, and The contact plug comprises a conductive material.

12. A semiconductor device, comprising: A stacked pattern, featuring a memory cell array area and a stepped area; A stacked structure extending from the memory cell array region to the stepped region, the stacked structure being on the stacked pattern, wherein the stacked structure includes interlayer insulating layers and gate electrodes alternately disposed in a vertical direction, the gate electrodes including gate contact pads defining steps in the stepped region; A channel structure that extends through the stacked structure in the vertical direction within the memory cell array region; A first contact plug extends through the gate electrode and the interlayer insulating layer in the stepped region; A first dummy vertical structure extends through the gate electrode and the interlayer insulating layer in the stepped region, and the first dummy vertical structure is adjacent to the first contact plug; A first contact insulation structure, alternately disposed with the interlayer insulation layer, surrounds the first contact plug; and A first dummy insulation structure is alternately arranged with the interlayer insulation layer, and the first dummy insulation structure surrounds the first dummy vertical structure. The first contact insulation structure is spaced apart from the first dummy insulation structure. Each of the first dummy insulation structures includes The first dummy insulating pattern surrounds the first portion of the first dummy vertical structure. A second dummy insulating pattern surrounds a second portion of the first dummy vertical structure, the second portion of the first dummy vertical structure extending from the first portion, and A dummy insulating pad is created around the first dummy insulating pattern and the second dummy insulating pattern. Wherein, the first dummy insulation pattern includes a first insulating material, and The second dummy insulation pattern includes a second insulation material that is different from the first insulation material.

13. The semiconductor device according to claim 12, in, Each of the first contact insulation structures includes a first contact insulation pattern surrounding the first contact plug and a first contact insulation pad surrounding the first contact insulation pattern, and The first contact insulation pattern includes the first insulation material.

14. The semiconductor device according to claim 13, wherein, The first dummy insulation pattern is closer to the first contact insulation pattern than the second dummy insulation pattern.

15. The semiconductor device of claim 14, comprising: The second contact plug extends through the gate electrode and the interlayer insulating layer in the stepped region; A second dummy vertical structure extends through the gate electrode and the interlayer insulating layer in the stepped region, and the second dummy vertical structure is adjacent to the second contact plug; as well as A second contact insulation structure is alternately disposed with the interlayer insulation layer, the second contact insulation structure surrounding the second contact plug and the second dummy vertical structure.

16. The semiconductor device according to claim 15, in, Each of the second contact insulation structures includes: The third contact insulation pattern contacts the second contact plug and the third part of the second dummy vertical structure; A fourth contact insulating pattern contacts a fourth portion of the second dummy vertical structure, the fourth portion of the second dummy vertical structure extending from the third portion; and The second contact insulating pad surrounds the third and fourth contact insulating patterns. The third contact insulation pattern includes the first insulation material, and The fourth contact insulation pattern includes the second insulation material.

17. The semiconductor device according to claim 15, in, The first contact plug and the first dummy vertical structure are spaced apart from each other by a first distance in the horizontal direction, and The second contact plug and the second dummy vertical structure are spaced apart from each other by a second distance along the horizontal direction, and the second distance is less than the first distance.

18. The semiconductor device of claim 12, comprising: The second dummy vertical structure extends through the gate electrode and the interlayer insulating layer in the stepped region. The second dummy vertical structure is adjacent to the first contact plug. The second dummy vertical structure is spaced apart from the first dummy vertical structure in a first direction that intersects the vertical direction. The third dummy vertical structure is spaced apart from the first dummy vertical structure in a second direction that intersects the vertical direction and the first direction; A second dummy insulation structure is alternately provided with the interlayer insulation layer, and the second dummy insulation structure surrounds the second dummy vertical structure; as well as A third dummy insulation structure is alternately arranged with the interlayer insulation layer, and the third dummy insulation structure surrounds the third dummy vertical structure. The second dummy insulation structure and the third dummy insulation structure are spaced apart from the first contact insulation structure.

19. The semiconductor device of claim 18, comprising: An isolation structure extends through the gate electrode, extends in the first direction, and is spaced apart from each other in the second direction; The isolation structure includes a first isolation structure and a second isolation structure spaced apart from the first isolation structure in the second direction; The first contact plug is located between the first isolation structure and the second isolation structure; Wherein, the first dummy vertical structure and the second dummy vertical structure are in contact with the first isolation structure, and The third dummy vertical structure is in contact with the second isolation structure.

20. A data storage system, comprising: Semiconductor memory devices, including: A first semiconductor structure includes circuit devices and circuit interconnects electrically connected to the circuit devices; A second semiconductor structure, on the first semiconductor structure, the second semiconductor structure including a first region and a second region; and Input / output pads, electrically connected to the circuit devices; and A controller, electrically connected to the semiconductor memory device via the input / output pad, is electrically configured to control the semiconductor memory device; The second semiconductor structure includes: Plate layer; Gate electrodes are stacked vertically and spaced apart from each other on the upper surface of the plate layer. The gate electrodes extend to different lengths in the second region in a first direction intersecting the vertical direction. Each gate electrode includes a pad region, the upper surface of which is exposed. An interlayer insulating layer is alternately disposed with the gate electrode; A channel structure extends through the gate electrode and the interlayer insulating layer in the first region, the channel structure extending in the vertical direction; A contact plug extends through the pad region of each of the gate electrodes in the second region, the contact plug extending in the vertical direction, the contact plug electrically connecting the gate electrode to at least one corresponding circuit interconnect in the circuit interconnect; A dummy vertical structure extends through the gate electrode and the interlayer insulating layer in the second region, the dummy vertical structure extending in the vertical direction and spaced apart from the contact plug in a horizontal direction intersecting the vertical direction; and A contact insulating structure, alternately disposed with the interlayer insulating layer, is provided in the corresponding pad region of the gate electrode, and the contact insulating structure surrounds the contact plug. Wherein, the pad region of each of the gate electrodes includes a first pad region, and the first contact plug of the contact plug extends through the first pad region; The dummy vertical structure includes a first dummy vertical structure adjacent to the first contact plug, and Each of the contact insulation structures includes The first contact insulation pattern contacts the first contact plug and the first portion of the first dummy vertical structure in the first pad area, and The second contact insulating pattern contacts the second portion of the first dummy vertical structure, and the second portion of the first dummy vertical structure is connected to the first portion of the first dummy vertical structure.

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