Semiconductor device and method of manufacture, power module, power conversion circuit and vehicle

Abstract

This invention discloses a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle. The fabrication method includes: providing a semiconductor body, including a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region, the first region being located on the first surface, and the well region being located on the side of the first region away from the first surface; forming a gate structure on the first surface, or forming a gate structure extending from the first surface into the semiconductor body; forming an isolation protective layer on the side of the gate structure away from the semiconductor body and on both sides of the gate structure; forming an ohmic contact layer on both sides of the isolation protective layer and the gate structure, and on the first surface, using a thermal annealing process; the ohmic contact layer contacting the first region; and removing carbon residue precipitated on the side of the isolation protective layer away from the semiconductor body due to thermal annealing using a resist removal process. This invention enables interference-free defect scanning and detection.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] Currently, to form an ohmic contact layer between the source and the semiconductor body, metallic nickel is first deposited on the surface of a silicon carbide metal-oxide-semiconductor field-effect transistor (MOSFET) semiconductor device. Then, a low-resistivity nickel-silicon compound is formed through two high-temperature thermal annealing processes, thus creating the ohmic contact. However, during the high-temperature thermal annealing process, some carbon atoms from the semiconductor body migrate to the device surface, forming carbon residues. This causes significant interference in quality control during wafer fabrication and affects the identification of device defects. Summary of the Invention

[0003] This invention provides a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, to solve the problem of carbon residue on the surface of devices caused by high-temperature thermal annealing.

[0004] In a first aspect, the present invention provides a method for fabricating a semiconductor device, the method comprising: A semiconductor body is provided, the semiconductor body is configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other, the semiconductor body also includes a well region and a first region, the first region is configured with the first conductivity type and is located on the first surface, the well region is configured with the second conductivity type and is located on the side of the first region away from the first surface; the first conductivity type and the second conductivity type are different; the semiconductor body includes a silicon carbide semiconductor body; A gate structure is formed on the first surface, or a gate structure is formed extending from the first surface into the semiconductor body; An isolation protective layer is formed on the side of the gate structure away from the semiconductor body and on both sides of the gate structure; Using a thermal annealing process, an ohmic contact layer is formed on both sides of the isolation protective layer and the gate structure, and on the first surface; the ohmic contact layer is in contact with the first region; The carbon residue precipitated during thermal annealing on the side of the isolation protective layer away from the semiconductor body is removed using a resist removal process.

[0005] Optionally, a resist-removal process is used to remove carbon residue precipitated during thermal annealing on the side of the insulating protective layer furthest from the semiconductor body, including: The adhesive stripping process is used to remove free carbon and / or graphene residues precipitated during thermal annealing on the side of the isolation protective layer away from the semiconductor body.

[0006] Optionally, a resist-removal process is used to remove carbon residue precipitated during thermal annealing on the side of the insulating protective layer furthest from the semiconductor body, including: Oxygen plasma is used to ashing carbon residues, causing the carbon residues to react with oxygen to generate volatile oxidation products. Discharge volatile oxidation products.

[0007] Optionally, before ashing the carbon residue using oxygen plasma, the process further includes: The semiconductor device, after the formation of the ohmic contact layer, is placed in the plasma reaction chamber; An oxygen-containing process gas is introduced into the plasma reaction chamber, and the oxygen-containing process gas is excited to generate oxygen plasma.

[0008] Optionally, using a thermal annealing process, an ohmic contact layer is formed on both sides of the isolation protective layer and the gate structure, and on the first surface, including: A nickel metal layer is deposited on both sides of the isolation protection layer and the gate structure, and on the first surface; A first thermal annealing process is performed to allow the nickel metal layer to react with the semiconductor body to generate an intermediate state first nickel silicide layer. The unreacted portion of the nickel metal layer on the side furthest from the semiconductor body is removed using a wet etching process; A second thermal annealing process is performed to transform the intermediate first nickel silicide layer into a second nickel silicide layer; the resistivity of the second nickel silicide layer is less than that of the first nickel silicide layer; thereby forming an ohmic contact layer.

[0009] Optionally, after removing the carbon residue precipitated during thermal annealing on the side of the insulating protective layer away from the semiconductor body using a resist-removal process, the process further includes: Remove the protective layer.

[0010] Optionally, the isolation protective layer is removed, including: A photoresist layer is formed on the side of the ohmic contact layer and the isolation protective layer away from the semiconductor body; Expose the photoresist layer; The photoresist layer is developed by repeatedly coating the developing solution and immersing it in a static solution to remove the photoresist layer on the side of the isolation protective layer away from the semiconductor body. The isolation protective layer is etched to remove it, and the remaining photoresist layer is also removed.

[0011] Optionally, the photoresist layer is developed, including: The photoresist layer is developed, and the development process includes at least eight cycles of coating with developer and static immersion.

[0012] Optionally, the photoresist layer is developed, including: The photoresist layer is developed by repeatedly coating it with developer and then immersing it in the solution for 15-60 seconds.

[0013] Optionally, after removing the isolation protective layer, it also includes: A first insulating layer is formed on the side of the gate structure away from the semiconductor body and on both sides of the gate structure; the vertical projection of the first insulating layer on the semiconductor body covers the vertical projection of the gate structure on the semiconductor body. A source electrode is formed on the side of the first insulating layer and the ohmic contact layer away from the semiconductor body; A drain electrode is formed on the second surface.

[0014] Optionally, a gate structure is formed on the first surface, including: A second insulating layer is formed on the first surface; A gate is formed on the side of the second insulating layer away from the semiconductor body; A gate trench is formed on a first surface of the semiconductor body; a gate structure extending from the first surface into the semiconductor body is formed, including: A second insulating layer is formed at the bottom and sidewalls of the gate trench; A gate is formed in the gate trench on the side of the second insulating layer away from the semiconductor body.

[0015] Secondly, the present invention provides a semiconductor device, wherein the semiconductor device is manufactured using the semiconductor device fabrication method provided in any embodiment of the present invention; the semiconductor device includes: The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region and a first region. The first region is configured with the first conductivity type and is located on the first surface. The well region is configured with the second conductivity type and is located on the side of the first region away from the first surface. The first conductivity type and the second conductivity type are different. The semiconductor body includes a silicon carbide semiconductor body. A gate structure is located on the first surface or extends from the first surface into the semiconductor body; The first insulating layer is located on the side of the gate structure away from the semiconductor body and on both sides of the gate structure; the vertical projection of the first insulating layer on the semiconductor body covers the vertical projection of the gate structure on the semiconductor body. An ohmic contact layer is located on both sides of the gate structure and the first insulating layer; the ohmic contact layer is in contact with the first region; The source is located on the side of the first insulating layer and the ohmic contact layer away from the semiconductor body; The drain electrode is located on the second surface.

[0016] Thirdly, the present invention provides a power module comprising a substrate and at least one semiconductor device as provided in any embodiment of the present invention, wherein the substrate is used to support the semiconductor device.

[0017] Fourthly, the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as provided in any embodiment of the present invention, the semiconductor device being electrically connected to the circuit board.

[0018] Fifthly, the present invention provides a vehicle including a load and a power conversion circuit as provided in the fourth aspect above, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0019] The technical solution of this invention addresses the problem of significant interference in defect scanning detection of silicon carbide MOSFET devices after the high-temperature thermal annealing process of the ohmic contact layer 4. Through analysis of the reaction mechanism, a creative adhesive removal process is added after high-temperature thermal annealing and before defect scanning detection. This effectively removes the carbon residue precipitated during the high-temperature thermal annealing process, resulting in interference-free defect scanning detection, reducing the difficulty of defect detection, and lowering the risk of continued current failure due to misjudgment of interference.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figures 2-6 This is a schematic diagram of the structure corresponding to each step in the fabrication method of a semiconductor device provided in an embodiment of the present invention; Figure 7 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of some steps in another method for fabricating a semiconductor device provided in this embodiment of the invention. Figure 9 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided in an embodiment of the present invention. Figure 11 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided in an embodiment of the present invention. Figure 13 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention; Figures 14-15 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided in an embodiment of the present invention. Figure 16 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention; Figures 17-19 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Figures 2-6 This is a schematic diagram of the structure corresponding to each step in the fabrication method of a semiconductor device provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the preparation method includes: S100: Provide a semiconductor body, the semiconductor body is configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other, the semiconductor body also includes a well region and a first region, the first region is configured with the first conductivity type and is located on the first surface, the well region is configured with the second conductivity type and is located on the side of the first region away from the first surface; the first conductivity type and the second conductivity type are different; the semiconductor body includes a silicon carbide semiconductor body.

[0026] Specifically, such as Figure 2 As shown, a semiconductor body 1 is first provided, which may include a silicon carbide semiconductor body. The semiconductor body 1 may include a substrate 11 and an epitaxial layer 12. In some embodiments of the present invention, the semiconductor body 1 may also include only the epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may also include a substrate 11 and a semiconductor layer formed by other processes. The epitaxial layer 12 is a semiconductor layer formed on the substrate 11 by a single epitaxial process, including chemical vapor deposition (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).

[0027] The semiconductor body 1 may also include a well region 13, a first region 14, and a second region 15. The well region 13, the first region 14, and the second region 15 are formed on the side of the epitaxial layer 12 away from the substrate 11 by processes such as doping, and then the doped impurities are activated by an annealing process.

[0028] MOSFET semiconductor devices can include N-channel MOSFET semiconductor devices or P-channel MOSFET semiconductor devices. For example, in an N-channel MOSFET semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type. The semiconductor body 1 is an N-type semiconductor body, the well region 13 is a P-type well region, the first region 14 is an N+ doped region, the second region 15 is a P+ doped region, the substrate 11 is an N+ substrate, and the epitaxial layer 12 is an N- epitaxial layer. For a P-channel MOSFET semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type. The semiconductor body 1 is a P-type semiconductor body, the well region 13 is an N-type well region, the first region 14 is a P+ doped region, the second region 15 is an N+ doped region, the substrate 11 is a P+ substrate, and the epitaxial layer 12 is a P- epitaxial layer.

[0029] S110: Form a gate structure on the first surface, or form a gate structure extending from the first surface into the semiconductor body.

[0030] Specifically, such as Figure 3 As shown, a gate structure 2 is formed on one side of the semiconductor body 1. The gate structure 2 may include a second insulating layer 21 and a gate 22, wherein the second insulating layer 21 may include a gate dielectric layer and the gate 22 may include a polysilicon gate.

[0031] like Figure 3 As shown, the semiconductor device provided in this embodiment of the invention may include a planar semiconductor device, that is, a planar gate structure. In this case, a second insulating layer 21 is formed on the first surface 101 of the semiconductor body 1, and a gate 22 is formed on the side of the second insulating layer 21 away from the semiconductor body 1. The thickness of the second insulating layer 21 may be 500 Å, and the thickness of the gate 22 may be 5000 Å.

[0032] In some embodiments of the present invention, the semiconductor device provided by the embodiments of the present invention may further include a single-trench semiconductor device or a double-trench semiconductor device, that is, the gate structure is a trench-type gate structure. In this case, the semiconductor body 1 may be provided with a gate trench, which can extend from the first surface 101 into the semiconductor body 1. At this time, a second insulating layer 21 is formed at the bottom and sidewalls of the gate trench, and a gate 22 is formed in the gate trench on the side of the second insulating layer 21 away from the semiconductor body 1.

[0033] S120: An isolation protective layer is formed on the side of the gate structure away from the semiconductor body and on both sides of the gate structure.

[0034] Specifically, such as Figure 4 As shown, an isolation protection layer 3 is formed on the side of the gate structure 2 away from the semiconductor body 1 and on both sides of the gate structure 2. The isolation protection layer 3 can surround the gate 22, thereby forming an isolation protection for the gate 22. The isolation protection layer 3 can include a composite structure of an undoped silicate glass (USG) layer and a borosilicate glass (BPSG) layer, wherein the thickness of the USG layer can be 2000 Å and the thickness of the BPSG layer can be 10000 Å.

[0035] S130: Using a thermal annealing process, an ohmic contact layer is formed on both sides of the isolation protection layer and the gate structure, and on the first surface; the ohmic contact layer is in contact with the first region.

[0036] Specifically, such as Figure 5As shown, an ohmic contact layer 4 can be formed between the source and the semiconductor body 1. Metallic nickel can be deposited on both sides of the isolation protection layer 3 and the gate structure 2. Then, the ohmic contact layer 4 is formed through a two-step high-temperature thermal annealing process. The ohmic contact layer 4 can contact the first region 14. During the high-temperature thermal annealing process, silicon in the semiconductor body 1 reacts with metallic nickel, causing carbon atoms in the semiconductor body 1 to escape. Some carbon atoms migrate to the side of the isolation protection layer 3 away from the semiconductor body 1, forming carbon residue 10.

[0037] S140: Use a resist removal process to remove carbon residues deposited on the side of the isolation protective layer away from the semiconductor body due to thermal annealing.

[0038] Specifically, such as Figure 6 As shown, in order to remove carbon residue on the side of the isolation protective layer 3 away from the semiconductor body 1, the carbon residue is removed by an asher process, that is, by using oxygen to react with the carbon residue in an oxidation-reduction reaction, thereby achieving the purpose of removing the carbon deposited on the surface.

[0039] Existing methods for forming the ohmic contact layer between the source electrode and the semiconductor body using high-temperature thermal annealing suffer from significant interference during defect scanning and detection. This is due to carbon precipitation caused by the reaction between metallic nickel and silicon in the semiconductor body, impacting online wafer yield monitoring. Maintaining this status quo leads to inspectors misinterpreting true defects as noise, causing wafer follow current and potentially resulting in product scrap, further reducing device yield. It also imposes additional workload and training costs on online inspectors. This invention addresses this issue by adding a resist removal process after high-temperature thermal annealing to remove residual carbon before performing defect scanning and detection, thus resolving the significant interference from carbon residue in defect scanning and detection.

[0040] The technical solution of this invention addresses the problem of significant interference in defect scanning detection of silicon carbide MOSFET devices after the high-temperature thermal annealing process of the ohmic contact layer 4. Through analysis of the reaction mechanism, a creative adhesive removal process is added after high-temperature thermal annealing and before defect scanning detection. This effectively removes the carbon residue precipitated during the high-temperature thermal annealing process, resulting in interference-free defect scanning detection, reducing the difficulty of defect detection, and lowering the risk of continued current failure due to misjudgment of interference.

[0041] Optionally, based on the above embodiments, such as Figure 5As shown, during the high-temperature thermal annealing process, silicon in the semiconductor body 1 reacts with metallic nickel, causing carbon atoms in the semiconductor body 1 to escape. Some carbon atoms migrate to the side of the isolation protective layer 3 away from the semiconductor body 1, forming carbon residue 10. Carbon residue 10 may include free carbon and / or graphene residue. For example... Figure 6 As shown, in this embodiment of the invention, a resist removal process can be used to remove free carbon and / or graphene residues precipitated on the side of the isolation protective layer 3 away from the semiconductor body 1 due to thermal annealing.

[0042] Meanwhile, the free carbon and / or graphene residue precipitated due to thermal annealing will increase the number of defects in the device. Actual production shows that the number of defects in the device without the added adhesive removal process is about 279,771, while the number of defects in the device with the added adhesive removal process is about 29, and the product yield is also increased from 97% to 99.57%.

[0043] Optionally, based on the above embodiments, Figure 7 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of some steps in another method for fabricating a semiconductor device provided in this embodiment of the invention, as shown below. Figure 7 As shown, the preparation method includes: S200: Provide a semiconductor body, the semiconductor body is configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other, the semiconductor body also includes a well region and a first region, the first region is configured with the first conductivity type and is located on the first surface, the well region is configured with the second conductivity type and is located on the side of the first region away from the first surface; the first conductivity type and the second conductivity type are different; the semiconductor body includes a silicon carbide semiconductor body.

[0044] S210: Form a gate structure on the first surface, or form a gate structure extending from the first surface into the semiconductor body.

[0045] S220: An isolation protective layer is formed on the side of the gate structure away from the semiconductor body and on both sides of the gate structure.

[0046] S230: Using a thermal annealing process, an ohmic contact layer is formed on both sides of the isolation protection layer and the gate structure, and on the first surface; the ohmic contact layer is in contact with the first region.

[0047] S240: Place the semiconductor device after the formation of the ohmic contact layer in the plasma reaction chamber.

[0048] Specifically, such as Figure 5As shown, a semiconductor device with an ohmic contact layer 4 is placed in a plasma reaction chamber. At this time, the surface of the isolation protective layer 3 away from the semiconductor body 1 has carbon residue 10 precipitated due to high-temperature thermal annealing.

[0049] S250: Introduce oxygen-containing process gas into the plasma reaction chamber and excite the oxygen-containing process gas to generate oxygen plasma.

[0050] Specifically, oxygen-containing process gas is then introduced into the plasma reaction chamber, and the oxygen-containing process gas is excited to generate oxygen plasma.

[0051] S260: Uses oxygen plasma to ashing carbon residue, causing the carbon residue to react with oxygen to generate volatile oxidation products.

[0052] Specifically, such as Figure 8 As shown, by controlling the process temperature, the oxygen plasma reacts with the free carbon residue in a redox reaction to generate volatile gases, such as carbon dioxide or carbon monoxide.

[0053] S270: Discharges volatile oxidation products.

[0054] Specifically, it removes volatile oxidation products to achieve the removal of carbon residues.

[0055] Optionally, based on the above embodiments, Figure 9 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided in this embodiment of the invention, as shown below. Figure 9 As shown, the preparation method includes: S300: Provides a semiconductor body, the semiconductor body is configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other, the semiconductor body also includes a well region and a first region, the first region is configured with the first conductivity type and is located on the first surface, the well region is configured with the second conductivity type and is located on the side of the first region away from the first surface; the first conductivity type and the second conductivity type are different; the semiconductor body includes a silicon carbide semiconductor body.

[0056] S310: Form a gate structure on the first surface, or form a gate structure extending from the first surface into the semiconductor body.

[0057] S320: An isolation protective layer is formed on the side of the gate structure away from the semiconductor body and on both sides of the gate structure.

[0058] S330: A nickel metal layer is deposited on both sides of the isolation protection layer and the gate structure, and on the first surface.

[0059] Specifically, such as Figure 10 As shown, a nickel metal layer 41 is deposited on both sides of the isolation protection layer 3 and the gate structure 2, and on the first surface 101.

[0060] S340: Perform the first thermal annealing process to allow the nickel metal layer to react with the semiconductor bulk to generate the first nickel silicide layer in an intermediate state.

[0061] Specifically, such as Figure 10 As shown, after depositing the nickel metal layer 41, the silicon carbide wafer undergoes two high-temperature thermal annealing processes. The first high-temperature thermal annealing process is performed at a relatively low temperature, allowing the nickel metal layer 41 to react with the silicon in the semiconductor body 1 to form a high-resistivity nickel-silicon compound intermediate state, i.e., generating the high-resistivity first nickel silicide layer. For example, the first nickel silicide layer may include Ni... 32 Si 12 And Ni2Si.

[0062] S350: Uses a wet etching process to remove the unreacted portion of the nickel metal layer on the side furthest from the semiconductor body.

[0063] Specifically, such as Figure 10 As shown, after the first high-temperature thermal annealing treatment, there is an unreacted nickel metal layer 41 on the side of the nickel metal layer 41 away from the semiconductor body 1. This unreacted nickel metal layer 41 is removed using a wet etching process. For example, the unreacted nickel metal layer 41 can be removed by a solution of sulfuric acid and hydrogen peroxide.

[0064] S360: A second thermal annealing process is performed to transform the intermediate first nickel silicide layer into a second nickel silicide layer; the resistivity of the second nickel silicide layer is less than that of the first nickel silicide layer; thereby forming an ohmic contact layer.

[0065] Specifically, such as Figure 10 and Figure 5 As shown, after removing the unreacted nickel metal layer 41, a second thermal annealing process is performed. The temperature of the second thermal annealing process can be higher than that of the first thermal annealing process. The second thermal annealing process can further transform the intermediate high-resistivity first nickel silicide layer into a low-resistivity second nickel silicide layer, thereby forming an ohmic contact layer 4. For example, the second nickel silicide layer is Ni2Si and / or NiSi.

[0066] Optionally, based on the above embodiments, Figure 11 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Figure 12 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided in this embodiment of the invention, as shown below. Figure 11 As shown, the preparation method includes: S400: Provides a semiconductor body, the semiconductor body is configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other, the semiconductor body also includes a well region and a first region, the first region is configured with the first conductivity type and is located on the first surface, the well region is configured with the second conductivity type and is located on the side of the first region away from the first surface; the first conductivity type and the second conductivity type are different; the semiconductor body includes a silicon carbide semiconductor body.

[0067] S410: Form a gate structure on the first surface, or form a gate structure extending from the first surface into the semiconductor body.

[0068] S420: An isolation protective layer is formed on the side of the gate structure away from the semiconductor body and on both sides of the gate structure.

[0069] S430: Using a thermal annealing process, an ohmic contact layer is formed on both sides of the isolation protection layer and the gate structure, and on the first surface; the ohmic contact layer is in contact with the first region.

[0070] S440: Uses a resist removal process to remove carbon residues deposited during thermal annealing on the side of the isolation protective layer away from the semiconductor body.

[0071] S450: Remove the isolation protective layer.

[0072] Specifically, such as Figure 6 and Figure 12 As shown, the isolation layer 3 can be disposed around the gate 22. During the formation of the ohmic contact layer 4, the isolation layer 3 can effectively protect the gate 22 and prevent short circuits between the ohmic contact layer 4 and the gate 22. After the ohmic contact layer 4 is formed, the carbon residue precipitated due to thermal annealing on the side of the isolation layer 3 away from the semiconductor body 1 is removed using a resist-removal process. This process will cause an increase in the roughness of the side of the isolation layer 3 away from the semiconductor body 1, and the film properties may change. Therefore, the isolation layer 3 cannot be retained as an interlayer dielectric layer and needs to be removed to avoid affecting the final performance of the device.

[0073] Optionally, based on the above embodiments, Figure 13 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Figures 14-15 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided in this embodiment of the invention, as shown below. Figure 13 As shown, the preparation method includes: S500: Provides a semiconductor body, the semiconductor body is configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other, the semiconductor body also includes a well region and a first region, the first region is configured with the first conductivity type and is located on the first surface, the well region is configured with the second conductivity type and is located on the side of the first region away from the first surface; the first conductivity type and the second conductivity type are different; the semiconductor body includes a silicon carbide semiconductor body.

[0074] S510: Form a gate structure on the first surface, or form a gate structure extending from the first surface into the semiconductor body.

[0075] S520: An isolation protective layer is formed on the side of the gate structure away from the semiconductor body and on both sides of the gate structure.

[0076] S530: Using a thermal annealing process, an ohmic contact layer is formed on both sides of the isolation protection layer and the gate structure, and on the first surface; the ohmic contact layer is in contact with the first region.

[0077] S540: Uses a resist removal process to remove carbon residues deposited during thermal annealing on the side of the isolation protective layer away from the semiconductor body.

[0078] S550: A photoresist layer is formed on the side of the ohmic contact layer and the isolation protection layer away from the semiconductor body, and the photoresist layer is exposed.

[0079] Specifically, such as Figure 14 As shown, a photoresist layer 3 is removed from the side of the isolation protective layer 3 away from the semiconductor body 1 due to thermal annealing using a photoresist stripping process. This process increases the roughness of the side of the isolation protective layer 3 away from the semiconductor body 1, and the film properties may change. Therefore, it is necessary to remove the isolation protective layer 3. First, a photoresist layer 51 is formed on the side of the isolation protective layer 3 away from the semiconductor body 1, and the photoresist layer 51 is exposed to transfer the mask pattern onto the photoresist layer 51.

[0080] S560: The photoresist layer is developed. The development process includes multiple cycles of applying developer and static immersion to remove the photoresist layer on the side of the isolation protective layer away from the semiconductor body.

[0081] Specifically, such as Figure 14 and Figure 15As shown, in order to remove the photoresist layer 51 on the side of the isolation protective layer 3 away from the semiconductor body 1, the photoresist layer 51 after exposure needs to be developed. However, since the side of the isolation protective layer 3 away from the semiconductor body 1 has an uneven surface, the photoresist layer 51 may remain on this side during development. Therefore, in this embodiment of the invention, the development process involves multiple cycles of coating with developer and static immersion to optimize and improve the photolithography process, thereby enhancing the development capability and achieving complete removal of the photoresist layer 51 on the side of the isolation protective layer 3 away from the semiconductor body 1.

[0082] S570: Etch the isolation protective layer to remove the isolation protective layer and remove the remaining photoresist layer.

[0083] Specifically, such as Figure 15 and Figure 12 As shown, the isolation protective layer 3 is etched to remove the isolation protective layer 3. Then the remaining photoresist layer 51 is removed.

[0084] Optionally, based on the above embodiments, such as Figure 14 and Figure 15 As shown, when developing the photoresist layer 51, the developing process may include at least eight cycles of coating with the developing solution and then immersing in it. In some embodiments of the present invention, the number of cycles of coating with the developing solution and immersing in it can be arbitrarily set according to actual conditions, and may be less than eight. No specific limitation is made here, as long as the photoresist layer 51 on the side of the isolation protective layer 3 away from the semiconductor body 1 is completely removed.

[0085] Optionally, based on the above embodiments, such as Figure 14 and Figure 15 As shown, the photoresist layer 51 undergoes a development process, which includes multiple coatings of the developing solution followed by a 15-60 second static immersion cycle. In some embodiments of the present invention, the static immersion time can be arbitrarily set according to actual conditions, and can be less than 15 seconds or greater than 60 seconds. No specific limitation is made here, as long as the photoresist layer 51 on the side of the isolation protective layer 3 away from the semiconductor body 1 is completely removed.

[0086] Optionally, based on the above embodiments, Figure 16 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Figures 17-19 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided in this embodiment of the invention, as shown below. Figure 16 As shown, the preparation method includes: S600: Provides a semiconductor body, the semiconductor body is configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other, the semiconductor body also includes a well region and a first region, the first region is configured with the first conductivity type and is located on the first surface, the well region is configured with the second conductivity type and is located on the side of the first region away from the first surface; the first conductivity type and the second conductivity type are different; the semiconductor body includes a silicon carbide semiconductor body.

[0087] S610: Form a gate structure on the first surface, or form a gate structure extending from the first surface into the semiconductor body.

[0088] S620: An isolation protective layer is formed on the side of the gate structure away from the semiconductor body and on both sides of the gate structure.

[0089] S630: Using a thermal annealing process, an ohmic contact layer is formed on both sides of the isolation protection layer and the gate structure, and on the first surface; the ohmic contact layer is in contact with the first region.

[0090] S640: Uses a resist removal process to remove carbon residues deposited during thermal annealing on the side of the isolation protective layer away from the semiconductor body.

[0091] S650: Remove the isolation protective layer.

[0092] S660: A first insulating layer is formed on the side of the gate structure away from the semiconductor body and between the gate structure and the ohmic contact layer; the vertical projection of the first insulating layer on the semiconductor body covers the vertical projection of the gate structure on the semiconductor body.

[0093] Specifically, such as Figure 17 As shown, a first insulating layer 6 is formed on the side of the gate structure 2 away from the semiconductor body 1 and on both sides of the gate structure 2. The first insulating layer 6 can serve as an interlayer dielectric layer to insulate and isolate the gate 22 and the source.

[0094] S670: The source is formed on the side of the first insulating layer and the ohmic contact layer away from the semiconductor body.

[0095] Specifically, such as Figure 18 As shown, a source electrode 7 is formed on the side of the first insulating layer 6 and the ohmic contact layer 4 away from the semiconductor body 1. The source electrode 7 achieves ohmic contact with the semiconductor body 1 through the ohmic contact layer 4.

[0096] like Figure 18As shown, the semiconductor device provided in this embodiment of the invention may include a planar semiconductor device, that is, a planar gate structure and a planar source structure. In this case, a second insulating layer 21 is formed on the first surface 101 of the semiconductor body 1, and a gate 22 is formed on the side of the second insulating layer 21 away from the semiconductor body 1. No source trench or source insulating layer is provided in the semiconductor body 1, and the source 7 is located on the side of the first insulating layer 6 and the ohmic contact layer 4 away from the semiconductor body 1.

[0097] In some embodiments of the present invention, the semiconductor device provided by the embodiments of the present invention may further include a single-trench semiconductor device or a double-trench semiconductor device. For a single-trench semiconductor device, the gate structure is a trench-type gate structure and the source structure is a planar source structure. In this case, the semiconductor body 1 may be provided with a gate trench, which can extend from the first surface 101 into the semiconductor body 1. At this time, a second insulating layer 21 is formed at the bottom and sidewalls of the gate trench. On the side of the second insulating layer 21 away from the semiconductor body 1, a gate 22 is formed in the gate trench. No source trench or source insulating layer is provided in the semiconductor body 1, and the source 7 is located on the side of the first insulating layer 6 and the ohmic contact layer 4 away from the semiconductor body 1. For a dual-trench semiconductor device, the gate structure is a trench gate structure and the source structure is a trench source structure. At this time, a source trench is provided in the semiconductor body 1. The source trench can extend along the first surface 101 into the interior of the second region 15. A source insulating layer is provided on the bottom surface and sidewalls of the source trench. A source filling structure can be provided in the source trench on the side away from the semiconductor body 1, or no source filling structure can be provided. The source is also located on the side of the first insulating layer 6 and the ohmic contact layer 4 away from the semiconductor body 1.

[0098] S680: Drain electrode is formed on the second surface.

[0099] Specifically, such as Figure 19 As shown, the side of the substrate 11 away from the epitaxial layer 12 can be thinned, and then the drain 8 can be formed on the second surface 102. During the formation of the drain 8, after the substrate 11 is thinned, metallic nickel can be deposited on the side of the substrate 11 away from the epitaxial layer 12, and then the ohmic contact layer of the drain 8 can be formed by high-temperature thermal annealing. If carbon in the semiconductor body 1 migrates to the side of the ohmic contact layer of the drain 8 away from the semiconductor body 1 at this time, a new resist removal process can be added to remove the carbon residue.

[0100] Figure 19 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, wherein the semiconductor device is fabricated using the fabrication method of the semiconductor device provided in any of the above embodiments of the present invention. Figure 19As shown, the semiconductor device includes: a semiconductor body 1, configured for a first conductivity type, including a first surface 101 and a second surface 102 disposed opposite to each other; the semiconductor body 1 also includes a well region 13 and a first region 14, the first region 14 being configured for the first conductivity type and located on the first surface 101, and the well region 13 being configured for the second conductivity type and located on the side of the first region 14 away from the first surface 101. The first conductivity type and the second conductivity type are different; the semiconductor body 1 includes a silicon carbide semiconductor body. A gate structure 2 is located on the first surface 101, or extends from the first surface 101 into the semiconductor body 1. A first insulating layer 6 is located on the side of the gate structure 2 away from the semiconductor body 1, and is located on both sides of the gate structure 2. The vertical projection of the first insulating layer 6 on the semiconductor body 1 covers the vertical projection of the gate structure 2 on the semiconductor body 1. An ohmic contact layer 4 is located on both sides of the gate structure 2 and the first insulating layer 6, and the ohmic contact layer 4 contacts the first region 14. A source 7 is located on the side of the first insulating layer 6 and the ohmic contact layer 4 away from the semiconductor body 1. A drain 8 is located on the second surface 102.

[0101] Optionally, such as Figure 19 As shown, the semiconductor body 1 may also include a second region 15, the doping concentration of the second region 15 being greater than the doping concentration of the well region 13, which can form a good ohmic contact with the source 7.

[0102] It should be noted that MOSFET semiconductor devices can include N-channel MOSFET semiconductor devices or P-channel MOSFET semiconductor devices. For example, for an N-channel MOSFET semiconductor device, the first conductivity type is N-type, and the second conductivity type is P-type. Semiconductor body 1 is an N-type semiconductor body, well region 13 is a P-type well region, first region 14 is an N+ doped region, and second region 15 is a P+ doped region. For a P-channel MOSFET semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type. Semiconductor body 1 is a P-type semiconductor body, well region 13 is an N-type well region, first region 14 is a P+ doped region, and second region 15 is an N+ doped region.

[0103] For example, such as Figure 19As shown, the semiconductor body 1 may further include a substrate 11 and an epitaxial layer 12. For an N-channel MOSFET semiconductor device, the substrate 11 includes an N+ substrate, and the epitaxial layer 12 includes an N- epitaxial layer. For a P-channel MOSFET semiconductor device, the substrate 11 includes a P+ substrate, and the epitaxial layer 12 includes a P- epitaxial layer. In some embodiments of the present invention, the semiconductor body 1 may also include only the epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may also include a substrate 11 and a semiconductor layer formed by other processes. The epitaxial layer 12 is a semiconductor layer formed on the substrate 11 by a single epitaxial process, including chemical vapor deposition (CVE), molecular beam epitaxy (MBE), and atomic layer epitaxy (ALE).

[0104] The gate structure 2 may include a second insulating layer 21 and a gate 22, wherein the second insulating layer 21 may include a gate dielectric layer and the gate 22 may include a polysilicon gate. The first insulating layer 6 may serve as an interlayer dielectric layer to insulate and isolate the gate 22 and the source 7, and the source 7 achieves ohmic contact with the semiconductor body 1 through the ohmic contact layer 4.

[0105] This invention provides a power module, wherein the power module includes a substrate and at least one semiconductor device provided in any of the above embodiments of this invention, and the substrate is used to carry at least one semiconductor device provided in any of the above embodiments of this invention.

[0106] The power module provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0107] This invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction.

[0108] The power conversion circuit includes a circuit board and at least one semiconductor device provided in any of the above embodiments of the present invention, wherein the semiconductor device is electrically connected to the circuit board.

[0109] The power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0110] This invention provides a vehicle, wherein the vehicle includes a load and a power conversion circuit provided in any of the above embodiments of the invention. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0111] The vehicle provided in any of the above embodiments of the present invention includes the power conversion circuit provided in any of the above embodiments of the present invention, and the power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention. Therefore, the vehicle provided in any of the above embodiments of the present invention has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0112] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0113] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor body is provided, the semiconductor body being configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other, the semiconductor body further including a well region and a first region, the first region being configured with the first conductivity type and located on the first surface, the well region being configured with the second conductivity type and located on the side of the first region away from the first surface; the first conductivity type and the second conductivity type are different; the semiconductor body includes a silicon carbide semiconductor body; A gate structure is formed on the first surface, or the gate structure extends from the first surface into the semiconductor body; An isolation protective layer is formed on the side of the gate structure away from the semiconductor body and on both sides of the gate structure; Using a thermal annealing process, an ohmic contact layer is formed on both sides of the isolation protective layer and the gate structure, and on the first surface; the ohmic contact layer is in contact with the first region; The carbon residue precipitated due to thermal annealing on the side of the isolation protective layer away from the semiconductor body is removed using a resist-removal process.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, Removing residual carbon deposited during thermal annealing on the side of the protective layer away from the semiconductor body using a resist-removal process includes: The free carbon and / or graphene residue precipitated due to thermal annealing on the side of the isolation protective layer away from the semiconductor body is removed using a resist removal process.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, Removing residual carbon deposited during thermal annealing on the side of the protective layer away from the semiconductor body using a resist-removal process includes: The carbon residue is ashed using oxygen plasma, causing the carbon residue to react with oxygen to generate volatile oxidation products. The volatile oxidation products are discharged.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, Before ashing the carbon residue using oxygen plasma, the process further includes: The semiconductor device after the formation of the ohmic contact layer is placed in a plasma reaction chamber; An oxygen-containing process gas is introduced into the plasma reaction chamber, and the oxygen-containing process gas is excited to generate the oxygen plasma.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, Using a thermal annealing process, an ohmic contact layer is formed on both sides of the isolation protective layer and the gate structure, and on the first surface, including: A nickel metal layer is deposited on both sides of the isolation protective layer and the gate structure, and on the first surface; A first thermal annealing process is performed to allow the nickel metal layer to react with the semiconductor body to generate an intermediate state first nickel silicide layer. The unreacted portion of the nickel metal layer on the side furthest from the semiconductor body is removed using a wet etching process; A second thermal annealing process is performed to transform the intermediate first nickel silicide layer into a second nickel silicide layer; the resistivity of the second nickel silicide layer is less than that of the first nickel silicide layer; thereby forming the ohmic contact layer.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, After removing the carbon residue precipitated during thermal annealing on the side of the insulating protective layer away from the semiconductor body using a resist-removal process, the method further includes: Remove the isolation protective layer.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, Removing the protective isolation layer includes: A photoresist layer is formed on the side of the ohmic contact layer and the isolation protective layer away from the semiconductor body; The photoresist layer is exposed to light; The photoresist layer is subjected to a development process, which includes multiple cycles of coating with developer and static immersion to remove the photoresist layer on the side of the isolation protective layer away from the semiconductor body. The isolation protective layer is etched to remove the isolation protective layer, and the remaining photoresist layer is removed.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The photoresist layer is developed, including: The photoresist layer is subjected to a development process, which includes at least eight cycles of coating with developer and then immersing in still water.

9. The method for fabricating a semiconductor device according to claim 7, characterized in that, The photoresist layer is developed, including: The photoresist layer is subjected to a development process, which includes multiple coatings with developer and cycles of static immersion for 15-60 seconds.

10. The method for fabricating a semiconductor device according to claim 6, characterized in that, After removing the protective isolation layer, the method further includes: A first insulating layer is formed on the side of the gate structure away from the semiconductor body and on both sides of the gate structure; the vertical projection of the first insulating layer on the semiconductor body covers the vertical projection of the gate structure on the semiconductor body. A source electrode is formed on the side of the first insulating layer and the ohmic contact layer away from the semiconductor body; A drain electrode is formed on the second surface.

11. The method for fabricating a semiconductor device according to claim 1, characterized in that, A gate structure is formed on the first surface, including: A second insulating layer is formed on the first surface; A gate is formed on the side of the second insulating layer away from the semiconductor body; A gate trench is provided on the first surface of the semiconductor body; forming the gate structure extending from the first surface into the semiconductor body includes: A second insulating layer is formed at the bottom and sidewalls of the gate trench; The gate is formed on the side of the second insulating layer away from the semiconductor body and within the gate trench.

12. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method for preparing a semiconductor device according to any one of claims 1-11; the semiconductor device comprises: A semiconductor body, wherein the semiconductor body is configured with a first conductivity type, includes a first surface and a second surface disposed opposite to each other, the semiconductor body further includes a well region and a first region, the first region being configured with the first conductivity type and located on the first surface, and the well region being configured with the second conductivity type and located on the side of the first region away from the first surface; the first conductivity type and the second conductivity type are different; the semiconductor body includes a silicon carbide semiconductor body; A gate structure is located on the first surface or extends from the first surface into the semiconductor body; A first insulating layer is located on the side of the gate structure away from the semiconductor body and on both sides of the gate structure; the vertical projection of the first insulating layer on the semiconductor body covers the vertical projection of the gate structure on the semiconductor body. An ohmic contact layer is located on both sides of the gate structure and the first insulating layer; the ohmic contact layer is in contact with the first region; The source electrode is located on the side of the first insulating layer and the ohmic contact layer away from the semiconductor body; The drain electrode is located on the second surface.

13. A power module, characterized in that, It includes a substrate and at least one semiconductor device as described in any one of claims 12, wherein the substrate is used to support the semiconductor device.

14. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 12, the semiconductor device being electrically connected to the circuit board.

15. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 14, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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