semiconductor structure

Abstract

This invention discloses a semiconductor structure including a drift region formed in a substrate and having a first conductivity type. The semiconductor structure includes a body region formed in the substrate and having a second conductivity type different from the first conductivity type. The semiconductor structure includes a gate structure formed above and adjacent to the drift region, and a drain region formed in the drift region and having the first conductivity type. The semiconductor structure includes a source region formed in the body region and having the first conductivity type, and a first well region adjacent to the drift region and having the first conductivity type. A second well region adjacent to the first well region, having the second conductivity type, and the first well region directly contacting the second well region.

Description

Technical Field

[0001] This invention relates generally to semiconductor technology, and in particular to a semiconductor structure. Background Technology

[0002] Recently, with the increasing demand for high-voltage devices such as power semiconductor devices, there has been a growing interest in researching high-voltage metal-oxide-semiconductor field-effect transistors (HV MOSFETs) used in high-voltage devices.

[0003] Among various types of high voltage metal-oxide-semiconductor field-effect transistors (HV MOSFETs), semiconductor devices such as lateral double diffused metal-oxide-semiconductor (LDMOS) devices are frequently used.

[0004] However, with advancements in semiconductor manufacturing technology, the breakdown voltage of high-voltage MOSFETs used in high-voltage devices needs further improvement. Therefore, a reliable high-voltage MOSFET is required to meet the performance requirements of high-voltage devices, as the demand for semiconductor manufacturing of high-voltage devices continues to grow. Summary of the Invention

[0005] This invention provides an exemplary embodiment of a semiconductor structure including a substrate and a drift region formed in the substrate, having a first conductivity type. The semiconductor structure includes a body region formed in the substrate, having a second conductivity type different from the first conductivity type. The semiconductor structure includes a gate structure formed above the drift region and adjacent to the body region, and a drain region formed in the drift region, having a first conductivity type. The semiconductor structure includes a source region formed in the body region, having a first conductivity type, and a first well region adjacent to the drift region. The first well region has a first conductivity type. The semiconductor structure includes a second well region adjacent to the first well region, the second well region having a second conductivity type. The first well region is in direct contact with the second well region.

[0006] Another embodiment of the semiconductor structure of the present invention includes a substrate and a drift region formed in the substrate, having a first conductivity type. The semiconductor structure includes a body region formed in the substrate, having a second conductivity type different from the first conductivity type. The semiconductor structure includes a gate structure formed above the drift region and a drain region formed in the drift region, having a first conductivity type. The semiconductor structure includes a source region formed in the body region, having a first conductivity type, and an inner ring surrounding the gate structure, drain region, and source region, the inner ring having a first conductivity type. The semiconductor structure includes an outer ring surrounding the inner ring, the outer ring having a second conductivity type.

[0007] Another embodiment of the present invention includes a semiconductor structure comprising a substrate and a drift region formed in the substrate having a first conductivity type. The semiconductor structure includes a body region formed in the substrate having a second conductivity type different from the first conductivity type. The semiconductor structure includes a gate structure formed above the drift region and an inner ring surrounding the gate structure. The semiconductor structure includes an outer ring surrounding the inner ring, and the inner ring or the outer ring has a plurality of first sub-parts having the first conductivity type and a plurality of second sub-parts having the second conductivity type. Attached Figure Description

[0008] A more complete understanding of the invention can be obtained by reading the following detailed description and referring to the accompanying drawings, wherein:

[0009] Figure 1 This is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention;

[0010] Figure 2 It is along Figure 1 A top view of the semiconductor structure of line AA', according to some embodiments of the present invention;

[0011] Figure 3 This is a circuit diagram of a step-down device, according to some embodiments of the present invention;

[0012] Figure 4 This is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention;

[0013] Figure 5 It is along Figure 4 A top view of the semiconductor structure of line AA', according to some embodiments of the present invention;

[0014] Figure 6 This is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention;

[0015] Figure 7 It is along Figure 6A top view of the semiconductor structure of line AA', according to some embodiments of the present invention;

[0016] Figure 8 This is a top view of a semiconductor structure according to some embodiments of the present invention;

[0017] Figure 9 This is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention;

[0018] Figure 10 It is along Figure 9 A top view of the semiconductor structure of line AA', according to some embodiments of the present invention;

[0019] Figure 11 This is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention;

[0020] Figure 12 It is along Figure 11 A top view of the semiconductor structure of line AA', according to some embodiments of the present invention;

[0021] Figure 13 This is a top view of a semiconductor structure according to some embodiments of the present invention. Detailed Implementation

[0022] The following description is intended to illustrate the general principles of the invention and should not be considered limiting. The scope of the invention is best determined by referring to the appended claims.

[0023] This invention will be described in conjunction with specific embodiments and certain illustrations, but is not limited thereto, only by the claims. The described illustrations are merely illustrative and not restrictive. In the illustrations, the dimensions of some elements may be exaggerated for illustrative purposes and are not drawn to scale. Dimensions and relative dimensions do not correspond to actual dimensions in the practice of this invention.

[0024] Additional elements may be added to the embodiments described below. For example, the description of "the first element is on / on the second element" may include an embodiment in which the first element and the second element are in direct contact, or it may include an embodiment in which an additional element is placed between the first element and the second element, such that the first element and the second element are not in direct contact.

[0025] Furthermore, the description of "the first element extending through the second element" may include embodiments in which the first element is disposed in the second element and extends from one side of the second element to the opposite side of the second element, wherein the surface of the first element may be substantially flush with the surface of the second element, or the surface of the first element may be outside the surface of the second element.

[0026] The spatial relative descriptors of the first and second elements may change as the structure is operated or used in different directions. Furthermore, reference numerals and / or letters may be repeated in various embodiments of the invention. This repetition is for simplicity and clarity and does not inherently determine the relationship between the various embodiments discussed. For the avoidance of doubt, the X, Y, and Z directions in the figures are perpendicular to each other and used consistently.

[0027] A semiconductor structure includes an active region and a peripheral region, with a transistor formed in the active region and multiple guard rings formed in the peripheral region. The transistor in the active region is surrounded by the guard rings. The guard rings manage breakdown paths away from the active region. There can be two or three guard rings. The guard rings are designed to establish a breakdown voltage relatively lower than the breakdown voltage of the active region. High voltages or high currents will be connected to a ground-optional location (GND) through the guard rings. Therefore, the transistor in the active region is protected from damage by the guard rings.

[0028] Figure 1 This is a cross-sectional view of a semiconductor structure 100a according to some embodiments of the present invention. Additional features can be added to the semiconductor structure 100a. Some features described below can be replaced or eliminated to adapt to different embodiments. For simplicity, only a portion of the semiconductor structure 100a is shown. In some embodiments, the semiconductor structure 100a is a laterally diffused metal-oxide-semiconductor (LDMOS) transistor.

[0029] like Figure 1 As shown, according to some embodiments, semiconductor structure 100a includes a substrate 102, a drift region 110, and a body region 120. The substrate 102 includes an active region 10 surrounded by a peripheral region 20. The drift region 110 is formed in the substrate 102 and has a first conductivity type. The body region 120 is formed in the substrate 102 and has a second conductivity type different from the first conductivity type. In some embodiments, the drift region 110 has an N-type conductivity type, and the body region 120 has a P-type conductivity type. Semiconductor structure 100a is substantially symmetrical with respect to the body region 120.

[0030] The substrate 102 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP).

[0031] The semiconductor structure 100a further includes a plurality of isolation structures 108 located in the substrate 102. The isolation regions are also referred to as shallow trench isolation (STI) features. In some embodiments, the isolation structures 108 include silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), other suitable insulating materials, or combinations thereof. In some embodiments, the isolation structures 108 are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0032] The semiconductor structure 100a further includes a transistor comprising a gate structure 130, a drain region 114, and a source region 124, respectively formed on both sides of the gate structure 130. A drift region 110 is laterally located between the source region 124 and the drain region 114.

[0033] The gate structure 130 includes a gate dielectric layer 132 and a gate electrode layer 134 formed on the gate dielectric layer 132. A pair of gate spacer layers 136 are formed on the opposing sidewall surfaces of the gate structure 130. The gate electrode layer 134 is separated from the drift region 110 by the gate dielectric layer 132. The channel region 131 is located directly below the gate structure 130 and between the source region 124 and the drain region 114.

[0034] In some embodiments, the dielectric constant of the gate dielectric layer 132 is greater than the dielectric constant of the gate spacer layer 136. In some embodiments, the gate dielectric layer 132 comprises one or more dielectric materials, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 132 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0035] In some embodiments, the gate spacer layer 136 comprises a dielectric material, such as silicon dioxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride carbon (SiOCN), or a combination thereof. In some embodiments, the gate spacer layer 136 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0036] In some embodiments, the gate electrode layer 134 comprises one or more conductive material layers, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, titanium aluminum, titanium aluminum nitride, tantalum carbonitride, tantalum carbide, silicon tantalum nitride, metal alloys, other suitable materials, or combinations thereof. In some embodiments, the gate electrode layer 134 is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable methods, or combinations thereof.

[0037] Other conductive layers, such as work function metal layers, may also be formed in the gate structure 130, although they are not shown in the figures. In some embodiments, the n-type work function layer includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), silicon tantalum nitride (TaSiN), manganese (Mn), zirconium (Zr), or combinations thereof. In some embodiments, the p-type work function layer includes titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), molybdenum nitride (MoN), tungsten nitride (WN), ruthenium (Ru), or combinations thereof.

[0038] Drain region 114 is formed in drift region 110 and has a first conductivity type. In some embodiments, drain region 114 is doped with an N-type dopant, and drift region 110 is also doped with an N-type dopant. In some embodiments, the doping concentration of drain region 114 is greater than the doping concentration of drift region 110. In some embodiments, the doping concentration of drain region 114 is in the range of 10. 14 / cm 2 To about 10 15 / cm 2 In some embodiments, the doping concentration of the drift region 110 ranges from approximately 3. 10 12 / cm 2To about 6 10 12 / cm 2 .

[0039] Source region 124 is formed in body region 120 and has a first conductivity type. In some embodiments, source region 124 is doped with an N-type dopant. Furthermore, contact region 126 is formed in body region 120 and adjacent to source region 124. Contact region 126 directly contacts source region 124. Contact region 126 has a second conductivity type. In some embodiments, contact region 126 is doped with a p-type dopant. In some embodiments, the doping concentration of body region 120 ranges from approximately 10⁻⁶. 13 / cm 2 To about 10 14 / cm 2 .

[0040] A silicide barrier layer 142 is formed on a portion of the gate structure 130, a portion of the gate spacer layer 136, and the substrate 102. More specifically, the silicide barrier layer 142 covers the top surface of the gate electrode layer 134 of the gate structure 130 and the sidewall surface of the gate spacer layer 136. In some embodiments, the silicide barrier layer 142 is configured to block the deposition of a silicide layer.

[0041] In some embodiments, the silicide barrier layer 142 comprises an oxide or nitride, such as silicon dioxide, silicon oxynitride, silicon nitride, or other suitable materials. In some embodiments, the silicide barrier layer 142 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0042] After forming the silicide barrier layer 142, a metal silicide layer 143 is formed on a portion of the top surface of the source region 124, the drain region 114, and at least the gate electrode layer 134 of the gate structure 130 to reduce contact resistance. The metal silicide layer 143 comprises one or more cobalt silicides, nickel silicides, platinum silicides, or other suitable materials.

[0043] The metal silicide layer 143 can be formed by forming a metal layer on a portion of the top surface of the source region 124, the drain region 114, and at least the gate electrode layer 134 of the gate structure 130, and annealing the metal layer to form the metal silicide layer 143. After the metal silicide layer 143 is formed, any unreacted metal layer can be removed.

[0044] A first well region 162 is formed in the vicinity of the drift region 110, and a second well region 182 is adjacent to the first well region 162. The first well region 162 directly contacts the drift region 110, and the first well region 162 directly contacts the second well region 182. The first well region 162 has a first conductivity type, and the second well region 182 has a second conductivity type. In some embodiments, the first well region 162 is doped with N-type, and the second well region 182 is doped with P-type. An interface (or PN interface or PN junction) exists between the first well region 162 and the second well region 182.

[0045] Inner ring 166, middle ring 176 and outer ring 186 are formed in peripheral region 20. Gate structure 130, source region 124 and drain region 114 are surrounded by inner ring 166, middle ring 176 and outer ring 186.

[0046] An inner ring 160 is formed in a first well region 162. The first well region 162 has a first conductivity type, and the inner ring 166 also has a first conductivity type. In some embodiments, the first well region 162 is doped with N-type, and the inner ring 166 is doped with N-type. In some embodiments, the doping concentration of the inner ring 166 is greater than the doping concentration of the first well region 162. In some embodiments, the doping concentration of the drift region 110 is greater than the doping concentration of the first well region 162. In some embodiments, the doping concentration of the inner ring 166 ranges from 10. 14 / cm 2 To about 10 15 / cm 2 In some embodiments, the doping concentration of the first well region 162 ranges from approximately 1. 10 12 / cm 2 To about 2 10 12 / cm 2 .

[0047] A middle ring 176 is formed in the adjacent region of the inner ring 166. The middle ring 176 is also formed in the first well region 162. More specifically, the middle ring 176 has a second conductivity type in the first well region 162. In some embodiments, the first well region 162 is doped with N-type, and the middle ring 176 is doped with P-type. An interface (or PN interface or PN junction) exists between the first well region 162 and the middle ring 176.

[0048] The isolation structure 108 is located between the inner ring 166 and the middle ring 176. The inner ring 166 is separated from the middle ring 176 by the isolation structure 108. The depth of the isolation structure 108 is greater than the depth of both the inner ring 166 and the middle ring 176. In other words, the bottom surface of the isolation structure 108 is lower than the bottom surface of both the inner ring 166 and the middle ring 176.

[0049] An outer ring 186 is formed adjacent to a middle ring 176, which is located between an inner ring 166 and an outer ring 186. The inner ring 166 and the middle ring 176 are surrounded by the outer ring 186. The outer ring 186 is formed within a second well region 182. The second well region 182 has a second conductivity type, and the outer ring 186 also has a second conductivity type. In some embodiments, the second well region 182 is p-type doped, and the outer ring 186 is p-type doped.

[0050] The isolation structure 108 is located between the middle ring 176 and the outer ring 186. Furthermore, the isolation structure 108 is located between the first well region 162 and the second well region 182. The middle ring 176 is separated from the outer ring 186 by the isolation structure 108. The depth of the isolation structure 108 is greater than the depth of both the middle ring 176 and the outer ring 186. In other words, the bottom surface of the isolation structure 108 is lower than the bottom surfaces of both the middle ring 176 and the outer ring 186.

[0051] A dielectric layer 150 is formed on the gate structure 130, the drain region 114, and the source region 124. The dielectric layer 150 may comprise a multilayer made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and / or other suitable low-dielectric-constant materials. The dielectric layer 150 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0052] In addition, one or more etch stop layers (not shown) may be formed in the dielectric layer 150 to serve as etch stop layers during the etching process. The etch stop layers comprise dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The etch stop layers are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0053] Contact structure 186 is formed in dielectric layer 150. Furthermore, contact structure 186 is formed on contact region 126, and metal silicide layer 143 is located between contact region 126 and contact structure 186. Contact region 126 is electrically connected to contact structure 186 through metal silicide layer 143.

[0054] Contact structure 186 includes a conductive material, such as copper, tungsten, aluminum, silver, or a combination thereof. In some embodiments, the conductive material is formed by performing a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0055] A diffusion barrier layer may be formed prior to the formation of the conductive material. In some embodiments, the diffusion barrier layer is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable materials. In some embodiments, the diffusion barrier layer is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0056] In some embodiments, the contact opening is formed through a dielectric layer 150. The contact opening can be formed using photolithography and etching processes. Next, a diffusion barrier layer and a conductive material are filled into the contact opening to form a contact structure 186.

[0057] A drain contact structure 188 is formed in the dielectric layer 150. Furthermore, the drain contact structure 188 is formed on the drain region 114, and a metal silicide layer 143 is located between the drain region 114 and the drain contact structure 188. The drain region 114 is electrically connected to the drain contact structure 188 through the metal silicide layer 143. The drain contact structure 188 comprises a conductive material, such as copper, tungsten, aluminum, silver, or a combination thereof.

[0058] Inner contact structure 190a, middle contact structure 190b, and outer contact structure 190c are formed in dielectric layer 150. Furthermore, inner contact structure 190a is formed on and electrically connected to inner ring 166. Middle contact structure 190b is formed on and electrically connected to middle ring 17. Outer contact structure 190c is formed on and electrically connected to outer ring 186. Middle contact structure 190b is located between inner contact structure 190a and outer contact structure 190c. Inner contact structure 190a, middle contact structure 190b, and outer contact structure 190c comprise conductive materials, such as copper, tungsten, aluminum, silver, or combinations thereof.

[0059] A conductive layer 192 is formed on the drain region 114 and the inner ring 166. The conductive layer 192 is formed on and electrically connected to the drain contact structure 188 and the inner contact structure 190a. The conductive layer 192 is electrically connected to a high voltage (HV). The conductive layer 192 comprises a conductive material, such as copper, tungsten, aluminum, silver, or a combination thereof.

[0060] Conductive layer 194 is formed on the middle ring 176 and the outer ring 186. Conductive layer 194 is formed on and electrically connected to the middle contact structure 190b and the outer contact structure 190c. Conductive layer 194 is electrically connected to the ground potential position (GND). The inner contact structure 190a is electrically isolated from the outer contact structure 190c. Conductive layer 192 is electrically isolated from conductive layer 194. Conductive layer 194 comprises a conductive material, such as copper, tungsten, aluminum, silver, or a combination thereof.

[0061] like Figure 1 As shown, since the first well region 162 and the middle ring 176 have different conductivity types, a first interface (PN interface or PN junction) exists between the first well region 162 and the middle ring 176. Furthermore, since the first well region 162 and the second well region 182 have different conductivity types, a second interface (PN interface or PN junction) exists between the first well region 162 and the second well region 182. In some embodiments, when a high voltage (HV) is connected to the drain contact structure 188 and the inner contact structure 190a, and the ground potential position (GND) is connected to the middle contact structure 190b and the outer contact structure 190c, the first breakdown path 11 passes through the first interface between the first well region 162 and the middle ring 176. Furthermore, a second breakdown path 12 passes through the second interface between the first well region 162 and the second well region 182. Since the doping concentration of the middle ring 176 is higher than that of the second well region 182, the first breakdown voltage through the first breakdown path 11 is lower than the second breakdown voltage through the second breakdown path 12. Therefore, high voltage or high current can be connected to the ground potential (GND) through the first breakdown path 11 or the second breakdown path 12. Thus, the gate structure 130 of the transistor in the active region 10 is protected by the design of the inner ring 166, middle ring 176, and outer ring 186. When the semiconductor structure 100a operates under high voltage, the transistor in the active region 10 is not damaged. As described above, the first breakdown path 11 or the second breakdown path 12 is constructed by forming a PN junction or PN interface. The first breakdown path 11 or the second breakdown path 12 can effectively guide high voltage or high current to the ground potential (GND). Therefore, the transistor in the active region 10 is protected from damage, and the performance of the semiconductor structure 100a is improved. Figure 2 According to some embodiments of the present invention... Figure 1A top view of the semiconductor structure 100a of line AA'. The active region 10 is surrounded by the peripheral region 20. A gate structure 130, a source region 124, and a drain region 114 are formed in the active region 10. An inner ring 116, a middle ring 176, and an outer ring 186 are formed in the peripheral region 20. For clarity, the detailed structure within the active region 10 is not shown. Figure 2 As shown, the active region 10 is surrounded by an inner ring 166, a middle ring 176, and an outer ring 186. An isolation structure 108 is located between the inner ring 166 and the middle ring 176. The isolation structure 108 is located between the middle ring 176 and the outer ring 186. From a top view, the isolation structure 108 forms multiple rings. It should be noted that the inner ring 166, middle ring 176, and outer ring 186 are for illustrative purposes only; more rings may be provided in the peripheral region 20 of the semiconductor structure 100a. Figure 3 This is a circuit diagram of a buck converter device 60 according to some embodiments of the present invention. The buck converter device 60 includes, as follows: Figure 1 and Figure 2 The transistor of semiconductor structure 100a is shown. Buck converter device 60 includes a buck controller 30, a high-voltage side (HS) device 40, and a low-voltage side (LS) device 50. The input terminal Vin is connected to the buck controller 30, which is connected to both the high-voltage side (HS) device 40 and the low-voltage side (LS) device 50. The high-voltage side (HS) device 40 includes the transistor of semiconductor structure 100a. The transistor of semiconductor structure 100a includes a gate structure 130, a drain region 114, and a source region 124. The battery terminal Vbat is connected to the drain region 114, the buck controller 30 is connected to the gate structure 130, and the source region 124 is connected to the low-voltage side (LS) device 50 and the inductor 4. The inductor 4 is connected to the output terminal Vout and is connected to ground (GND) via a capacitor 6. Figure 4 This is a cross-sectional view of a semiconductor structure 100b according to some embodiments of the present invention. Additional features can be added to the semiconductor structure 100b. Some features described below can be replaced or eliminated in different embodiments. It should be noted that the semiconductor structure 100b may include features related to... Figure 1 The components shown in the semiconductor structure 100a are the same as or similar to those shown. For the sake of simplicity, these components will not be discussed in detail. Figure 4 The semiconductor structure 100b includes and Figure 1 The semiconductor structure 100a is similar to or the same as the component. Figure 4 and Figure 1 The difference lies in that the middle ring 176 is located within the second well region 182 and has a first conductivity type. In some embodiments, the middle ring 176 is doped with N-type, and the second well region 182 is doped with P-type. Therefore, an interface (or PN interface or PN junction) is formed between the middle ring 176 and the second well region 182. Figure 4As shown, when a high voltage (HV) is connected to the drain contact structure 188 and the inner contact structure 190a, and the ground potential position (GND) is connected to the middle contact structure 190b and the outer contact structure 190c, the first breakdown path 11 passes through the first well region 162 and the middle ring 176. Furthermore, a second breakdown path 12 passes through the second interface between the first well region 162 and the second well region 182. In some embodiments, the first breakdown voltage through the first breakdown path 11 can be adjusted by controlling the distance between the first well region 162 and the middle ring 176. In some other embodiments, the first breakdown voltage through the first breakdown path 11 can be adjusted by controlling the doping concentration of the middle ring 176. Similar to... Figure 1 In semiconductor structure 100a, the first breakdown voltage through the first breakdown path 11 is lower than the second breakdown voltage through the second breakdown path 12. Therefore, high voltage or high current can be connected to ground potential (GND) through either the first breakdown path 11 or the second breakdown path 12. Thus, the gate structure 130 of the transistor in active region 10 is protected by the design of the inner ring 166, middle ring 176, and outer ring 186. When semiconductor structure 100b operates under high voltage, the transistor in active region 10 will not be damaged. Figure 5 According to some embodiments of the present invention, along Figure 4 Top view of the semiconductor structure 100b of line AA'.

[0062] like Figure 5 As shown, the active area 10 is surrounded by an inner ring 166, a middle ring 176, and an outer ring 186. An isolation structure 108 is located between the inner ring 166 and the middle ring 176. The isolation structure 108 is located between the middle ring 176 and the outer ring 186. From a top view, the isolation structure 108 forms multiple rings.

[0063] Figure 6 This is a cross-sectional view of semiconductor structure 100c according to some embodiments of the present invention. Additional features may be added to semiconductor structure 100c. Some features described below may be replaced or omitted in different embodiments. It should be noted that semiconductor structure 100c may include... Figure 1 The components shown in the semiconductor structure 100a are the same as or similar to those shown. For the sake of simplicity, these components will not be discussed in detail.

[0064] Figure 6 The semiconductor structure 100c includes and Figure 1 The semiconductor structure 100a is similar to or the same as the component. Figure 6 and Figure 1The difference lies in the absence of a middle ring, and the outer ring 186 comprises multiple first sub-parts 186a having a first conductivity type and multiple second sub-parts 186b having a second conductivity type, formed in the second well region 182. The inner ring 166 is surrounded by the outer ring 186. The inner ring 166 is formed in the first well region 162, and the outer ring 186 is formed in the second well region 182. The first well region 162 is in direct contact with the second well region 182.

[0065] The first sub-parts 186a and the second sub-parts 186b are arranged alternately. In some embodiments, the area of ​​each first sub-part 186a is approximately equal to the area of ​​each second sub-part 186b.

[0066] When a high voltage (HV) is connected to the drain contact structure 188 and the inner contact structure 190a, and the ground potential position (GND) is connected to the outer contact structure 190c, the first breakdown path 11 passes through the first well region 162 and the outer ring 186. Furthermore, the second breakdown path 12 passes through the second interface between the first well region 162 and the second well region 182.

[0067] In some embodiments, the first breakdown voltage through the first breakdown path 11 can be adjusted by controlling the distance between the first well region 162 and the outer ring 186. In other embodiments, the first breakdown voltage through the first breakdown path 11 can be adjusted by controlling the doping concentration of the first sub-part 186a and the second sub-part 186b of the middle ring 176.

[0068] Similar to Figure 1 In the semiconductor structure 100a, the first breakdown voltage through the first breakdown path 11 is lower than the second breakdown voltage through the second breakdown path 12. Therefore, high voltage or high current can be connected to ground potential (GND) through either the first breakdown path 11 or the second breakdown path 12. Thus, the gate structure 130 of the transistor in the active region 10 is protected by the design of the inner ring 166, middle ring 176, and outer ring 186. When the semiconductor structure 100c operates under high voltage, the transistor in the active region 10 will not be damaged.

[0069] Figure 7 It is along Figure 6 A top view of the semiconductor structure 100c of line AA', according to some embodiments of the present invention. It should be noted that the active region 10 is surrounded by two rings, rather than through the rings. The active region 10 is surrounded by an inner ring 166 and an outer ring 186. The sidewall surface of the first sub-part 186a of the outer ring 186 is adjacent to and in direct contact with the sidewall surface of the second sub-part 186b of the outer ring 186.

[0070] Figure 8 This is a top view of the semiconductor structure 100c' according to some embodiments of the present invention. Figure 8The semiconductor structure 100c' includes and Figure 7 Semiconductor structures 100c similar to or identical to those of other components Figure 8 and Figure 7 The difference lies in that the area of ​​the first sub-part 186a is larger than the area of ​​each of the second sub-parts 186b. In some embodiments, the ratio of the area of ​​the first sub-part 186a to the area of ​​the second sub-part 186b is in the range of approximately 2 to approximately 1.

[0071] Figure 9 This is a cross-sectional view of semiconductor structure 100d according to some embodiments of the present invention. Additional features may be added to semiconductor structure 100d. Some features described below may be replaced or omitted in different embodiments. It should be noted that semiconductor structure 100d may include... Figure 1 The components shown in the semiconductor structure 100a are the same as or similar to those shown. For the sake of simplicity, these components will not be discussed in detail.

[0072] Figure 9 The semiconductor structure 100d includes and Figure 1 The semiconductor structure 100a is similar to or the same as the component. Figure 9 and Figure 1 The difference lies in that the high voltage (HV) is connected to the drain contact structure 188, the inner contact structure 190a, and the middle contact structure 190b, and the ground potential position (GND) is connected to the outer contact structure 190c. Furthermore, the middle ring 176 has a second conductivity type. In some embodiments, the middle ring 176 is doped with P-type. An interface (or PN interface or PN junction) exists between the first well region 162 and the middle ring 176.

[0073] The first breakdown path 11 passes through the middle ring 176 and the second well region 182. Furthermore, the second breakdown path 12 passes through the second interface between the first well region 162 and the second well region 182.

[0074] In some embodiments, the first breakdown voltage through the first breakdown path 11 can be adjusted by controlling the distance between the middle ring 176 and the second well region 182. In other embodiments, the first breakdown voltage through the first breakdown path 11 can be adjusted by controlling the doping concentration of the middle ring 176.

[0075] Similar to Figure 1In the semiconductor structure 100a, the first breakdown voltage through the first breakdown path 11 is lower than the second breakdown voltage through the second breakdown path 12. Therefore, high voltage or high current can be connected to the ground potential (GND) through either the first breakdown path 11 or the second breakdown path 12. Thus, the gate structure 130 of the transistor in the active region 10 is protected by the design of the inner ring 166, middle ring 176, and outer ring 186. When the semiconductor structure 100d operates under high voltage, the transistor in the active region 10 will not be damaged.

[0076] Figure 10 It is along Figure 9 A top view of the semiconductor structure 100d with AA' lines, according to some embodiments of the present invention. Note that the active region 10 is surrounded by an inner ring 166, a middle ring 176, and an outer ring 186. An isolation structure 108 is located between the inner ring 166 and the middle ring 176. The isolation structure 108 is located between the middle ring 176 and the outer ring 186. From the top view, the isolation structure 108 forms multiple rings. Figure 11 This is a cross-sectional view of semiconductor structure 100e according to some embodiments of the present invention. Additional features may be added to semiconductor structure 100e. Some features described below may be replaced or eliminated in different embodiments. It should be noted that semiconductor structure 100e may include features related to... Figure 1 The semiconductor structure 100a shown here contains the same or similar components, which will not be discussed in detail for the sake of simplicity. Figure 11 The semiconductor structure 100e includes and Figure 1 The semiconductor structure 100a is similar to or the same as the element. Figure 11 and Figure 1 The difference lies in that the inner ring 166 includes a plurality of first sub-parts 166a having a first conductivity type and a plurality of second sub-parts 166b having a second conductivity type, formed in the first well region 162. The first sub-parts 166a and the second sub-parts 166b are arranged alternately. In some embodiments, the area of ​​each first sub-part 166a is approximately equal to the area of ​​each second sub-part 166b. Furthermore, there is no middle ring in the semiconductor structure 100f. Figure 12 It is along Figure 11 A top view of the semiconductor structure 100e with AA' lines, according to some embodiments of the present invention. It should be noted that the active region 10 is surrounded by two rings, rather than through the rings. The active region 10 is surrounded by an inner ring 166 and an outer ring 186. The sidewall surface of the first sub-part 166a of the inner ring 166 is adjacent to and directly contacts the sidewall surface of the second sub-part 166b of the inner ring 166. Figure 13 This is a top view of the semiconductor structure 100e' according to some embodiments of the present invention. Figure 13 The semiconductor structure 100e' includes and Figure 12Semiconductor structures with similar or identical elements to 100e Figure 13 and Figure 12 The difference lies in the area of ​​the first sub-part 166a being larger than the area of ​​each of the second sub-parts 166b. In some embodiments, the ratio of the area of ​​the first sub-part 166a to the area of ​​the second sub-part 166b is in the range of about 2 to about 1. As previously described, the semiconductor structures 100a-100e' may include two or three rings to protect the semiconductor structures 100a-100e' from damage. Figure 1 and Figure 2 In the illustrated embodiment, semiconductor structure 100a includes an inner ring 166, a middle ring 176, and an outer ring 186. The first breakdown path 11 or the second breakdown path 12 is constructed by forming a PN junction or PN interface. Figure 4 and Figure 5 In the illustrated embodiment, semiconductor structure 100b includes an inner ring 166, a middle ring 176, and an outer ring 186. Figure 6 , 7 In the embodiments shown in Figure 8, semiconductor structures 100c and 100c' include an inner ring 166 and an outer ring 186. The outer ring 186 includes a plurality of first sub-parts 186a having a first conductivity type and a plurality of second sub-parts 186b having a second conductivity type, formed in a second well region 182. Figure 9 and Figure 10 In the illustrated embodiment, the semiconductor structure 100d includes an inner ring 166, a middle ring 176, and an outer ring 186. Figure 11 , 12In the embodiments shown in Figure 13, semiconductor structures 100e and 100e' include an inner ring 166 and an outer ring 186. The inner ring 166 includes a plurality of first sub-parts 166a having a first conductivity type and a plurality of second sub-parts 166b having a second conductivity type, formed in a first well region 162. The design of the guard rings 166, 176, and 186 of semiconductor structures 100a-100e' allows for breakdown of transistors away from the active region 10 between the isolation structures 108. A first breakdown path 11 or a second breakdown path 12 is constructed by forming a PN junction or PN interface. The first breakdown path 11 or the second breakdown path 12 can effectively direct high voltage or high current to a ground-selectable location (GND). Therefore, transistors in the active region can be protected from damage, and the performance of semiconductor structures 100a-100e' is improved. In summary, the semiconductor structure according to the invention includes a substrate and a drift region formed in the substrate having a first conductivity type. The semiconductor structure includes a body region formed in the substrate having a second conductivity type. The semiconductor structure includes a gate structure formed above a drift region and adjacent to a body region, and a drain region formed in the drift region, having a first conductivity type. The semiconductor structure includes a source region formed in the body region, having a first conductivity type, and a first well region adjacent to the drift region. The first well region has a first conductivity type. The semiconductor structure includes a second well region adjacent to the first well region, the second well region having a second conductivity type. The first well region directly contacts the second well region. In summary, the semiconductor structure according to the invention includes a substrate and a drift region formed in the substrate, having a first conductivity type. The semiconductor structure includes a body region formed in the substrate, having a second conductivity type different from the first conductivity type. The semiconductor structure includes a gate structure formed above the drift region and a drain region formed in the drift region, having a first conductivity type. The semiconductor structure includes a source region formed in the body region, having a first conductivity type, and an inner ring surrounding the gate structure, drain region, and source region, the inner ring having a first conductivity type. The semiconductor structure includes an outer ring surrounding the inner ring, the outer ring having a second conductivity type.

[0077] In summary, the semiconductor structure according to the present invention includes a substrate and a drift region formed in the substrate having a first conductivity type. The semiconductor structure includes a body region formed in the substrate having a second conductivity type different from the first conductivity type. The semiconductor structure includes a gate structure formed above the drift region and an inner ring surrounding the gate structure. The semiconductor structure includes an outer ring surrounding the inner ring, and the inner or outer ring has a plurality of first sub-parts having the first conductivity type and a plurality of second sub-parts having the second conductivity type.

[0078] While the invention has been described by way of examples and preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (as would be understood by those skilled in the art). Therefore, the scope of the dependent claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor structure, comprising: A substrate; A drift region is formed in the substrate and has a first conductivity type; A bulk region is formed in the substrate and has a second conductivity type different from the first conductivity type; A gate structure is formed above the drift region and adjacent to the body region; A drain region is formed in the drift region and has a first conductivity type; A source region is formed in the bulk region and has a first conductivity type; A first well region is adjacent to the drift region, wherein the first well region has a first conductivity type; as well as A second well region is adjacent to the first well region, wherein the second well region has a second conductivity type, and the first well region is in direct contact with the second well region.

2. The semiconductor structure of claim 1, further comprising: An inner ring is formed in the first well region, wherein the inner ring has a first conductivity type.

3. The semiconductor structure as described in claim 1, further comprising: An outer ring is formed in the second well region, wherein the outer ring has a second conductivity type.

4. The semiconductor structure of claim 1, further comprising: An isolation structure is located between the first well region and the second well region.

5. The semiconductor structure of claim 1, further comprising: An inner ring is located adjacent to the drain region; A middle ring road is adjacent to the inner ring road; as well as An outer ring is adjacent to the middle ring, wherein the middle ring is located between the inner ring and the outer ring.

6. The semiconductor structure of claim 5, wherein the middle ring has a second conductivity type and is formed in the first well region.

7. The semiconductor structure of claim 5, wherein the middle ring has a first conductivity type and is formed in the second well region.

8. The semiconductor structure of claim 1, further comprising: An inner ring is adjacent to the drain region, wherein the inner ring includes a plurality of first sub-parts having a first conductivity type and a plurality of second sub-parts having a second conductivity type, formed in the first well region.

9. The semiconductor structure of claim 1, further comprising: An outer ring is adjacent to the drain region, wherein the outer ring includes a plurality of first sub-parts having a first conductivity type and a plurality of second sub-parts having a second conductivity type, formed in the second well region.

10. The semiconductor structure of claim 1, further comprising: A drain contact structure is formed on the drain region; An inner ring is located adjacent to the drain region; An inner contact structure is formed on the inner ring; as well as A conductive layer is formed on the drain contact structure and the inner contact structure.

11. A semiconductor structure, comprising: A substrate; A drift region is formed in the substrate and has a first conductivity type; A bulk region is formed in the substrate and has a second conductivity type different from the first conductivity type; A gate structure is formed above the drift region; A drain region is formed in the drift region and has a first conductivity type; A source region is formed in the bulk region and has a first conductivity type; An inner ring surrounds the gate structure, the drain region, and the source region, wherein the inner ring has a first conductivity type; and An outer ring surrounds the inner ring, wherein the outer ring has a second conductivity type.

12. The semiconductor structure of claim 11, wherein the inner ring is formed in a first well region and the outer ring is formed in a second well region, wherein the first well region is in direct contact with the second well region.

13. The semiconductor structure of claim 11, further comprising: A middle ring is located between the inner ring and the outer ring, wherein the middle ring has a first conductivity type or a second conductivity type.

14. The semiconductor structure of claim 11, wherein the inner ring comprises a plurality of first sub-parts having a first conductivity type and a plurality of second sub-parts having a second conductivity type.

15. The semiconductor structure of claim 11, wherein the outer ring comprises a plurality of first sub-parts having a first conductivity type and a plurality of second sub-parts having a second conductivity type.

16. The semiconductor structure of claim 11, further comprising: A drain contact structure is formed on the drain region; An inner contact structure is formed on the inner ring; as well as A conductive layer is formed on the drain contact structure and the inner contact structure.

17. The semiconductor structure of claim 11, further comprising: An external contact structure is formed on the outer ring, wherein the external contact structure is connected to a ground potential location.

18. A semiconductor structure comprising: A drift region is formed in a substrate and has a first conductivity type; A bulk region is formed in the substrate and has a second conductivity type different from the first conductivity type; A gate structure is formed above the drift region; An inner ring surrounds the gate structure; as well as An outer ring surrounds the inner ring, wherein the inner ring or the outer ring includes a plurality of first sub-parts having a first conductivity type and a plurality of second sub-parts having a second conductivity type.

19. The semiconductor structure of claim 18, wherein the area of ​​the first sub-part is equal to or greater than the area of ​​the second sub-part.

20. The semiconductor structure of claim 18, further comprising: The inner contact structure formed on the inner ring; and An outer contact structure is formed on the outer ring, wherein the inner contact structure is electrically isolated from the outer contact structure.

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