P-channel SiC MOSFET devices and their fabrication methods

Abstract

This invention provides a P-channel SiC MOSFET device and its fabrication method. The P-channel SiC MOSFET device includes a substrate, an N-type SiC epitaxial layer, a gate, a P-Well region, a P+ region, an N-type graphene layer, a source, and a drain. The N-type SiC epitaxial layer is disposed on the substrate. The gate is disposed on the N-type SiC epitaxial layer. The P-Well region is disposed within the N-type SiC epitaxial layer and located on both sides of the gate. The P+ region is disposed within the P-Well region and located on both sides of the gate, with the P+ region located on the side of the P-Well region away from the substrate. The N-type graphene layer is disposed between the gate and the N-type SiC epitaxial layer and connects to the P+ region. The source is disposed on the N-type SiC epitaxial layer and located on one side of the gate, with the source above the P+ region. The drain is disposed on the N-type SiC epitaxial layer and located on the other side of the gate, with the drain above the P+ region. This invention can improve the hole mobility of P-channel SiC MOSFET devices, thereby matching them with N-channel SiC MOSFET devices with high electron mobility for use in SiC CMOS logic circuits.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a P-channel SiC MOSFET device and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) materials possess characteristics such as a wide bandgap, high electron mobility, and high thermal conductivity, making them widely used in high-power devices in new energy vehicles. Furthermore, due to their high thermal conductivity and radiation resistance, SiC also shows great potential in SiC complementary metal-oxide-semiconductor (CMOS) integrated circuits. In particular, integrating N-channel and P-channel SiC MOSFETs simultaneously on a single chip to construct SiC CMOS circuits allows for the implementation of complex logic functions, signal processing, or drive circuits. SiC CMOS can be monolithically integrated with the N-channel SiC MOSFETs in the power section to create a complete "system-on-a-chip," thereby improving the reliability and integration of the entire system.

[0003] Monolithic integration technologies of SiC CMOS and SiC MOSFET offer significant advantages in extreme environments, particularly in applications related to space database strategies, including: 1. High-reliability space data management and processing: used to construct core logic and analog circuits for spacecraft computers, data processors, and sensor interfaces operating in high-temperature and high-radiation environments, offering core advantages such as high-temperature stability, strong radiation resistance, and high energy efficiency; 2. High-power-density energy and power distribution systems: used to build high-efficiency, high-power-density high-voltage DC-DC converters, solar array regulators, and high-current-blocking current limiters, offering core advantages such as high power handling capacity, high switching frequency, and high voltage resistance; 3. Novel radiation-hardened storage hardware: based on SiC atomic-level defects, used to construct ultra-high-density, ultra-long-life quantum storage prototype devices, offering advantages such as atomic-level storage, data persistence, and intrinsic radiation tolerance; 4. Deep space and extreme environment exploration: used in electronic systems for probes to the surfaces of high-temperature, high-radiation planets such as Venus and Mars, as well as power management and control systems for extraterrestrial facilities such as lunar bases, offering advantages such as extreme temperature resistance and system integration potential.

[0004] Currently, N-channel SiC MOSFET devices are developing rapidly due to the urgent needs of new energy vehicles, and the electron mobility in the N-channel can reach 72.3 cm⁻¹. 2 / (V·s), while the highest hole mobility in a P-channel SiC MOSFET is approximately 30 cm⁻¹. 2 / (V·s). This electron-hole mobility mismatch in CMOS directly and significantly affects circuit performance. The switching speed of CMOS logic gates (such as rise time tr and fall time tf) depends on the charging and discharging speed of the load capacitor by the PMOS and NMOS transistors. Due to the low hole mobility, the on-state current (I) of the PMOS transistor is relatively low. on The P-channel MOSFET is much smaller than an NMOS transistor of the same size. The highest operating frequency of the overall circuit is determined by the slower PMOS; the signal waveform becomes asymmetrical, with the rising edge being slower than the falling edge, potentially causing timing issues. Therefore, improving the hole mobility of the P-channel MOSFET is of great significance. Summary of the Invention

[0005] In view of this, the present invention provides a P-channel SiC MOSFET device and its fabrication method, which can effectively improve the hole mobility of the P-channel SiC MOSFET device, thereby matching the high electron mobility of the N-channel SiC MOSFET device for use in SiC CMOS logic circuits.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a P-channel SiC MOSFET device, comprising: Substrate; An N-type SiC epitaxial layer is disposed on the substrate; The gate is disposed on the N-type SiC epitaxial layer; The P-Well region is disposed within the N-type SiC epitaxial layer and located on both sides of the gate. The P+ region is disposed within the P-Well and located on both sides of the gate, with the P+ region located on the side of the P-Well region away from the substrate; An N-type graphene layer is disposed between the gate and the N-type SiC epitaxial layer, and is connected to the P+ region; A source electrode is disposed on the N-type SiC epitaxial layer and located on one side of the gate electrode, the source electrode being located above the P+ region; and, The drain is disposed on the N-type SiC epitaxial layer and located on the other side of the gate, with the drain located above the P+ region.

[0007] Preferably, the substrate comprises a 4H-SiC substrate; and / or, The side of the N-type SiC epitaxial layer away from the substrate is the C-plane; and / or... The thickness of the N-type SiC epitaxial layer is 5 μm to 20 μm; and / or, The room-temperature carrier concentration of the N-type SiC epitaxial layer is 5E15 cm⁻¹.-3 ~5E17 cm -3 .

[0008] Preferably, the thickness of the P-well region is 0.5 μm to 2 μm; and / or, The doping concentration of the P-well region is 5E16 cm⁻¹. -3 ~5E17 cm -3 ; and / or, The thickness of the P+ region is 0.1 μm to 0.5 μm; and / or, The doping concentration of the P+ region is 1E18 cm⁻¹ -3 ~1E21 cm -3 .

[0009] Preferably, the thickness of the N-type graphene layer is 0.5 nm to 10 nm.

[0010] Preferably, it further includes a gate oxide layer disposed between the gate and the N-type graphene layer.

[0011] Preferably, the device further includes a dielectric layer disposed on the gate.

[0012] Preferably, an opening is provided on the dielectric layer, and a gate metal connected to the gate is disposed in the opening.

[0013] Preferably, it further includes: A source ohmic contact layer, wherein the source ohmic contact layer is disposed between the source electrode and the N-type SiC epitaxial layer; and / or, A drain ohmic contact layer is disposed between the drain and the N-type SiC epitaxial layer.

[0014] Secondly, the present invention also provides a method for fabricating the aforementioned P-channel SiC MOSFET device, comprising the following steps: S1. An N-type SiC epitaxial layer is formed on the substrate; S2. Ion implantation is performed on the N-type SiC epitaxial layer to form a P-well region; S3. Ion implantation is performed on the P-well region to form a P+ region; S4. At least an N-type graphene layer, a gate, a source, and a drain are formed on the N-type SiC epitaxial layer to obtain a P-channel SiC MOSFET device.

[0015] Preferably, the P-channel SiC MOSFET device further includes a gate oxide layer, a dielectric layer, a gate metal, a source ohmic contact layer, and a drain ohmic contact layer; step S4 includes: S41. An N-type graphene layer is formed on the N-type SiC epitaxial layer; S42. A gate oxide layer is formed on the N-type graphene layer; S43. A gate electrode is formed on the gate oxide layer; S44. A dielectric layer is formed on the gate; S45. A source ohmic contact layer and a drain ohmic contact layer are formed on the P+ region, respectively. S46. Etch openings in the dielectric layer; S47. A source and a drain are formed on the source ohmic contact layer and the drain ohmic contact layer, respectively, and a gate metal is formed in the opening; thus, a P-channel SiC MOSFET device is obtained.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: In this invention, an N-type graphene layer is used as a substitute for SiC as the channel, which can effectively improve the hole mobility of the P-channel SiC MOSFET device, reduce the channel resistance, thereby reducing the power consumption of the device, and can be matched with the high electron mobility of the N-channel SiC MOSFET device for use in SiC CMOS logic circuits. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of an embodiment of the P-channel SiC MOSFET device provided by the present invention; Figure 2 This is a schematic flowchart of an embodiment of the fabrication method of the P-channel SiC MOSFET device provided by the present invention.

[0018] Explanation of reference numerals in the attached figures: 1. Substrate; 2. N-type SiC epitaxial layer; 3. P-Well region; 4. P+ region; 5. N-type graphene layer; 6. Gate oxide layer; 7. Gate; 8. Dielectric layer; 9. Source ohmic contact layer; 10. Drain ohmic contact layer; 11. Source; 12. Drain; 13. Gate metal. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to specific embodiments, so that those skilled in the art can more clearly understand the present invention.

[0020] In a first aspect, the present invention provides a P-channel SiC MOSFET device, see [link to relevant documentation]. Figure 1A P-channel SiC MOSFET device includes a substrate 1, an N-type SiC epitaxial layer 2, a gate 7, a P-Well region 3, a P+ region 4, an N-type graphene layer 5, a source 11, and a drain 12. The N-type SiC epitaxial layer 2 is disposed on the substrate 1. The gate 7 is disposed on the N-type SiC epitaxial layer 2. The P-Well region 3 is disposed within the N-type SiC epitaxial layer 2 and located on both sides of the gate 7. The P+ region 4 is disposed within the P-Well and located on both sides of the gate 7. The P+ region 4 is located on the side of the P-Well region 3 away from the substrate 1; the N-type graphene layer 5 is disposed between the gate 7 and the N-type SiC epitaxial layer 2, and is connected to the P+ region 4; the source 11 is disposed on the N-type SiC epitaxial layer 2, and is located on one side of the gate 7, and the source 11 is located above the P+ region 4; the drain 12 is disposed on the N-type SiC epitaxial layer 2, and is located on the other side of the gate 7, and the drain 12 is located above the P+ region 4.

[0021] In this invention, N-type graphene layer 5 is used as a substitute for SiC as the channel, which can effectively improve the hole mobility of P-channel SiC MOSFET devices, reduce the channel resistance, thereby reducing the power consumption of the devices, and can match the high electron mobility of N-channel SiC MOSFET devices for use in SiC CMOS logic circuits.

[0022] It should be noted that graphene is used with ultra-high hole mobility (up to 10 in high-quality graphene). 4 ~10 5 cm 2 / V·s) Substitute SiC as the channel can achieve orders of magnitude R on Reduced. During forward conduction, the high carrier mobility of graphene can effectively improve the hole mobility of P-channel SiC MOSFET devices, reducing channel resistance and thus power consumption. From a working principle perspective, during forward conduction, V... GS <V th N-type graphene undergoes inversion with the N-SiC surface layer, allowing inverted holes to enter the graphene layer and form rapidly transportable hole channels. Applying V... DSAt voltages greater than 0 V, holes in the P+ region of the source rapidly flow to the graphene and then from the graphene to the P+ region of the drain. This involves the following issues related to hole transport at the heterogeneous interface: 1. Holes flow from the P+ SiC source to the inverted P-type graphene layer. The work function of P+ SiC has a large adjustable range (4.0 eV~6.0 eV), while the work function of the inverted P-type graphene is between 4.5 eV and 4.9 eV. By adjusting the work function of P+ SiC to match that of the inverted P-type graphene, near-ohmic contact functionality is achieved; 2. Due to the matching of their work functions, holes also flow from the inverted P-type graphene to P+ SiC, similarly forming a near-ohmic contact. At reverse breakdown voltage, the gate voltage V... GS =0 V,V DS When a high voltage is applied, as the previous analysis shows, there is a large potential barrier between N-type graphene and P+ SiC, which can effectively suppress leakage current and achieve turn-off.

[0023] Furthermore, the high hole mobility directly translates into an extremely short channel transit time. Combined with graphene's excellent saturation velocity, this enables devices to achieve switching speeds with GHz potential. High-speed switching can significantly reduce voltage-current overlap time, thereby significantly reducing energy loss per switch (E0). on E off This enables P-channel SiC MOSFET devices to possess excellent high-frequency switching characteristics. Lower Ri on Graphene, with its excellent thermal conductivity (approximately 3000~5000 W / mK in-plane thermal conductivity), can fundamentally reduce on-state heat sources. The channel itself serves as an efficient lateral heat diffusion path, rapidly dissipating hotspot heat and improving the overall thermal reliability of the device. Furthermore, the decrease in carrier mobility with increasing temperature in graphene is typically less pronounced than in SiC, which helps the device maintain superior performance at high temperatures. This enables P-channel SiC MOSFET devices to exhibit excellent thermal management and high-temperature stability. Combining the wide bandgap characteristics of SiC with the thermal stability of graphene provides a crucial P-type solution for realizing high-performance all-SiC CMOS and constructing high-speed, high-temperature, radiation-resistant all-SiC complementary logic circuits and power integration modules, thereby fostering new applications and improving system performance.

[0024] It can be understood that the P-Well region 3 is located close to the upper surface of the N-type SiC epitaxial layer 2, the P+ region 4 is formed in the P-body region, and the upper surface of the P+ region 4 coincides with the upper surface of the N-type SiC epitaxial layer 2; the downward projection of the source 11 at least partially covers the P+ region 4, and the downward projection of the drain 12 at least partially covers the P+ region 4.

[0025] In some embodiments, the substrate 1 comprises a 4H-SiC substrate. It should be noted that the substrate 1 may also be a Si substrate, a GaN substrate, a diamond substrate, or a Ga2O3 substrate.

[0026] In some embodiments, the side of the N-type SiC epitaxial layer 2 that is away from the substrate 1 is the C-plane.

[0027] In some embodiments, the thickness of the N-type SiC epitaxial layer 2 is 5 μm to 20 μm.

[0028] In some embodiments, the room-temperature carrier concentration of the N-type SiC epitaxial layer 2 is 5E15 cm⁻¹. -3 ~5E17 cm -3 .

[0029] In some embodiments, the thickness of the P-Well region 3 is 0.5 μm to 2 μm.

[0030] In some embodiments, the doping concentration of the P-Well region 3 is 5E16 cm⁻¹. -3 ~5E17 cm -3 .

[0031] In some embodiments, the thickness of the P+ region 4 is 0.1 μm to 0.5 μm.

[0032] In some embodiments, the doping concentration of the P+ region 4 is 1E18 cm⁻¹. -3 ~1E21 cm -3 .

[0033] In some embodiments, the thickness of the N-type graphene layer 5 is 0.5 nm to 10 nm.

[0034] In some embodiments, a gate oxide layer 6 is further included, which is disposed between the gate 7 and the N-type graphene layer 5.

[0035] The gate oxide layer 6 is made of a material with a high dielectric constant. In some embodiments, the material of the gate oxide layer 6 includes at least one of halide, aluminum oxide, and titanium oxide.

[0036] In some embodiments, the thickness of the gate oxide layer 6 is 10 nm to 100 nm.

[0037] In some embodiments, a dielectric layer 8 is further included, which is disposed on the gate 7. It is understood that the dielectric layer covers the gate 7 to isolate electrodes such as the source 11 and drain 12.

[0038] In some embodiments, the material of the dielectric layer 8 includes at least one of silicon oxide and silicon nitride.

[0039] In some embodiments, the thickness of the dielectric layer 8 is 500 nm to 2000 nm.

[0040] In some embodiments, an opening is provided on the dielectric layer 8, and a gate metal 13 connected to the gate 7 is disposed within the opening. It is understood that the opening penetrates the dielectric layer 8 and connects to the gate 7, and the gate metal 13 is used to lead out the gate 7 covered by the dielectric layer 8.

[0041] In some embodiments, the material of the gate metal 13 includes at least one of AlCu alloy and Au.

[0042] The gate 7 is a metal gate, and in some embodiments, the material of the gate 7 includes Au.

[0043] In some embodiments, a source ohmic contact layer 9 is further included, which is disposed between the source 11 and the N-type SiC epitaxial layer 2.

[0044] In some embodiments, the material of the source ohmic contact layer 9 includes a TiNiAl alloy.

[0045] In some embodiments, the material of the source electrode 11 includes Al.

[0046] In some embodiments, a drain ohmic contact layer 10 is further included, which is disposed between the drain 12 and the N-type SiC epitaxial layer 2.

[0047] In some embodiments, the material of the drain ohmic contact layer 10 includes a TiNiAl alloy.

[0048] In some embodiments, the material of the drain electrode 12 includes Al.

[0049] Secondly, the present invention also provides a method for fabricating the aforementioned P-channel SiC MOSFET device, comprising the following steps: S1. An N-type SiC epitaxial layer 2 is formed on substrate 1; S2. Ion implantation is performed on the N-type SiC epitaxial layer 2 to form a P-Well region 3; S3. Ion implantation is performed on the P-Well region 3 to form the P+ region 4; S4. At least an N-type graphene layer 5, a gate 7, a source 11, and a drain 12 are formed on the N-type SiC epitaxial layer 2 to obtain a P-channel SiC MOSFET device.

[0050] It should be noted that Al atoms can be injected into P-Well region 3 and P+ region 4.

[0051] In some embodiments, the side of the N-type SiC epitaxial layer 2 away from the substrate 1 is the C-plane. The SiC epitaxial layer with one C-plane can be formed by epitaxy or by bond-bonding lift-off film transfer. It should be noted that the epitaxy method refers to direct epitaxy of the SiC substrate C-plane; the bond-bonding lift-off film transfer method refers to bond-bonding lift-off film transfer of the SiC substrate Si-plane. Specifically, this can involve H ion implantation into the donor SiC substrate Si-plane, followed by bonding with the target SiC substrate Si-plane, and then transferring the SiC thin layer above the implanted layer onto the target SiC substrate via annealing lift-off.

[0052] In some embodiments, the N-type graphene layer 5 is formed by in-situ growth. It should be noted that the in-situ growth method of the N-type graphene layer 5 can specifically involve first etching the surface damage of a SiC epitaxial wafer in a hydrogen atmosphere at 1500 °C, then annealing it under ultra-high vacuum at 600 °C to remove residual gas, and finally annealing it in a nitrogen atmosphere at 1200~1400 °C to prepare the N-type graphene layer 5.

[0053] In some embodiments, the P-channel SiC MOSFET device further includes a gate oxide layer 6, a dielectric layer 8, a gate metal 13, a source ohmic contact layer 9, and a drain ohmic contact layer 10; step S4 includes: S41. An N-type graphene layer 5 is formed on the N-type SiC epitaxial layer 2; S42. A gate oxide layer 6 is formed on the N-type graphene layer 5; S43. A gate electrode 7 is formed on the gate oxide layer 6; S44. A dielectric layer 8 is formed on the gate 7; S45. A source ohmic contact layer 9 and a drain ohmic contact layer 10 are formed on the P+ region 4, respectively. S46. Etch openings in the dielectric layer 8; S47. A source 11 and a drain 12 are formed on the source ohmic contact layer 9 and the drain ohmic contact layer 10, respectively, and a gate metal 13 is formed in the opening; thus, a P-channel SiC MOSFET device is obtained.

[0054] In some embodiments, step S45 includes: depositing ohmic contact metal of source 11 and ohmic contact metal of drain 12 at corresponding positions in the P+ region 4, and annealing them by RTA to form source ohmic contact layer 9 and drain ohmic contact layer 10, respectively; wherein the annealing temperature is 750 ℃~1000 ℃ and the annealing time is 0.5 min~5 min.

[0055] In one embodiment, please refer to Figure 2The fabrication method of the P-channel SiC MOSFET device includes the following steps: Step 1: Epitaxially grow an N-type SiC epitaxial layer 2 on a 4H-SiC substrate 1; Step 2: Form a P-Well region 3 in the N-type SiC epitaxial layer 2 by ion implantation; Step 3: P+ region 4 is formed in P-Well region 3 by ion implantation, followed by high-temperature activation and surface protection with carbon film; Step 4: An N-type graphene layer 5 is formed on the surface of the N-type SiC epitaxial layer 2 by in-situ growth; Step 5: Deposit a gate oxide layer 6 with a high dielectric constant on the surface of the N-type graphene layer 5; Step 6: Form a metal gate 7 on the gate oxide layer 6; Step 7: Deposit dielectric layer 8 on the surface of gate 7 and gate oxide layer 6, and form dielectric layer 8 on gate 7 by mask etching, while etching to the surface of N-type SiC epitaxial layer 2 to form source region and drain region respectively. Step 8: Deposit ohmic contact metal of source 11 and ohmic contact metal of drain 12 in the source region and drain region respectively, anneal, and form source ohmic contact layer 9 and drain ohmic contact layer 10. Clean the ohmic contact metal in the remaining regions. Step 9: Etch an opening in the dielectric layer 8 above the gate 7 to form the gate metal contact region; Step 10: Deposit the corresponding electrode metals on the surfaces of the source ohmic contact layer 9, the drain ohmic contact layer 10, and the gate metal contact area, and etch them to isolate them, forming the source 11, the drain 12, and the gate metal 13; thus obtaining a P-channel SiC MOSFET device.

[0056] Unless otherwise specified, all raw materials used in this invention are existing substances that can be purchased directly from the market.

[0057] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A P-channel SiC MOSFET device, characterized in that, include: Substrate; An N-type SiC epitaxial layer is disposed on the substrate; The gate is disposed on the N-type SiC epitaxial layer; The P-Well region is disposed within the N-type SiC epitaxial layer and located on both sides of the gate. The P+ region is disposed within the P-Well and located on both sides of the gate, with the P+ region located on the side of the P-Well region away from the substrate; An N-type graphene layer is disposed between the gate and the N-type SiC epitaxial layer, and is connected to the P+ region; A source electrode is disposed on the N-type SiC epitaxial layer and located on one side of the gate electrode, the source electrode being located above the P+ region; and, The drain is disposed on the N-type SiC epitaxial layer and located on the other side of the gate, with the drain located above the P+ region.

2. The P-channel SiC MOSFET device according to claim 1, characterized in that, The substrate includes a 4H-SiC substrate; and / or, The side of the N-type SiC epitaxial layer away from the substrate is the C-plane; and / or... The thickness of the N-type SiC epitaxial layer is 5 μm to 20 μm; and / or, The room-temperature carrier concentration of the N-type SiC epitaxial layer is 5E15 cm⁻¹. -3 ~5E17 cm -3 .

3. The P-channel SiC MOSFET device according to claim 1, characterized in that, The thickness of the P-well region is 0.5 μm to 2 μm; and / or, The doping concentration of the P-well region is 5E16 cm⁻¹. -3 ~5E17 cm -3 ; and / or, The thickness of the P+ region is 0.1 μm to 0.5 μm; and / or, The doping concentration of the P+ region is 1E18 cm⁻¹ -3 ~1E21 cm -3 .

4. The P-channel SiC MOSFET device according to claim 1, characterized in that, The thickness of the N-type graphene layer is 0.5 nm to 10 nm.

5. The P-channel SiC MOSFET device according to claim 1, characterized in that, It also includes a gate oxide layer disposed between the gate and the N-type graphene layer.

6. The P-channel SiC MOSFET device according to claim 1, characterized in that, It also includes a dielectric layer disposed on the gate.

7. The P-channel SiC MOSFET device according to claim 6, characterized in that, An opening is provided on the dielectric layer, and a gate metal connected to the gate is disposed in the opening.

8. The P-channel SiC MOSFET device according to claim 1, characterized in that, Also includes: A source ohmic contact layer is disposed between the source electrode and the N-type SiC epitaxial layer; And / or, A drain ohmic contact layer is disposed between the drain and the N-type SiC epitaxial layer.

9. The method for fabricating a P-channel SiC MOSFET device according to any one of claims 1 to 8, characterized in that, Includes the following steps: S1. An N-type SiC epitaxial layer is formed on the substrate; S2. Ion implantation is performed on the N-type SiC epitaxial layer to form a P-well region; S3. Ion implantation is performed on the P-well region to form a P+ region; S4. At least an N-type graphene layer, a gate, a source, and a drain are formed on the N-type SiC epitaxial layer to obtain a P-channel SiC MOSFET device.

10. The method for fabricating a P-channel SiC MOSFET device according to claim 9, characterized in that, The P-channel SiC MOSFET device further includes a gate oxide layer, a dielectric layer, a gate metal, a source ohmic contact layer, and a drain ohmic contact layer; step S4 includes: S41. An N-type graphene layer is formed on the N-type SiC epitaxial layer; S42. A gate oxide layer is formed on the N-type graphene layer; S43. A gate electrode is formed on the gate oxide layer; S44. A dielectric layer is formed on the gate; S45. A source ohmic contact layer and a drain ohmic contact layer are formed on the P+ region, respectively. S46. Etch openings in the dielectric layer; S47. A source and a drain are formed on the source ohmic contact layer and the drain ohmic contact layer, respectively, and a gate contact is formed in the opening; thus, a P-channel SiC MOSFET device is obtained.

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