Semiconductor device

Abstract

A semiconductor device includes an n-type semiconductor substrate; a seal ring wiring formed in a ring shape so as to surround a first region and a second region of the semiconductor substrate in a plan view; and a p-type impurity region formed in the semiconductor substrate. The impurity region is provided between the first region and the second region so as to extend to a position overlapping the seal ring wiring in the plan view. A ground potential is supplied to the impurity region.

Description

Cross-references to related applications

[0001] The disclosure of Japanese Patent Application No. 2024-209443, filed on December 2, 2024, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0002] This invention relates to a semiconductor device. Background Technology

[0003] The disclosed technologies are listed below.

[0004] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2015-88617

[0005] A semiconductor device has been developed in which two output power metal-oxide-semiconductor field-effect transistors (MOSFETs) and control circuitry for controlling the operation of each of the two output power MOSFETs are mounted together. For example, Patent Document 1 discloses an intelligent power device (IPD) as such a semiconductor device.

[0006] The semiconductor device of Patent Document 1 includes a first region in which one of the output power MOSFETs is formed, a second region in which another output power MOSFET is formed, and a third region in which a MOSFET for control circuitry is formed.

[0007] Furthermore, Patent Document 1 discloses the following problem: Electrical noise with a high potential higher than the drain potential can be applied from outside the semiconductor device to the source electrode of the output terminal of the power MOSFET constituting the first region. In this case, parasitic current flows from the p-type body region of the first region to the n-type semiconductor substrate. At this time, the leakage current, as a component of the parasitic current, flows from the p-type body region of the first region to the p-type body region of the second region. In addition, the leakage current also flows from the p-type body region of the first region to the p-type well region of the third region.

[0008] This type of leakage current causes failures in the power MOSFETs in the second region and the MOSFETs in the third region. Summary of the Invention

[0009] In Patent Document 1, a p-type impurity region is formed in the semiconductor substrate to absorb the leakage current as described above. The p-type impurity region is disposed between the first and second regions, between the first and third regions, and between the second and third regions. By connecting the battery potential (drain potential) to the p-type impurity region, the leakage current is absorbed into the p-type impurity region. Therefore, faults in the power MOSFET in the second region and the MOSFET in the third region can be suppressed.

[0010] Recent IPD (Integrated Device Development) advancements have facilitated the miniaturization of semiconductor devices, leading to more stringent requirements for suppressing leakage current. To further suppress leakage current and improve the reliability of semiconductor devices, it is possible to consider, for example, setting p-type impurity regions around each of the first, second, and third regions in a planar view. However, this increases the planar area used to set the p-type impurity regions and the planar dimensions of the semiconductor device, making miniaturization more difficult. Therefore, a technique is needed that can suppress the increase in the planar dimensions of semiconductor devices, suppress leakage current, and improve the reliability of semiconductor devices.

[0011] Other issues and novel features will become apparent from the description in this specification and the accompanying drawings.

[0012] In the embodiments disclosed in this application, a summary of representative embodiments will be briefly described below.

[0013] A semiconductor device according to one embodiment includes a semiconductor substrate of a first conductivity type; a sealing ring wiring formed in a ring shape to surround a first region and a second region of the semiconductor substrate in a plan view; and an impurity region formed in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type. The impurity region is disposed between the first and second regions to extend to a location overlapping the sealing ring wiring in a plan view. A ground potential is supplied to the impurity region.

[0014] A semiconductor device according to one embodiment includes a semiconductor substrate of a first conductivity type; a sealing ring wiring formed in a ring shape to surround a first region and a second region of the semiconductor substrate in a plan view; and an impurity region formed in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type. The impurity region is disposed between the first region and the second region and between the sealing ring wiring and a portion of the second region. A ground potential is supplied to the impurity region.

[0015] According to one embodiment, the increase in the planar size of a semiconductor device can be suppressed, and the reliability of the semiconductor device can be improved. Attached Figure Description

[0016] Figure 1 This is a plan view of a semiconductor device according to a first embodiment.

[0017] Figure 2 This is a plan view of a semiconductor device according to a first embodiment.

[0018] Figure 3 This is a cross-sectional view of a semiconductor device according to the first embodiment.

[0019] Figure 4 This is a cross-sectional view of a semiconductor device according to the first embodiment.

[0020] Figure 5 This is a cross-sectional view of a semiconductor device according to the first embodiment.

[0021] Figure 6 This is a cross-sectional view of the parasitic current and leakage current occurring in the first embodiment.

[0022] Figure 7 This is a plan view of a semiconductor device according to the first variant.

[0023] Figure 8 This is a plan view of a semiconductor device according to the second variant.

[0024] Figure 9 This is a plan view of a semiconductor device based on the third variant.

[0025] Figure 10 This is a plan view of a semiconductor device according to the fourth variant.

[0026] Figure 11 This is a plan view of a semiconductor device based on the fifth variant.

[0027] Figure 12 This is a cross-sectional view of a semiconductor device according to the fifth variant.

[0028] Figure 13 This is a plan view of a semiconductor device according to a second embodiment.

[0029] Figure 14 This is a plan view of a semiconductor device illustrated in the inspection example. Detailed Implementation

[0030] In the following description, embodiments will be described in detail with reference to the accompanying drawings. In all the drawings used for the illustrated embodiments, components with the same function are indicated by the same reference numerals, and repeated descriptions thereof will be omitted. Furthermore, in the following embodiments, unless specifically necessary, descriptions of the same or similar components will generally not be repeated.

[0031] The X, Y, and Z directions described in this application intersect and are orthogonal to each other. In this application, the Z direction will be described as the vertical direction, depth direction, or thickness direction of the structure. Furthermore, expressions such as "plan view" or "planer view" used in this application mean that the plane formed by the X and Y directions is defined as a "plane," and that the "plane" is viewed from the Z direction.

[0032] (First embodiment)

[0033] <Structure of Semiconductor Devices>

[0034] Reference Figures 1 to 5 The structure of the semiconductor device (semiconductor chip) 100 according to the first embodiment will be described. Figure 1 This is a plan view of the semiconductor device 100 shown in the figure. Figure 2 It is a diagram. Figure 1 A plan view of the wiring layer above the layer. Figure 3 It is along Figure 1 and Figure 2 The cross-sectional view shown is taken by line AA. Figure 4 It is along Figure 1 and Figure 2 The cross-sectional view shown is taken by line BB. Figure 5 It is along Figure 1 and Figure 2 The cross-sectional view shown is taken by line CC.

[0035] like Figure 1 As shown, the semiconductor device 100 includes region 1A, region 2A adjacent to region 1A, and region 3A adjacent to both region 1A and region 2A. Furthermore, as... Figure 3 , Figure 4 and Figure 5 As shown, the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. (As...) Figure 3 and Figure 4 As shown, multiple n-type power MOSFETs 1Q are formed in the region (first region) corresponding to region 1A of the semiconductor substrate SUB. Figure 3 As shown, a plurality of n-type power MOSFETs 2Q are formed in a region (second region) corresponding to region 2A of the semiconductor substrate SUB. Furthermore, the semiconductor device 100 includes control circuitry for controlling the operation of each of the plurality of power MOSFETs 1Q and the plurality of power MOSFETs 2Q. Figure 4 As shown, multiple p-type MOSFETs 3Q and multiple n-type MOSFETs 3Q constituting the control circuit are formed in the region (third region) of the semiconductor substrate SUB corresponding to region 3A.

[0036] like Figure 3 , Figure 4 and Figure 5 As shown, the semiconductor device 100 includes multiple wirings M1 formed on the semiconductor substrate SUB, multiple wirings M2 formed on the multiple wirings M1, and multiple wirings M3 formed on the multiple wirings M2.

[0037] Multiple wiring M1 includes absorption wiring AW1 and sealing ring wiring SL1. Figure 1 The diagram illustrates the absorption wiring AW1 and the sealing ring wiring SL1. The sealing ring wiring SL1 is formed in a ring shape to surround region 1A (i.e., the first region of the semiconductor substrate SUB), region 2A (i.e., the second region of the semiconductor substrate SUB), and region 3A (i.e., the third region of the semiconductor substrate SUB) in a plan view. Although not shown here, the sealing ring wiring SL2 and the sealing ring wiring SL3 electrically connected to the sealing ring wiring SL1 are also formed in a ring shape to surround regions 1A, 2A, and 3A in a plan view.

[0038] An absorption region PA, serving as a p-type impurity region, is formed in the semiconductor substrate SUB. The absorption region PA is disposed between regions 1A and 2A, between regions 1A and 3A, and between regions 2A and 3A. Furthermore, the absorption region PA extends to a position overlapping with the sealing ring wiring SL1 in a plan view. In addition, in the first embodiment, the absorption region PA also overlaps with portions of the sealing ring wiring SL1 surrounding regions 1A and 2A in a plan view.

[0039] Although not illustrated here, the absorption area PA extends to the location where it overlaps with the sealing ring wiring SL2 and the sealing ring wiring SL3 located above the sealing ring wiring SL1. Furthermore, in the plan view, the absorption area PA also partially overlaps with the areas surrounding areas 1A and 2A of the sealing ring wiring SL2 and sealing ring wiring SL3.

[0040] Absorption wiring AW1 is formed on and electrically connected to absorption area PA. Absorption wiring AW1 is disposed between areas 1A and 2A, between areas 1A and 3A, and between areas 2A and 3A, so as to cover a portion of absorption area PA in a plan view. Absorption wiring AW1 is separate from sealing ring wiring SL1.

[0041] Ground potential is supplied to the absorption region PA via absorption wiring AW1. As described below, sealing ring wiring SL1 is electrically connected to the drain electrode DE via semiconductor substrate SUB. Therefore, drain potential is supplied to sealing ring wiring SL1. Absorption region PA and absorption wiring AW1 are electrically insulated from sealing ring wiring SL1.

[0042] Figure 2 The diagram illustrates the sealing ring wiring SL3, source electrode SE1, source electrode SE2, multiple pads PAD, and multiple absorption wirings AW3 within multiple wirings M3. Source electrode SE1 is electrically connected to the source region NS and body region PB of power MOSFET 1Q. Source electrode SE2 is electrically connected to the source region NS and body region PB of power MOSFET 2Q. Multiple pads PAD are electrically connected to MOSFET 3Q and MOSFET 3Q.

[0043] By connecting external connection components to the upper surfaces of the sealing ring wiring SL3, source electrode SE1, source electrode SE2, multiple pads PAD, and multiple absorber wiring AW3, the semiconductor device 100 is electrically connected to a lead frame, wiring substrate, or another semiconductor chip. The external connection components are, for example, wires made of aluminum, gold, or copper, or clamps made of copper plates.

[0044] Absorption wiring AW3 is electrically connected to absorption region PA via absorption wiring AW2 and absorption wiring AW1. By connecting the terminal for ground potential located outside the semiconductor device 100 and absorption wiring AW3 to an external connection member, ground potential is supplied to absorption region PA.

[0045] In the following text, reference will be made to Figures 3 to 5 Describe the cross-sectional structure of semiconductor device 100.

[0046] like Figures 3 to 5 As shown, the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB is made of n-type silicon. The semiconductor substrate SUB has an n-type drift region NV and an n-type drain region ND. The impurity concentration of the drain region ND is higher than the impurity concentration of the drift region NV.

[0047] The semiconductor substrate SUB can be a stack of an n-type silicon substrate and an n-type silicon layer grown on the silicon substrate, with n-type impurities introduced by epitaxial growth. In this case, the silicon layer constitutes the drift region NV, and the silicon substrate constitutes the drain region ND. The resistivity of the silicon substrate is 1.0 Ω·cm or higher and 2.5 Ω·cm or lower, and the resistivity of the silicon layer is 0.158 Ω·cm or higher and 0.160 Ω·cm or lower.

[0048] The drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB. The drain electrode DE is made of, for example, a single-layer metal film, such as an aluminum film, titanium film, nickel film, gold film, or silver film, or a laminated film obtained by appropriately stacking these metal films. The drain electrode DE is formed over the entire lower surface BS of the semiconductor substrate SUB. A drain potential is supplied from the drain electrode DE to the semiconductor substrate SUB (drain region ND and drift region NV).

[0049] In the following text, reference will be made to Figure 3 The cross-sectional structures of region 1A and region 2A are described. Since the cross-sectional structure of power MOSFET 2Q in region 2A is essentially the same as that of power MOSFET 1Q in region 1A, the cross-sectional structure of power MOSFET 1Q will be described representatively here.

[0050] like Figure 3As shown, a trench TR is formed in a semiconductor substrate SUB such that it reaches a predetermined depth from the upper surface TS of the semiconductor substrate SUB. A gate electrode GE1 is formed in the trench TR via a gate insulating film GI1. The gate insulating film GI1 is, for example, a silicon oxide film. The gate electrode GE1 is, for example, a polycrystalline silicon film with n-type impurities introduced.

[0051] In the semiconductor substrate SUB, a p-type body region PB is formed such that the depth of the TS from the upper surface of the semiconductor substrate SUB is shallower than the depth of the trench TR. An n-type source region NS is formed in the body region PB. The impurity concentration of the source region NS is higher than that of the drift region NV. In the body region PB, the portion adjacent to the gate electrode GE1 via the gate insulating film GI1 and located between the source region NS and the drift region NV constitutes the channel region of the power MOSFET 1Q. That is, the power MOSFET 1Q in this embodiment is a so-called vertical field-effect transistor (power semiconductor), in which current flows in the thickness direction of the semiconductor substrate SUB.

[0052] An interlayer insulating film IL0 is formed on the upper surface TS of the semiconductor substrate SUB to cover the trench TR. The interlayer insulating film IL0 is made of, for example, a silicon oxide film. Holes are formed in the interlayer insulating film IL0 to penetrate the source region NS and reach the body region PB. At the bottom of the holes, a diffusion region PR is formed in the body region PB. The diffusion region PR has a higher impurity concentration than the body region PB. The diffusion region PR is configured primarily to reduce the contact resistance with the plug PG and to prevent latch-up.

[0053] Within the hole, a plug PG is formed. The plug PG is electrically connected to the source region NS, the body region PB, and the diffusion region PR. The plug PG includes, for example, a first barrier metal film and a first conductive film formed on the first barrier metal film. The first barrier metal film is, for example, a laminate of titanium film and titanium nitride film. The first conductive film is, for example, a tungsten film.

[0054] Wiring M1 is formed on the interlayer insulating film IL0. M1 is electrically connected to the plug PG. Wiring M1 includes, for example, a second barrier metal film, a second conductive film formed on the second barrier metal film, and a third barrier metal film formed on the second conductive film. The second barrier metal film and the third barrier metal film are each, for example, a laminate of a titanium film and a titanium nitride film. The second conductive film is, for example, an aluminum alloy film with copper or silicon added.

[0055] An interlayer insulating film IL1 is formed on the interlayer insulating film IL0 to cover the wiring M1. The interlayer insulating film IL1 is made of, for example, a silicon oxide film. A cavity is formed in the interlayer insulating film IL1 to allow access to the wiring M1. A via V1 is formed in this cavity. The via V1 is electrically connected to the wiring M1. A wiring M2 is formed on the interlayer insulating film IL1. The wiring M2 is electrically connected to the via V1.

[0056] An interlayer insulating film IL2 is formed on the interlayer insulating film IL1 to cover the wiring M2. The interlayer insulating film IL2 is made of, for example, a silicon oxide film. Holes are formed in the interlayer insulating film IL2 to allow access to the wiring M2. Through-holes V2 are formed in the aforementioned holes. Through-holes V2 are electrically connected to the wiring M2. Wiring M3 is formed on the interlayer insulating film IL2. Wiring M3 is electrically connected to through-holes V2.

[0057] Through-holes V2 and V1 have structures similar to those of plug PG and include a first blocking metal film and a first conductive film. Wiring M3 and M2 have structures similar to those of wiring M1 and include a second blocking metal film, a second conductive film, and a third blocking metal film. The thickness of wiring M3 is greater than the thickness of each of wiring M2 and wiring M1.

[0058] The source potential is supplied from the source electrode SE1 (wiring M3) to the source region NS, body region PB, and diffusion region PR of power MOSFET 1Q. The source potential is supplied from the source electrode SE2 (wiring M3) to the source region NS, body region PB, and diffusion region PR of power MOSFET 2Q.

[0059] like Figure 3 and Figure 4 As shown, a field insulating film IF0 and an absorption region PA are formed in the semiconductor substrate SUB between regions 1A and 2A, between regions 1A and 3A, and between regions 2A and 3A. The field insulating film IF0 is, for example, a silicon oxide film. The absorption region PA is disposed in the portion of the semiconductor substrate SUB where the field insulating film IF0 is not formed, and is electrically connected to the absorption wiring AW1 via a plug PG.

[0060] In a first embodiment, the absorption region PA includes a p-type well region HPW, a p-type well region PW, and a p-type diffusion region PM, which constitutes a p-type impurity region of the absorption region PA. The well region HPW is formed in the semiconductor substrate SUB such that it reaches a predetermined depth from the upper surface TS of the semiconductor substrate SUB. The well region PW is formed in the well region HPW. The diffusion region PM is formed in the well region PW. The impurity concentration in the well region PW is higher than the impurity concentration in the well region HPW. The impurity concentration in the diffusion region PM is higher than the impurity concentration in the well region PW.

[0061] The well region HPW, well region PW, and diffusion region PM constituting the absorber region PA are formed by the same manufacturing process as those forming the well region HPW, well region PW, and diffusion region PM in region 3A, which will be described later. It should be noted that the p-type impurity region constituting the absorber region PA is merely an example, and the absorber region PA may be composed of other p-type impurity regions, or it may be composed of a single p-type impurity region.

[0062] In the following text, reference will be made to Figure 4 The cross-sectional structure of region 3A is described. Although semiconductor device 100 includes control circuitry for controlling the operation of each of the plurality of power MOSFETs 1Q and 2Q, semiconductor device 100 may also include other circuitry, such as charge pump circuitry, temperature sensing circuitry, or current sensing circuitry. The plurality of p-type MOSFETs 3Q and n-type MOSFETs 3Q formed in region 3A serve not only as components of the control circuitry but also as components of other circuitry.

[0063] like Figure 4 As shown, a p-type well region HPW is formed in a semiconductor substrate SUB. Within the well region HPW, an n-type well region NW and a p-type well region PW are formed.

[0064] On the well region NW, a gate electrode GE2 is formed via a gate insulating film GI2. The gate insulating film GI2 is, for example, a silicon oxide film. The gate electrode GE2 is, for example, a polysilicon film with p-type impurities introduced. Paired p-type diffusion regions PM are formed within the well region NW. These paired diffusion regions PM constitute the source or drain region of the MOSFET 3Q. The portion of the well region NW located below the gate electrode GE2 and between the paired diffusion regions PM constitutes the channel region of the MOSFET 3Q. That is, the MOSFET 3Q in this embodiment is a so-called lateral field-effect transistor, in which current flows along the upper surface TS of the semiconductor substrate SUB. The impurity concentration in the well region NW is higher than the impurity concentration in the drift region NV.

[0065] On the well region PW, a gate electrode GE3 is formed via a gate insulating film GI3. The gate insulating film GI3 is, for example, a silicon oxide film. The gate electrode GE3 is, for example, a polycrystalline silicon film with n-type impurities introduced. Paired n-type diffusion regions NM are formed in the well region PW. These paired diffusion regions NM constitute the source or drain region of the MOSFET 4Q. The portion of the well region PW located below the gate electrode GE3 and between the paired diffusion regions NM constitutes the channel region of the MOSFET 4Q. That is, the MOSFET 4Q in this embodiment is a so-called lateral field-effect transistor, in which current flows along the upper surface TS of the semiconductor substrate SUB. The impurity concentration in the diffusion region NM is higher than the impurity concentration in the drift region NV.

[0066] Gate electrode GE2, diffusion region PM, gate electrode GE3, and diffusion region NM are electrically connected to wiring M1 via plug PG. Multiple MOSFETs 3Q and multiple MOSFETs 3Q are appropriately wired using plug PG, wiring M1, via V1, wiring M2, via V2, and wiring M3 to construct the aforementioned control circuit and other circuits.

[0067] Additionally, the connection between the control circuit and each gate electrode GE1 of the multiple power MOSFETs 1Q and the multiple power MOSFETs 2Q can be made, for example, by routing wiring M1 or wiring M2 from zone 3A to zones 1A and 2A.

[0068] In the following text, reference will be made to Figure 5 Describe the cross-sectional structure around the sealing ring wiring SL1, SL2 and SL3.

[0069] like Figure 5 As shown, an n-type diffusion region NM is formed in the semiconductor substrate SUB. A sealing ring wiring SL1 is electrically connected to the diffusion region NM via a plug PG. A sealing ring wiring SL2 is electrically connected to the sealing ring wiring SL3 via a via V2. The semiconductor substrate SUB (diffusion region NM, drift region NV, and drain region ND) is electrically connected to the drain electrode DE. Therefore, the drain potential is supplied from the drain electrode DE to the sealing ring wirings SL1, SL2, and SL3 via the semiconductor substrate SUB.

[0070] Absorption wiring AW1 is electrically connected to absorption area PA via plug PG. Absorption wiring AW2 is electrically connected to absorption wiring AW1 via through hole V1. Absorption wiring AW3 is electrically connected to absorption wiring AW2 via through hole V2. Absorption wirings AW1, AW2, and AW3 are separate from and electrically insulated from sealing ring wirings SL1, SL2, and SL3.

[0071] It should be noted that, here, the absorption area PA overlaps with each of the sealing ring wirings SL1, SL2, and SL3 in the plan view. However, the absorption area PA only needs to overlap with at least one of the sealing ring wirings SL1, SL2, and SL3 in the plan view. In the following description, the case where the absorption area PA overlaps with the sealing ring wiring SL1 in the plan view will be illustrated representatively.

[0072] <Influence of PA in the Absorption Region>

[0073] In the following text, reference will be made to Figure 6 Describe the effect obtained by setting the absorption region PA.

[0074] In some cases, as electrical noise, a high potential higher than the drain potential is applied from outside the semiconductor device 100 to the source electrode SE1, which constitutes the output terminal of the power MOSFET 1Q. In such cases, the body region PB of the power MOSFET 1Q is forward biased. Then, as... Figure 6 As shown, parasitic current I B The current flows from the body region PB of the power MOSFET 1Q to the semiconductor substrate SUB.

[0075] At this point, a parasitic PNP transistor 10 is formed, wherein the body region PB of power MOSFET 1Q serves as the emitter, the semiconductor substrate SUB serves as the base, and the body region PB of power MOSFET 2Q serves as the collector. Therefore, in the parasitic current I... B While flowing, as a parasitic current I B Leakage current I of the component C The current flows from the body region PB of power MOSFET 1Q to the body region PB of power MOSFET 2Q.

[0076] Furthermore, a p-type well region HPW has been formed in the semiconductor substrate SUB in region 3A. Therefore, another parasitic PNP transistor 10 is also formed, where the body region PB of the power MOSFET 1Q serves as the emitter, the semiconductor substrate SUB serves as the base, and the well region HPW in region 3A serves as the collector. Therefore, the leakage current I... C It also flows from the body region PB of the power MOSFET 1Q to the well region HPW of region 3A.

[0077] In some cases, a high potential is also applied as electrical noise to the source electrode SE2, which constitutes the output of the power MOSFET 2Q. In such cases, the leakage current I... C The leakage current I flows from the body region PB of power MOSFET 2Q to the body region PB of power MOSFET 1Q. C The current flows from the body region PB of the power MOSFET 2Q to the well region HPW of region 3A.

[0078] This type of leakage current I C This can be a factor that causes failures in power MOSFET 3Q, power MOSFET 3Q, MOSFET 3Q and MOSFET 3Q.

[0079] The absorption region PA absorbs this type of leakage current I. C The absorption region PA is configured between regions 1A and 2A, between regions 1A and 3A, and between regions 2A and 3A. Furthermore, a ground potential is connected to the absorption region PA. Then, in the leakage current I... C Before reaching the body region PB or well region HPW in region 3A, the leakage current I C The power MOSFET 3Q is absorbed by the PA region. Therefore, faults in the power MOSFET 3Q, MOSFET 3Q, and MOSFET 3Q can be suppressed.

[0080] <Key Features of the First Embodiment>

[0081] The main features of the first embodiment will now be described. Before that, an inspection example will be described. Figure 14The illustration shows a semiconductor device of an inspection example inspected by the inventors, and illustrates the planar layout of the absorption region PA in the inspection example.

[0082] By comparison Figure 1 and Figure 14 It is understood that in the first embodiment and the inspection example, the absorption region PA surrounds regions 1A and 2A in the plan view. However, in the inspection example, the absorption wiring AW1 also surrounds regions 1A and 2A in the plan view, and the absorption region PA does not overlap with the sealing ring wiring SL1 in the plan view. Although not illustrated here, the absorption region PA also does not overlap with the sealing ring wiring SL2 and SL3 in the plan view.

[0083] The absorption region PA and absorption wirings AW1, AW2, and AW3 need to be electrically insulated from the sealing ring wirings SL1, SL2, and SL3. Therefore, in the inspection example, the sealing ring wirings SL1, SL2, and SL3 extend outward toward the peripheral edge of the semiconductor device. As a result, the planar dimensions of the semiconductor device increase in the inspection example.

[0084] However, in the first embodiment, as Figure 5 As shown, the plug PG for connecting the semiconductor substrate SUB and the sealing ring wiring SL1 is positioned closer to the outer ring of the sealing ring wiring SL1 than the inner ring of the sealing ring wiring SL1. Therefore, as Figure 1 and Figure 5 As shown, it is easier to extend the absorption area PA to the location where it overlaps with the sealing ring wiring SL1, SL2 and SL3 in the plan view.

[0085] Furthermore, although the absorption wiring AW1 is provided between zone 1A and zone 2A, between zone 1A and zone 3A, and between zone 2A and zone 3A, the absorption wiring AW1 is separated from the sealing ring wiring SL1 and is not provided between the sealing ring wiring SL1 and zone 1A, zone 2A, and zone 3A.

[0086] Therefore, the absorption region PA in the first embodiment suppresses the increase in the planar size of the semiconductor device 100 and suppresses the leakage current I. C And it can improve the reliability of semiconductor device 100.

[0087] Furthermore, the potential supplied to the absorption region PA is the ground potential. Compared to the case where the drain potential is supplied to the absorption region PA, the potential difference between the high potential supplied to the source electrode SE1 (as noise) and the potential supplied to the absorption region PA becomes larger. Therefore, the leakage current I... C It is more easily attracted to the absorption region PA, and the absorption leakage current I of the absorption region PA can be increased. CThe ability to absorb leakage current I. When the ground potential is supplied to the absorption region PA, compared to the case where the drain potential is supplied to the absorption region PA, the absorption leakage current I. C Their abilities improved by approximately 20%.

[0088] Furthermore, the depth of the absorption region PA is greater than the depth of the body region PB of power MOSFET 1Q and the depth of the body region PB of power MOSFET 2Q. This is achieved by increasing the leakage current I... C A relatively deep absorption region PA is set at the location of the path, and the leakage current I C It is more easily absorbed in the absorption region PA.

[0089] (First variant)

[0090] In the following text, reference will be made to Figure 7 A semiconductor device 100 according to a first variant of the first embodiment is described below. In the following description, the differences from the first embodiment will be mainly described, and the overlaps with the first embodiment will be omitted.

[0091] In the first embodiment, the absorption region PA completely surrounds each of regions 1A and 2A in a plan view.

[0092] like Figure 7 As shown, in the first variant, the absorption region PA partially surrounds the periphery of each of regions 1A, 2A, and 3A in a plan view. That is, the absorption region PA overlaps in a plan view with the portion of the sealing ring wiring SL1 adjacent to each of regions 1A, 2A, and 3A.

[0093] In other words, in the portion where the absorption region PA is located between region 1A and region 2A, the absorption region PA extends to the position where it overlaps with the sealing ring wiring SL1 in the plan view, and partially surrounds the periphery of each of region 1A and region 2A in the plan view. Furthermore, in the portion where the absorption region PA is located between region 1A and region 3A, the absorption region PA extends to the position where it overlaps with the sealing ring wiring SL1 in the plan view, and partially surrounds the periphery of each of region 1A and region 3A in the plan view. Furthermore, in the portion where the absorption region PA is located between region 2A and region 3A, the absorption region PA extends to the position where it overlaps with the sealing ring wiring SL1 in the plan view, and partially surrounds the periphery of each of region 2A and region 3A in the plan view.

[0094] By increasing the area of ​​the absorption region PA, the absorption leakage current I can be increased. C On the other hand, as the area of ​​the absorption region PA increases, the junction leakage between the absorption region PA and the semiconductor substrate SUB increases. If the junction leakage increases, the total power consumption in the semiconductor device 100 increases.

[0095] In the first embodiment, since the absorption region PA completely surrounds each of regions 1A and 2A in a plan view, the leakage current I from region 1A to region 2A or region 3A is... C The current path and the leakage current I from zone 2A to zone 1A or zone 3A C The current path is blocked. On the other hand, in the first embodiment, it becomes easier to increase the area of ​​the absorption region PA.

[0096] Therefore, in the first variant, the leakage current I C The current path is partially blocked. This is achieved by increasing the leakage current I. C The circuitous current path can, to some extent, maintain the absorption of leakage current I. C The ability to reduce junction leakage can decrease the amount of area reduction corresponding to the absorption region PA. Therefore, in the first variant, the total power consumption in the semiconductor device 100 can be reduced compared to the first embodiment.

[0097] (Second variant)

[0098] In the following text, reference will be made to Figure 8 A semiconductor device 100 according to a second variation of the first embodiment is described below. In the following description, the differences from the first variation will be mainly described, and the overlaps with the first variation will be omitted.

[0099] like Figure 8 As shown, in the second variant, the absorption region PA partially surrounds the periphery of each of regions 1A and 2A in a plan view. That is, the absorption region PA overlaps in a plan view with the portion of the sealing ring wiring SL1 adjacent to each of regions 1A and 2A.

[0100] The second variation differs from the first variation in the following ways: In the portion between region 1A and region 3A, the absorption region PA extends to the position where it overlaps with the sealing ring wiring SL1 in the plan view, and partially surrounds the periphery of region 1A, but not the periphery of region 3A. In the portion between region 2A and region 3A, the absorption region PA extends to the position where it overlaps with the sealing ring wiring SL1 in the plan view, and partially surrounds the periphery of region 2A, but not the periphery of region 3A.

[0101] In the second variant, compared to the first variant, the leakage current I C The current path has a shorter detour distance, thus absorbing less leakage current I. C The capability is superior to that of the second variant in the first variant. However, in the second variant, the total power consumption in the semiconductor device 100 can be further reduced compared to the first variant.

[0102] (Third variant)

[0103] In the following text, reference will be made to Figure 9 A semiconductor device 100 according to a third variation of the first embodiment is described below. In the following description, the differences from the first variation will be mainly described, and the overlaps with the first variation will be omitted.

[0104] like Figure 9 As shown, in the third variation, the absorption region PA partially surrounds the periphery of each of regions 1A, 2A, and 3A in the plan view. That is, the absorption region PA overlaps in the plan view with the portion of the sealing ring wiring SL1 adjacent to each of regions 1A, 2A, and 3A.

[0105] The third variation differs from the first variation in the following ways: In the portion between region 1A and region 3A, the absorption region PA extends to the position where it overlaps with the sealing ring wiring SL1 in the plan view, and partially surrounds the periphery of region 3A, but not the periphery of region 1A. In the portion between region 2A and region 3A, the absorption region PA extends to the position where it overlaps with the sealing ring wiring SL1 in the plan view, and partially surrounds the periphery of region 3A, but not the periphery of region 2A.

[0106] In the third variant, compared to the first variant, the leakage current I C The current path has a shorter detour distance, thus absorbing less leakage current I. C The capability is superior to that of the third variant in the first variant. However, in the third variant, the total power consumption in the semiconductor device 100 can be further reduced compared to the first variant.

[0107] (Fourth variant)

[0108] In the following text, reference will be made to Figure 10 A semiconductor device 100 according to a fourth variation of the first embodiment is described below. In the following description, the differences from the first variation will be mainly described, and the overlaps with the first variation will be omitted.

[0109] like Figure 10 As shown, in the fourth variant, the absorption region PA extends to the location where it overlaps with the sealing ring wiring SL1 in the plan view. However, in the fourth variant, the absorption region PA does not extend to partially surround the periphery of each of regions 1A, 2A, and 3A in the plan view.

[0110] In the fourth variant, compared with the first, second, and third variants, the leakage current I... C The current path has a shorter detour distance, thus absorbing less leakage current I. CThe capability is superior to the fourth variant in the first, second, and third variants. However, in the fourth variant, the total power consumption in the semiconductor device 100 can be further reduced compared to the first, second, and third variants.

[0111] (Fifth variant)

[0112] In the following text, reference will be made to Figure 11 and Figure 12 The semiconductor device 100 according to the fifth variant of the first embodiment is described below. In the following description, the differences from the fourth variant will be mainly described, and the overlap with the fourth variant will be omitted.

[0113] like Figure 11 As shown, in the fifth variation, similar to the fourth variation, the absorption region PA does not extend to partially surround the periphery of each of regions 1A, 2A, and 3A in the plan view. In the fifth variation, the absorption region PA extends to intersect with the sealing ring wiring SL1 in the plan view.

[0114] In the fifth variant, compared to the fourth variant, the leakage current I C The current path has a longer detour, thus absorbing more leakage current I. C The fifth variant outperforms the fourth variant in terms of capability. However, in the fifth variant, the total power consumption in the semiconductor device 100 increases compared to the fourth variant.

[0115] like Figure 12 As shown, the plug PG used to connect the semiconductor substrate SUB and the sealing ring wiring SL1 is not formed on the absorption region PA, so that the absorption region PA is not electrically connected to the sealing ring wiring SL1.

[0116] (Second Embodiment)

[0117] In the following text, reference will be made to Figure 13 A semiconductor device 100 according to a second embodiment is described below. In the following description, the differences from the first embodiment will be mainly described, and the overlaps with the first embodiment will be omitted.

[0118] like Figure 13 As shown, similar to the first embodiment, in the second embodiment, the absorption region PA is disposed between region 1A and region 2A, between region 1A and region 3A, and between region 2A and region 3A. However, in the second embodiment, the absorption region PA does not overlap with the sealing ring wiring SL1 in the plan view and is disposed between the portion of the sealing ring wiring SL1 and region 3A. The absorption wiring AW covers the absorption region PA in the plan view.

[0119] In the second embodiment, the leakage current I C The current path is partially blocked. This is achieved by increasing the leakage current I.C The detour of the current path can, to some extent, maintain the absorption of leakage current I. C The ability to reduce junction leakage can decrease the amount of area reduction corresponding to the absorption region PA. Therefore, in the second embodiment, the total power consumption in the semiconductor device 100 can be reduced compared to the first embodiment.

[0120] The technique of the second embodiment can be applied to situations where it is difficult to extend the absorption region PA to a position that overlaps with the sealing ring wiring SL1, SL2 and SL3 in a plan view, or to situations where there are few MOSFETs 3Q in region 3A and there is a margin for arranging the absorption region PA.

[0121] As described above, the present invention has been specifically described based on embodiments, but the present invention is not limited to the above embodiments and various modifications can be made without departing from its spirit.

[0122] For example, the number of wiring layers is not limited to three layers, such as wiring M1, M2 and M3, but can be two, four or more layers.

[0123] Furthermore, although it has been described that the semiconductor device 100 (i.e., the semiconductor substrate SUB) includes three regions, the number of regions included in the semiconductor device 100 may be two. In this case, for example, an n-type power MOSFET is formed in the first region, and a p-type MOSFET and an n-type MOSFET are formed in the second region as a control circuit for controlling the operation of the power MOSFET formed in the first region.

[0124] Furthermore, although the trench gate power MOSFET has been described as a vertical field-effect transistor (i.e., a power semiconductor) formed in regions 1A (i.e., the first region of the semiconductor substrate SUB) and 2A (i.e., the second region of the semiconductor substrate SUB) of the semiconductor device 100 (i.e., the semiconductor substrate SUB), the device is not limited to a power MOSFET and can be an insulated gate bipolar transistor (IGBT).

[0125] Furthermore, the power MOSFET is not limited to n-type; it can also be p-type. In this case, the conductivity type of the semiconductor substrate SUB and each impurity region is configured to be the opposite of the conductivity type described in the above embodiments.

Claims

1. A semiconductor device, comprising: A semiconductor substrate of a first conductivity type, the semiconductor substrate having an upper surface and a lower surface; A vertical first field-effect transistor, wherein the first field-effect transistor is formed in a first region of the semiconductor substrate and is a power semiconductor; A second field-effect transistor is formed in a second region of the semiconductor substrate adjacent to the first region and is configured to control the operation of the first field-effect transistor. Sealing ring wiring is formed in a ring shape to surround the first region and the second region in a plan view, and is formed on the upper surface of the semiconductor substrate; as well as Impurity regions are formed in the semiconductor substrate to a predetermined depth from the upper surface of the semiconductor substrate and have a second conductivity type opposite to the first conductivity type. The impurity area is positioned between the first and second areas to extend to a location overlapping the sealing ring wiring in a plan view. The ground potential is supplied to the impurity region.

2. The semiconductor device according to claim 1, A vertically oriented third field-effect transistor is formed in a third region of the semiconductor substrate adjacent to each of the first and second regions. This third field-effect transistor is a power semiconductor. The sealing ring wiring formed on the upper surface of the semiconductor substrate is formed in the ring shape to surround the first region, the second region, and the third region in a plan view, and The impurity area is disposed between the first area and the second area, between the first area and the third area, and between the second area and the third area, so as to extend to the location that overlaps with the sealing ring wiring in a plan view.

3. The semiconductor device according to claim 2, Each of the first field-effect transistor and the second field-effect transistor is a power MOSFET.

4. The semiconductor device according to claim 3, further comprising: A first wiring is formed on the upper surface of the semiconductor substrate and electrically connected to the impurity region. The first wiring is disposed between the first area and the second area, between the first area and the third area, and between the second area and the third area, so as to cover a portion of the impurity area in a plan view and be separate from the sealing ring wiring.

5. The semiconductor device according to claim 4, further comprising: Drain electrode, the drain electrode being formed on the lower surface of the semiconductor substrate. The sealing ring wiring is electrically connected to the drain electrode via the semiconductor substrate, and The impurity region and the first wiring are electrically insulated from the sealing ring wiring.

6. The semiconductor device according to claim 3, The first field-effect transistor includes: In the first region, a first trench is formed in the semiconductor substrate, the first trench being formed to a predetermined depth from the upper surface of the semiconductor substrate. A first gate electrode is formed in the first trench via a first gate insulating film. In the first region, a first body region of the second conductivity type is formed in the semiconductor substrate, the first body region being formed such that its depth from the upper surface of the semiconductor substrate is shallower than the depth of the first trench, and A first source region of the first conductivity type is formed in the first body region. The third field-effect transistor includes: In the third region, a second trench is formed in the semiconductor substrate, the second trench being formed to a predetermined depth from the upper surface of the semiconductor substrate. The second gate electrode is formed in the second trench via a second gate insulating film. In the third region, a second body region of the second conductivity type is formed in the semiconductor substrate, the second body region being formed such that its depth from the upper surface of the semiconductor substrate is shallower than the depth of the second trench, and A second source region of the first conductivity type is formed in the second body region, and The second field-effect transistor includes: In the second region, a first well region of the second conductivity type is formed in the semiconductor substrate, the first well region being formed to a predetermined depth from the upper surface of the semiconductor substrate. The diffusion region of the first conductivity type is formed in the first well region and constitutes the source or drain region of the second field-effect transistor. The third gate electrode is formed on the first well region via a third gate insulating film.

7. The semiconductor device according to claim 6, The depth of the impurity region is greater than the depth of the first body region and the depth of the second body region.

8. The semiconductor device according to claim 3, The impurity region extends to intersect with the sealing ring wiring in a plan view.

9. The semiconductor device according to claim 3, The impurity region overlaps with a portion of the sealing ring wiring surrounding the first region and the third region in a plan view.

10. The semiconductor device according to claim 3, The impurity region overlaps in a plan view with the portion of the sealing ring wiring adjacent to the corresponding portions of the first and third regions.

11. The semiconductor device according to claim 10, The impurity region overlaps in a plan view with a portion of the sealing ring wiring adjacent to a portion of the second region.

12. A semiconductor device, comprising: A semiconductor substrate of a first conductivity type, the semiconductor substrate having an upper surface and a lower surface; A vertical first field-effect transistor, wherein the first field-effect transistor is formed in a first region of the semiconductor substrate and is a power semiconductor; A second field-effect transistor is formed in a second region of the semiconductor substrate adjacent to the first region and is configured to control the operation of the first field-effect transistor. Sealing ring wiring is formed in a ring shape to surround the first region and the second region in a plan view, and is formed on the upper surface of the semiconductor substrate; as well as Impurity regions are formed in the semiconductor substrate to a predetermined depth from the upper surface of the semiconductor substrate and have a second conductivity type opposite to the first conductivity type. The impurity region is located between the first region and the second region, and is located between the sealing ring wiring and a portion of the second region. The ground potential is supplied to the impurity region.

13. The semiconductor device according to claim 12, A vertically oriented third field-effect transistor is formed in a third region of the semiconductor substrate adjacent to each of the first and second regions. This third field-effect transistor is a power semiconductor. The sealing ring wiring formed on the upper surface of the semiconductor substrate is formed in the ring shape to surround the first region, the second region, and the third region in a plan view, and The impurity area is disposed between the first area and the second area, between the first area and the third area, between the second area and the third area, and between the sealing ring wiring and the portion of the second area.

14. The semiconductor device according to claim 13, Each of the first field-effect transistor and the second field-effect transistor is a power MOSFET.

15. The semiconductor device of claim 14, further comprising: A first wiring is formed on the upper surface of the semiconductor substrate to cover the impurity region in a plan view and is electrically connected to the impurity region; as well as A drain electrode is formed on the lower surface of the semiconductor substrate. The sealing ring wiring is electrically connected to the drain electrode via the semiconductor substrate, and The impurity region and the first wiring are electrically insulated from the sealing ring wiring.

16. The semiconductor device according to claim 14, The first field-effect transistor includes: In the first region, a first trench is formed in the semiconductor substrate, the first trench being formed to a predetermined depth from the upper surface of the semiconductor substrate. A first gate electrode is formed in the first trench via a first gate insulating film. In the first region, a first body region of the second conductivity type is formed in the semiconductor substrate, the first body region being formed such that its depth from the upper surface of the semiconductor substrate is shallower than the depth of the first trench, and A first source region of the first conductivity type is formed in the first body region. The third field-effect transistor includes: In the third region, a second trench is formed in the semiconductor substrate, the second trench being formed to a predetermined depth from the upper surface of the semiconductor substrate. The second gate electrode is formed in the second trench via a second gate insulating film. In the third region, a second body region of the second conductivity type is formed in the semiconductor substrate, the second body region being formed such that its depth from the upper surface of the semiconductor substrate is shallower than the depth of the second trench, and A second source region of the first conductivity type is formed in the second body region, and The second field-effect transistor includes: In the second region, a first well region of the second conductivity type is formed in the semiconductor substrate such that it reaches a predetermined depth from the upper surface of the semiconductor substrate. The diffusion region of the first conductivity type is formed in the first well region and constitutes the source or drain region of the second field-effect transistor. The third gate electrode is formed on the first well region via a third gate insulating film.

17. The semiconductor device according to claim 16, The depth of the impurity region is greater than the depth of the first body region and the depth of the second body region.

18. The semiconductor device according to claim 14, The impurity area does not overlap with the sealing ring wiring in the plan view.

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