Heterogeneously integrated dual-color infrared focal plane chip

Abstract

This disclosure provides a heterogeneous integrated dual-color infrared focal plane array chip, comprising: a dual-color readout circuit wafer (1), including a dual-color readout circuit substrate (11), and a top electrode contact (121) and a common electrode contact (122) spaced apart on the dual-color readout circuit substrate (11); a first detector wafer (2), bonded to the upper surface of the dual-color readout circuit wafer (1); a second detector wafer (3), after the substrate of the first detector wafer (2) is removed, bonded to the upper surface of the first detector wafer (2), and after the substrate of the second detector wafer (3) is removed, forming a heterogeneous integrated wafer with the first detector wafer (2); a pixel mesa array and a common electrode region, etched and formed on the first detector wafer (2) and the second detector wafer (3).

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to the field of infrared detectors, and more specifically to a heterogeneously integrated dual-color infrared focal plane array chip. Background Technology

[0002] The dual-color infrared focal plane array detector achieves a comprehensive improvement in reliability, accuracy, and intelligent detection level through dual-band information fusion, making it an ideal choice for high-precision sensing in complex and harsh environments.

[0003] Current advanced dual-color detectors employ a stacked structure where two bands of epitaxial layers are sequentially grown on a single substrate. However, the two infrared detection materials grown sequentially in this structure require lattice matching with the underlying substrate. This can prevent the integration of many high-performance materials due to mismatches in lattice constants or coefficients of thermal expansion. Furthermore, the sequential growth of multiple materials on a single substrate leads to the continuous accumulation of interlayer lattice mismatches, easily generating interface defects and resulting in decreased material uniformity and yield.

[0004] Traditional infrared focal plane array (FLAS) chip manufacturing processes achieve mechanical and electrical interconnection between the infrared detector and readout circuitry via flip-chip bonding. With the continuous miniaturization of detector pixel sizes, the fabrication of tiny, uniform indium pillar arrays is becoming increasingly challenging. Furthermore, this process requires dicing large-area infrared detector wafers and readout circuit wafers into independent chip units before bonding, significantly increasing the number of process steps and costs, hindering large-scale production. Summary of the Invention

[0005] (a) Technical problems to be solved

[0006] In view of the above problems, this disclosure provides a heterogeneous integrated dual-color infrared focal plane array chip, which at least partially solves the technical problems of limited material system, high process complexity and high manufacturing cost of current dual-color infrared focal plane array chips.

[0007] (II) Technical Solution

[0008] The first aspect of this disclosure provides a heterogeneously integrated dual-color infrared focal plane array chip, comprising: a dual-color readout circuit wafer, including a dual-color readout circuit substrate, and top electrode contacts and common electrode contacts spaced apart on the dual-color readout circuit substrate; a first detector wafer bonded to the upper surface of the dual-color readout circuit wafer; a second detector wafer bonded to the upper surface of the first detector wafer after the substrate of the first detector wafer is removed, wherein the second detector wafer and the first detector wafer form a heterogeneously integrated wafer after the substrate of the second detector wafer is removed; a pixel mesa array and a common electrode region are etched and formed on the first detector wafer and the second detector wafer.

[0009] According to embodiments of this disclosure, the device further includes: a top electrode, deposited and stripped to form a selected area on the surface of the pixel mesa array, one end of the top electrode extending out of the upper surface of the second detector wafer, and the other end forming an electrical contact with a top electrode contact through a top electrode via, wherein the top electrode via penetrates through the first and second detector wafers to the upper surface of the top electrode contact; and a common electrode, deposited and stripped to form a selected area on the surface of the common electrode region, one end of the common electrode extending out of the upper surface of the remaining first detector wafer after etching, and the other end forming an electrical contact with a common electrode contact through a common electrode via, wherein the common electrode via penetrates through the remaining first detector wafer after etching to the upper surface of the common electrode contact.

[0010] According to embodiments of this disclosure, it further includes: a first passivation layer deposited on the sidewall of the pixel mesa array, and on the upper surfaces of a portion of the second detector wafer and the first detector wafer.

[0011] According to embodiments of this disclosure, it further includes: a second passivation layer deposited between the sidewall of the top electrode via and the top electrode.

[0012] According to embodiments of this disclosure, the dual-color readout circuit wafer further includes: a dielectric layer covering the upper surface of the dual-color readout circuit substrate, the top electrode contact, and the common electrode contact.

[0013] According to an embodiment of the present disclosure, the first detector wafer comprises, from top to bottom: a first detector substrate, a first etch stop layer, and a first detector epitaxial layer; wherein the first detector substrate and the first etch stop layer constitute the substrate of the first detector wafer.

[0014] According to an embodiment of the present disclosure, the first detector epitaxial layer comprises, from top to bottom, a first contact layer, a first absorption layer, a first barrier layer, and a second contact layer; wherein the upper surface of the second contact layer is exposed in the common electrode region to form a connection interface for ohmic contact.

[0015] According to an embodiment of this disclosure, the second detector wafer comprises, from top to bottom: a second detector substrate, a second etch stop layer, and a second detector epitaxial layer; wherein the second detector substrate and the second etch stop layer constitute the substrate of the second detector wafer.

[0016] According to embodiments of this disclosure, the second detector epitaxial layer comprises, from top to bottom: a third contact layer, a second barrier layer, a second absorption layer, and a fourth contact layer.

[0017] According to embodiments of this disclosure, a heterogeneous integrated wafer is divided into multiple independent single-chip dual-color infrared focal plane arrays.

[0018] (III) Beneficial Effects

[0019] This disclosure overcomes the shortcomings of existing technologies by providing a heterogeneously integrated dual-color infrared focal plane array chip. The dual-color readout circuit wafer is sequentially and directly bonded to the first and second detector wafers at low temperatures. This breaks the strict limitations of traditional stacked structures on material and substrate lattice matching, allowing for more flexible selection of infrared materials suitable for different wavelength bands and significantly broadening the material selection range. Simultaneously, by using a method of overall heterogeneous integration followed by dicing, the complex and difficult operations of traditional flip-chip bonding are eliminated, reducing process steps and simplifying the production process. Furthermore, the reduction in process steps and the increase in production efficiency effectively reduce manufacturing costs. Attached Figure Description

[0020] To gain a more complete understanding of this disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, wherein:

[0021] Figure 1 This schematic diagram illustrates the structure of a heterogeneously integrated dual-color infrared focal plane array chip provided in an embodiment of the present disclosure.

[0022] Figure 2 This schematically illustrates a low-temperature direct bonding of a first detector wafer and a dual-color readout circuit wafer provided in an embodiment of this disclosure;

[0023] Figure 3 This schematic diagram illustrates the removal of the substrate of the first detector wafer after low-temperature bonding of the first detector wafer and the dual-color readout circuit wafer provided in the embodiments of this disclosure.

[0024] Figure 4 This illustration shows a schematic diagram of a low-temperature direct bonding between a second detector wafer and a first detector wafer provided in an embodiment of this disclosure;

[0025] Figure 5 This schematic diagram illustrates the removal of the substrate of the second detector wafer after low-temperature bonding between the second detector wafer and the first detector wafer, as provided in an embodiment of this disclosure.

[0026] Figure 6 This schematically illustrates a diagram of etching first and second detector wafers to form a pixel mesa array and a common electrode region, according to an embodiment of this disclosure.

[0027] Figure 7 The schematic diagram illustrates the etching of first and second detector wafers to form top electrode vias and common electrode vias according to embodiments of the present disclosure.

[0028] Explanation of reference numerals in the attached figures:

[0029] 1- Dual-color readout circuit wafer; 11- Dual-color readout circuit substrate; 121- Top electrode contact; 122- Common electrode contact; 13- Dielectric layer; 2- First detector wafer; 21- First detector substrate; 22- First etch stop layer; 23- First detector epitaxial layer; 231- First contact layer; 232- First absorption layer; 233- First barrier layer; 234- Second contact layer; 3- Second detector wafer; 31- Second detector substrate; 32- Second etch stop layer; 33- Second detector epitaxial layer; 331- Third contact layer; 332- Second barrier layer; 333- Second absorption layer; 334- Fourth contact layer; 41- First passivation layer; 42- Second passivation layer; 431- Top electrode; 432- Common electrode. Detailed Implementation

[0030] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0032] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0033] Research has shown that current dual-color detectors typically employ a stacked structure with two sequentially epitaxial layers for different wavelength bands on a single substrate. This allows for precise vertical integration of the two detection pixels, ensuring their spatial alignment and avoiding registration errors caused by beam splitting or splicing. It also simplifies the optical system structure, making the detector more compact and reliable. By precisely designing the composition and thickness of each layer through band engineering, dual-color responses in specific detection bands can be achieved. However, this structure has limitations. Both epitaxial infrared materials need to be lattice-matched with the substrate, which can prevent the integration of many high-performance materials due to lattice or thermal expansion coefficient mismatches. Furthermore, growing multiple materials on a single substrate can lead to accumulated interlayer lattice mismatches and interface defects, reducing material uniformity and yield.

[0034] Traditional infrared focal plane array (FLAS) chip manufacturing processes connect the infrared detector and readout circuitry via flip-chip bonding. However, with the continuous miniaturization of detector pixels, the limitations of traditional indium pillar flip-chip bonding are becoming increasingly apparent. As pixel pitch decreases, the indium pillars corresponding to each pixel also shrink proportionally. Furthermore, to avoid bridging and short circuits during bonding, it is necessary to fabricate an array of indium pillars with extremely small dimensions and high uniformity in shape and height, significantly increasing the fabrication difficulty. Moreover, this process requires first dicing a large wafer into individual chip units, followed by flip-chip bonding, underfilling, and substrate thinning of each chip, increasing the process flow and cost, and hindering large-scale production.

[0035] In view of this, embodiments of the present disclosure provide a heterogeneously integrated dual-color infrared focal plane array chip.

[0036] Figure 1 The schematic diagram illustrates the structure of a heterogeneously integrated dual-color infrared focal plane array chip provided in an embodiment of this disclosure.

[0037] like Figure 1 As shown, the heterogeneously integrated dual-color infrared focal plane array chip includes a dual-color readout circuit wafer 1, a first detector wafer 2, a second detector wafer 3, a pixel mesa array, and a common electrode area.

[0038] For example, the dual-color readout circuit wafer 1 can be a group IV detector wafer, etc.

[0039] The dual-color readout circuit wafer 1 includes a dual-color readout circuit substrate 11, and a top electrode contact 121 and a common electrode contact 122 spaced apart on the dual-color readout circuit substrate 11.

[0040] The dual-color readout circuit wafer 1 also includes a dielectric layer 13, covering the upper surface of the dual-color readout circuit substrate 11, the top electrode contact 121, and the common electrode contact 122. The dielectric layer 13 can be SiO2, Al2O3, or Si... x N y The deposition method can be plasma-enhanced chemical vapor deposition or atomic layer deposition, etc. After deposition, the dielectric layer 13 can be chemically and mechanically planarized to make the surface of the dielectric layer 13 flat and smooth.

[0041] The first detector wafer 2 can be a group IV detector wafer, a group III-V detector wafer, or a group II-VI detector wafer, etc.

[0042] The first detector wafer 2 comprises, from top to bottom, a first detector substrate 21, a first etch stop layer 22, and a first detector epitaxial layer 23. Specifically, the first detector wafer 2 includes a first detector substrate 21, a first etch stop layer 22 disposed on the surface of the first detector substrate 21, and a first detector epitaxial layer 23 disposed on the surface of the first etch stop layer 22. The first detector substrate 21 and the first etch stop layer 22 constitute the substrate of the first detector wafer 2.

[0043] Furthermore, the first detector epitaxial layer 23 comprises, from top to bottom, a first contact layer 231, a first absorption layer 232, a first barrier layer 233, and a second contact layer 234. The first contact layer 231 is disposed on the lower surface of the first corrosion-stopping layer 22, and the upper surface of the second contact layer 234 is exposed in the common electrode region to form a connection interface for ohmic contact.

[0044] The material structures of the first contact layer 231, the first absorption layer 232, the first barrier layer 233, and the second contact layer 234 can all be designed according to the material of the first detector substrate 21 and the requirements of the target detection band. In some cases, the first barrier layer 233 and the second contact layer 234 can be omitted.

[0045] For example, the first detector substrate 21 can be an N-type GaSb substrate in the (001) direction; the first corrosion stop layer 22 can be InAs0.91Sb0.09 with a lattice matching the GaSb substrate and a thickness of 0.5~1μm; the materials of the first contact layer 231 and the second contact layer 234 can be InAs0.91Sb0.09, InAs / GaSb superlattice, or InAs / InAsSb superlattice and a thickness of 0.1~0.5μm; the material of the first absorption layer 232 can be AlAs0.08Sb0.92, InAs / GaSb / AlSb / GaSb superlattice, or AlAsSb / InAsSb superlattice and a thickness of 0.1~0.3μm; the material of the first barrier layer 233 can be InAs0.91Sb0.09, InAs / GaSb superlattice, or InAs / InAsSb superlattice and a thickness of 1~6μm. The first contact layer 231 and the second contact layer 234 are heavily doped layers with opposite doping polarities, the first etch stop layer 22 is an unintentionally doped layer, and the first absorption layer 232 and the first barrier layer 233 can be unintentionally doped layers or lightly doped layers.

[0046] Figure 2 The illustration shows a schematic diagram of the low-temperature direct bonding of the first detector wafer and the dual-color readout circuit wafer provided in the embodiments of this disclosure.

[0047] like Figure 2As shown, the first detector wafer 2 and the readout circuit wafer can be directly bonded at low temperature, that is, the first detector wafer 2 is bonded to the upper surface of the dual-color readout circuit wafer 1. Specifically, the epitaxial layer 23 of the first detector is directly bonded to the dual-color readout circuit wafer 1. The flip-chip first detector wafer 2 is aligned with the dual-color readout circuit wafer 1, so that the second contact layer 234 and the dielectric layer 13 are in contact with each other. Pressure is applied to bond the two together through van der Waals forces. The bonded wafer is placed in a bonding device, and the temperature and pressure are increased to form a tight covalent bond between the second contact layer 234 and the dielectric layer 13, completing the first wafer bonding.

[0048] In some exemplary embodiments, the surface treatment prior to bonding may include wet cleaning and plasma activation. Wet cleaning is used to remove residual contaminants from the surface of the dielectric layer 13, while plasma activation is used to break the chemical bonds on the surface of the dielectric layer 13, generating a large number of dangling bonds.

[0049] like Figure 3 As shown, after the first wafer bonding is completed, the substrate of the first detector wafer 2 can be removed, that is, the first detector substrate 21 and the first etch stop layer 22 of the first detector wafer 2 can be removed. In this process, the first detector substrate 21 can be thinned to 30-200 μm by mechanical grinding and polishing, and then the first detector substrate 21 can be completely removed by the first chemical etching solution, exposing the first etch stop layer 22. Then, the first etch stop layer 22 can be completely removed by the second chemical etching solution, exposing the first contact layer 231.

[0050] For example, the first chemical etching solution can be a chromium trioxide (CrO3):hydrogen fluoride (HF):water (H2O) solution with a ratio of 10:1:20, to selectively etch the first detector substrate 21 without etching the first etching stop layer 22. Furthermore, the second chemical etching solution can be a citric acid (C6H8O7):hydrogen peroxide (H2O2):water (H2O) solution with a ratio of 2:1:20, to selectively etch the first etching stop layer 22 without etching the first detector epitaxial layer 23.

[0051] The second detector wafer 3 is similar to the first detector wafer 2 in terms of material and structure.

[0052] The second detector wafer 3 comprises, from top to bottom, a second detector substrate 31, a second etch stop layer 32, and a second detector epitaxial layer 33. The second detector substrate 31 and the second etch stop layer 32 constitute the substrate of the second detector wafer 3.

[0053] Furthermore, the second detector epitaxial layer 33 includes, from top to bottom, a third contact layer 331, a second barrier layer 332, a second absorption layer 333, and a fourth contact layer 334. The third contact layer 331 is disposed on the lower surface of the second corrosion stopping layer 32.

[0054] Figure 4 The illustration shows a schematic diagram of the low-temperature direct bonding of the second detector wafer and the first detector wafer provided in the embodiments of this disclosure.

[0055] like Figure 4 As shown, the second detector wafer 3 and the first detector wafer 2 can be directly bonded at low temperature. That is, after the substrate of the first detector wafer 2 is removed, the second detector wafer 3 is bonded to the upper surface of the first detector wafer 2. Specifically, the second detector epitaxial layer 33 can be directly bonded to the first detector epitaxial layer 23, and the substrate removal process is the same as that described above for removing the substrate of the first detector wafer 2. There is no dielectric layer between the first detector wafer 2 and the second detector wafer 3, so direct electrical contact can be achieved. Therefore, only one electrode contact needs to be set on each mesa. In practical applications, the signal extraction path can be precisely controlled by flexibly changing the bias voltage applied to the electrode contact. That is, when the bias voltage is adjusted to a certain range, the signal from the first detector wafer 2 can be extracted preferentially; while when the bias voltage is adjusted to another different range, the signal from the second detector wafer can be extracted specifically.

[0056] Understandably, extracting signals from different wafers by changing the bias voltage simplifies the circuit structure, reduces the number of electrode contacts, lowers manufacturing costs and process complexity, and significantly improves the accuracy and controllability of signal extraction, providing strong support for the efficient and stable operation of the detector in complex environments. During bonding, the fourth contact layer 334 contacts the first contact layer 231. It is important to note that the fourth contact layer 334 and the first contact layer 231 must have the same doping type, and the fourth contact layer 334 and the third contact layer 331 must have different doping types. In some cases, the second barrier layer 332 and the fourth contact layer 334 can be omitted.

[0057] It should be noted that the second detector wafer 3 can also be a two-dimensional material, organic material, etc., which can be transferred to the first detector wafer 2 by spin coating or other methods without wafer bonding. This will not be elaborated here.

[0058] like Figure 5 As shown, the substrate of the second detector wafer 3 can be removed to form a heterogeneous integrated wafer, that is, after the substrate of the second detector wafer 3 is removed, it forms a heterogeneous integrated wafer with the first detector wafer 2.

[0059] The pixel mesa array and common electrode region are etched and formed on the first detector wafer 2 and the second detector wafer 3. Specifically, the pixel mesa array and common electrode region are disposed on the detector epitaxial layers (including the first detector epitaxial layer 23 and the second detector epitaxial layer 33). The etched portion penetrates half of the third contact layer 331, the second barrier layer 332, the second absorption layer 333, and the fourth contact layer 334, as well as the first contact layer 231, the first absorption layer 232, the first barrier layer 233, and the second contact layer 234. Figure 6 As shown.

[0060] For example, the deposition of the first mask layer on the third contact layer 331 can be performed using plasma-enhanced chemical vapor deposition (PECVD) or inductively coupled plasma-enhanced chemical vapor deposition (ICPCVD). The material of the first mask layer can be SiO2 or Si. x N y The thickness can range from 200nm to 2000nm, and the mask thickness is selected according to the etching depth and etching selectivity.

[0061] A mesa pattern is formed on a first mask layer using photolithography and etching processes, wherein the outline of the mesa pattern is identical to the outline of the pixel mesa array. For example, the process for forming the mesa pattern includes photolithography, etching of the first mask layer, and removal of photoresist. Another example is the use of ultraviolet lithography, including steps such as spin coating, pre-baking, exposure, development, hardening, and pattern inspection, to form a patterned photoresist layer on the surface of the first mask layer. Yet another example is the use of reactive ion etching, where the photoresist layer is used as a mask to dry-etch the first mask layer, removing the portion of the first mask layer not covered by the photoresist. Still another example is the removal of the photoresist layer by organic reagent water bath cleaning or ultrasonic cleaning.

[0062] The first detector epitaxial layer 23 and the second detector epitaxial layer 33 are etched to half the depth of the fourth contact layer 234 to form a pixel mesa array and a common electrode region. For example, inductively coupled plasma etching is used to remove the first detector epitaxial layer 23 and the second detector epitaxial layer 33 that are not covered by the first mask layer, with the etching depth reaching half the depth of the fourth contact layer 234, thus forming the pixel mesa array and the common electrode region. For example, the etching gas used can be CH4 / H2 / BCl3 / Cl2 / Ar or other etching gases suitable for the materials of the first detector epitaxial layer 23 and the second detector epitaxial layer 33, and other etching parameters are selected according to the specific materials.

[0063] For the first mask layer, dry etching can be performed using reactive ion etching, or wet etching can be performed using a hydrofluoric acid solution to remove the remaining first mask layer.

[0064] Continue to refer to Figure 1The heterogeneously integrated dual-color infrared focal plane array chip also includes a first passivation layer 41, which is deposited on the sidewall of the pixel mesa array and on the upper surface of part of the second detector wafer 3 and the first detector wafer 2.

[0065] Specifically, a first passivation layer 41 can be deposited on the surface of the detector epitaxial layer using plasma-enhanced chemical vapor deposition or atomic layer deposition. The first passivation layer 41 is then etched using ultraviolet lithography and reactive ion etching to form a window pattern, so that the first passivation layer 41 covers the sidewalls of the pixel mesa array and a portion of the fourth contact layer 234. The material of the first passivation layer 41 can be SiO2, Si... x N y It can be any one or a combination of several of the following materials: SiON, Al2O3, ZnS, photoresist, epoxy resin, etc.

[0066] Figure 7 The schematic diagram illustrates the etching of first and second detector wafers to form top electrode vias and common electrode vias according to embodiments of the present disclosure.

[0067] like Figure 7 As shown, etching the first detector wafer 2 and the second detector wafer 3, specifically etching the second detector epitaxial layer 33, the first detector epitaxial layer 23, and the dielectric layer 13, can form top electrode vias and common electrode vias to expose portions of the top electrode contact 121 and the common electrode contact 122. The top electrode via penetrates through both the first detector wafer 2 and the second detector wafer 3, extending to the upper surface of the top electrode contact 121; the common electrode via penetrates through the remaining portion of the first detector wafer 2 after etching, extending to the upper surface of the common electrode contact 122. The basic steps are the same as etching the pixel mesa array and the common electrode region.

[0068] It should be noted that the orthographic projection of the uncovered portion of the second mask layer coincides with the top electrode contact 121 and the common electrode contact 122, respectively.

[0069] For example, inductively coupled plasma etching can be used to etch the second detector epitaxial layer 33 and the first detector epitaxial layer 23 down to the bottom of the second contact layer 234 to expose the dielectric layer 13. Then, reactive ion etching can be used to continue etching the exposed dielectric layer 13 down to the bottom of the dielectric layer 13 to form the top electrode via and the common electrode via.

[0070] like Figure 1 As shown, the heterogeneously integrated dual-color infrared focal plane array chip also includes a second passivation layer 42, which is deposited between the sidewall of the top electrode via and the top electrode 431.

[0071] Specifically, after the top electrode via and the common electrode via are etched, the second mask layer on the surface of the epitaxial layer can be removed by reactive ion etching, and a second passivation layer 42 can be formed on the sidewall of the top electrode via.

[0072] The second passivation layer 42 can be deposited on the surface of the epitaxial layer using plasma-enhanced chemical vapor deposition or atomic layer deposition. The second passivation layer 42 is then etched using ultraviolet lithography and reactive ion etching to form a window pattern. This ensures that the second passivation layer 42 covers the sidewall of the top electrode via and part of the third contact layer 331, but does not cover the surface of the sidewall of the common electrode via, the top electrode contact 121, and the common electrode contact 122. The material of the second passivation layer 42 can be SiO2, Si... x N y It can be any one or a combination of several of the following materials: SiON, Al2O3, ZnS, photoresist, epoxy resin, etc.

[0073] Continue to refer to Figure 1 It also includes a top electrode 431 and a common electrode 432. The top of the platform is electrically connected to the top electrode contact via the top electrode 431, and the common electrode area is electrically connected to the common electrode contact via the common electrode 432.

[0074] Specifically, a top electrode 431 can be formed on the pixel mesa array. The top electrode 431 is deposited and stripped onto a selected area of ​​the surface of the pixel mesa array. One end of the top electrode 431 extends beyond the upper surface of the second detector wafer 3, and the other end forms an electrical contact with the top electrode contact 121 through a top electrode via. This allows the third contact layer 331 to be electrically connected to the top electrode contact 121 through the top electrode via. A common electrode 432 can be formed in the common electrode region. The common electrode 432 is deposited and stripped onto a selected area of ​​the surface of the common electrode region. One end of the common electrode 432 extends beyond the upper surface of the remaining first detector wafer 2 after etching, and the other end forms an electrical contact with the common electrode contact 122 through a common electrode via. This allows the second contact layer 234 to be electrically connected to the common electrode contact 122 through the common electrode via.

[0075] A patterned third mask layer is formed on the surface of the detector epitaxial layer. The third mask layer is used to expose the top electrode via sidewall, the top electrode contact, the portion of the third contact layer 331 adjacent to the top electrode via, the common electrode via sidewall, the common electrode contact, and the portion of the second contact layer 234 adjacent to the common electrode via.

[0076] Among them, the top electrode 431 and the common electrode 432 can be formed by negative photoresist lithography, electron beam evaporation and lift-off processes based on the patterned third mask layer.

[0077] The formed top electrode 431 is located near the top electrode via at the center of the pixel mesa array. It starts from the portion of the third contact layer 331 not covered by the second passivation layer 42, extends through the second passivation layer 42 to the bottom of the top electrode via, and covers the top electrode contact 121, thus achieving electrical connection between the third contact layer 331 and the top electrode contact 121. The formed common electrode 432 is located near the common electrode via in the common electrode region. It starts from the surface of the second contact layer 234, extends through the sidewall of the common electrode via to the bottom of the common electrode via, and covers the common electrode contact 122.

[0078] The top electrode 431 and the common electrode 432 can be made of metal, for example, Ti / Pt / Au. Ti enhances the adhesion between the metal electrode and the detector epitaxial layer, Pt prevents Au from diffusing into Ti and the detector epitaxial layer, and Au enables electrical connection.

[0079] The heterogeneous integrated wafer is divided into multiple independent single dual-color infrared focal plane array chips.

[0080] For example, a high-precision laser cutting device or diamond blade cutter can be used to divide a heterogeneous integrated wafer into multiple independent single-chip dual-color infrared focal plane arrays according to a pre-designed chip size and layout. Each divided chip retains the core characteristics of the heterogeneous integrated wafer and can independently achieve efficient detection and conversion of infrared radiation in two bands, laying the foundation for subsequent chip packaging, testing, and integration into various infrared imaging systems.

[0081] Understandably, direct wafer bonding and heterogeneous integration have broadened the material system for dual-color devices and reduced process complexity and production costs.

[0082] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0083] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents.

Claims

1. A heterogeneously integrated dual-color infrared focal plane array chip, characterized in that, include: The dual-color readout circuit wafer (1) includes a dual-color readout circuit substrate (11), and a top electrode contact (121) and a common electrode contact (122) spaced apart on the dual-color readout circuit substrate (11). The first detector wafer (2) is bonded to the upper surface of the dual-color readout circuit wafer (1); The second detector wafer (3) is bonded to the upper surface of the first detector wafer (2) after the substrate of the first detector wafer (2) is removed. The second detector wafer (3) forms a heterogeneous integrated wafer with the first detector wafer (2) after the substrate of the second detector wafer (3) is removed. The pixel mesa array and the common electrode area are etched and formed on the first detector wafer (2) and the second detector wafer (3).

2. The chip according to claim 1, characterized in that, Also includes: A top electrode (431) is deposited and stripped to form a selected area on the surface of the pixel mesa array. One end of the top electrode (431) extends out of the upper surface of the second detector wafer (3), and the other end forms an electrical contact with the top electrode contact (121) through a top electrode via. The top electrode via penetrates the first detector wafer (2) and the second detector wafer (3) to the upper surface of the top electrode contact (121). A common electrode (432) is deposited and stripped to form a selected area on the surface of the common electrode region. One end of the common electrode (432) extends out of the upper surface of the remaining first detector wafer (2) after etching, and the other end forms an electrical contact with the common electrode contact (122) through a common electrode via. The common electrode via penetrates the remaining first detector wafer (2) after etching and extends to the upper surface of the common electrode contact (122).

3. The chip according to claim 1, characterized in that, Also includes: A first passivation layer (41) is deposited on the sidewall of the pixel mesa array and on the upper surface of a portion of the second detector wafer (3) and the first detector wafer (2).

4. The chip according to claim 2, characterized in that, Also includes: A second passivation layer (42) is deposited between the sidewall of the top electrode via and the top electrode (431).

5. The chip according to claim 1, characterized in that, The dual-color readout circuit wafer (1) also includes: A dielectric layer (13) covers the upper surface of the dual-color readout circuit substrate (11), the top electrode contact (121), and the common electrode contact (122).

6. The chip according to claim 1, characterized in that, The first detector wafer (2) comprises, from top to bottom: The first detector substrate (21), the first etch stop layer (22), and the first detector epitaxial layer (23); wherein, The first detector substrate (21) and the first etch stop layer (22) constitute the substrate of the first detector wafer (2).

7. The chip according to claim 5, characterized in that, The first detector epitaxial layer (23) comprises, from top to bottom: The system comprises a first contact layer (231), a first absorption layer (232), a first barrier layer (233), and a second contact layer (234); wherein, The upper surface of the second contact layer (234) is exposed in the common electrode area to form a connection interface for ohmic contact.

8. The chip according to claim 1, characterized in that, The second detector wafer (3) comprises, from top to bottom: The second detector substrate (31), the second etch stop layer (32), and the second detector epitaxial layer (33); wherein, The second detector substrate (31) and the second etch stop layer (32) constitute the substrate of the second detector wafer (3).

9. The chip according to claim 7, characterized in that, The second detector epitaxial layer (33) comprises, from top to bottom: The third contact layer (331), the second barrier layer (332), the second absorption layer (333), and the fourth contact layer (334).

10. The chip according to claim 1, characterized in that, The heterogeneous integrated wafer is divided into multiple independent single-chip dual-color infrared focal plane array.

Images