A micro display device and a method of fabricating the same

Abstract

This application provides a microdisplay device and its fabrication method, relating to the field of semiconductor technology. The method includes providing a substrate structure and grinding the back side of the substrate structure to ensure that the warpage of the substrate structure is within a threshold range; sequentially depositing an ohmic contact layer, a reflective layer, and a suppressor layer on the substrate structure; annealing the substrate structure in an oxygen-containing gas atmosphere; sequentially depositing a diffusion barrier layer and a protective layer on the suppressor layer; and etching along the stacking direction from the edge of the protective layer into the substrate structure to create a convex step structure with the center of the substrate structure protruding. The ohmic contact layer, reflective layer, suppressor layer, diffusion barrier layer, and protective layer are all located on the protruding step surface of the substrate structure. An ohmic contact layer is disposed between the reflective layer and the substrate structure, and annealed in an oxygen-containing gas atmosphere. The thermal annealing process is optimized to improve the ohmic contact performance and the light transmittance of the ohmic contact layer, thereby improving the electrical injection efficiency and light extraction efficiency of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a micro-display device and its fabrication method. Background Technology

[0002] The excellent physicochemical properties of GaN-based semiconductor materials have led to their wide application in optoelectronic devices and have enabled large-scale industrialization. Currently, however, p-type GaN and p-type AlGaN materials suffer from poor contact performance with metal electrode materials, severely hindering carrier transport at the metal-semiconductor interface, thus impeding current injection and reducing the device's electro-injection efficiency. Summary of the Invention

[0003] The purpose of this application is to provide a micro-display device and its fabrication method, which can effectively improve ohmic contact performance and reflectivity, and enhance the device's electrical injection efficiency and light extraction efficiency.

[0004] One aspect of this application provides a micro-display device, comprising: A substrate structure is provided, and the back side of the substrate structure is ground to make the warpage of the substrate structure within a threshold range; wherein the substrate structure includes a substrate, and a first semiconductor layer, a quantum well structure and a second semiconductor layer disposed on the substrate; An ohmic contact layer, a reflective layer, and an inhibitory layer are sequentially deposited on the substrate structure; Annealing in an oxygen-containing gaseous atmosphere; A diffusion barrier layer and a protective layer are sequentially deposited on the inhibition layer; The protective layer is etched into the substrate structure along the stacking direction from the edge of the protective layer to make the middle of the substrate structure protrude to form a convex step structure. The ohmic contact layer, the reflective layer, the suppression layer, the diffusion barrier layer and the protective layer form an electrode, which is located on the first semiconductor layer and the second semiconductor layer.

[0005] Optionally, the thickness of the substrate structure along the stacking direction before grinding is ≥550µm and ≤750µm, and the warpage of the substrate structure after grinding is ≤10µm.

[0006] Optionally, the method further includes providing a substrate structure and grinding the back surface of the substrate structure to ensure that the warpage of the substrate structure is within a threshold range, after which the method comprises: The ground substrate structure was subjected to organic ultrasonic cleaning, inorganic cleaning, deionized water cleaning, and nitrogen drying in sequence. The cleaned and dried substrate structure is then immersed in hydrochloric acid solution and ammonium fluoride solution in sequence to perform surface treatment on the substrate structure surface.

[0007] Optionally, the step of sequentially depositing an ohmic contact layer, a reflective layer, and a suppressive layer on the substrate structure includes: A first nickel layer is deposited on the substrate structure as the ohmic contact layer; A silver layer is deposited on the first nickel layer as the reflective layer; A second nickel layer is deposited on the silver layer as the suppression layer; along the stacking direction, the thickness of the ohmic contact layer is ≥0.1 nm, the thickness of the reflective layer is ≥10 nm, and the thickness of the suppression layer is ≥1 nm.

[0008] Optionally, the annealing treatment in an oxygen-containing gas atmosphere includes: Annealing temperature ≥350℃ and ≤700℃, annealing time ≥10s and ≤10min.

[0009] Optionally, the step of sequentially depositing a diffusion barrier layer and a protective layer on the inhibition layer includes: A titanium layer, a third nickel layer, or a platinum layer is deposited on the inhibition layer as the diffusion barrier layer; A gold layer is deposited on the diffusion barrier layer as the protective layer; the thickness of both the diffusion barrier layer and the protective layer is ≥5 nm along the stacking direction.

[0010] Optionally, the etching along the stacking direction from the edge of the protective layer into the substrate structure causes the center of the substrate structure to bulge out to form a U-shaped step structure. The ohmic contact layer, the reflective layer, the suppression layer, the diffusion barrier layer, and the protective layer form electrodes, which are located on the first semiconductor layer and the second semiconductor layer, including: Photoresist is coated onto the gold layer; After photolithography and development, the photoresist is used as a mask, and ion beam etching is used to etch it into the substrate structure to form the convex step structure.

[0011] Optionally, the etching along the stacking direction from the edge of the protective layer into the substrate structure causes the center of the substrate structure to bulge out to form a U-shaped step structure. The ohmic contact layer, the reflective layer, the suppression layer, the diffusion barrier layer, and the protective layer form electrodes, which are located on the first semiconductor layer and the second semiconductor layer. The method then further includes: The photoresist was removed by sequentially soaking in N-methylpyrrolidone and then by ultrasonication. The sidewalls of the convex-shaped step structure were repaired by soaking in potassium hydroxide solution.

[0012] In another aspect of this application, a microdisplay device is provided, which is fabricated using the above-described microdisplay device fabrication method. The device includes: a substrate structure comprising a substrate, on which a first semiconductor layer, a quantum well structure, a second semiconductor layer, and at least one light-emitting unit are disposed. The substrate structure forms a stepped structure with a central convex U-shape. The second semiconductor layer and the quantum well structure are located on the convex stepped structure. The first semiconductor layer extends beyond the stepped structure onto the substrate. Electrodes are disposed on both the first and second semiconductor layers. Each electrode comprises an ohmic contact layer, a reflective layer, a suppressor layer, a diffusion barrier layer, and a protective layer stacked sequentially.

[0013] Optionally, the ohmic contact layer includes a first nickel layer, the reflective layer includes a silver layer, the suppression layer includes a second nickel layer, the diffusion barrier layer includes at least one of a titanium layer, a third nickel layer, a platinum layer, and a chromium layer, and the protective layer includes a gold layer.

[0014] The micro-display device and its fabrication method provided in this application embodiment provide an ohmic contact layer between the reflective layer and the substrate structure, and perform annealing treatment in an oxygen-containing gas atmosphere. The thermal annealing process is optimized to improve the ohmic contact performance and the light transmittance of the ohmic contact layer, thereby improving the electrical injection efficiency and light extraction efficiency of the device. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figures 1a-1e This is a schematic diagram of the fabrication method of the micro-display device provided in this embodiment; Figures 2-7 This is a schematic diagram of the fabrication process of the micro-display device provided in this embodiment; Figure 8 This is one of the structural schematic diagrams of the microdisplay device provided in this embodiment; Figure 9 This is the second schematic diagram of the structure of the microdisplay device provided in this embodiment.

[0017] Icons: 10A - Substrate structure; 10 - Substrate; 101 - Buffer layer; 102 - Third semiconductor layer; 103 - First semiconductor layer; 104 - Quantum well structure; 105 - Second semiconductor layer; 106 - Insulating layer; 107 - Current spreading layer; 108 - Electrode layer; 11 - Ohmic contact layer; 12 - Reflective layer; 13 - Suppression layer; 14 - Diffusion barrier layer; 15 - Protective layer; 16 - Photoresist; 21 - Metal bump; 22 - Light-emitting unit; 23 - Driving substrate; F - Stacking direction; F1 - First direction. Detailed Implementation

[0018] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0019] In the description of this application, it should be noted that the terms "inner" and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0020] It should also be noted that, unless otherwise explicitly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0021] Currently, the poor contact performance between p-type GaN and p-type AlGaN materials and metal electrode materials severely hinders carrier transport at the metal-semiconductor interface, resulting in impeded current injection. Furthermore, the low reflectivity of the electrodes reduces the device's electrical injection efficiency. Simultaneously, a significant amount of electrical energy is converted into heat at the contact interface, causing changes in device operating parameters, thermal stability, and reduced lifespan. The poor ohmic contact performance between p-type GaN and p-type AlGaN and the electrodes is a major factor hindering the further development of GaN-based semiconductor devices. Researching the metal-semiconductor contact characteristics of p-type (Al)GaN materials with metal electrodes and achieving high-quality ohmic contact between p-type (Al)GaN materials and metal electrodes is of great significance for improving the operating efficiency, reliability, and lifespan of GaN-based semiconductor devices.

[0022] In addition to good ohmic contact performance, optoelectronic devices such as silicon-based solar electrodes, flip-chip LEDs, photodetectors and sensors, and vertical-cavity surface-emitting lasers also require electrodes with high reflectivity to improve light extraction efficiency. However, since the design of micro-display devices must first consider good ohmic contact performance, the contact layer metal will have a serious light absorption problem, and it is difficult to balance reflectivity. Therefore, the existing GaN-based P electrodes generally have the problem of low reflectivity.

[0023] Finally, yield is one of the most critical variables affecting manufacturing costs. Improving yield directly translates to lower costs for scrap, rework, and warranty, thereby optimizing the cost structure per unit and significantly expanding profit margins. Lift-off fabrication of metal electrode materials is currently the main process. However, GaN-based P electrodes suffer from poor adhesion between the contact material and GaN, leading to metal peeling issues during the peeling process, which severely restricts product yield and mass production.

[0024] Ag is a commonly used material for electrode reflectors, and it has the highest reflectivity in the visible light range. However, its contact performance with high work function semiconductor materials such as P-type GaN is poor. In addition, Ag has poor adhesion and is prone to peeling during the peeling process when in direct contact with semiconductor materials. Finally, Ag has poor thermal stability and is prone to diffusion in high-temperature processes, which can cause device leakage or even short circuits.

[0025] Therefore, researching micro-display devices that combine low specific contact resistivity, high reflectivity, and high yield is of great significance for improving the working efficiency, reliability, lifespan, and mass production of solid-state optoelectronic devices.

[0026] In view of this, to solve the above problems, please refer to Figure 1a As shown in the figure, this application provides a method for fabricating a micro-display device, the method comprising: like Figure 2 As shown, step 200: Provide a substrate structure 10A and grind the back side of the substrate structure 10A so that the warpage of the substrate structure 10A is within a threshold range.

[0027] For example, this application takes a blue light epitaxial wafer with sapphire as the substrate structure 10A as an example. The substrate structure 10A provides a substrate for the growth of GaN. The initial thickness of the substrate structure 10A along the stacking direction F is ≥550um and ≤750um. For example, the thickness of the substrate structure 10A is about 650um. When the surface warpage is >50um and shows a trend of being high in the middle and low at the edges, it has a significant impact on the heat uniformity during the annealing of micro-display devices.

[0028] Therefore, this application reduces the warpage of the substrate structure 10A by grinding. Generally, by grinding to thin the back side of the substrate structure, the warpage of the thinned substrate structure 10A is ≤10µm, making the surface of the substrate structure 10A flat and ensuring that the substrate structure 10A is heated uniformly during the annealing process.

[0029] Among them, such as Figure 8 As shown, the substrate structure 10A includes a substrate 10, and a first semiconductor layer 103, a quantum well structure 104, and a second semiconductor layer 105 disposed on the substrate 10.

[0030] The ground substrate structure 10A was subjected to organic ultrasonic cleaning, inorganic cleaning, deionized water cleaning, and nitrogen drying in sequence.

[0031] Specifically, during epitaxial growth and subsequent storage and transportation, contaminants such as particles, chemicals, metal ions, and bacteria can adhere to the surface of GaN. The presence of these contaminants hinders close contact between the metal and the semiconductor, affecting ohmic contact performance. Therefore, they need to be removed to maintain the cleanliness of the GaN surface. This application cleans the surface of the substrate structure 10A using organic ultrasonic cleaning, inorganic cleaning, deionized water cleaning, and nitrogen drying.

[0032] Then, the cleaned and dried substrate structure 10A is sequentially immersed in hydrochloric acid solution and ammonium fluoride solution to perform surface treatment on the surface of substrate structure 10A.

[0033] Because a thin insulating layer of about 2 nm forms on the bare GaN surface in air, the barrier height increases by about 0.2 eV to 0.3 eV, resulting in a strong increase in specific contact resistivity. Therefore, the substrate 10A needs to be surface-treated to remove this insulating layer before depositing metal on the substrate 10A.

[0034] This application removes the aforementioned insulating layer by first immersing the substrate structure 10A in a hydrochloric acid solution and then immersing it in an ammonium fluoride solution, thereby making the surface of the substrate structure 10A smooth.

[0035] like Figure 3 As shown, step 201: An ohmic contact layer 11, a reflective layer 12, and an inhibitory layer 13 are sequentially deposited on the substrate structure 10A.

[0036] For example, this application uses electron beam deposition to prepare metals.

[0037] like Figure 1b As shown, step 201-1: deposit a first nickel layer as an ohmic contact layer 11 on the substrate structure 10A. For example, the thickness of the first nickel layer is ≥0.1 nm.

[0038] Step 201-2: Deposit a silver layer on the first nickel layer as a reflective layer 12. For example, the thickness of the silver layer is ≥10 nm.

[0039] Step 201-3: Deposit a second nickel layer on the silver layer as a suppression layer 13. For example, the thickness of the second nickel layer is ≥1 nm. In this application, thickness refers to the dimension in the stacking direction F.

[0040] The first nickel layer is used as an ohmic contact layer 11, which is attached to the substrate structure 10A to suppress the diffusion of the silver layer during the subsequent high-temperature annealing process. After annealing, the first nickel layer will form NiOX (nickel oxide), which is a transparent material and does not affect the reflectivity.

[0041] In some embodiments, the thickness of the first nickel layer is ≥0.1 nm and ≤10 nm. A thinner first nickel layer can improve the reflectivity of the silver layer.

[0042] The second nickel layer also serves as an adhesion layer metal to suppress the diffusion of the silver layer during the high-temperature annealing process.

[0043] like Figure 4 As shown, step 202: Annealing treatment in a gaseous atmosphere containing oxygen.

[0044] This application employs rapid thermal annealing for two main purposes: First, to achieve close contact between metal atoms and semiconductors at the atomic scale. To ensure good conductivity, the metal is tightly fused to the wafer surface after heat treatment at 350°C. Second, rapid thermal annealing is necessary to promote chemical reactions between metals and between metals and semiconductors. This is crucial for forming chemicals with low resistance and for creating highly doped layers at the contact interface, ultimately determining whether an ohmic contact with excellent properties can be formed.

[0045] This application involves annealing in an oxygen-containing gas atmosphere at an annealing temperature ≥350℃ and ≤700℃, and for an annealing time ≥10s and ≤10min.

[0046] like Figure 5 As shown, step 203: deposit a diffusion barrier layer 14 and a protective layer 15 sequentially on the inhibition layer 13.

[0047] Also using electron beams, such as Figure 1c As shown, step 203-1: deposit at least one of a titanium layer, a third nickel layer, a platinum layer and a chromium layer on the inhibition layer 13 as a diffusion barrier layer 14; Step 203-2: Deposit a gold layer on the diffusion barrier layer 14 as a protective layer 15.

[0048] Along the stacking direction F, the thickness of both the diffusion barrier layer 14 and the protective layer 15 is ≥5nm.

[0049] The diffusion barrier layer 14 is used to block the electromigration of the silver and gold layers; it can also serve as a protective metal layer 15 to prevent the etching process from affecting the electrode contact interface.

[0050] The protective layer 15 is used to isolate water and oxygen and to prevent the etching process from affecting the electrode contact interface.

[0051] like Figure 6 , Figure 7 As shown, in step 204: the protective layer 15 is etched into the substrate structure 10A along the stacking direction F from the edge of the protective layer 15, so that the middle of the substrate structure 10A protrudes to form a convex step structure. The ohmic contact layer 11, the reflective layer 12, the suppression layer 13, the diffusion barrier layer 14 and the protective layer 15 form an electrode, which is located on the first semiconductor layer and the second semiconductor layer of the substrate structure 10A.

[0052] like Figure 1d As shown, step 204-1: Coat the gold layer with photoresist 16; Step 204-2: After photolithography and development, using photoresist 16 as a mask, ion beam etching is used to etch the material into the substrate structure 10A to form a convex step structure.

[0053] The purpose of photolithography is to transfer the designed pattern on the mask onto the photoresist 16 to prepare for the next step of etching. In this application, the photoresist 16 is used as a mask for etching.

[0054] Using IBE (ion beam etching) to simultaneously etch the metal and substrate structure 10A, achieving integrated etching, has the following advantages: First, a single photolithography etching process can fabricate both the Mesa step (a step structure of a specific height) and the P electrode (multilayer metal layers as the P electrode); second, since the P electrode has been annealed before etching, the leakage problem of Ag-based electrodes prepared by the lift-off process under high-temperature processes is significantly improved; third, the P electrode and the Mesa step are the same size along the first direction F1 (perpendicular to the stacking direction F), which increases the contact area and reflection area of ​​the P electrode, improves the electrical injection efficiency and light extraction efficiency, and is particularly suitable for Micro-led products.

[0055] like Figure 1e As shown, step 205: The photoresist 16 is removed by immersion in N-methylpyrrolidone (NMP) and by ultrasonication.

[0056] This invention employs a combination of NMP high-temperature immersion and ultrasonic removal. NMP effectively swells and breaks down the 16 molecular chains of photoresist, while high temperature (e.g., 60°C) accelerates molecular motion and improves dissolution efficiency. Ultrasonic waves generate microbubbles through cavitation, and their bursting releases energy to disrupt the colloidal structure. Ultrasonic vibration also allows the cleaning solution to penetrate into the gaps between components, enhancing the cleaning effect. This application combines these two methods for highly efficient photoresist removal.

[0057] Step 206: Soak in potassium hydroxide (KOH) solution to repair the sidewalls of the convex step structure.

[0058] The sidewalls of the etched Mesa were repaired by immersing the device in a heated KOH solution. The Ag-based multilayer metal microdisplay device of this application is resistant to KOH solution corrosion, and the sidewalls are repaired without damaging the overall microdisplay device.

[0059] The microdisplay device fabrication method provided in this application involves inserting a first nickel layer as an ohmic contact layer 11 between the reflective layer 12 and the P-type GaN cross-section (substrate structure 10A), and optimizing the thermal annealing process to improve the ohmic contact performance, thereby addressing the poor contact performance between the Ag electrode and the P-type GaN material. Simultaneously, the annealing process is optimized to enhance the reflectivity of the Ag-based electrode, preventing the Ag-based electrode's reflection from decreasing due to light absorption by the ohmic contact layer 11. A diffusion barrier layer 14 and a protective layer 15 are provided to address the poor thermal stability and electromigration issues of the Ag-based electrode. This application employs an integrated etching process instead of the existing lift-off process, resolving leakage and metal peeling issues under the Ag-based electrode lift-off process, as well as the complexity of the process and the existence of edge sacrifice regions when using the lift-off process for Ag-based multilayer metal microdisplay devices. This application also employs a pre-grinding followed by annealing method to improve annealing uniformity and yield, thereby mitigating the problem of uneven heat distribution during annealing caused by the uneven surface of the GaN-based epitaxial wafer.

[0060] The method for fabricating micro-display devices provided in this application embodiment can provide micro-display devices with low specific contact resistivity, high reflectivity, good thermal stability and yield. It can significantly improve the photoelectric conversion efficiency of optoelectronic devices, has high process redundancy, wide applicability, and is safe and reliable. It solves the problems of poor ohmic contact performance, leakage current, poor thermal stability and low yield that occur when using single-layer metal Ag for P-type GaN electrodes.

[0061] The preparation method described above will be specifically illustrated below through different examples: In Example 1, NiAgNiTiAu (1nm / 100nm / 2nm / 50nm / 75nm) was used as the metal layer of the micro-display device.

[0062] Preparation method: 1. Grinding: Grinding reduces the thickness by 50µm and decreases surface warpage.

[0063] 2. Epitaxial wafer cleaning: The epitaxial wafer surface is cleaned by acetone at level 7 with organic ultrasonic cleaning for 10 minutes, immersion in piranha solution for 10 minutes, rinsing with deionized water, and drying with nitrogen.

[0064] 3. Surface treatment: Soak in hydrochloric acid solution for 2 minutes, then soak in ammonium fluoride solution for 2 minutes.

[0065] 4. Metal deposition: Metals were prepared using electron beam deposition. First, a 1 nm layer of Ni was deposited, followed by a 100 nm layer of Ag, and finally a 2 nm layer of Ni was deposited.

[0066] 5. Rapid thermal annealing: Anneal at 450℃ for 4 minutes in an air atmosphere.

[0067] 6. Metal deposition: Electron beam deposition was used to continue metal deposition. First, a 50 nm Ti layer was deposited, followed by a 75 nm Au layer to complete the metal deposition.

[0068] 7. Photolithography: Etching is performed using photoresist 16 as a mask.

[0069] 8. Metal-in-metal etching: IBE is used to simultaneously etch metal and GaN.

[0070] 9. Adhesive removal: Adhesive is removed by high-temperature immersion in NMP and ultrasonic treatment.

[0071] 10. Sidewall repair: Soak in 50% KOH solution at 60℃ for 20 minutes.

[0072] In Example 2, NiAgNiNiAu (1nm / 100nm / 2nm / 50nm / 75nm) was used as the metal layer of the micro-display device.

[0073] Preparation method: 1. Grinding: Grinding reduces the thickness by 50µm and decreases surface warpage.

[0074] 2. Epitaxial wafer cleaning: The epitaxial wafer surface is cleaned by acetone at level 7 with organic ultrasonic cleaning for 10 minutes, immersion in piranha solution for 10 minutes, rinsing with deionized water, and drying with nitrogen.

[0075] 3. Surface treatment: Soak in hydrochloric acid solution for 2 minutes, then soak in ammonium fluoride solution for 2 minutes.

[0076] 4. Metal deposition: Metals were prepared using electron beam deposition. First, a 1 nm layer of Ni was deposited, followed by a 100 nm layer of Ag, and finally a 2 nm layer of Ni was deposited.

[0077] 5. Rapid thermal annealing: Anneal at 450℃ for 4 minutes in an air atmosphere.

[0078] 6. Metal deposition: Electron beam deposition was used to continue metal deposition. First, a 50 nm layer of Ni was deposited, followed by a 75 nm layer of Au to complete the metal deposition.

[0079] 7. Photolithography: Etching is performed using photoresist 16 as a mask.

[0080] 8. Metal-on-metal etching: IBE is used to simultaneously etch metal and GaN. 9. Adhesive removal: Adhesive is removed by high-temperature immersion in NMP and ultrasonic treatment.

[0081] 10. Sidewall repair: Soak in 50% KOH solution at 60℃ for 20 minutes.

[0082] In Example 3, NiAgNiPtAu (1nm / 200nm / 2nm / 50nm / 75nm) was used as the metal layer of the micro-display device.

[0083] Preparation method: 1. Grinding: Grinding reduces the thickness by 50µm and decreases surface warpage.

[0084] 2. Epitaxial wafer cleaning: The epitaxial wafer surface is cleaned by acetone at level 7 with organic ultrasonic cleaning for 10 minutes, immersion in piranha solution for 10 minutes, rinsing with deionized water, and drying with nitrogen.

[0085] 3. Surface treatment: Soak in hydrochloric acid solution for 2 minutes, then soak in ammonium fluoride solution for 2 minutes.

[0086] 4. Metal deposition: Metals were prepared using electron beam deposition. First, a 1 nm layer of Ni was deposited, followed by a 200 nm layer of Ag, and finally a 2 nm layer of Ni was deposited.

[0087] 5. Rapid thermal annealing: Anneal at 450℃ for 4 minutes in an air atmosphere.

[0088] 6. Metal deposition: Electron beam deposition was used to continue metal deposition. First, a 50 nm layer of Pt was deposited, followed by a 75 nm layer of Au to complete the metal deposition.

[0089] 7. Photolithography: Etching is performed using photoresist 16 as a mask.

[0090] 8. Metal-on-metal etching: IBE is used to simultaneously etch metal and GaN. 9. Adhesive removal: Adhesive is removed by high-temperature immersion in NMP and ultrasonic treatment.

[0091] 10. Sidewall repair: Soak in 50% KOH solution at 60℃ for 20 minutes.

[0092] Based on this, please refer to Figure 8 As shown in the embodiments of this application, a micro-display device is also disclosed, which is fabricated using any of the above-mentioned micro-display device fabrication methods. It includes a substrate structure 10A, which forms a convex U-shaped step structure in the middle. The substrate structure 10A includes a substrate 10, and a first semiconductor layer 103, a quantum well structure 104, and a second semiconductor layer 105 disposed on the substrate 10. The second semiconductor layer 105 and the quantum well structure 104 are located on the convex step structure. The first semiconductor layer 103 extends to the substrate 10 outside the step structure and is exposed. Electrodes are disposed on both the first semiconductor layer 103 and the second semiconductor layer 105. The electrodes include an ohmic contact layer 11, a reflective layer 12, a suppression layer 13, a diffusion barrier layer 14, and a protective layer 15 stacked sequentially.

[0093] The ohmic contact layer 11 includes a first nickel layer, the reflective layer 12 includes a silver layer, the inhibition layer 13 includes a second nickel layer, the diffusion barrier layer 14 includes at least one of a titanium layer, a third nickel layer, a platinum layer, and a chromium layer, and the protective layer 15 includes a gold layer.

[0094] In addition, at least one light-emitting unit 22 is provided on the substrate structure 10A. The light-emitting unit 22 independently generates controllable light signals, thereby forming the basis for displaying images or information.

[0095] The microdisplay device also includes a third semiconductor layer 102, a buffer layer 101, a current spreading layer 107, an electrode layer 108, and an insulating layer 106. The current spreading layer 107 is disposed on the second semiconductor layer 105 and on the exposed first semiconductor layer 103. The electrode layer 108 is disposed on the current spreading layer 107, and the insulating layer 106 is located on the second semiconductor layer 105.

[0096] like Figure 9 As shown, it also includes metal bumps 21, which are bonded to the driving substrate 23 to provide electrical drive for the light-emitting unit, thus obtaining a micro display device.

[0097] The micro-display device provided in this application embodiment, through the design of Ag-based multilayer metal micro-display device, has good ohmic contact performance, high reflectivity, high process yield and good thermal stability.

[0098] Based on the optimized ohmic contact annealing process under an air atmosphere: it has excellent ohmic contact performance, high visible light reflectivity and good surface uniformity.

[0099] Compared to the lift-off process, the metal-integrated etching process for mesa fabrication completes both mesa etching and P-electrode fabrication in a single photolithography etching cycle, significantly reducing process complexity and cost. The P-electrode is the same size as the mesa electrode, providing a larger area for electrical injection and reflection, resulting in higher electrical injection and light extraction efficiency. Annealing before pixel fabrication significantly improves the thermal stability of the Ag-based electrode, resolving the leakage problem caused by thermal diffusion of Ag during annealing. The alloyed interfaces of the P-electrode layers after annealing exhibit high bonding strength, avoiding metal peeling during the stripping process and significantly improving yield.

[0100] The micro-display device of this application can be applied to optoelectronic devices such as silicon-based solar electrodes, flip-chip LEDs, photodetectors and sensors, and vertical-cavity surface-emitting lasers.

[0101] This microdisplay device has the same structure and beneficial effects as the fabrication method of the microdisplay device in the foregoing embodiments. The structure and beneficial effects of the fabrication method of the microdisplay device have been described in detail in the foregoing embodiments and will not be repeated here.

[0102] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a micro-display device, characterized in that, include: A substrate structure is provided, and the back side of the substrate structure is ground to make the warpage of the substrate structure within a threshold range; wherein the substrate structure includes a substrate, and a first semiconductor layer, a quantum well structure and a second semiconductor layer disposed on the substrate; An ohmic contact layer, a reflective layer, and an inhibitory layer are sequentially deposited on the substrate structure; Annealing in an oxygen-containing gaseous atmosphere; A diffusion barrier layer and a protective layer are sequentially deposited on the inhibition layer; The protective layer is etched into the substrate structure along the stacking direction from the edge of the protective layer to make the middle of the substrate structure protrude to form a convex step structure. The ohmic contact layer, the reflective layer, the suppression layer, the diffusion barrier layer and the protective layer form an electrode, which is located on the first semiconductor layer and the second semiconductor layer.

2. The method for fabricating a microdisplay device according to claim 1, characterized in that, Before grinding, the thickness of the substrate structure along the stacking direction is ≥550µm and ≤750µm, and after grinding, the warpage of the substrate structure is ≤10µm.

3. The method for fabricating a microdisplay device according to claim 1 or 2, characterized in that, The method involves providing a substrate structure and grinding the back surface of the substrate structure to ensure that the warpage of the substrate structure is within a threshold range. The method then includes: The ground substrate structure was subjected to organic ultrasonic cleaning, inorganic cleaning, deionized water cleaning, and nitrogen drying in sequence. The cleaned and dried substrate structure is then immersed in hydrochloric acid solution and ammonium fluoride solution in sequence to perform surface treatment on the substrate structure surface.

4. The method for fabricating a microdisplay device according to claim 1, characterized in that, The process of sequentially depositing an ohmic contact layer, a reflective layer, and a suppressive layer on the substrate structure includes: A first nickel layer is deposited on the substrate structure as the ohmic contact layer; A silver layer is deposited on the first nickel layer as the reflective layer; A second nickel layer is deposited on the silver layer as the suppression layer; along the stacking direction, the thickness of the ohmic contact layer is ≥0.1 nm, the thickness of the reflective layer is ≥10 nm, and the thickness of the suppression layer is ≥1 nm.

5. The method for fabricating a microdisplay device according to claim 4, characterized in that, The annealing process in an oxygen-containing gas atmosphere includes: Annealing temperature ≥350℃ and ≤700℃, annealing time ≥10s and ≤10min.

6. The method for fabricating a microdisplay device according to claim 4 or 5, characterized in that, The process of sequentially depositing a diffusion barrier layer and a protective layer on the inhibition layer includes: At least one of a titanium layer, a third nickel layer, a platinum layer, and a chromium layer is deposited on the suppression layer using an electron beam method as the diffusion barrier layer; A gold layer is deposited on the diffusion barrier layer as the protective layer; the thickness of both the diffusion barrier layer and the protective layer is ≥5 nm along the stacking direction.

7. The method for fabricating a microdisplay device according to claim 6, characterized in that, The protective layer is etched into the substrate structure along the stacking direction from its edge to form a U-shaped step structure, causing the center of the substrate structure to bulge out. The ohmic contact layer, the reflective layer, the suppression layer, the diffusion barrier layer, and the protective layer form electrodes, which are located on the first semiconductor layer and the second semiconductor layer. Photoresist is coated onto the gold layer; After photolithography and development, the photoresist is used as a mask, and ion beam etching is used to etch it into the substrate structure to form the convex step structure.

8. The method for fabricating a microdisplay device according to claim 7, characterized in that, The method involves etching along the stacking direction from the edge of the protective layer into the substrate structure, causing the center of the substrate structure to bulge out to form a U-shaped stepped structure. The ohmic contact layer, the reflective layer, the suppression layer, the diffusion barrier layer, and the protective layer form electrodes located on the first semiconductor layer and the second semiconductor layer. The method then further includes: The photoresist was removed by sequentially soaking in N-methylpyrrolidone and then by ultrasonication. The sidewalls of the convex-shaped step structure were repaired by soaking in potassium hydroxide solution.

9. A microdisplay device, fabricated using the method for fabricating a microdisplay device according to any one of claims 1 to 8, characterized in that, The invention includes a substrate structure comprising a substrate on which a first semiconductor layer, a quantum well structure, a second semiconductor layer, and at least one light-emitting unit are disposed. The substrate structure forms a stepped structure with a central convex shape. The second semiconductor layer and the quantum well structure are located on the convex stepped structure. The first semiconductor layer extends onto the substrate beyond the stepped structure. Electrodes are disposed on both the first and second semiconductor layers. Each electrode comprises an ohmic contact layer, a reflective layer, a suppressive layer, a diffusion barrier layer, and a protective layer stacked sequentially.

10. The microdisplay device according to claim 9, characterized in that, The ohmic contact layer includes a first nickel layer, the reflective layer includes a silver layer, the inhibition layer includes a second nickel layer, the diffusion barrier layer includes at least one of a titanium layer, a third nickel layer, a platinum layer, and a chromium layer, and the protective layer includes a gold layer.

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