A schottky diode and a method of manufacturing the same
By forming a first P+ layer and a second P+ layer in a Schottky diode and adjusting their concentration and depth, the problem of improving forward characteristics within a limited device size was solved, and the effects of improving reverse characteristics and reducing device area were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JILIN SINO MICROELECTRONICS CO LTD
- Filing Date
- 2022-03-22
- Publication Date
- 2026-06-23
Smart Images
Figure CN114664923B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a Schottky diode and a manufacturing method thereof. BACKGROUND
[0002] MPS diode (Merged PIN Schottky Diode) has been widely used due to its good switching characteristics, high blocking voltage, low leakage current of PiN diode, small opening voltage, large conduction current and high switching speed of SBD and other advantages.
[0003] For the Schottky diode of MPS structure, the forward characteristic of the device is an important indicator to measure its performance. Generally speaking, the forward characteristic has relevance with the device size. Therefore, how to effectively improve the forward characteristic of the MPS diode within the limited device size range is an important direction that the technical personnel in the field have been committed to research. SUMMARY
[0004] Based on the above, the present application provides a Schottky diode and a manufacturing method thereof, which can effectively improve the reverse characteristic of the device under the premise of making the device area as small as possible.
[0005] First, in a first aspect, the embodiments of the present application provide a Schottky diode, comprising:
[0006] a substrate;
[0007] a first epitaxial layer located on the substrate, the first epitaxial layer having a first P+ layer therein, the first P+ layer comprising a plurality of first P+ regions spaced apart from each other;
[0008] a second epitaxial layer located on the first epitaxial layer, the second epitaxial layer having a second P+ layer therein, the second P+ layer comprising a plurality of second P+ regions spaced apart from each other; wherein the first P+ regions on opposite sides of the first P+ layer are in contact with the second P+ regions on opposite sides of the second P+ layer, respectively;
[0009] a contact metal layer located on a side of the second epitaxial layer away from the first epitaxial layer, the contact metal layer forming a Schottky contact with a barrier region of the Schottky diode and forming an Ohmic contact with the second P+ regions.
[0010] In an optional embodiment of the present application, the Schottky diode further comprises:
[0011] an electrode metal layer located on a side of the contact metal layer away from the second epitaxial layer.
[0012] In an alternative implementation of the embodiment of the application, the thickness of the contact metal layer is less than 1000 angstroms, and the thickness of the electrode metal layer is greater than 40000 angstroms.
[0013] In an alternative implementation of the embodiment of the application, the thickness of the second epitaxial layer is less than the thickness of the first epitaxial layer.
[0014] In an alternative implementation of the embodiment of the application, the thickness of the first epitaxial layer is 4-4.5 microns, and the thickness of the second epitaxial layer is 0.8-1.2 microns.
[0015] In a second aspect, the embodiment of the application also provides a method for manufacturing a Schottky diode, which comprises:
[0016] forming a first epitaxial layer on the surface of the substrate;
[0017] performing selective impurity implantation on the first epitaxial layer to form a first P+ layer with a plurality of first P+ regions arranged at intervals;
[0018] forming a second epitaxial layer on the side of the first epitaxial layer away from the substrate;
[0019] performing selective impurity implantation on the second epitaxial layer to form a second P+ layer with a plurality of second P+ regions arranged at intervals, and making the second P+ regions on the opposite sides of the second P+ layer respectively contact the first P+ regions on the opposite sides of the first P+ layer to form a PIN diode part of the Schottky diode;
[0020] forming a silicide dielectric layer on the side of the second epitaxial layer away from the substrate, and removing the silicide dielectric layer in the areas corresponding to the barrier region and the P+ region of the Schottky diode to form a metal contact hole;
[0021] forming a contact metal layer through the metal contact hole, which forms Schottky contact with the barrier region and ohmic contact with the second P+ region.
[0022] In an alternative implementation of the embodiment of the application, the method further comprises:
[0023] forming an electrode metal layer on the side of the contact metal layer away from the substrate.
[0024] In an alternative implementation of the embodiment of the application, forming a contact metal layer through the metal contact hole comprises:
[0025] adopting a sputtering method to sputter a first metal target through the metal contact hole to the surface of the second epitaxial layer to form the contact metal layer;
[0026] forming an electrode metal layer on a side of the contact metal layer away from the substrate, comprising:
[0027] sputtering a second metal target on a surface of the contact metal layer to form the electrode metal layer by a sputtering method.
[0028] In an alternative embodiment of the present application, the method further comprises:
[0029] forming a barrier silicide on a surface of the second epitaxial layer by a rapid thermal processing method or a furnace annealing method between the first metal of the contact metal layer and the second metal of the electrode metal layer.
[0030] In an alternative embodiment of the present application, the method further comprises:
[0031] performing a thinning process on a side of the substrate away from the first epitaxial layer, and then depositing a back metal on the side of the thinned substrate.
[0032] Compared with the prior art, the Schottky diode and the manufacturing method thereof provided by the present application can realize the forward conduction of the PIN diode and improve the forward characteristics of the Schottky diode by forming the first P+ layer and the second P+ layer, and adjusting the concentration and depth of the first P+ layer and the second P+ layer. For example, the first P+ layer can be used as a deepened P region of the PIN diode. When the second P+ layer is reverse biased, the second P+ region of the second P+ layer introduced can form an extension of the depletion region of the PN junction in the reverse blocking state, and can play an electric field shielding effect, thereby reducing the surface electric field strength at the Schottky junction, reducing the leakage current dominated by the hot electron emission and tunneling current, and improving the reverse characteristics of the device. At the same time, by reducing the lateral size of the P+ region and increasing the longitudinal depth, the device area can be smaller under the same forward PN junction injection. BRIEF DESCRIPTION OF DRAWINGS
[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be considered as limiting the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.
[0034] Figure 1 is a schematic diagram of a Schottky diode provided by an embodiment of the present application.
[0035] Figures 2-8 is a schematic diagram of the structure change of the Schottky diode in each process step of a manufacturing method of the Schottky diode provided by an embodiment of the present application. Detailed Implementation
[0036] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0037] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0038] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0039] In the description of this application, it should be understood that the terms "upper", "lower", "inner", "outer", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are used only for the convenience of describing this application and simplifying the description, and are not intended to indicate or imply that the equipment or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0040] Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0041] In the description of this application, it should also be noted that, unless otherwise explicitly specified and limited, terms such as "setup" and "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0042] Based on the technical problems mentioned in the background section, in order to improve the termination efficiency of Schottky diodes, this application provides a Schottky diode and a method for manufacturing the same. The specific embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0043] <First Embodiment>
[0044] First, such as Figure 1 The diagram shown is one of the structural schematic diagrams of a Schottky diode provided in the first embodiment of this application. It includes a substrate 100, a first epitaxial layer 210 on the substrate 100, and a second epitaxial layer 220 on the first epitaxial layer 210. The first epitaxial layer 210 has a first P+ layer, which includes a plurality of first P+ regions 211 spaced apart from each other. The second epitaxial layer 220 has a second P+ layer, which includes a plurality of second P+ regions 221 spaced apart from each other. The first P+ regions 211 on opposite sides of the first P+ layer contact the second P+ regions 221 on opposite sides of the second P+ layer to form the PIN diode portion of the Schottky diode.
[0045] In this embodiment, the first epitaxial layer 210 and the second epitaxial layer 220 together form the entire epitaxial layer of the Schottky diode. The first P+ region 211 and the second P+ region 221 form the entire P+ region of the Schottky diode. The thickness of the second epitaxial layer 220 is less than the thickness of the first epitaxial layer 210. For example, the thickness of the first epitaxial layer 210 can be 4–4.5 micrometers, and the thickness of the second epitaxial layer 220 can be 0.8–1.2 micrometers. As a preferred example, the thickness of the first epitaxial layer 210 can be 4 micrometers, and the thickness of the second epitaxial layer 220 can be 1 micrometer.
[0046] Furthermore, the Schottky diode may also include a contact metal layer 400 located on the side of the second epitaxial layer 220 away from the first epitaxial layer 210. The contact metal layer 400 forms a Schottky contact with the barrier region of the Schottky diode and an ohmic contact with the second P+ region 221. The region located between the barrier region and the second P+ region 221 is also included.
[0047] Furthermore, in this embodiment, the Schottky diode may further include an electrode metal layer 500 located on the side of the contact metal layer 400 away from the second epitaxial layer 220. The thickness of the contact metal layer 400 is less than 1000 angstroms, and the thickness of the electrode metal layer 500 is greater than 40000 angstroms.
[0048] The Schottky diode may further include a barrier silicide (not shown) formed on the surface of the second epitaxial layer 220 by a rapid thermal treatment method or furnace annealing, whereby the first metal of the contact metal layer 400 and the second metal of the electrode metal layer 500 are formed. For example, the barrier silicide may be silicon dioxide, silicon carbide, or silicon oxide. Furthermore, in this embodiment, the Schottky diode may also include silicide dielectric layers 300 located at opposite ends of the second epitaxial layer 220 away from the first epitaxial layer 210 and covered by the contact metal layer 400. The barrier silicide may be formed in the region of the second epitaxial layer 220 located between the silicide dielectric layers 300.
[0049] <Second Embodiment>
[0050] Combination Figures 2-7 The following is an exemplary description of the method for manufacturing a Schottky diode provided in the second embodiment of this application.
[0051] The first process, for example Figure 2 As shown, a first epitaxial layer 210 is formed on the surface of the substrate 100.
[0052] The concentration of the first epitaxial layer 210 can be 1E15 CM-3, and the thickness can be 4 to 4.5 micrometers, preferably 4 micrometers.
[0053] The second process, such as Figure 3 As shown, selective impurity implantation is performed on the first epitaxial layer 210 to form a first P+ layer with a plurality of spaced first P+ regions 211.
[0054] In one alternative embodiment of this invention, impurities can be implanted from the side of the first epitaxial layer 210 away from the substrate 100 using a mask with a preset window pattern, thereby forming the first P+ region 211.
[0055] The third process, such as Figure 4 As shown, a second epitaxial layer 220 is formed on the side of the first epitaxial layer 210 away from the substrate 100. Simultaneously, selective impurity implantation is performed on the second epitaxial layer 220 to form a second P+ layer with a plurality of spaced second P+ regions 221, such that the second P+ regions 221 on opposite sides of the second P+ layer contact the first P+ regions 211 on opposite sides of the first P+ layer, thereby forming the PIN diode portion of the Schottky diode. The concentration of the second epitaxial layer 220 can be the same as, or substantially the same as, the concentration of the first epitaxial layer 210.
[0056] The fourth process, such as Figure 5 and Figure 6As shown, a silicide dielectric layer 300 is formed on the side of the second epitaxial layer 220 away from the substrate 100, and the silicide dielectric layer corresponding to the barrier region and P+ region of the Schottky diode is removed to form a metal contact hole 310.
[0057] The fifth process, such as Figure 7 As shown, a contact metal layer 400 is formed through the metal contact hole 310. The contact metal layer 400 forms a Schottky contact with the barrier region and an ohmic contact with the second P+ region 221. The barrier region is located between adjacent second P+ regions. In this embodiment, the contact metal layer 400 can be formed by sputtering a first metal target onto the surface of the second epitaxial layer 220 through the metal contact hole 310.
[0058] The sixth process, such as Figure 8 As shown, an electrode metal layer 500 is formed on the side of the contact metal layer 400 away from the substrate 100. In this embodiment, the thickness of the contact metal layer 400 is preferably less than 1000 angstroms, and the thickness of the electrode metal layer 500 is preferably greater than 40000 angstroms.
[0059] In this embodiment, the electrode metal layer 500 can be formed by sputtering a second metal target onto the surface of the contact metal layer 400.
[0060] Based on the above, the method provided in this example can also use a rapid heat treatment method or a furnace annealing method to form a barrier silicide on the surface of the second epitaxial layer 220 by the first metal of the contact metal layer 400 and the second metal of the electrode metal layer 500.
[0061] Following the above steps, in this embodiment, the side of the substrate 100 away from the first epitaxial layer 210 can be thinned (e.g., thinned to 180 micrometers), and then a back metal is deposited on the side of the thinned substrate 100 to form a back metal region.
[0062] In one possible implementation of this embodiment, the Schottky diode is an MPS silicon carbide Schottky diode. Generally, an MPS silicon carbide Schottky diode is a Schottky diode with a hybrid PIN structure on a silicon carbide substrate. When a large forward current is applied, the PIN diode conducts, reducing the on-state voltage drop and thus improving the device's forward characteristics. Furthermore, the forward turn-on voltage of a silicon carbide Schottky diode is approximately 0.8V, while that of a silicon carbide PIN diode is approximately 2.7V. This requires a larger current density and a wider P+ region, which is detrimental to chip size reduction.
[0063] Based on this, the Schottky diode and its manufacturing method provided in this application, by forming a first P+ layer and a second P+ layer, can ultimately achieve forward conduction of the PIN diode and improve the forward characteristics of the Schottky diode by adjusting the concentration and depth of the first P+ layer and the second P+ layer. For example, the first P+ layer can serve as a deeper P-region of the PIN diode. When the second P+ layer is reverse biased, the second P+ region 221 introduced by the second P+ layer expands the depletion region of the PN junction in the reverse blocking state, which can play an electric field shielding effect, reduce the surface electric field intensity at the Schottky, thereby reducing the leakage current dominated by thermionic emission and tunneling current, and improving the reverse characteristics of the device. At the same time, this structure, by reducing the lateral dimension of the P+ region and increasing the vertical depth, can achieve a smaller device area while maintaining the same forward PN junction injection.
[0064] For illustrative purposes, the foregoing description has been made with reference to specific embodiments. However, the foregoing illustrative discussions are not intended to be exhaustive or to limit the present application to the precise forms disclosed. Numerous modifications and variations are possible in accordance with the foregoing teachings. These embodiments were chosen and described to best illustrate the principles of the present application and its practical application, thereby enabling those skilled in the art to best utilize the present application and to employ various embodiments with different modifications to suit a particular intended application.
Claims
1. A Schottky diode, characterized in that, include: Base; A first epitaxial layer is located on the substrate, the first epitaxial layer having a first P+ layer, the first P+ layer including a plurality of first P+ regions spaced apart from each other; A second epitaxial layer is located on the first epitaxial layer, and the second epitaxial layer has a second P+ layer, the second P+ layer including a plurality of second P+ regions spaced apart from each other; wherein, the first P+ regions on opposite sides of the first P+ layer are respectively in contact with the second P+ regions on opposite sides of the second P+ layer. A silicide dielectric layer located on the side of the second epitaxial layer away from the substrate, the silicide dielectric layer having metal contact holes; A contact metal layer located on the side of the second epitaxial layer away from the first epitaxial layer, the contact metal layer forms a Schottky contact with the barrier region of the Schottky diode through the metal contact hole, and forms an ohmic contact with the second P+ region; The concentration of the second epitaxial layer is the same as that of the first epitaxial layer, the thickness of the second epitaxial layer is less than that of the first epitaxial layer, and the first P+ layer is the deepened P region of the diode.
2. The Schottky diode according to claim 1, characterized in that, Also includes: The electrode metal layer is located on the side of the contact metal layer away from the second epitaxial layer.
3. The Schottky diode according to claim 2, characterized in that, The thickness of the contact metal layer is less than 1000 angstroms, and the thickness of the electrode metal layer is greater than 40000 angstroms.
4. The Schottky diode according to claim 1, characterized in that, The thickness of the first epitaxial layer is 4 to 4.5 micrometers, and the thickness of the second epitaxial layer is 0.8 to 1.2 micrometers.
5. A method for manufacturing a Schottky diode, characterized in that, The method includes: A first epitaxial layer is formed on the surface of the substrate; Selective impurity implantation is performed on the first epitaxial layer to form a first P+ layer with a plurality of spaced first P+ regions; A second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate; Selective impurity implantation is performed on the second epitaxial layer to form a second P+ layer with a plurality of spaced second P+ regions, and the second P+ regions on opposite sides of the second P+ layer are respectively in contact with the first P+ regions on opposite sides of the first P+ layer to form the PIN diode portion of the Schottky diode. A silicide dielectric layer is formed on the side of the second epitaxial layer away from the substrate, and the silicide dielectric layer corresponding to the barrier region and P+ region of the Schottky diode is removed to form a metal contact hole; A contact metal layer is formed through the metal contact hole. The contact metal layer forms a Schottky contact with the barrier region through the metal contact hole and an ohmic contact with the second P+ region. The concentration of the second epitaxial layer is the same as that of the first epitaxial layer. The thickness of the second epitaxial layer is less than that of the first epitaxial layer. The first P+ layer is the deepened P region of the diode.
6. The method for manufacturing a Schottky diode according to claim 5, characterized in that, The method further includes: An electrode metal layer is formed on the side of the contact metal layer away from the substrate.
7. The method for manufacturing a Schottky diode according to claim 6, characterized in that, Forming a contact metal layer through the metal contact hole includes: The first metal target is sputtered onto the surface of the second epitaxial layer through the metal contact hole to form the contact metal layer; An electrode metal layer is formed on the side of the contact metal layer away from the substrate, comprising: The electrode metal layer is formed by sputtering a second metal target onto the surface of the contact metal layer.
8. The method for manufacturing a Schottky diode according to claim 7, characterized in that, The method further includes: A barrier silicide is formed on the surface of the second epitaxial layer by using a rapid heat treatment method or a furnace annealing method.
9. The method for manufacturing a Schottky diode according to any one of claims 5-8, characterized in that, The method further includes: The side of the substrate away from the first epitaxial layer is thinned, and then back metal is deposited on the side of the thinned substrate.