Sub-10 nm gate length ferroelectric transistor memory and compute-in-memory drive array and method of making the same

Abstract

This invention discloses a storage-computing-display driving array of sub-10 nanometer gate-length ferroelectric transistors and its fabrication method, relating to the field of display driving technology. The array structure includes a supporting substrate, vertical sub-10 nanometer gate-length ferroelectric transistors, and micro-light-emitting diodes (LEDs). The vertical sub-10 nanometer gate-length ferroelectric transistors serve as the driving units of the array, and the micro-LEDs serve as the light-emitting units. The light-emitting units and their corresponding driving units are directly stacked and integrated in the vertical direction. This invention natively integrates storage and computing functions into the display pixel unit, enabling in-situ data processing and feature extraction on the display module, thereby breaking through the physical bottleneck of data transport and opening up a new display strategy integrating storage, computing, and display.

Description

Technical Field

[0001] This invention relates to the field of display driving technology, and in particular to a memory-based display driving array of sub-10 nanometer gate-length ferroelectric transistors and its fabrication method. Background Technology

[0002] With the powerful penetration of artificial intelligence technology, intelligent displays are evolving from a one-way output medium to a smart window with computing and interactive capabilities. Currently, the application of intelligent displays is rapidly expanding into diverse scenarios such as travel, home, and office, deeply integrating into intelligent human-computer interaction and content presentation in areas ranging from in-vehicle augmented reality navigation to smart conferencing. At the same time, cutting-edge fields such as augmented reality, virtual reality devices, and wearable devices are placing higher demands on the miniaturization, high brightness, and low power consumption of display technology. However, the physical separation of storage, computing, and display units in traditional display driver architectures forces data to be frequently moved between different modules, resulting in high system latency, a sharp increase in power consumption, and limiting further reduction in pixel size. This architectural flaw not only makes it difficult to meet the growing demands for energy efficiency and high-speed visual processing but also restricts high-density, low-cost integrated storage-computing-display at the chip level, fundamentally failing to support the inherent requirements of next-generation intelligent displays for high contrast, high resolution, low power consumption, and native intelligence. Therefore, for those skilled in the art, how to natively integrate storage and computing functions into display pixel units to enable a new display approach integrating storage, computing, and display is an urgent problem to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a memory-based display driving array of sub-10 nanometer gate-length ferroelectric transistors and its fabrication method, so as to solve the problems mentioned in the background art and realize in-situ data processing and feature extraction on the display module.

[0004] To achieve the above objectives, the present invention provides the following solution: On one hand, a memory computing display driving array of sub-10 nanometer gate ferroelectric transistors is provided, including a supporting substrate, a vertical sub-10 nanometer gate ferroelectric transistor, and a Micro-LED; the vertical sub-10 nanometer gate ferroelectric transistor serves as the driving unit of the array, and the Micro-LED serves as the light-emitting unit of the array; the light-emitting unit and the corresponding driving unit are directly stacked and integrated in the vertical direction.

[0005] Preferably, the vertical sub-10 nanometer gate ferroelectric transistor includes a first insulating layer, a gate layer, and a second insulating layer stacked sequentially from bottom to top; wherein, a ferroelectric dielectric layer is disposed on the side regions of the first insulating layer, the gate layer, and the second insulating layer, and a Z-shaped vertical channel layer is disposed on the side of the ferroelectric dielectric layer.

[0006] Preferably, a source electrode and a drain electrode are provided on both sides of the Z-shaped vertical channel layer, and the Z-shaped vertical channel layer is a semiconductor thin film or a bipolar semiconductor thin film.

[0007] Preferably, a passivation protective layer is provided on the ferroelectric dielectric layer, the Z-shaped vertical channel layer, the source electrode, and the drain electrode.

[0008] Preferably, the Micro-LED includes a source electrode, a first bump, a second bump, a second electrode, and a Micro-LED device; the Micro-LED device is connected to the driving unit through the first bump and the second bump.

[0009] Preferably, the thickness of the ferroelectric dielectric layer is 10~20 nm; the thickness of the Z-shaped vertical channel layer is 5~15 nm.

[0010] Preferably, the semiconductor thin film or bipolar semiconductor thin film is any one of MoS2, MoTe2, WSe2, WS2, ZnO, In2O3, Ga2O3, SnO2, IZO and IGZO thin films.

[0011] On the other hand, a method for fabricating a memory-based display driving array of a sub-10 nanometer gate-length ferroelectric transistor is provided, the specific steps of which include the following:

[0012] A first insulating layer is formed on a substrate, and a gate layer is prepared on the first insulating layer by magnetron sputtering.

[0013] A second insulating layer is deposited on the gate layer using atomic layer deposition.

[0014] After photolithography and development in the right side region of the first to second insulating layers, the sidewall structure is formed by inductively coupled plasma etching.

[0015] A ferroelectric dielectric layer was deposited on the sidewall structure using atomic layer deposition.

[0016] A Z-shaped vertical channel layer is formed by transferring a semiconductor thin film or bipolar semiconductor thin film material over the ferroelectric dielectric layer;

[0017] After photolithography is used to develop the Z-shaped channel layer, metal is deposited on both sides to obtain the source and drain electrodes.

[0018] A passivation protective layer was deposited at low temperature using plasma-enhanced chemical vapor deposition equipment;

[0019] The source, drain, and second electrode regions are patterned using ultraviolet exposure equipment. Through-holes are etched using reactive ion etching equipment to expose the underlying source, drain metal, and second electrode regions. The second electrode region, the first bump, and the second bump region are patterned again using ultraviolet exposure equipment. Metal is deposited using electron beam evaporation equipment. The Micro-LED device is bonded to the first bump and the second bump using bonding equipment.

[0020] Preferably, the material of the gate layer is selected from any one or more of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

[0021] Preferably, the materials of the first insulating layer and the second insulating layer are selected from any one of silicon oxide, aluminum with alumina, porous silicate, fluorosilicone glass, carbon-doped silicon oxide, and organosilicon glass.

[0022] Preferably, the thickness of the Micro-LED device is 5~10 μm and the width is 10~30 μm.

[0023] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0024] (1) A vertical sub-10 nanometer gate length transistor is used as the display driving unit, and a Z-shaped vertical channel structure is innovatively introduced. This structure enables carriers to transport along a direction perpendicular to the substrate. Compared with the horizontal channel design of traditional planar devices, it can significantly reduce the lateral feature size of the transistor, thereby greatly improving the chip integration density and scalability. At the same time, the Z-shaped configuration extends the effective channel length in the vertical direction, which can significantly suppress the short-channel effect and ensure the reliable switching characteristics of the device at the nanoscale.

[0025] (2) The Micro-LED light-emitting unit and the driving transistor are three-dimensionally integrated in the vertical direction, which further eliminates the area redundancy in the planar layout and is expected to greatly improve the pixel density per unit area. This highly integrated vertical architecture not only provides a physical basis for realizing ultra-high resolution displays, but also opens up a new path for integrating more functional modules in a limited chip space in the future.

[0026] (3) The ferroelectric transistor, as the core driving unit, has an in-memory computing function. It not only retains the switching and current driving capabilities of traditional transistors, but also utilizes the non-volatile polarization characteristics of ferroelectric materials to achieve independent and precise control of the light emission duration of pixel units. By precisely adjusting the gate voltage, the output brightness of Micro-LEDs can be continuously and flexibly adjusted. This control mechanism based on the integration of driving and ferroelectric storage provides key technical support for achieving high grayscale levels and high-quality image display. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a front view of the memory-to-display driver array structure of the present invention;

[0029] Figure 2 This is a top view of the memory-to-display driver array structure of the present invention;

[0030] Figure 3 This is a schematic diagram of the connection relationship of the in-memory display array of the present invention;

[0031] Figure 4 This is a layout of a Micro-LED array driven by a vertical sub-10 nanometer gate length transistor according to the present invention.

[0032] Among them, 1 is Micro-LED, 2 is vertical sub-10 nanometer gate ferroelectric transistor, 3 is passivation protection layer, 4 is ferroelectric dielectric layer, 5 is second insulating layer, 6 is gate layer, 7 is first insulating layer, 8 is supporting substrate, 9 is source, 10 is channel material layer, 11 is drain, 12 is Micro-LED device, 13 is first bump, 14 is second bump, 15 is second electrode, 16 is array vertical sub-10 nanometer gate ferroelectric transistor gate layer column interconnect metal layer, 17 is array vertical sub-10 nanometer gate ferroelectric transistor drain layer column interconnect metal layer, and 18 is array Micro-LED negative electrode row interconnect metal layer. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] The purpose of this invention is to provide a memory-based display driver array for sub-10 nanometer gate-length ferroelectric transistors, such as... Figure 1 and Figure 2 As shown, the array includes: a supporting substrate 8, a Micro-LED 1, and a vertical sub-10 nanometer gate ferroelectric transistor 2; the vertical sub-10 nanometer gate ferroelectric transistor 2 serves as the driving unit of the array, and the Micro-LED 1 serves as the light-emitting unit of the array; the light-emitting unit and the corresponding driving unit are directly stacked and integrated in the vertical direction. A vertical sub-10 nanometer gate ferroelectric transistor refers to a ferroelectric transistor whose channel is perpendicular to the substrate and whose gate length can be in the sub-10 nanometer range. This invention innovatively applies the vertical sub-10 nanometer gate ferroelectric transistor driving unit structure to the display driving field, designing a novel Micro-LED array driven by a vertical sub-10 nanometer gate ferroelectric transistor with in-memory computing capabilities. The vertical sub-10 nanometer gate ferroelectric transistor structure includes a reconfigurable transistor structure, which can achieve electron-driven and hole-driven Micro-LED light emission through ferroelectric polarity switching.

[0035] Furthermore, the supporting substrate is a silicon-based substrate. The vertical sub-10 nanometer gate length ferroelectric transistor 2 region includes a first insulating layer 7, a gate layer 6, and a second insulating layer 5 stacked sequentially from bottom to top; a ferroelectric dielectric layer 4 is disposed on the side regions of the gate layer 6, the first insulating layer 7, and the second insulating layer 5, and the ferroelectric dielectric layer 4 completely covers the first insulating layer 7 to the second insulating layer 5 and the side regions; a Z-shaped vertical channel layer 10 is disposed on the side of the ferroelectric dielectric layer 4, and the Z-shaped vertical channel layer 10 is a semiconductor thin film or a bipolar semiconductor thin film; a source electrode 9 and a drain electrode 11 are disposed on the left and right sides of the Z-shaped vertical channel layer 10; a passivation protection layer 3 is disposed on the ferroelectric dielectric layer 4, the Z-shaped vertical channel layer 10, the source electrode 9, and the drain electrode 11.

[0036] Furthermore, the material of the gate layer 6 is selected from any one or more of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide. The material of the first insulating layer 7 or the second insulating layer 5 is selected from any one of silicon oxide, aluminum oxide-coated metal, porous silicate, fluorosilicone glass, carbon-doped silicon oxide, and organosilicon glass. The thickness of the second insulating layer 5 is 10-20 nm, and the width of the second insulating layer 5 is 23-25 ​​μm. The material of the passivation protection layer 3 is silicon dioxide or hafnium oxide, and the deposition thickness is 35 nm.

[0037] The ferroelectric dielectric layer 4 includes a hafnium-based ferroelectric material layer, which includes any one of HfZrOX, HfAlOX, HfSiOX, HfTiOX, and HfYOX. The thickness of the ferroelectric dielectric layer 4 is 10~20 nm, and the thickness of the Z-shaped vertical channel layer 10 is 5~15 nm. The semiconductor thin film or bipolar semiconductor thin film is any one of MoS2, MoTe2, WSe2, WS2, ZnO, In2O3, Ga2O3, SnO2, IZO, and IGZO thin films.

[0038] Micro-LED 1 includes a source electrode 9, a first bump 13, a second bump 14, a second electrode 15, and a Micro-LED device 12; the Micro-LED device 12 is connected to the driving unit via the bumps. The source electrode 9, drain electrode 11, first bump 13, second bump 14, and second electrode 15 are made of any one of palladium, gold, tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide. The thickness of the Micro-LED device 12 is 5~10 μm, and the width is 10~30 μm.

[0039] like Figure 3 As shown, the array is connected as follows: the drains of each column of vertical sub-10 nanometer gate ferroelectric transistors are connected together; the positive terminal of each unit Micro-LED is connected to the source terminal of the vertical sub-10 nanometer gate ferroelectric transistor of that unit; the negative terminals of each row of Micro-LEDs are connected together; and the gates of each column of vertical sub-10 nanometer gate ferroelectric transistors are connected together. Figure 4 The top view of the array connection is shown. Then, the array vertical sub-ten nanometer gate length ferroelectric transistor gate layer column interconnect metal layer 16, the array vertical sub-ten nanometer gate length ferroelectric transistor drain layer column interconnect metal layer 17, and the array Micro-LED negative electrode row interconnect metal layer 18 will lead out the wires.

[0040] Furthermore, a method for fabricating a memory-based display driving array of sub-10 nanometer gate-length ferroelectric transistors is provided, the specific steps of which include the following:

[0041] First, a silicon dioxide first insulating layer 7 (300 nm) is formed on the substrate. Then, a metal gate layer 6 is deposited on the first insulating layer 7 by magnetron sputtering. The metal deposited on the gate layer is preferably titanium nitride or tungsten (with a deposition thickness of 5~30 nm).

[0042] A second insulating layer 5 of silicon dioxide (10~20 nm) is grown by using an atomic layer thin film deposition device, and the sidewall region is developed by ultraviolet lithography in the area from the first insulating layer 7 to the right side of the second insulating layer 5. Then, the sidewall structure is formed by inductively coupled plasma etching.

[0043] An HZO ferroelectric dielectric layer 4 (10~20 nm) is deposited on the sidewall structure using an atomic layer thin film deposition (ALD) apparatus. A semiconductor thin film or bipolar semiconductor thin film material is transferred over the ferroelectric dielectric layer 4 to form a Z-shaped vertical channel layer 10. After photolithography and development on the Z-shaped channel layer 10 using an ultraviolet lithography apparatus, metal is deposited on both sides using thermal evaporation or electron beam evaporation to obtain the source electrode 9 and the drain electrode 11.

[0044] A passivation protective layer 3 (made of silicon dioxide or hafnium oxide, with a deposition thickness of 35 nm) was deposited at low temperature using a plasma-enhanced chemical vapor deposition apparatus.

[0045] The source electrode 9, drain electrode 11 and second electrode 15 regions are patterned using ultraviolet exposure equipment. Through holes are etched using reactive ion etching equipment to expose the underlying source electrode 9, drain electrode 11 metal and second electrode 15 regions. The second electrode 15 region, first bump 13 and second bump 14 are patterned again using ultraviolet exposure equipment. Metal is deposited using electron beam evaporation equipment. The Micro-LED device 12 is bonded to the first bump 13 and second bump 14 using bonding equipment.

[0046] The device operates as follows: In the vertical sub-10 nm gate length ferroelectric transistor 2, the drain interconnect metal layer 17 is connected to the power supply voltage signal (VDD), and the gate interconnect metal layer 16 is connected to the data signal (Vdata). The source 9 is connected to the first bump 13 of the Micro-LED 1. The first bump 13 is connected to the positive electrode of the Micro-LED, and the negative electrode of the Micro-LED is connected to the second bump 14. The second bump 14 is connected to the second electrode 15 and grounded (GND) through the Micro-LED negative electrode interconnect metal layer 18, thus forming a complete driving circuit. The gate layer 6 is disposed between the first insulating layer 5 and the second insulating layer 7. The insulating layer shields the vertical electric field on the gate surface, and only the electric field on the right side of the gate layer 6 can regulate the channel. The ferroelectric dielectric layer 4 integrated between the gate layer 6 and the Z-shaped vertical channel 10 can non-volatilely regulate the channel conductivity through the spontaneous polarization effect of the ferroelectric material, ensuring the stable maintenance and accurate reproduction of the driving signal. This Z-shaped channel structure significantly suppresses short-channel effects by extending the effective channel length in the vertical direction, ensuring reliable switching characteristics of the device at the nanoscale. It has broad application prospects in cutting-edge fields such as neuromorphic computing and smart displays. In-memory computing-display integrated arrays built based on this architecture can perform matrix multiplication and addition calculations, enabling real-time on-chip related operations and meeting the high energy efficiency requirements of in-situ integration of storage, computing, and display functions in smart display systems.

[0047] This invention achieves integrated in-memory computing and display functionality by precisely controlling the gate voltage to regulate the spontaneous polarization reversal of ferroelectric materials. It not only enables precise control of each micro-LED through pulse width modulation but also ensures excellent retention of the driving current throughout the frame cycle. Specifically, the device features a Z-shaped vertical channel layer on the side of the ferroelectric dielectric layer. This structure improves the area efficiency of the integrated circuit while significantly suppressing the short-channel effect by extending the channel length in the vertical direction, thus balancing device miniaturization and high performance requirements. This driving architecture utilizes partial polarization reversal characteristics to precisely compensate for electrical differences between pixels, thereby achieving excellent continuous brightness adjustability, fine grayscale control, and superior reliability, providing an innovative solution for high-quality and high-uniformity display applications.

[0048] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A memory-based display driver array for sub-10 nanometer gate-length ferroelectric transistors, characterized in that, It includes a supporting substrate, a vertical sub-10 nanometer gate ferroelectric transistor, and a Micro-LED; the vertical sub-10 nanometer gate ferroelectric transistor serves as the driving unit of the array, and the Micro-LED serves as the light-emitting unit of the array; the light-emitting unit and the corresponding driving unit are directly stacked and integrated in the vertical direction.

2. The memory-based display driving array for a sub-10 nanometer gate-length ferroelectric transistor according to claim 1, characterized in that, The vertical sub-10 nanometer gate ferroelectric transistor includes a first insulating layer, a gate layer, and a second insulating layer stacked sequentially from bottom to top; wherein, a ferroelectric dielectric layer is disposed on the side regions of the first insulating layer, the gate layer, and the second insulating layer, and a Z-shaped vertical channel layer is disposed on the side of the ferroelectric dielectric layer.

3. The memory-based display driving array for a sub-10 nanometer gate-length ferroelectric transistor according to claim 2, characterized in that, The Z-shaped vertical channel layer has a source and a drain on both sides, and the Z-shaped vertical channel layer is a semiconductor thin film or a bipolar semiconductor thin film.

4. The memory-based display driving array for a sub-ten-nanometer gate-length ferroelectric transistor according to claim 3, characterized in that, A passivation protective layer is provided on the ferroelectric dielectric layer, the Z-shaped vertical channel layer, the source electrode, and the drain electrode.

5. The memory display driving array for a sub-ten-nanometer gate-length ferroelectric transistor according to claim 1, characterized in that, The Micro-LED includes a source electrode, a first bump, a second bump, a second electrode, and a Micro-LED device; the Micro-LED device is connected to the driving unit through the first bump and the second bump.

6. The memory-based display driving array for a sub-ten-nanometer gate-length ferroelectric transistor according to claim 4, characterized in that, The thickness of the ferroelectric dielectric layer is 10~20 nm; the thickness of the Z-shaped vertical channel layer is 5~15 nm.

7. The memory display driving array for a sub-ten-nanometer gate-length ferroelectric transistor according to claim 3, characterized in that, The semiconductor thin film or bipolar semiconductor thin film is any one of MoS2, MoTe2, WSe2, WS2, ZnO, In2O3, Ga2O3, SnO2, IZO and IGZO thin films.

8. A method for fabricating a memory-based display driving array of a sub-10 nanometer gate-length ferroelectric transistor, characterized in that, The specific steps include the following: A first insulating layer is formed on a substrate, and a gate layer is prepared on the first insulating layer by magnetron sputtering. A second insulating layer is deposited on the gate layer using atomic layer deposition. After photolithography and development in the right side region of the first to second insulating layers, the sidewall structure is formed by inductively coupled plasma etching. A ferroelectric dielectric layer was deposited on the sidewall structure using atomic layer deposition. A Z-shaped vertical channel layer is formed by transferring a semiconductor thin film or bipolar semiconductor thin film material over the ferroelectric dielectric layer; After photolithography is used to develop the Z-shaped channel layer, metal is deposited on both sides to obtain the source and drain electrodes. A passivation protective layer was deposited at low temperature using plasma-enhanced chemical vapor deposition equipment; The source, drain, and second electrode regions are patterned using ultraviolet exposure equipment. Through-holes are etched using reactive ion etching equipment to expose the underlying source, drain metal, and second electrode regions. The second electrode region, the first bump, and the second bump region are patterned again using ultraviolet exposure equipment. Metal is deposited using electron beam evaporation equipment. The Micro-LED device is bonded to the first bump and the second bump using bonding equipment.

9. The method for fabricating a memory display driving array of a sub-ten nanometer gate-length ferroelectric transistor according to claim 8, characterized in that, The material of the gate layer is selected from any one or more of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

10. The method for fabricating a memory-based display driving array of a sub-ten-nanometer gate-length ferroelectric transistor according to claim 8, characterized in that, The materials of the first insulating layer and the second insulating layer are selected from any one of silicon oxide, aluminum with alumina, porous silicate, fluorosilicone glass, carbon-doped silicon oxide, and organosilicon glass.

Images