A perovskite thin-film transistor with a dual-channel structure and a method for controlling its threshold voltage.

Abstract

This invention relates to a perovskite thin-film transistor with a dual-channel structure and a method for controlling its threshold voltage, belonging to the field of microelectronic device technology. The transistor includes a gate, a gate insulating layer, a perovskite semiconductor channel layer, a source, and a drain. The perovskite semiconductor channel layer comprises a first semiconductor layer and a second semiconductor layer stacked perpendicular to the substrate. The first semiconductor layer is located on the back channel side, and its material has a higher density of first-type defect states (Type I) dominating carrier mobility than that of the second semiconductor layer. The second semiconductor layer is located near the gate insulating layer, and its material has a higher density of second-type defect states (Type II) dominating the threshold voltage than that of the first semiconductor layer. This invention is based on the tail-state donor density (NTD) dominating mobility and the Gaussian acceptor density (NGA) dominating the threshold voltage. By adjusting the thickness ratio of the second semiconductor layer to the first semiconductor layer, the spatial distribution of hole carriers in the vertical direction of the channel is changed, achieving linear control of the threshold voltage.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of microelectronic devices, and relates to a perovskite thin film transistor with a double-layer channel structure and a threshold voltage regulation method thereof. BACKGROUND

[0002] Perovskite thin film transistors (TFTs) have shown great application potential in new display and flexible electronics due to their excellent optoelectronic properties, high carrier mobility, good stability, and relatively simple solution-based fabrication process. Among them, tin-based perovskites (such as MASnI3) have become a research hotspot for P-type semiconductor channel materials due to their high theoretical mobility and relatively low toxicity.

[0003] Currently, research on improving the performance of perovskite TFTs mainly focuses on material modification and process optimization. For example, Chinese patent CN118401072A introduces a sulfur source dopant to form a stannous sulfide-tin-based perovskite heterojunction, aiming to reduce defect state density and improve device stability and mobility. Chinese patent CN118201442A uses a template growth method to induce perovskite directional growth using thiocyanate to improve thin film crystalline quality and optimize electrical performance. In addition, Chinese patent CN118042901A uses two-dimensional phenethylamine tin iodine doping to regulate the energy band structure and surface morphology of three-dimensional tin-based perovskite to improve transistor performance. These studies point to a core problem: defect states in perovskite materials are key factors that constrain device performance, especially causing threshold voltage (V th ) instability and difficulty in precise control.

[0004] However, existing technologies mainly focus on passively repairing or reducing defects through complex chemical doping or fine process control. Such methods not only increase process complexity, but also make the final result of threshold voltage highly dependent on process parameters such as crystallization temperature and component ratio, which are difficult to control accurately, resulting in poor consistency of device performance and low yield. In particular, in a single-layer channel structure, threshold voltage and carrier mobility are often coupled, making it difficult to optimize independently, making it a difficult problem in the industry to flexibly regulate threshold voltage in a wide range, linearly and stably.

[0005] Therefore, how to provide a perovskite thin film transistor structure with simple process, linear and wide range threshold voltage regulation, while considering carrier mobility, has become a technical problem to be solved in the field. SUMMARY

[0006] Therefore, the present application aims to solve the problem of difficulty in accurately and flexibly regulating the threshold voltage of existing perovskite thin film transistors, which is easily affected by fluctuations in the preparation process, and the mutual coupling of mobility and threshold voltage.

[0007] To achieve the above objectives, the present invention provides a perovskite thin-film transistor with a dual-channel structure, comprising a gate, a gate insulating layer, a perovskite semiconductor channel layer, a source, and a drain. The perovskite semiconductor channel layer includes a first semiconductor layer and a second semiconductor layer stacked in a direction perpendicular to the substrate. The first semiconductor layer is located on the back channel side, and its material has a first defect state density distribution, wherein the density of a first type of defect state that dominates the influence on carrier mobility is higher than that of the second semiconductor layer. The second semiconductor layer is located near the gate insulating layer side, and its material has a second defect state density distribution, wherein the density of a second type of defect state that dominates the influence on the threshold voltage is higher than that of the first semiconductor layer.

[0008] Preferably, the first type of defect state is a tail-state donor state, and the second type of defect state is a Gaussian acceptor state. More preferably, the tail-state donor state density (NTD) of the first semiconductor layer is higher than that of the second semiconductor layer, and the Gaussian acceptor state density (NGA) of the second semiconductor layer is higher than that of the first semiconductor layer; the tail-state donor state density (NTD) of the first semiconductor layer is... The order of magnitude, the Gaussian dominant state density (NGA) of the second semiconductor layer is... Magnitude.

[0009] In some embodiments, the first semiconductor layer and the second semiconductor layer are made of the same perovskite material, such as tin-based perovskite MASnI3, FASnI3, or CsSnI3.

[0010] In some embodiments, the total thickness of the perovskite semiconductor channel layer is 10 nm to 200 nm, and the thickness of the second semiconductor layer is 5% to 95% of the total thickness. By adjusting the thickness ratio of the second semiconductor layer to the first semiconductor layer, linear control of the threshold voltage can be achieved.

[0011] The present invention also provides a threshold voltage regulation method for the above-mentioned perovskite thin film transistor, which changes the spatial distribution of hole carriers in the vertical direction of the channel by adjusting the thickness ratio of the second semiconductor layer to the first semiconductor layer in the perovskite semiconductor channel layer, thereby achieving linear regulation of the threshold voltage.

[0012] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) Based on the functional understanding of different types of defect state tail state NTD-type donor state (dominant mobility) and Gaussian acceptor state density NGA-type threshold voltage in perovskite materials, this invention creatively divides the channel layer of the same material into functional layers, transforming the complex material defect control problem into a structural layer thickness control problem that is easy to implement in engineering.

[0013] (2) The present invention only requires changing the thickness ratio of the double layer, without the need for complex chemical doping or strict process control, which reduces the sensitivity to process parameters such as crystallization temperature and component ratio, and is conducive to improving device yield and consistency.

[0014] (3) While achieving significant control of the threshold voltage, the present invention maintains a high carrier mobility, breaking through the bottleneck that it is difficult to balance mobility and threshold voltage in a single-layer structure.

[0015] (4) The double-layer channel structure design shown in this invention can be extended to a variety of perovskite material systems, such as FASnI3 or CsSnI3, as well as a variety of preparation processes, such as spin coating, inkjet printing, and blade coating, providing a new idea for the industrialization of high-performance and high-stability perovskite thin film transistors.

[0016] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0017] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the device structure of the perovskite thin film transistor provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the density of states model of the perovskite material used in Embodiment 1 of the present invention; Figure 3 This is a graph showing the transfer characteristics of the device under different NGA layer thicknesses in Embodiment 1 of the present invention. Figure 4 This is a graph showing the relationship between the threshold voltage and the NGA layer thickness in Embodiment 1 of the present invention; Figure 5 This is a hole current density distribution diagram near the off state of the device when the NGA layer thickness is 5nm in Embodiment 1 of the present invention. Figure 6 This is a hole current density distribution diagram near the off state of the device when the NGA layer thickness is 15nm in Embodiment 1 of the present invention. Figure 7 This is a hole current density distribution diagram near the off state of the device when the NGA layer thickness is 25nm in Embodiment 1 of the present invention. Figure 8 This is a hole current density distribution diagram near the off state of the device when the NGA layer thickness is 35nm in Embodiment 1 of the present invention. Detailed Implementation

[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0019] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0020] Example 1 provides a double-channel perovskite thin-film transistor with flexible threshold voltage control and its control method.

[0021] like Figure 1 As shown, a thin-film transistor with a bottom-gate top-contact structure is constructed. The substrate is heavily doped p-type Si, which also serves as the gate (G). A 100 nm thick SiO2 layer is formed on the substrate as the gate insulating layer (GI). On the SiO2 layer, a 40 nm thick MASnI3 semiconductor layer is formed as the channel layer (SC). Finally, Au source (S) and drain (D) electrodes with a thickness of 40 nm are formed on the channel layer using mask evaporation. The channel aspect ratio (W / L) is 500 μm / 100 μm. The work function of the Au electrode is 5.1 eV.

[0022] To accurately simulate the electrical properties of polycrystalline perovskite materials, an effective medium approximation method is employed. Considering that the device size is much larger than the perovskite grain size, the density of states (DOS) of the material is described as a combination of exponentially distributed band-tailed states and Gaussian distributed deep-energy states, specifically including quasi-receptive band-tailed states. TA (E) donor-like valence band tail state g TD (E), acceptor-like energy state density g GA (E) and donor-like energy state density g GD (E), such as Figure 2 As shown. The tail-state-like acceptor state density NTD corresponds to g. TD The integral of the Gaussian class subject to the principal state density NGA corresponds to g GA The points.

[0023] Keeping other parameters constant, the NTD and NGA were changed separately using TCAD simulation software to observe the changes in device transfer characteristics. The simulation conditions were: drain-source voltage VDS = -40V, and gate-source voltage VGS scanned from -40V to 40V.

[0024] The results showed that as the NTD increased, the hole saturation mobility of the device decreased sharply. When the NTD reached... Near this point, the saturation mobility drops to approximately 1 cm² / V·s. As the NGA increases, the device's threshold voltage shifts positively, making it more difficult to turn off. When the NGA reaches... When the threshold voltage is near the threshold, the transfer characteristic curve already exhibits obvious on-state characteristics, meaning the device is difficult to turn off. This indicates that the NTD mainly affects carrier mobility, while the NGA plays a dominant role in the threshold voltage.

[0025] Based on the above analysis, this embodiment proposes a double-layer channel structure.

[0026] The MASnI3 channel layer, with a total thickness of 40nm, is divided into upper and lower layers: ① The first semiconductor layer (NTD layer) is located on the back channel side (near the source and drain electrodes), and its tail state is similar to the master state density. Set NTD to a higher value ; ② The layer located near the gate insulating layer is the second semiconductor layer (NGA layer), whose Gaussian class is set to a lower value by the dominant state density NGA. .

[0027] To verify the control effect of the present invention, the materials of the first semiconductor layer and the second semiconductor layer are kept the same as MASnI3, and the total thickness is kept constant at 40 nm. Only the thickness of the second semiconductor layer (NGA layer) is changed, and is set to 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm and 35 nm respectively. The corresponding thicknesses of the first semiconductor layer (NTD layer) are 35 nm, 30 nm, 25 nm, 20 nm, 15 nm, 10 nm and 5 nm respectively.

[0028] like Figure 3 As shown, as the NGA layer thickness increases from 5 nm to 35 nm, the device's transfer characteristic curve shifts to the right (positive direction) overall. Figure 4 The relationship between the threshold voltage and the NGA layer thickness was quantitatively demonstrated: the threshold voltage gradually increased from approximately -5.56 V to approximately 5.05 V, exhibiting an approximately linear increasing trend. As a control, pure NGA layer thickness was used... The threshold voltage extracted from the single-layer channel (equivalent to an NGA layer thickness of 0 nm) is -7.18V, derived from pure... The threshold voltage extracted from the single-layer channel (equivalent to an NGA layer thickness of 40 nm) is 7.00 V. Therefore, the dual-layer channel structure of this invention achieves continuous and linear control of the threshold voltage between -7.18 V and 7.00 V, while the carrier mobility can reach up to [missing value]. .

[0029] Figures 5 to 8 The hole current density distribution near the off state of the device is shown at different NGA layer thicknesses (5 nm, 15 nm, 25 nm, and 35 nm). As the NGA layer thickness increases, the high current density region gradually expands from the interface near the gate dielectric layer to the entire channel layer, and the maximum current density also increases by nearly two orders of magnitude. This indicates that by changing the thickness ratio between the two layers, the spatial distribution of hole carriers in the vertical direction of the channel can be effectively adjusted. To turn off the transistor, a corrected gate voltage needs to be applied to attract electrons to accumulate in the lower half of the channel for hole recombination, thus thinning the channel current density distribution thickness; this gate voltage is the threshold voltage. Therefore, the bilayer structure of this invention achieves precise modulation of the threshold voltage by controlling the NGA layer thickness, and... Figure 4 The changing patterns are completely consistent.

[0030] In other embodiments, the perovskite material is not limited to MASnI3, but can also be other tin-based perovskites, such as FASnI3 or CsSnI3, or mixed halide perovskites. The key is to identify the defect state types that dominate the threshold voltage and mobility in the material system and to perform corresponding layered design. For example, for FASnI3, a similar method can be used to set the first semiconductor layer to have a high valence band tail state density, the second semiconductor layer to have a high deep-level defect state density, and adjust the thickness ratio while maintaining a total thickness of 50 nm, thus achieving linear control of the threshold voltage.

[0031] Furthermore, the total thickness of the channel layer is not limited to 40 nm and can vary from 10 nm to 200 nm depending on the device design requirements. The thickness of the second semiconductor layer (NGA layer) can account for 5% to 95% of the total thickness to achieve different controllable ranges. By adjusting the thickness ratio, the threshold voltage can be continuously adjusted between -15 V and +15 V. The gate insulating layer is not limited to SiO2 and can be a high-k dielectric such as Al2O3 or HfO2, with a thickness selectable from 30 to 300 nm; the source and drain electrodes can be work function-matched metals or conductive oxides such as Au, Ni, Pt, and Ag, with a thickness selectable from 30 to 100 nm.

[0032] Example 2 is basically the same as Example 1, except that the materials of both the first and second semiconductor layers are FASnI3, with a total thickness of 50 nm. By setting the first semiconductor layer to have a high NTD (e.g., ... The second semiconductor layer has a high NGA (e.g., By adjusting the thickness of the second semiconductor layer to 5 nm, 10 nm, 20 nm, 30 nm, and 40 nm, linear control of the threshold voltage was achieved, with a control range of -10 V to +8 V and a mobility maintained above 10 cm² / V·s.

[0033] Example 3 provides a method for preparing the above-mentioned double-layer channel structure, the specific steps of which are as follows: (1) Substrate cleaning: The heavily doped p-type silicon wafer with 100 nm SiO2 grown on the surface was ultrasonically cleaned with acetone and isopropanol for 15 minutes, dried with a nitrogen gun, and then treated with ultraviolet ozone for 10 minutes.

[0034] (2) Preparation of precursor solution: Prepare two portions of MASnI3 precursor solution. The first solution is used to form the NTD layer. By adding a small amount of guanidine iodide or adjusting the annealing conditions, it is made to have a high density of tail-state donor-like states (NTD target value) after annealing. The second solution was used to form the NGA layer. By adding a small amount of hydroquinone or adjusting the annealing conditions, it was made to have a lower density of Gaussian acceptor states after annealing (the target NGA value). The solvent volume ratio was DMF:DMSO = 4:1, and the MASnI3 concentration was 0.5 mol / L.

[0035] (3) Preparation of double-layer film: a two-step spin coating method was adopted.

[0036] First, the second solution is spin-coated onto the SiO2 substrate at a low speed of 2000 rpm for 30 seconds, and then pre-annealed on a hot plate at 70°C for 5 minutes to form an NGA layer with a thickness of approximately d2. d2 can be controlled by adjusting the spin-coating speed and concentration.

[0037] Next, the first solution was spin-coated onto the NGA layer at 3000 rpm for 40 seconds, and then annealed on a hot plate at 100°C for 15 minutes to form an NTD layer with a thickness of (40-d2) nm.

[0038] By changing the thickness of the NGA layer after pre-annealing, double-layer channels with different thickness ratios can be obtained.

[0039] (4) Electrode preparation: Vacuum thermal evaporation coating is used, under vacuum conditions. Under these conditions, a 40 nm thick gold layer was deposited on the channel layer using a mask as the source and drain electrodes, with a channel aspect ratio of 500 μm / 100 μm.

[0040] In other embodiments, the fabrication process is not limited to a two-step spin coating method; solution-based processes such as inkjet printing, blade coating, and slot coating can also be used, or photolithography can be combined to achieve a more precisely defined bilayer structure. If physical vapor deposition, such as sputtering or evaporation, can be used, perovskite layers with different defect state densities can be deposited in stages. Furthermore, the substrate can be a rigid substrate, such as silicon, glass, or sapphire, or a flexible substrate, such as polyimide, PET, or PEN, to meet the application requirements of flexible electronic devices.

[0041] As can be seen from the above embodiments and variations, the double-channel perovskite thin-film transistor and its control method provided by the present invention, compared with traditional single-layer structures or heterojunction structures, achieve a wide range (up to ±15 V), linear, and continuous control of the threshold voltage, with high control sensitivity; the control method is simple, requiring only changes in the thickness ratio of the double layers, avoiding complex chemical doping or stringent process control; while controlling the threshold voltage, it maintains a high carrier mobility (up to 11.58 cm² / V·s or higher), solving the problem of difficulty in balancing mobility and threshold voltage in single-layer structures; this structural design is universal and can be extended to various perovskite material systems and various fabrication processes, providing a feasible solution for the industrialization of high-performance, high-stability perovskite thin-film transistors.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A perovskite thin-film transistor with a dual-channel structure, comprising a gate, a gate insulating layer, a perovskite semiconductor channel layer, a source, and a drain, characterized in that, The perovskite semiconductor channel layer includes a first semiconductor layer and a second semiconductor layer stacked in a direction perpendicular to the substrate. The first semiconductor layer is located on the back channel side, and its material has a first defect state density distribution. The density of the first type of defect state, which has a dominant effect on carrier mobility, is higher than that of the second semiconductor layer. The second semiconductor layer is located near the gate insulating layer and its material has a second defect state density distribution. The density of the second type of defect state, which has a dominant effect on the threshold voltage, is higher than that of the first semiconductor layer.

2. The perovskite thin-film transistor with a dual-channel structure according to claim 1, characterized in that, The first type of defect state is a tail-state donor state, and the second type of defect state is a Gaussian acceptor state.

3. The perovskite thin-film transistor with a dual-channel structure according to claim 2, characterized in that, The tail-state donor density NTD of the first semiconductor layer is higher than that of the second semiconductor layer, and the Gaussian acceptor density NGA of the second semiconductor layer is higher than that of the first semiconductor layer.

4. The perovskite thin-film transistor with a dual-channel structure according to claim 3, characterized in that, The tail-state donor state density NTD of the first semiconductor layer is The order of magnitude, the Gaussian dominant state density (NGA) of the second semiconductor layer is... Magnitude.

5. The perovskite thin-film transistor with a double-channel structure according to any one of claims 1-4, characterized in that, The first semiconductor layer and the second semiconductor layer are made of the same perovskite material.

6. The perovskite thin-film transistor with a dual-channel structure according to claim 5, characterized in that, The perovskite material is a tin-based perovskite, specifically MASnI3, FASnI3, or CsSnI3.

7. The perovskite thin-film transistor with a double-channel structure according to any one of claims 1-4, characterized in that, The total thickness of the perovskite semiconductor channel layer is 10 nm to 200 nm, and the thickness of the second semiconductor layer is 5% to 95% of the total thickness.

8. The perovskite thin-film transistor with a double-channel structure according to any one of claims 1-4, characterized in that, The threshold voltage of the transistor is linearly controlled by adjusting the thickness ratio of the second semiconductor layer to the first semiconductor layer.

9. The perovskite thin-film transistor with a double-channel structure according to any one of claims 1-4, characterized in that, The gate is made of heavily doped silicon, the gate insulating layer is made of SiO2, Al2O3 or HfO2, and the source and drain are made of Au, Ni, Pt or ITO.

10. A method for threshold voltage regulation of a perovskite thin-film transistor with a double-channel structure as described in any one of claims 1-9, characterized in that, By adjusting the thickness ratio of the second semiconductor layer to the first semiconductor layer in the perovskite semiconductor channel layer, the spatial distribution of hole carriers in the vertical direction of the channel is changed, thereby achieving linear adjustment of the threshold voltage.

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