A display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes a display area and a non-display area surrounding the display area. The display panel further includes an array substrate and a counter substrate disposed opposite to each other. The array substrate includes a first substrate and a plurality of thin-film transistors located on the first substrate and facing the counter substrate. In the non-display area, the thin-film transistors include first thin-film transistors, each including a first active layer. The array substrate also includes a planarization layer, which includes a first planarization portion covering the first active layer. The counter substrate includes a second substrate and a pad layer located on the second substrate and facing the array substrate. The projection of the pad layer onto the plane of the first substrate is a first projection, and the projection of the first planarization portion onto the plane of the first substrate is a second projection. The first projection is located on the side of the second projection furthest from the display area. This application's solution can effectively improve the support stability of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] With the continuous development of display technology, thin film transistor (TFT) structures with active layers made of oxide semiconductor materials (such as IGZO, Indium Gallium Zinc Oxide) are widely used in high-resolution, low-power display devices due to their excellent carrier mobility and good uniformity.

[0003] The planarization layer in a display panel typically extends to the perimeter. This layer is usually made of organic materials and is hydrophilic, allowing external moisture to easily penetrate the panel and affect the surrounding metal traces. This moisture can cause corrosion of the traces, leading to open or short circuits and impacting the panel's electrical performance and lifespan. Furthermore, oxide semiconductor materials are extremely sensitive to oxygen in the environment and are prone to oxidation or reduction reactions due to fluctuations in oxygen levels. This can result in electrical performance degradation issues such as threshold voltage drift and decreased mobility, affecting the device's stability and reliability.

[0004] To prevent such problems, a planarization layer is typically retained in the periphery of the display panel, where the thin-film transistors are located, to prevent oxygen from directly contacting the oxide semiconductor material; a planarization layer cutout design is used where the metal traces are located to prevent moisture from penetrating through the planarization layer and causing metal corrosion.

[0005] Due to the design of retaining or cutting out the planarization layer in different areas, the support structure under the sealant is uneven and unstable, which can easily lead to panel structure deformation and thus cause appearance defects such as yellowing around the display panel.

[0006] Therefore, optimizing the structural design between the planarization layer and the support structure while ensuring the stability of the oxide semiconductor material and metal trace performance, and avoiding problems such as yellowing around the perimeter caused by uneven support structure, is a critical technical challenge that urgently needs to be solved in the current design and manufacturing of display panels.

[0007] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0008] Based on this, embodiments of this application provide a display panel and a display device that can improve problems such as yellowing around the edges caused by uneven support structure, and enhance the overall display effect of the display panel.

[0009] According to some embodiments, this application provides a display panel, including: The display area and the non-display area surrounding the display area; The display panel also includes: an array substrate and an opposing substrate arranged opposite each other; The array substrate includes a first substrate and a plurality of thin-film transistors located on the first substrate and facing the opposing substrate. In the non-display area, the thin-film transistors include a first thin-film transistor, and the first thin-film transistor includes a first active layer. The array substrate also includes a planarization layer, which includes a first planarization portion that covers the first active layer; The opposing substrate includes a second substrate and a pad layer located on the second substrate and facing the array substrate. The projection of the pad layer onto the plane of the first substrate is a first projection, and the projection of the first flat portion onto the plane of the first substrate is a second projection. The first projection is located on the side of the second projection away from the display area.

[0010] According to some embodiments, this application also provides a display device, including the display panel provided in the foregoing embodiments.

[0011] The display panel and display device provided in this application improve the problem of unstable support by designing a step compensation for the flat layer cut out above the metal trace, thereby improving the problem of yellowing around the display panel and enhancing the overall display effect of the display panel. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0013] Figure 1 This is a top view of a display panel provided in an embodiment of this application; Figure 2 yes Figure 1 Enlarged schematic diagram of the array substrate in region B1; Figure 3 yes Figure 1 Enlarged schematic diagram of the opposing substrate in region B1; Figure 4This is a cross-sectional structural diagram of a display panel in the prior art; Figure 5 The embodiments of this application provide the following: Figure 2 and Figure 3 A schematic diagram of the cross-sectional structure along the A-A' direction; Figure 6 The embodiments of this application provide the following: Figure 2 and Figure 3 Another cross-sectional structural diagram along the A-A' direction; Figure 7 The embodiments of this application provide the following: Figure 2 and Figure 3 Another cross-sectional structural diagram along the A-A' direction; Figure 8 The embodiments of this application provide the following: Figure 2 and Figure 3 Another cross-sectional structural diagram along the A-A' direction; Figure 9 This is provided by the embodiments of this application. Figure 8 Enlarged schematic diagram of the intermediate cushion layer structure; Figure 10 This is provided by the embodiments of this application. Figure 8 Another enlarged schematic diagram of the intermediate cushion layer structure; Figure 11 This is provided by the embodiments of this application. Figure 8 Another enlarged schematic diagram of the intermediate cushion layer structure; Figure 12 This is provided by the embodiments of this application. Figure 8 Another enlarged schematic diagram of the intermediate cushion layer structure; Figure 13 The embodiments of this application provide the following: Figure 2 and Figure 3 Another cross-sectional structural diagram along the A-A' direction; Figure 14 The embodiments of this application provide the following: Figure 2 and Figure 3 Another cross-sectional structural diagram along the A-A' direction; Figure 15 This is provided in the embodiments of this application. Figures 5 to 8 and Figures 13 to 14 The corresponding figure in any of the middle Figure 1 The projection of the pad, planarization layer and first active layer in region B1 onto the plane of the first substrate. Figure 16 This is provided in the embodiments of this application. Figures 5 to 8 and Figures 13 to 14 The corresponding figure in any of the middle Figure 1Another projection of the pad, planarization layer and first active layer in region B1 in the direction of the plane where the first substrate is located; Figure 17 This is provided in the embodiments of this application. Figures 5 to 8 and Figures 13 to 14 The corresponding figure in any of the middle Figure 1 Another projection of the pad, planarization layer and first active layer in region B1 onto the plane of the first substrate. Figure 18 This is provided in the embodiments of this application. Figures 5 to 8 and Figures 13 to 14 The corresponding figure in any of the middle Figure 1 Another projection of the pad, planarization layer and first active layer in region B1 onto the plane of the first substrate. Figure 19 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Figure 1 This is a top view structural diagram of a display panel provided in an embodiment of this application. Figure 2 yes Figure 1 An enlarged schematic diagram of the array substrate in region B1. Figure 3 yes Figure 1 An enlarged schematic diagram of the opposing substrate in region B1. Figure 4 This is a cross-sectional structural diagram of a display panel in the prior art. Figure 5 The embodiments of this application provide the following: Figure 2 A schematic diagram of the cross-sectional structure along the A-A' direction.

[0016] The B1 area is the area where the display area and the non-display area meet, and the location of the B1 area does not impose any restrictions on this application. Figure 4 The cross-sectional diagram provided corresponds to the position on the display panel, which can be used as a reference. Figure 2 and Figure 3 The A-A' section line in the diagram.

[0017] This application provides a display panel 100, for reference... Figures 1 to 3 and Figure 5The display panel 100 includes a display area A1 and a non-display area A2 surrounding the display area; the display panel 100 also includes an array substrate 10 and a counter substrate 20 disposed opposite to each other; the array substrate 10 includes a first substrate 11 and a plurality of thin film transistors 12 located on the first substrate 11 facing the counter substrate 20; in the non-display area A2, the thin film transistors 12 include a first thin film transistor 120, and the first thin film transistor 120 includes a first active layer 1211; the array substrate 10 also includes a planarization layer 13, the planarization layer 13 includes a first planarization portion 131, and the first planarization portion 131 covers the first active layer 1211.

[0018] It should be noted that both display area A1 and non-display area A2 have a flattening layer 13. The flattening layer 13 of display area A1 and the flattening layer 13 / 131 of non-display area A2 can be continuous or discontinuous.

[0019] In one embodiment of this application, reference is made to Figure 2 , Figure 3 and Figure 5The array substrate 10 includes a first substrate 11 and a plurality of thin-film transistors 12 located on the first substrate 11 and facing the opposing substrate 20. In the display area A1, the array substrate 10 includes a thin-film transistor 12, a gate line 101 connected to the gate 1224 of the thin-film transistor, a data line 102 connected to the source 1222 of the thin-film transistor, and a pixel electrode 16 connected to the drain 1223 of the thin-film transistor. The opposing substrate 20 includes a color resist 27 corresponding to the pixel electrode 16 on the array substrate 10, and a main spacer 25 and an auxiliary spacer 26 located between the color resists 27. In the non-display area A2, the thin-film transistor 12 includes a first thin-film transistor 120, which includes a gate 1214, a first active layer 1211, an insulating layer 1215 located between the gate 1214 and the first active layer 1211, and a source 1212 and a drain 1213 in contact with the first active layer 1211. In the non-display area A2, a first flat portion 131 is also included. The first flat portion 131 is located on the side of the first active layer 1211 away from the first substrate 11 and covers the first active layer 1211. The projection of the first active layer 1211 on the plane of the first substrate 11 is completely within the projection of the first flat portion 131 on the plane of the first substrate 11. In this embodiment, a passivation layer 1216 is provided between the first flat portion 131 and the first active layer 121. Optionally, the first flat portion 131 and the first active layer 121 may also be in direct contact or have other functional layers or structural layers, such as metal layers, etc. This application does not specifically limit this. Regardless of whether the first flat portion 131 is in direct contact with the first active layer 1211, the first flat portion 131 is always located above the first active layer 1211 to protect the first active layer 1211 and prevent it from undergoing oxidation or reduction reactions due to environmental factors (such as oxygen) in subsequent processes, which could lead to electrical performance degradation problems such as threshold voltage drift and decreased mobility, thus affecting the stability and reliability of the device.

[0020] Unless otherwise specified, in the array substrate 10, "above" B means that A is located on the side of B that is away from the first substrate 11.

[0021] It should be noted that thin-film transistors can be like... Figure 5As shown, this is a back-channel etching (BCE) type in a bottom-gate structure, where the source and drain electrodes are fabricated on the active layer using an etching process. In other embodiments, the thin-film transistor can also be a bottom-gate structure with a back-channel etch-stop layer (ESL), where an etch-stop layer is added on the active layer before the source and drain electrodes are fabricated using a photolithography etching process. In other embodiments, the thin-film transistor can also be a top-gate structure, where the gate is located above the active layer. This application does not specifically limit this type of structure.

[0022] In related technologies, such as Figure 4 As shown, in the non-display area A2, the display panel 100' includes a sealant 32' disposed between the array substrate 10' and the opposing substrate 20', and a support member 31' located within the sealant 32'. In the non-display area A2, the first thin-film transistor 120' is located away from the display area A1. The array substrate 10' also includes multiple metal traces 14' located on the first substrate 11' facing the opposing substrate 20'. Typically, the planarization layer 13' above the metal traces 14' is completely removed to prevent moisture from entering from the external environment and penetrating through the planarization layer 13' to the surface of the metal traces 14', thereby preventing corrosion of the metal traces 14' under moisture, which could lead to open or short circuits and affect the electrical performance and lifespan of the display panel 100'. However, combined with... Figure 4 As shown, since the first flat portion 131' is retained above the first active layer 121', while the flat portion 13' is removed above the metal trace 14', the support of the support member 31' varies at different locations in the surrounding area. This results in unstable support of the support member 31' in the surrounding area of ​​the display panel, leading to yellowing and other appearance defects in the surrounding area of ​​the display panel, and even affecting the display performance and reliability of the product.

[0023] To solve the above problems, refer to Figure 5 and Figures 15 to 18As shown, the present application proposes a counter substrate 20 including a second substrate 21 and a pad layer 24 located on the second substrate 21 facing the array substrate 10. The projection of the pad layer 24 onto the plane of the first substrate 11 is a first projection S1 / S11, and the projection of the first flat portion 131 onto the plane of the first substrate 11 is a second projection S31. The first projection S1 / S11 is located on the side of the second projection S31 away from the display area A1. Furthermore, the projection S31 of the first flat portion 131 onto the plane of the first substrate 11 overlaps with the projection S2 of the first active layer 1211 onto the plane of the first substrate 11. On the opposing substrate 20, a pad 24 is provided at the position where the planarization layer 13 is removed above the metal trace 14. The pad 24 corresponds vertically to the area of ​​the planarization layer 13 removed above the metal trace 14, thereby structurally replacing the thickness of the removed planarization layer 13. The first projection S1 / S11 is located on the side of the second projection S31 away from the display area A1. This is mainly because the metal trace 14 is located on the side of the second projection S31 away from the display area, so that the position of the pad 24 corresponds to the position of the metal trace 14. This effectively compensates for the thickness of the removed planarization layer 13 above the metal trace 14, helps to maintain the uniformity and consistency of the spacing between the array substrate 10 and the opposing substrate 20, avoids the problem of uneven liquid crystal cell thickness, and effectively prevents appearance defects such as yellowing around the display panel caused by differences in liquid crystal cell thickness.

[0024] Optionally, the material of the metal trace 14 may include copper (Cu). Copper has a much lower resistivity than other metal materials. Under the same linewidth, copper metal traces have a higher current carrying capacity, which can effectively reduce line loss, improve signal integrity, and reduce heat generation in high current transmission or high frequency signal transmission. Furthermore, in display panels using oxide thin film transistors, the etching process of copper metal traces has a smaller impact on oxide semiconductor devices.

[0025] In one embodiment of this application, reference continues to be made to... Figure 5As shown, in the non-display area A2, the display panel 100 further includes a sealant 32 disposed between the array substrate 10 and the opposing substrate 20, and a support member 31 located within the sealant 32. Optionally, the support member 31 located within the sealant 32 may be a spherical support particle. Optionally, the sealant 32 overlaps with at least a portion of the pad layer 24 in a direction perpendicular to the plane of the first substrate 11, and overlaps with at least a portion of the first flat portion 131. The support member 31 is located within the sealing adhesive 32 and, together with the pad 24 on the opposing substrate 20 or the first flat portion 131 on the array substrate 10, provides support in a direction perpendicular to the first substrate 11. Through the cooperation between the support member 31 and the pad 24, the support area between the array substrate 10 and the opposing substrate 20 can be effectively increased in the non-display area A2, thereby improving the support effect of the support member 31. Furthermore, the support member 31, together with the support structures 25 / 26 in the display area A1, can effectively maintain the spacing between the upper and lower substrates, ensuring that the thickness of the liquid crystal cell remains consistent throughout the entire display panel, reducing stress concentration caused by uneven support, thereby improving display performance and structural stability.

[0026] In one embodiment of this application, reference continues to be made to... Figure 5 As shown, in the direction perpendicular to the plane of the first substrate 11, the pad 24 and the first flat portion 131 do not overlap. Specifically, in the direction parallel to the plane of the first substrate 11, the pad 24 is located on the side of the first flat portion 131 away from the display area A1, and the projections of the pad 24 and the first flat portion 131 in the direction perpendicular to the first substrate 11 are exactly adjacent; or, the projections of the pad 24 and the first flat portion 131 in the direction perpendicular to the first substrate 11 have a certain distance; optionally, the distance between the projections of the edge of the pad 24 near the first flat portion 131 and the edge of the first flat portion 131 near the pad 24 in the direction perpendicular to the first substrate 11 can be in the range of 1µm to 5µm. The setting of this distance takes into account the particle size characteristics of the support member 31. If the distance is too small, the support member 31 may be supported by two support structures 24 / 131 at the same time, thereby affecting its support effect and the support thickness between the array substrate 10 and the opposing substrate 20. By controlling the relationship between the spacing and the particle size of the support member 31, the distribution stability of the support member 31 and the reliability of the overall support structure can be improved. Therefore, this design helps to avoid structural interference or stress concentration caused by the height difference between the pad layer 24 and the first flat portion 131, and reduces the risk of poor appearance caused by local thickness abrupt changes due to the support member 31 falling between the pad layer 24 and the first flat portion 131.

[0027] Figure 6 The embodiments of this application provide the following: Figure 2 and Figure 3Another cross-sectional structural diagram along the A-A' direction; Figure 7 The embodiments of this application provide the following: Figure 2 and Figure 3 Another cross-sectional structural diagram along the A-A' direction.

[0028] In one embodiment of this application, reference is made to Figures 6 to 7 The display area A1 includes a main spacer 25 and an auxiliary spacer 26. The thickness d1 of the main spacer 25 in the direction perpendicular to the plane of the first substrate 11 is greater than the thickness d2 of the auxiliary spacer 26 in the direction perpendicular to the plane of the first substrate 11. Please refer to [link to relevant documentation]. Figure 6 The thickness d1 of the main spacer 25 differs from the thickness d4 of the first flat portion 131 by |d1-d4| < 0.2 μm, and the thickness d3 of the pad 24 differs from the thickness d1 of the main spacer 25 by |d3-d1| < 0.2 μm; or, please refer to Figure 7 The difference between the thickness d2 of the auxiliary spacer 26 and the thickness d4 of the first flat portion 131 is |d2-d4|<0.2um, and the difference between the thickness d3 of the pad 24 and the thickness d2 of the auxiliary spacer 26 is |d3-d2|<0.2um.

[0029] It should be noted that, due to the varying thicknesses of the source 1212, drain 1213, and active layer 1211 covered beneath the first flattened portion 131 in different regions, the thickness of the first flattened portion 131 also varies at different locations. Therefore, the thickness d4 of the first flattened portion 131 can be understood as the vertical distance from the surface of the first flattened layer 131 near the sealant 32 to the surface of the first flattened layer 131 near a certain reference position below it. This reference position can be any structural layer beneath the first flattened layer 131, such as, but not limited to, the first active layer 1211, the source 1212, or the drain 1213. This application does not limit the specific selection of the reference position.

[0030] Specifically, the display panel 100 includes an array substrate 10 and an opposing substrate 20. In the display area A1, the array substrate 10 includes a plurality of thin-film transistors 12. Each thin-film transistor 12 includes a gate 1224, an active layer 1221, an insulating layer 1225 located between the gate 1224 and the active layer 1221, and a source electrode 1222 and a drain electrode 1223 in contact with the active layer 1221. Above the source electrode 1222 and the drain electrode 1223, a planarization layer 13 is also included. The planarization layer 13 is located on the side of the active layer 1221 away from the first substrate 11 and covers the active layer 1221. Above the planarization layer 13, a common electrode 15 and a pixel electrode 16 are also disposed. The pixel electrode 16 is electrically connected to the drain electrode 1223 (or the source electrode 1222) of the thin-film transistor 12 through a via. Typically, the common electrode 15 and the pixel electrode 16 are conductors made of oxide materials, such as ITO (Indium Tin Oxide).

[0031] It should be noted that the common electrode 15 and the pixel electrode 16 can be disposed in different functional layers and interlayer insulation is achieved through the passivation layer 17; alternatively, they can be disposed in the same layer and electrically isolated from each other through an insulating structure. This application does not specifically limit this structural design.

[0032] Continue to refer to Figures 6 to 7 In the display area A1, the opposing substrate 20 includes a second substrate 21 and a protective layer 23 located on the second substrate 21 facing the array substrate 10. A black matrix 22 is also included between the second substrate 21 and the protective layer 23. The opposing substrate 20 also includes spacers located on the protective layer 23 facing the array substrate 10. The spacers include a main spacer 25 and an auxiliary spacer 26. The thickness d1 of the main spacer 25 in the direction perpendicular to the plane of the first substrate 11 is greater than the thickness d2 of the auxiliary spacer 26 in the direction perpendicular to the plane of the first substrate 11. Both the main spacer 25 and the auxiliary spacer 26 are used to maintain the spacing between the array substrate 10 and the opposing substrate 20, ensuring the stability and bonding accuracy of the display panel 100. The main spacer 25 is usually located in a critical position in the display area A1. It is relatively thick and serves as the main support structure, playing a core role in maintaining the substrate spacing. It has high mechanical strength and stability. The auxiliary spacers 26 are distributed in the blank areas between the main spacers 25. They are relatively thin and mainly serve to provide auxiliary support, adjust local stress, improve bonding uniformity, and reduce the risk of display defects. The two work together to ensure the structural strength of the display panel 100, improve bonding quality, and enhance overall display performance.

[0033] refer to Figure 6 and Figure 7When the difference between the thickness d1 of the main spacer in display area A1 and the thickness d4 of the first flat portion 131 in non-display area A2 is less than 0.2 μm, the difference between the thickness d3 of the pad 24 in non-display area A2 and the thickness d1 of the main spacer 25 is also less than 0.2 μm; when the difference between the thickness d2 of the auxiliary spacer 26 in display area A1 and the thickness d4 of the first flat portion 131 is less than 0.2 μm, the difference between the thickness d3 of the pad 24 in non-display area A2 and the thickness d1 of the auxiliary spacer 26 is also less than 0.2 μm. Optionally, the thickness d4 of the first flat portion 131 is 1-5 μm, the thickness d1 of the main spacer 25 is 3-5 μm, and the thickness d2 of the auxiliary spacer 26 is 1-3 μm. It should be noted that the above thickness range is only an exemplary embodiment, and in actual design, it can be adjusted according to the specific structure, process conditions, and performance requirements of the display panel 100. This application does not impose specific limitations on this. In one embodiment, such as Figure 6 As shown, the thickness d4 of the first flat portion 131 differs from the thickness d1 of the main spacer 25 by less than 0.2 μm. Therefore, the pad 24 and the main spacer 25 in the non-display area A2 can be formed through the same process step, and the thickness d3 of the formed pad 24 differs from the thickness d1 of the main spacer 25 by less than 0.2 μm. In another embodiment, as... Figure 7 As shown, the difference between the thickness d4 of the first flat portion 131 and the thickness d2 of the auxiliary spacer 26 is less than 0.2µm. Therefore, the pad 24 and the auxiliary spacer 26 in the non-display area A2 can be formed through the same process step, and the difference between the thickness d3 of the formed pad 24 and the thickness d2 of the auxiliary spacer 26 is less than 0.2µm. This allows the difference between the overall cell thickness at the location of the metal trace 14 in the non-display area A2 and the overall cell thickness at the location of the first active layer 1211 to be controlled within 0.2µm, helping to reduce stress concentration caused by height abrupt changes and improving the structural stability and reliability of the display panel 100. Furthermore, since the pad 24 in the non-display area A2 is formed through the same process step as the main spacer 25 or the auxiliary spacer 26, no additional process steps are required, effectively saving manufacturing costs and improving production efficiency.

[0034] Figure 8 The embodiments of this application provide the following: Figure 2 and Figure 3 Another cross-sectional structural diagram along the A-A' direction.

[0035] In one embodiment of this application, combined with Figure 2 , Figure 3 and Figure 8As shown, the opposing substrate 20 further includes a protective layer 23, which is located on the side of the pad layer 24 facing the array substrate 10; the display area A1 includes a color resist 27, which includes a red color resist 271, a green color resist 272, and a blue color resist 273; the material of the pad layer 24 is the same as any one of the red color resist 271, green color resist 272, and blue color resist 273; or, the pad layer 24 includes a multilayer stack of different materials, the materials of which include at least two of the red color resist 271, green color resist 272, and blue color resist 273. Specifically, as Figure 8 As shown, in display area A1, in the direction from the second substrate 21 to the array substrate 10, the opposing substrate 20 includes, from bottom to top, the second substrate 21, the black matrix 22, the color resist 27, and the protective layer 23. The color resist includes a red color resist 271, a green color resist 272, and a blue color resist 273. The color resist 27 is a key structural layer in the display panel for achieving color display. It is composed of red, green, and blue filter materials. Its main function is to decompose the white light from the backlight into the three primary colors of red, green, and blue, thereby achieving full-color display. The color resist 27 works in conjunction with the black matrix 22 to effectively improve the color saturation and contrast of the display panel 100. Optionally, the pad layer 24 in the non-display area A2 is located in the same film layer as the color resist in the display area A1, that is, between the black matrix 22 and the protective layer 23. The material of the pad layer 24 is the same as that of the red color resist 271 and is formed in the same process; or, the material of the pad layer 24 is the same as that of the green color resist 272 and is formed in the same process; or, the material of the pad layer 24 is the same as that of the blue color resist 273 and is formed in the same process. In this way, the difference between the entire cell thickness at the location of the metal trace 14 in the non-display area A2 and the entire cell thickness at the location of the first active layer 1211 can be controlled within 0.2um, which helps to reduce stress concentration caused by height abrupt changes and improve the structural stability and reliability of the display panel. In addition, the pad layer 24 in the non-display area A2 is formed using the same process steps as any of the color resists 27, which eliminates the need for additional process steps, effectively saving manufacturing costs and improving production efficiency.

[0036] Figure 9 This is provided by the embodiments of this application. Figure 8 Enlarged schematic diagram of the intermediate cushion layer structure; Figure 10 This is provided by the embodiments of this application. Figure 8 Another enlarged schematic diagram of the intermediate cushion layer structure; Figure 11 This is provided by the embodiments of this application. Figure 8 Another enlarged schematic diagram of the intermediate cushion layer structure; Figure 12 This is provided by the embodiments of this application. Figure 8 Another enlarged schematic diagram of the intermediate cushion layer structure.

[0037] In some other embodiments, such as Figures 8 to 12 As shown, the pad 24 comprises multiple layers formed of different materials, including at least two of the following materials: red color resist 271, green color resist 272, and blue color resist 273. Optionally, as... Figure 9 As shown, the pad 24 may comprise a laminate of two materials: red color resist 271 and green color resist 272; or, as... Figure 10 As shown, the pad 24 may include a laminate of two materials: red color resist 271 and blue color resist 273; or, as... Figure 11 As shown, the padding layer 24 may comprise a laminate of two materials: green color resist 272 and blue color resist 273; or, as... Figure 12 As shown, the pad 24 may include a stack of three materials: red color resist 271, green color resist 272, and blue color resist 273. Since a protective layer 23 covers the pad 24 when color resist 27 is used as the pad material, a good flatness of the protective layer 23 may weaken or eliminate the step difference inherent in the color resist 27 material itself in the final structure. However, the stacked structure composed of multiple layers of color resist 27 material, by increasing the number of color resist 27 material layers, forms a more significant step difference, thereby compensating for the height differences between different areas of the non-display area A2 and improving the structural stability and reliability of the display panel 100.

[0038] It should be noted that in the multilayer color resist material stacked structure used in this application, the arrangement order of each color resist material layer can be flexibly adjusted according to design requirements, process conditions, or display performance requirements. This application does not impose a specific limitation on the arrangement order of the color resist materials, in order to adapt to different application scenarios.

[0039] Figure 13 The embodiments of this application provide the following: Figure 2 and Figure 3 Another cross-sectional structural diagram along the A-A' direction; Figure 14 The embodiments of this application provide the following: Figure 2 and Figure 3 Another cross-sectional structural diagram along the A-A' direction.

[0040] In one embodiment of this application, such as Figures 13 to 14 As shown, the padding layer 24 includes multiple separately arranged sub-padding layer structures 241 in the direction from the non-display area A2 to the display area A1. Optionally, as... Figure 13As shown, the padding layer 24 includes multiple sub-padding layer structures 241, wherein the sub-padding layer structures 241 and the main spacer 25 can be formed through the same process step, and the difference between the thickness d3 of the formed padding layer 24 and the thickness d1 of the main spacer 25 is less than 0.2 μm; or, the padding layer 24 includes multiple sub-padding layer structures 241, wherein the sub-spacer structures 241 and the auxiliary spacer 26 can be formed through the same process step, and the difference between the thickness d3 of the formed padding layer 24 and the thickness d2 of the auxiliary spacer 26 is less than 0.2 μm. Optionally, as... Figure 14 As shown, the material of the sub-pad structure 241 is the same as that of the red color resist 271 and is formed in the same process; or, the material of the sub-pad structure 241 is the same as that of the green color resist 272 or the blue color resist 273 and is formed in the same process; or, the sub-pad structure 241 comprises a stack of multiple layers formed of different color resist 27 materials. Optionally, in the plurality of discretely arranged sub-pad structures 241, the minimum spacing between the two adjacent edges of two adjacent sub-pad structures 241 can be set to 1μm to 5μm. By controlling this spacing range, excessively large gaps between adjacent sub-pad structures 241 can be effectively avoided, thereby preventing the support member 31 from lacking a corresponding support pad in this area, ensuring the support stability and reliability of the overall structure. Because large-area pad structures may have problems such as uneven film formation, difficulty in etching control, and edge effects in actual processes, resulting in high process complexity and low yield, the pad structure 24 is designed as multiple discrete sub-pad structures 241. This not only effectively reduces the area of ​​a single process and improves the uniformity of film formation and etching, but also enables better structural support and height control in subsequent processes.

[0041] Continue to refer to Figure 14 In one embodiment of this application, the planarization layer 13 further includes a plurality of separately disposed second planarization portions 132, the second planarization portions 132 being located in a direction away from the display area A1 from the first planarization portion 131; in a direction perpendicular to the plane of the first substrate 11, the second planarization portions 132 do not overlap with the sub-pad structure 241. For example, as... Figure 14As shown, the planarization layer 13 also includes multiple separately arranged second planarization portions 132. The second planarization portions 132 are located above the metal traces 14 or in the gaps between adjacent metal traces 24. In the direction perpendicular to the plane of the first substrate 11, the second planarization portions 132 do not overlap with the sub-pad structure 241. The planarization layer 13 retained above the metal traces 14 includes independently arranged patterns at intervals, which can effectively block the path of moisture in the external environment of the display panel 100 to spread into the metal traces 14 through the continuous planarization layer 13, thereby preventing moisture from directly contacting the metal traces 14, reducing the risk of corrosion, and improving the structural stability of the metal traces 14 and the long-term reliability of the display panel 100. It also reduces the removal range of the planarization layer 13 above the metal traces 14, making the removal process easier to control, improving product yield, and improving structural stability. By separating the second planarization portions 132 from the sub-pad structure 241 in the vertical direction, the structural height transition between the display area A1 and the non-display area A2 can be better controlled. This design helps reduce height abrupt changes caused by structural stacking, thereby improving the bonding accuracy and structural stability of the display panel 100 and avoiding problems such as stress concentration or poor bonding caused by excessive height difference.

[0042] Figure 15 This is provided in the embodiments of this application. Figures 5 to 8 and Figures 13 to 14 The corresponding figure in any of the middle Figure 1 The projection of the pads 24 / 241, planarization layers 131 / 132, and first active layer 1311 in region B1 onto the plane of the first substrate 11; Figure 16 This is provided in the embodiments of this application. Figures 5 to 8 and Figures 13 to 14 The corresponding figure in any of the middle Figure 1 Another projection of the pads 24 / 241, planarization layers 131 / 132, and first active layer 1311 in region B1 onto the plane of the first substrate 11. Figure 17 This is provided in the embodiments of this application. Figures 5 to 8 and Figures 13 to 14 The corresponding figure in any of the middle Figure 1 Another projection of the padding layer 24 / 241, the planarization layer 131 / 132, and the first active layer 1311 in the B1 region onto the plane of the first substrate 11; Figure 18 This is provided in the embodiments of this application. Figures 5 to 8 and Figures 13 to 14 The corresponding figure in any of the middle Figure 1 Another projection of the pads 24 / 241, planarization layers 131 / 132, and first active layer 1311 in region B1 onto the plane of the first substrate 11.

[0043] In one embodiment of this application, combined with Figures 14 to 18 As shown, the planarization layer 13 also includes a plurality of separately arranged second planar portions 132, which are located in the direction away from the display area A1 of the first planar portion 131; in the first direction, the projection S32 of the second planar portion 132 in the direction perpendicular to the plane of the first substrate 11 and the projection S11 of the sub-pad structure 241 in the direction perpendicular to the plane of the first substrate 11 are alternately arranged; and / or, in the second direction, the projection S32 of the second planar portion 132 in the direction perpendicular to the plane of the first substrate 11 and the projection S11 of the sub-pad structure 241 in the direction perpendicular to the plane of the first substrate 11 are alternately arranged; the first direction is the direction from the non-display area A2 to the display area A1, and the second direction intersects the first direction. Specifically, as Figures 15 to 18 As shown, the first direction is the direction from the non-display area A2 to the display area A1, marked as the x-direction in the figure. The second direction intersects the first direction and is marked as the y-direction in the figure. Optionally, the y-direction of the second direction is perpendicular to the x-direction of the first direction. Alternatively, as... Figure 15 As shown, in the x-direction, the projection S32 of the second flat portion 132 in the direction perpendicular to the plane of the first substrate 11 and the projection S11 of the sub-pad structure 241 in the direction perpendicular to the plane of the first substrate 11 are alternately arranged; optionally, as... Figure 16 As shown, in the y-direction, the projection S32 of the second flat portion 132 in the direction perpendicular to the plane of the first substrate 11 and the projection S11 of the sub-pad structure 241 in the direction perpendicular to the plane of the first substrate 11 are alternately arranged; optionally, as shown... Figure 17 As shown, the projection S32 of the second flat portion 132 in the direction perpendicular to the plane of the first substrate 11 and the projection S11 of the sub-pad structure 241 in the direction perpendicular to the plane of the first substrate 11 are simultaneously and alternately arranged in the x and y directions. This structural design allows the second flat portion 132 and the sub-pad structure 241 to be spaced apart in the horizontal direction, thereby forming a uniform distribution of support points in the overall panel structure and effectively improving the support stability of the panel. Furthermore, since the second flat portion 132 and the sub-pad structure 241 do not overlap in the horizontal direction, the process steps in forming the planarization layer 13 removal structure and the sub-pad structure 241 are simpler, which is beneficial for improving process yield and production efficiency.

[0044] It should be noted that the first flat portion 131 covers the first active layer 1211. For ease of illustration, Figures 15 to 18 The first planarization layer 131 is shown in a transparent manner to clearly show the location of the first thin-film transistor 120 beneath it. This illustration is for convenience only and does not constitute any limitation on the embodiments of this application.

[0045] In addition, the shape of the sub-cushion layer 241 can be any shape, such as a circle, rectangle, polygon, or irregular shape, and this application does not impose any restrictions on it.

[0046] In one embodiment of this application, reference continues to be made to... Figures 15 to 18 The first flat portion 131 covers a plurality of first active layers 1211 arranged along the extension direction of the non-display area A2; in a plane parallel to the first substrate 11, the opposing edges of the pad layer 24 and the first flat portion 131 are parallel to each other. This ensures a uniform distribution of support points after bonding, which helps to improve the structural stability of the panel and reduce collapse or deformation caused by structural misalignment. In another embodiment of this application, reference continues to... Figures 15 to 18 In a direction parallel to the plane of the first substrate 11, the distance a1 between the edge of the pad 24 near the first flat portion 131 and the edge of the first flat portion 131 near the pad 24 ranges from 1µm to 5µm. Specifically, the distance a1 between the edge of the pad 24 near the first flat portion 131 and the edge of the first flat portion 131 near the pad 24 can be 3µm. Optionally, the display panel 100 further includes circuitry located in the non-display area A2, including at least one of a gate drive circuit, an anti-static circuit, a visual testing circuit, and a multiplexing circuit; the circuitry includes the first thin-film transistor 120. Specifically, refer to... Figures 15 to 18 The circuit covered by the first planarization layer 131 can be at least one of a gate driving circuit, an anti-static circuit, a visual testing circuit, and a multiplexing circuit. The circuit covered by the first planarization layer 131 includes a first thin-film transistor 120, which includes a first active layer 1211. The gate driving circuit can be located on the left and right sides of the display area A1, while the anti-static circuit, visual testing circuit, and multiplexing circuit can be located on the top and bottom sides of the display area A1. By providing a planarization layer 13 in the area of ​​at least one of the gate driving circuit, anti-static circuit, visual testing circuit, and multiplexing circuit, the active layer 1221 of the thin-film transistor 12 can be effectively isolated from the external environment, preventing the active layer 1221 from contacting oxygen, thereby avoiding oxidation or reduction reactions. This effectively improves the stability and lifespan of the circuit, reduces problems such as threshold voltage drift and increased leakage current of the thin-film transistor 12 caused by oxidation, and enhances the reliability of the gate driving circuit, anti-static circuit, visual testing circuit, and multiplexing circuit, improving the overall performance and yield of the display panel 100.

[0047] In one embodiment of this application, reference continues to be made to... Figures 5 to 8 and Figures 13 to 14The array substrate 10 also includes metal traces 14 located on the first substrate 11 facing the opposing substrate 20, and the pad layer 24 overlaps with one or more metal traces 14 in a direction perpendicular to the plane of the first substrate 11. Optionally, as Figures 5 to 8 As shown, the pad 24 is a continuous structure. The pad 24 overlaps with multiple metal traces 14 in a direction perpendicular to the plane of the first substrate 11, which effectively increases the support area of ​​the pad 24 and improves its structural stability. Optionally, as... Figures 13 to 14 As shown, the pad 24 consists of multiple discrete sub-pad structures 241. The sub-pad structures 241 overlap with one or more metal traces 14 in a direction perpendicular to the plane of the first substrate 11, which can effectively reduce the area of ​​a single process and improve the uniformity of film formation and etching.

[0048] Accordingly, embodiments of this application also provide a display device 200, such as... Figure 19 The diagram shown is a structural schematic of a display device 200 provided in an embodiment of this application. The display device 200 includes the aforementioned display panel 100. The display device 200 can be a mobile phone, computer, television, smart wearable device, etc., and this embodiment of the application does not limit its functionality. It is understood that the display device 200 can also achieve all the technical effects that the aforementioned display panel 100 can achieve, and will not be described in detail here.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: The display area and the non-display area surrounding the display area; The display panel further includes: an array substrate and an opposing substrate disposed opposite to each other; The array substrate includes a first substrate and a plurality of thin-film transistors located on the first substrate and facing the opposing substrate. In the non-display area, the thin-film transistors include a first thin-film transistor, and the first thin-film transistor includes a first active layer. The array substrate further includes a planarization layer, the planarization layer including a first planar portion, the first planar portion covering the first active layer; The opposing substrate includes a second substrate and a pad layer located on the second substrate and facing the array substrate. The projection of the pad layer onto the plane of the first substrate is a first projection, and the projection of the first flat portion onto the plane of the first substrate is a second projection. The first projection is located on the side of the second projection away from the display area.

2. The display panel according to claim 1, characterized in that, In a direction perpendicular to the plane of the first substrate, the pad layer does not overlap with the first flat portion.

3. The display panel according to claim 1, characterized in that, The display area includes a main spacer and an auxiliary spacer. The thickness of the main spacer in the direction perpendicular to the plane of the first substrate is greater than the thickness of the auxiliary spacer in the direction perpendicular to the plane of the first substrate. The thickness of the main spacer differs from the thickness of the first flat portion by less than 0.2 μm, and the thickness of the pad layer differs from the thickness of the main spacer by less than 0.2 μm; or, The thickness of the auxiliary spacer is less than 0.2 μm different from the thickness of the first flat portion, and the thickness of the pad layer is less than 0.2 μm different from the thickness of the auxiliary spacer.

4. The display panel according to claim 1, characterized in that, The opposing substrate further includes a protective layer located on the side of the pad layer facing the array substrate; The display area includes color resist, which includes red, green and blue color resist; The material of the pad layer is the same as that of any one of the red color resist, the green color resist, and the blue color resist; or, the pad layer comprises multiple layers of different materials, wherein the material of the layer comprises at least two of the red color resist, the green color resist, and the blue color resist.

5. The display panel according to claim 1, characterized in that, The padding layer includes multiple separately arranged sub-padding layer structures in the direction from the non-display area to the display area.

6. The display panel according to claim 5, characterized in that, The planarization layer further includes a plurality of separately arranged second planar portions, the second planar portions being located in the direction away from the display area of ​​the first planar portion; in the direction perpendicular to the plane of the first substrate, the second planar portions do not overlap with the sub-pad layer structure.

7. The display panel according to claim 5, characterized in that, The planarization layer further includes a plurality of separately arranged second planar portions, the second planar portions being located in a direction away from the display area of ​​the first planar portion; in a first direction, the projection of the second planar portion in a direction perpendicular to the plane of the first substrate is alternately arranged with the projection of the sub-pad structure in a direction perpendicular to the plane of the first substrate; and / or, in a second direction, the projection of the second planar portion in a direction perpendicular to the plane of the first substrate is alternately arranged with the projection of the sub-pad structure in a direction perpendicular to the plane of the first substrate; The first direction is the direction from the non-display area to the display area, and the second direction intersects with the first direction.

8. The display panel according to claim 1, characterized in that, The first flat portion covers a plurality of the first active layers arranged along the extension direction of the non-display area; In a plane parallel to the first substrate, the opposing edges of the pad and the first flat portion are parallel to each other.

9. The display panel according to claim 8, characterized in that, The display panel also includes circuitry located in the non-display area, the circuitry including at least one of a gate driving circuit, an anti-static circuit, a visual testing circuit, and a multiplexing circuit; The circuit includes the first thin-film transistor.

10. The display panel according to claim 1, characterized in that, The array substrate further includes metal traces located on the first substrate and facing the opposing substrate, and the pad layer overlaps with one or more of the metal traces in a direction perpendicular to the plane of the first substrate.

11. The display panel according to claim 1, characterized in that, In a direction parallel to the plane of the first substrate, the distance between the edge of the pad layer near the first flat portion and the edge of the first flat portion near the pad layer ranges from 1µm to 5µm.

12. The display panel according to claim 1, characterized in that, It also includes a sealing adhesive disposed between the array substrate and the opposing substrate, and a support member located within the sealing adhesive.

13. The display panel as claimed in claim 12, characterized in that, The sealing adhesive is located in the non-display area, and the sealing adhesive overlaps with at least a portion of the pad layer in a direction perpendicular to the plane of the first substrate, and also overlaps with at least a portion of the first flat portion.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1-13.

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