A memory device and method of manufacture

Abstract

This invention discloses a memory device and its manufacturing method. The memory device includes a phase-change memory cell disposed on a substrate. The phase-change memory cell includes a first electrode, a phase-change unit, and a second electrode sequentially connected along a direction away from the substrate surface. The phase-change unit is a first annular body. The top end of the first electrode is in direct contact with the bottom surface of the first annular body, and the outer periphery of the top end of the first electrode completely surrounds the inner periphery of the bottom surface of the first annular body. The outer periphery of the bottom surface of the first annular body also completely surrounds the outer periphery of the top end of the first electrode, thereby reducing the contact area between the first electrode and the phase-change unit. This invention saves space and simplifies the manufacturing process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a memory device and its manufacturing method. Background Technology

[0002] As semiconductor technology continues to advance, transistor sizes are shrinking, allowing for increasingly higher densities of contact holes. However, the miniaturization of embedded memories lags significantly behind these advancements. Traditional phase-change memories (PCMs) typically require blade electrodes with very small contact areas to generate significant heat when current flows, altering the resistive properties of the phase-change material. Manufacturing these blade electrodes consumes considerable vertical space and involves numerous process steps, increasing manufacturing complexity. Consequently, PCMs occupy significantly more vertical space than other types of memory, complicating embedding. Furthermore, these traditional embedded memories can only increase storage density by shrinking the critical dimensions of the storage film, hindering capacity expansion. Summary of the Invention

[0003] The purpose of this invention is to overcome the above-mentioned defects in the prior art and to provide a storage device and a manufacturing method thereof.

[0004] To achieve the above objectives, the technical solution of the present invention is as follows: This invention provides a storage device, comprising: A phase change memory cell disposed on a substrate includes a first electrode, a phase change unit, and a second electrode connected sequentially along a direction away from the substrate surface. The phase change unit is a first annular body. The top end of the first electrode is in direct contact with the bottom surface of the first annular body, and the outer periphery of the top end of the first electrode completely surrounds the inner periphery of the bottom surface of the first annular body. The outer periphery of the bottom surface of the first annular body completely surrounds the outer periphery of the top end of the first electrode, so as to reduce the contact area between the first electrode and the phase change unit.

[0005] Furthermore, there are multiple phase change memory cells, and the first annular body of each phase change memory cell is divided into upper and lower layers in a direction away from the substrate surface; In this configuration, the orthographic projections of each of the first annular bodies on the substrate surface form a non-overlapping array distributed in rows and columns. The two first annular bodies corresponding to two adjacent orthographic projections in the same row are located in different layers, and the two first annular bodies corresponding to two adjacent orthographic projections in the same column are located in different layers. In any 2×2 orthographic projections, the two first annular bodies corresponding to every two orthographic projections at diagonal positions are located in the same layer, forming a stacked storage device.

[0006] Furthermore, the second electrode is a second annular body, which is coaxially arranged with the first annular body and together forms an annular body. Furthermore, it also includes an electrode lead-out structure connected to the top surface of the second annular body away from the substrate.

[0007] Furthermore, the first electrode and the electrode lead-out structure include contact holes; and / or, a dielectric layer is provided on the surface of the substrate, and the phase change storage unit is disposed in the dielectric layer.

[0008] The present invention also provides a method for manufacturing a storage device, comprising: A phase change memory cell is formed on a substrate. The phase change memory cell includes a first electrode, a phase change unit, and a second electrode connected sequentially in a direction away from the substrate surface. The phase change unit is a first annular body. The top end of the first electrode is in direct contact with the bottom surface of the first annular body, and the outer periphery of the top end of the first electrode completely surrounds the inner periphery of the bottom surface of the first annular body. The outer periphery of the bottom surface of the first annular body completely surrounds the outer periphery of the top end of the first electrode, so as to reduce the contact area between the first electrode and the phase change unit.

[0009] Furthermore, when forming a phase change memory cell, the process includes forming a plurality of phase change memory cells, such that the first annular body of each phase change memory cell is divided into upper and lower layers in a direction away from the surface of the substrate. In this configuration, the orthographic projections of each of the first annular bodies on the substrate surface form a non-overlapping array distributed in rows and columns. The two first annular bodies corresponding to two adjacent orthographic projections in the same row are located in different layers, and the two first annular bodies corresponding to two adjacent orthographic projections in the same column are located in different layers. In any 2×2 orthographic projections, the two first annular bodies corresponding to every two orthographic projections at diagonal positions are located in the same layer, forming a stacked storage device.

[0010] Furthermore, the storage device forming the stacked structure specifically includes: A first dielectric layer is formed on the surface of the substrate; A plurality of first contact holes connected to the substrate are formed on the surface of the first dielectric layer, such that each of the first contact holes forms an array distributed in rows and columns on the surface of the substrate; A second dielectric layer is formed on the surface of the first dielectric layer to cover each of the first contact holes; A trench is formed on the surface of the second dielectric layer, exposing the top surface of each of the first contact holes located on the bottom surface of the trench; A lower phase change material layer and an electrode material layer are sequentially formed on the surface of the second dielectric layer, and the trench is filled. The lower phase change material layer and electrode material layer are patterned, and a phase change unit and a second electrode located in the lower layer are formed on the top surface of a portion of the first contact hole at the bottom of the trench, exposing the top surface of the remaining portion of the first contact hole. A third dielectric layer is formed on the surface of the second dielectric layer, covering the second electrode and phase change unit located in the lower layer, as well as the remaining exposed portion of the first contact hole, and forming a flat surface of the third dielectric layer. A second contact hole is formed on the surface of the third dielectric layer, the bottom of which is in contact with the top surface of the remaining portion of the first contact hole. An upper phase change material layer and an electrode material layer are sequentially formed on the surface of the third dielectric layer to cover the second contact hole; The upper phase change material layer and the electrode material layer are patterned, and a phase change unit and a second electrode are formed on the top surface of the second contact hole. The first contact hole connected to the phase change unit located in the lower layer forms the first electrode, and the second contact hole connected to the phase change unit located in the upper layer and the first contact hole together form the first electrode.

[0011] Furthermore, when forming the phase change unit and the second electrode, the phase change unit is formed as a first ring body, the second electrode is formed as a second ring body, and the second ring body and the first ring body are coaxially arranged to form a ring body together.

[0012] Furthermore, it also includes: A fourth dielectric layer is formed on the surface of the third dielectric layer, covering the second electrode and phase change unit located on the upper layer, and forming a flat surface of the fourth dielectric layer; A third contact hole is formed on the surface of the fourth dielectric layer, with its bottom surface corresponding to the top surface of the second electrode located in the lower layer and the top surface of the second electrode located in the upper layer. The third contact hole serves as an electrode lead-out structure; the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer together form a dielectric layer.

[0013] As can be seen from the above technical solution, this invention designs the phase change unit as a ring (first ring), so that the outer periphery of the top of the first electrode, which directly contacts the bottom surface of the ring, is located between the inner and outer peripheries of the bottom surface of the ring. This reduces the contact area between the first electrode and the phase change unit, achieving an effect similar to a blade electrode, thus replacing the traditional blade electrode. This saves the space occupied by the original blade electrode and simplifies the manufacturing process. Furthermore, by utilizing the space saved from the original blade electrode, an additional layer of phase change units can be added to the entire storage device. By staggering the upper and lower layers of phase change units, a non-overlapping array is formed on the plane, achieving a significant increase in storage density and expanding storage capacity. Attached Figure Description

[0014] Figures 1-2 This is a schematic diagram of a storage device according to a preferred embodiment of the present invention.

[0015] Figure 3 This is a top view of a toroidal phase transition unit according to a preferred embodiment of the present invention.

[0016] Figure 4 This is a top view of a phase change unit with a double-layered, staggered arrangement, according to a preferred embodiment of the present invention.

[0017] Figures 5-18 This is a schematic diagram of the manufacturing process steps of a preferred embodiment of the present invention for a memory device.

[0018] Figure 19 This is a schematic diagram comparing the structure of the phase-change memory cell of the present invention with that of a conventional phase-change memory cell. In the figure, (a) is the same as... Figure 1 The corresponding phase-change memory cell of the present invention, (b) is a conventional phase-change memory cell, and (c) is a phase-change memory cell with... Figure 2 The corresponding phase-change memory unit of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0020] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0021] refer to Figure 1 and Figure 3 A storage device according to the present invention includes a phase change memory cell 11 disposed on a substrate 10. The phase change memory cell 11 includes a first electrode 12, a phase change cell 13, and a second electrode 14 sequentially connected in a direction away from the upper surface of the substrate 10. Figure 1 The example shows a structure with two phase-change memory cells 11 on the substrate 10. However, it is understood that the present invention does not limit the number of phase-change memory cells 11. In application, the number of phase-change memory cells 11 can be determined according to design requirements.

[0022] The phase change unit 13 is configured as a first annular body 18 (i.e., the phase change unit 13 is annular in shape). The axial direction of the first annular body 18 is typically perpendicular to the surface of the substrate 10. For ease of understanding, Figure 1 The cross-sectional structure of one annular phase transition unit 13 located on the right is shown.

[0023] The top of the first electrode 12 is in direct contact with the bottom surface of the first annular body 18, and the outer periphery of the top of the first electrode 12 completely surrounds the inner periphery of the bottom surface of the first annular body 18, while the outer periphery of the bottom surface of the first annular body 18 completely surrounds the outer periphery of the top of the first electrode 12. This is done to reduce the contact area between the first electrode 12 and the phase change unit 13.

[0024] by Figure 3 In the example of the phase change unit 13, the first annular body 18 is a rectangular annular body, and the first electrode 12 is a rectangular cylinder (it can be understood that the first annular body 18 can also be a circular annular body or other suitable shapes, and the first electrode 12 can also be a cylindrical shape or other suitable shapes). If the rectangular side length of the top of the first electrode 12 is 60~80nm, and the inner perimeter of the rectangular bottom surface of the first annular body 18 is 50~70nm, then the contact area between the phase change unit 13 and the first electrode 12 can be controlled within the range of 800~1300nm. 2 Left and right, compared to traditional blade electrodes (reference) Figure 19 (b) The contact area range with the phase change unit is consistent. Thus, the cooperative structure of the phase change unit 13 and the first electrode 12 of the present invention achieves the same effect as the traditional blade electrode, and can replace the traditional blade electrode to heat the phase change unit 13, while saving the space occupied by the original blade electrode.

[0025] refer to Figure 19 .like Figure 19As shown in (b), the phase change unit 104 of a conventional phase change memory is generally a solid body. It typically requires a blade electrode 103 with a very small contact area to connect to the phase change unit 104, so that a large amount of heat is generated when current passes through it, thereby changing the resistivity characteristics of the phase change material in the phase change unit 104. Furthermore, the conventional blade electrode 103 needs to be connected to the substrate 101 through a contact hole 102. Therefore, the presence of the blade electrode 103 occupies a large vertical space, increasing the difficulty of device embedding.

[0026] Depend on Figure 19 (a) and Figure 19 (b) By comparison, it can be seen that since the present invention adopts the special matching structure in which the above-mentioned annular phase change unit 13 directly contacts the first electrode 12, the traditional blade electrode 103 can be eliminated. The first electrode 12 is used as both an electrode and a wire. Therefore, under the same area, the present invention can reduce the height of the device in the vertical direction, which is beneficial to reducing the size of the device.

[0027] refer to Figures 2-4 In some embodiments, there are multiple phase change memory cells 11, each phase change memory cell 11 including a first electrode 12, a phase change cell 13 and a second electrode 14 sequentially connected along a direction away from the upper surface of the substrate 10. Furthermore, the first annular body 18 of each phase change memory cell 11 is divided into upper and lower layers along a direction away from the surface of the substrate 10. Figure 2 and Figure 4 In this diagram, A represents the lower layer and B represents the upper layer.

[0028] In this array, the orthographic projections of the first annular bodies 18 of each phase change unit 13 onto the surface of the substrate 10 form a non-overlapping array distributed in rows and columns. The two first annular bodies 18 corresponding to two adjacent orthographic projections in the same row are located in different layers, and the two first annular bodies 18 corresponding to two adjacent orthographic projections in the same column are located in different layers. In any 2×2 orthographic projections, the two first annular bodies 18 corresponding to every two orthographic projections at diagonal positions are located in the same layer, forming a stacked memory device.

[0029] like Figure 4 As shown, it schematically illustrates an array of non-overlapping 4×2 orthographic projections formed by the orthographic projections of four phase change units 13 located in the lower layer A and four phase change units 13 located in the upper layer B onto the surface of the substrate 10. As defined... Figure 2 and Figure 4If the X-axis is the row direction and the Y-axis is the column direction, a 4-row × 2-column orthographic projection array is formed. The two phase-change units 13 corresponding to the two orthographic projections in any row of the array are located in the lower layer A and the upper layer B, respectively. Similarly, the two phase-change units 13 corresponding to any two adjacent orthographic projections in the same column are located in the lower layer A and the upper layer B, respectively. Within any rectangular area formed by 2 × 2 orthographic projections, the two phase-change units 13 corresponding to the two orthographic projections at one diagonal of the rectangle are located in the lower layer A, and the two phase-change units 13 corresponding to the two orthographic projections at the other diagonal are located in the upper layer B. Therefore, from a column perspective, the phase-change units 13 are arranged alternately in the lower layer A and upper layer B, and the positions of the phase-change units 13 in adjacent columns are staggered, forming a phase-change memory unit 11 array structure with two layers of staggered phase-change units 13. This achieves the effect of increasing storage density.

[0030] It should be noted that, Figure 2 The example shows an array of phase change memory cells 11 arranged in a left-right mirror distribution in a storage region, each array consisting of an equal number of multiple phase change memory cells 11 forming a two-layer structure of phase change cells 13. The phase change cells 13 located in the upper and lower layers of each phase change memory cell 11 on each side, when projected onto the surface of the substrate 10, respectively form a structure like... Figure 4 The planar projection array is shown. If the storage area has a large space along the X-axis, the number of columns of each phase-change memory cell 11 on each side can be appropriately increased from 2 columns. Of course, if the storage area is too small, only one phase-change memory cell 11 array can be set up, forming a shape similar to... Figure 4 The number of columns in the planar projection array shown can also be adjusted from 2 columns.

[0031] Depend on Figure 19 (c) and Figure 19 (b) By comparison, it can be seen that since the present invention adopts the special matching structure in which the annular phase change unit 13 is in direct contact with the first electrode 12, the traditional blade electrode 103 can be eliminated. Therefore, under the same area, the present invention can utilize the height space freed up in the vertical direction after eliminating the traditional blade electrode 103 to set up the phase change unit 13 with the above-mentioned upper and lower two-layer structure, thereby achieving the effect of doubling the storage density and expanding the storage capacity.

[0032] This invention provides new technical support for embedding and expanding memory devices in process platforms, enabling phase-change memory devices to be extended and expanded in the process. Simultaneously, this invention allows for further miniaturization and densification of devices, thereby enabling the application of embedded phase-change memories with larger storage capacities on semiconductor technology platforms.

[0033] refer to Figures 1-4In some embodiments, the first electrode 12 includes a contact hole. The contact hole of the first electrode 12 is in direct contact with the first annular body 18 of the phase change unit 13 located in the lower layer A and the first annular body 18 of the phase change unit 13 located in the upper layer B, respectively.

[0034] In some embodiments, the second electrode 14 is configured as a second annular body 17 (i.e., the shape of the second electrode 14 is an annular body).

[0035] In some embodiments, the second annular body 17 has the same shape as the first annular body 18. For example, when the first annular body 18 is as follows... Figure 3 or Figure 4 When the first ring body 18 is a rectangular ring body, the second ring body 17 is also a rectangular ring body. When the first ring body 18 is a ring body of other shapes, such as a circular ring body, the second ring body 17 is also a circular ring body. In this case, the first electrode 12 also corresponds to a rectangular cylinder or a circular cylinder.

[0036] In some embodiments, the second annular body 17 and the first annular body 18 have the same shape and are coaxially arranged in the vertical direction, together forming a rectangular annular body 16, or together forming a circular annular body, etc. When a phase change unit 13 is in the lower layer A, the second electrode 14 on its top surface is also in the lower layer A; when a phase change unit 13 is in the upper layer B, the second electrode 14 on its top surface is also correspondingly in the upper layer B. At this time, the second annular body 17 of the second electrode 14 and Figure 3 and Figure 4 The first annular body 18 of the phase change unit 13 shown is completely overlapped.

[0037] In some embodiments, an electrode lead-out structure 15 is further connected to the top surface of the second annular body 17 of the second electrode 14. That is, each phase-change memory cell 11 has an electrode lead-out structure 15 on the top surface of its second electrode 14, and each electrode lead-out structure 15 is connected to the top surface of the upper layer of the second electrode 14 and the top surface of the lower layer of the second electrode 14, respectively. For example, each electrode lead-out structure 15 is connected to the top surface of the second annular body 17 of each second electrode 14 and is offset from the center of the second annular body 17, such as... Figure 1 , Figure 2 and Figure 4 As shown. In the example Figure 4 In one example shown, the electrode lead-out structures 15 are distributed on the outer side of the top surface of the second annular body 17 in two rows along the Y direction. Preferably, the contact surface where the electrode lead-out structures 15 connect to the second annular body 17 falls between the inner and outer circumferences of the second annular body 17.

[0038] The cross-sectional shape of the electrode lead-out structure 15 can be rectangular, circular, or other conventional contact hole shapes. Figure 4An example of a rectangular cross-sectional shape is shown in the figure.

[0039] The electrode lead-out structure 15 includes a contact hole.

[0040] Electrode lead-out structure 15 connects to the upper metal interconnect layer (not shown). refer to Figure 2 In some embodiments, a gate lead-out structure 21 is also provided on the outside of the phase change memory cell 11 array. Multiple gate lead-out structures 21 can be arranged along the Y direction, each gate lead-out structure 21 corresponding to the first electrode 12 of a phase change memory cell 11, and respectively connected to a gate (not shown) disposed on the substrate 10.

[0041] The selector lead-out structure 21 includes a contact hole. The selector lead-out structure 21 is connected to the metal interconnect layer.

[0042] The space between the two gate tube lead-out structures 21 serves as a storage area, and the storage device is embedded in the storage area between the contact hole layer and the metal interconnect layer to form an embedded storage device.

[0043] refer to Figure 1 and Figure 2 In some embodiments, a dielectric layer 19 is provided on the surface of the substrate 10, and the phase change storage unit 11 is disposed in the dielectric layer 19.

[0044] In some embodiments, an interlayer isolation layer 20 is provided in the dielectric layer 19. The interlayer isolation layer 20 is disconnected in the storage region. A gate lead-out structure 21 is disposed through the interlayer isolation layer 20. The interlayer isolation layer 20 is located above the contact hole layer, and the contact hole portions of the first electrode 12 and the gate lead-out structure 21, respectively, located below the interlayer isolation layer 20, are located in the contact hole layer.

[0045] The substrate 10, dielectric layer 19, contact hole, phase change unit 13, second electrode 14, and interlayer isolation layer 20 can be made of conventional materials, and the present invention does not limit them.

[0046] The following detailed description, in conjunction with specific embodiments and accompanying drawings, provides a further detailed explanation of a method for manufacturing a storage device according to the present invention.

[0047] A method for manufacturing a storage device according to the present invention includes: A phase-change memory cell 11 is formed on a substrate 10. The phase-change memory cell 11 includes a first electrode 12, a phase-change unit 13, and a second electrode 14 sequentially connected along a direction away from the surface of the substrate 10. The phase-change unit 13 is a first annular body 18. The top end of the first electrode 12 is in direct contact with the bottom surface of the first annular body 18, and the outer periphery of the top end of the first electrode 12 completely surrounds the inner periphery of the bottom surface of the first annular body 18. The outer periphery of the bottom surface of the first annular body 18 completely surrounds the outer periphery of the top end of the first electrode 12, thereby reducing the contact area between the first electrode 12 and the phase-change unit 13. The above-described method for manufacturing a memory device according to the present invention can be used to manufacture, for example... Figure 1 The image shows a storage device.

[0048] In some embodiments, forming a phase-change memory cell 11 includes forming a plurality of phase-change memory cells 11, such that the first annular body 18 of each phase-change memory cell 11 is divided into upper and lower layers in a direction away from the surface of the substrate 10; wherein the orthographic projections of each first annular body 18 on the surface of the substrate 10 form a non-overlapping array distributed in rows and columns, the two first annular bodies 18 corresponding to two adjacent orthographic projections in the same row are located in different layers, the two first annular bodies 18 corresponding to two adjacent orthographic projections in the same column are located in different layers, and in any 2×2 orthographic projections, the two first annular bodies 18 corresponding to every two orthographic projections at diagonal positions are located in the same layer, forming a stacked memory device. The above-described method for manufacturing a memory device of the present invention can be used to manufacture, for example... Figure 2 The image shows a storage device.

[0049] refer to Figures 5-18 To manufacture, for example Figure 2 Taking the storage device shown as an example, the storage device forming a stacked structure specifically includes the following steps: Step S1: Form a first dielectric layer on the surface of substrate 10.

[0050] This invention can embed a storage device between the contact hole layer and the bottom metal interconnect layer (M1) based on the design rules of the contact hole layer and the bottom metal interconnect layer under standard process.

[0051] First, the front-end process and contact hole process on substrate 10 need to be completed.

[0052] like Figure 5 As shown, a first dielectric layer 191 with a flat surface is formed on the surface of the substrate 10 using a deposition process.

[0053] The substrate 10 may be, for example, a silicon substrate. The material of the first dielectric layer 191 may be, for example, silicon dioxide (the same applies to the dielectric layer materials below).

[0054] Step S2: A plurality of first contact holes connected to the substrate 10 are formed on the surface of the first dielectric layer 191.

[0055] like Figure 5 As shown in (a), a contact hole process, including photolithography, etching, and metal deposition, is used to form a plurality of first contact holes 121 on the surface of the first dielectric layer 191, with their bottoms connected to the substrate 10. Wherein, in Figure 5 (a) shows that a row of first contact holes 121-3 are formed on the outermost two sides for manufacturing the selector lead-out structure 21. The space between the two outermost rows of first contact holes 121-3 serves as a storage area for the embedded manufacturing of storage devices. Between the two outermost rows of first contact holes 121-3, two rows of first contact holes 121 are formed symmetrically on the left and right sides for placing phase change units 13. The two rows of first contact holes 121 on each side form an array distributed in rows and columns, and each belongs to a phase change memory unit 11 array to be formed, thus forming two phase change memory unit 11 arrays on the left and right sides. Figure 5 (a) shows a side view of the formed first contact hole 121. Figure 5 (b) shows Figure 5 (a) shows a top view of the layer containing the first contact hole 121 in the left-hand phase change memory cell array 11, and exemplarily illustrates the formation of 4×2 first contact holes 121 for placing phase change cells 13. Half of the four first contact holes 121-1 are used to place the phase change cells 13 located in the lower layer A, and the remaining half (four first contact holes 121-2) are used to place the phase change cells 13 located in the upper layer B. X represents the row direction, and Y represents the column direction. Figures 6-18 Middle row direction and Figure 5 Same, X and Y direction identifiers omitted) The material of the first contact hole 121 can be, for example, tungsten (the same applies to the contact hole materials below). The critical dimension of the first contact hole 121 can be 60~80nm.

[0056] Step S3: A second dielectric layer is formed on the surface of the first dielectric layer 191 to cover each of the first contact holes 121.

[0057] like Figure 5 As shown in (a), an interlayer isolation layer 20 and a second dielectric layer 192 are sequentially formed on the surface of the first dielectric layer 191 using a deposition process.

[0058] The interlayer isolation layer 20 can be made of standard contact hole interlayer isolation material. The interlayer isolation layer 20 material can be SiN or NDC. In this embodiment, the thickness of the interlayer isolation layer 20 is, for example, 300 angstroms.

[0059] The second dielectric layer 192 serves as a hard mask layer, used to prevent the material of the underlying interlayer isolation layer 20 from being affected during subsequent etching of the phase change material.

[0060] Step S4: A trench is formed on the surface of the second dielectric layer 192, exposing the top surface of each first contact hole 121 located on the bottom surface of the trench.

[0061] like Figure 6 As shown, a trench 22 is formed on the surface of the second dielectric layer 192 using photolithography and etching processes. The width of the trench 22 in the X-direction must be less than the distance between the two outermost rows of first contact holes 121-3. The etching process requires etching through the interlayer isolation layer 20 (etching away approximately 50-100 angstroms of the underlying first dielectric layer 191), so that the bottom of the trench 22 lies on each of the first contact holes 121-1 and 121-2 between the two outermost rows of first contact holes 121-3, and the top surfaces of the first contact holes 121-1 and 121-2 between the two outermost rows of first contact holes 121-3 are exposed on the bottom surface of the trench 22.

[0062] The width of the trench 22 in the X-direction (a critical dimension) defines the width range of the memory region. In one example, the width range of the trench 22 formed by photolithography can be the sum of the widths of four phase change cells 13 and their spacing, used to form two mirror-symmetric arrays of phase change memory cells 11 on the left and right sides. In this embodiment, a trench 22 with a relatively easy-to-implement width of 970 nm is described. Each phase change cell 13 occupies a width of 180 nm, and the spacing between the phase change cells 13 is 50 nm. Of course, if the allowable trench 22 space is too small, only one array of phase change memory cells 11 can be arranged.

[0063] Step S5: A lower phase change material layer and an electrode material layer are sequentially formed on the surface of the second dielectric layer 192, and the trench 22 is filled.

[0064] like Figure 7 As shown, a deposition process is used to sequentially deposit a lower phase change material layer 131 and a lower electrode material layer 141 on the surface of the second dielectric layer 192, and then fill the trench 22.

[0065] The phase change material layer material can be, for example, GST (Ge2Sb2Te5). The electrode material layer material can be, for example, TiN or TaN (the same below). In this embodiment, the thickness of the lower phase change material layer 131 is 400~2000 angstroms, preferably 1000 angstroms; the thickness of the lower electrode material layer 141 is 300~600 angstroms, preferably 400 angstroms.

[0066] Step S6: Pattern the lower phase change material layer 131 and the lower electrode material layer 141, and form the lower phase change unit 13 and the second electrode 14 on the top surface of part of the first contact hole 121-1 on the bottom surface of the trench 22, exposing the top surface of the remaining part of the first contact hole 121-2.

[0067] like Figure 8 As shown in (a), using photolithography and etching processes, phase change units 13 and second electrodes 14 located in the lower layer are formed on the top surface of half (4) of the first contact holes 121-1 on the bottom surface of trench 22, exposing the top surface of the remaining half (4) of the first contact holes 121-2. The top view of the four phase change units 13 and second electrodes 14 located in the lower layer A is shown below. Figure 8 As shown in (b), it is preferably aligned with the center of the top surface of the first contact hole 121-1 below. It can be seen that after etching the lower phase change material layer 131 and the lower electrode material layer 141, four annular bodies 16 (a combination of the second annular body 17 and the first annular body 18), such as rectangular ones, are formed and located on the top surface of the four first contact holes 121-1 shown in the figure. These serve as four lower phase change units 13 and second electrodes 14, and expose the top surfaces of the other four first contact holes 121-2. The four first contact holes 121-1 that connect to the four lower phase change units 13 and second electrodes 14 serve as the first electrodes 12 corresponding to the four phase change memory units 11 after manufacturing, and also provide the heating function of the original blade electrodes.

[0068] The inner perimeter of the rectangular ring body of the lower phase change unit 13 and the second electrode 14 can be 50~70nm.

[0069] The shapes of the lower phase change unit 13 and the second electrode 14 can be optimized based on the OPC correction and the actual size. This invention is described using only the layout of the square phase change unit 13 and the second electrode 14.

[0070] Step S7: A third dielectric layer is formed on the surface of the second dielectric layer 192, covering the second electrode 14 and phase change unit 13 located in the lower layer, as well as the remaining exposed portion of the first contact hole 121, and forming a flat surface of the third dielectric layer.

[0071] like Figure 9As shown in (a), a deposition process is used to form a third dielectric layer 193 on the surface of the remaining second dielectric layer 192 after etching. This covers the four second electrodes 14 and phase change units 13 located in the lower layer, as well as the four first contact holes 121-2 exposed at the top. It also covers the outermost two rows of first contact holes 121-3 and the exposed surface of the first dielectric layer 191. Then, planarization (e.g., chemical mechanical polishing, CMP) is used to eliminate surface step differences, forming a flat surface of the third dielectric layer 193, leaving sufficient thickness to accommodate the subsequent fabrication of the second contact holes and the spacing between the upper and lower phase change units 13. The morphology of the four lower second electrodes 14 and phase change units 13 covered by the third dielectric layer 193, and the four exposed first contact holes 121-2 at the top, is as follows: Figure 9 As shown in (b), the gap between the inner periphery of the annular body of the four lower second electrodes 14 and the phase change unit 13 is filled by the third dielectric layer 193, which closes the exposed top surface of the first contact hole 121-1 connected below.

[0072] The third dielectric layer 193, serving as a dielectric buffer layer, requires a relatively thick layer, for example, 2000-3000 angstroms, to prepare for CMP and the fabrication of the upper phase change unit 13. After CMP, the remaining thickness of the third dielectric layer 193 is approximately 1800 angstroms.

[0073] Step S8: Form a second contact hole on the surface of the third dielectric layer 193, the bottom of which is connected to the top surface of the remaining portion of the first contact hole 121-2.

[0074] like Figure 10 (a) As shown in ( Figure 10 (a) The display can be along Figure 10 (b) A cross-sectional view from the top row (first or third row direction), using photolithography and etching processes, forms first through-holes 23 on the surface of the third dielectric layer 193, whose bottoms correspond to the top surfaces of the four unused first contact holes 121-2. The critical dimensions of the first through-holes 23 can be consistent with the critical dimensions of the first contact holes 121. The shape of the four first through-holes 23 exposed at the top opening is as follows: Figure 10 As shown in (b).

[0075] like Figure 11As shown in (a), the first via 23 is then filled with tungsten using a metal deposition process, followed by CMP planarization to form second contact holes 24 that correspond to the top surfaces of the four remaining first contact holes 121-2. These connected first contact holes 121 and second contact holes 24 together form the first electrode 12, which connects to the phase change unit 13 to be formed on the upper layer. After CMP planarization, the residual thickness of the third dielectric layer 193 is approximately 1500 angstroms, and the top surfaces of the second contact holes 24 are exposed from the surface of the third dielectric layer 193. The morphology of the four exposed second contact holes 24 is as follows: Figure 11 As shown in (b).

[0076] Step S9: An upper phase change material layer and an upper electrode material layer are sequentially formed on the surface of the third dielectric layer 193 to cover the second contact hole 24.

[0077] like Figure 12 As shown, a deposition process is used to sequentially deposit an upper phase change material layer 132 and an upper electrode material layer 142 on the surface of the third dielectric layer 193. The deposition thickness can be the same as that of the lower phase change material layer 131 and the lower electrode material layer 141, and the second contact hole 24 is covered.

[0078] Step S10: Pattern the upper phase change material layer 132 and the upper electrode material layer 142 to form the upper phase change unit 13 and the second electrode 14 on the top surface of the second contact hole 24.

[0079] like Figure 13 (a) As shown in ( Figure 13 (a) The display can be along Figure 13 (b) The cross-sectional structure in the third row from the top. Also, to highlight the characteristics of the upper and lower layers, the section located in... Figure 13 (b) A rectangular annular body located on the upper layer is also shown in the second row from the top. Using photolithography and etching processes, phase change units 13 and second electrodes 14 located on the upper layer are formed on the top surface of the four second contact holes 24. At this point, the upper and lower layers of phase change units 13 and second electrodes 14 are manufactured, and the morphology of the eight phase change units 13 and second electrodes 14 arranged in the lower layer A and upper layer B is as follows. Figure 13 As shown in (b), eight independent phase change storage units 11 can be formed.

[0080] It can be seen that the first electrode 12 of each phase change memory cell 11 has two different heights on the substrate 10. The first electrode 12 connected to the lower phase change cell 13 is formed only by the first contact hole 121; while the first electrode 12 connected to the upper phase change cell 13 is formed by the lower first contact hole 121 and the upper second contact hole 24.

[0081] Further fabrication can be carried out on the electrode lead-out structure 15 and the selection tube lead-out structure 21. This includes the following steps: Step S11: A fourth dielectric layer is formed on the surface of the third dielectric layer 193, covering the second electrode 14 and the phase change unit 13 located on the upper layer, and forming a flat surface of the fourth dielectric layer.

[0082] like Figure 14 As shown, a fourth dielectric layer 194 is formed on the surface of the third dielectric layer 193 using a deposition process, covering the second electrode 14 and the phase change unit 13 located on the upper layer (including covering the first contact holes 121-3 located on the outermost sides), and the step difference existing on the surface is eliminated by CMP to form a flat surface of the fourth dielectric layer 194.

[0083] The fourth dielectric layer 194 serves as a buffer layer, and its deposition thickness can be 1500~2500 angstroms. Sufficient thickness of the fourth dielectric layer 194 needs to be left after CMP to allow space for the fabrication of the conductive lead-out structure of the memory device. In this embodiment, the thickness of the fourth dielectric layer 194 left after CMP is approximately 1500 angstroms. Specifically, the fourth dielectric layer 194 fills the gaps in the annular body of the four upper second electrodes 14 and the phase change unit 13, sealing the exposed top surface of the lower connected second contact hole 24.

[0084] Step S12: A third contact hole is formed on the surface of the fourth dielectric layer 194, with its bottom surface corresponding to the top surface of the second electrode 14 located in the lower layer and the top surface of the second electrode 14 located in the upper layer.

[0085] like Figure 15 As shown, photolithography and etching processes are used to form a second through-hole 25 on the surface of the fourth dielectric layer 194, with its bottom corresponding to the top surface of the first contact holes 121-3 on both outermost sides. The critical dimensions of the second through-hole 25 can be consistent with the critical dimensions of the first contact holes 121. During etching, the interlayer isolation layer 20 needs to be etched through to expose the top of the lower first contact holes 121-3.

[0086] like Figure 16 As shown in (a), next, photolithography and etching processes are used to form third vias 26 on the surface of the fourth dielectric layer 194, with their bottoms corresponding to the top surfaces of the four annular bodies (second electrodes 14) located in the lower layer. The morphology of the four third vias 26 with their top openings exposed is as follows. Figure 16 As shown in (b).

[0087] like Figure 17As shown in (a), next, photolithography and etching processes are used to form fourth through-holes 27 on the surface of the fourth dielectric layer 194, with their bottoms corresponding to the top surfaces of the four annular bodies (second electrodes 14) located in the upper layer. The morphology of the four fourth through-holes 27 and the four third through-holes 26 with their top openings exposed is as follows. Figure 17 As shown in (b).

[0088] like Figure 18 As shown in (a), finally, a metal deposition process is used to fill the second through-hole 25, the third through-hole 26, and the fourth through-hole 27 with tungsten, and CMP planarization is performed to form eight third contact holes 28 that correspond to the top surfaces of the second electrodes 14 located on the upper and lower layers of the eight phase change memory cells 11, serving as electrode lead-out structures 15. At the same time, third contact holes 28 that correspond to the top surfaces of the first contact holes 121-3 on the outermost two sides are also formed, and the connected first contact holes 121 and third contact holes 28 together form the selector tube lead-out structure 21.

[0089] The first dielectric layer 191, the second dielectric layer 192, the third dielectric layer 193, and the fourth dielectric layer 194 described above together form dielectric layer 19. This completes the process of... Figure 2 The manufacturing process of the storage device shown.

[0090] To adapt to the continuous iteration of semiconductor processes and the constant refinement of process platforms, this invention improves the traditional embedded phase-change memory structure by omitting the space and process steps of traditional blade electrodes, thereby reducing the number of manufacturing process steps for a single memory and reducing the process difficulty. Furthermore, by arranging an interleaved stacked memory device structure, the storage density is increased and the storage capacity is expanded.

[0091] In summary, this invention designs the phase change unit 13 as a ring (first ring 18), so that the outer periphery of the top of the first electrode 12, which directly contacts the annular bottom surface of the phase change unit 13, is located between the inner and outer peripheries of the annular bottom surface. This reduces the contact area between the first electrode 12 and the phase change unit 13, achieving an effect similar to a traditional blade electrode, thus replacing the traditional blade electrode. This saves the space occupied by the original blade electrode and simplifies the manufacturing process. Furthermore, using the space saved from the original blade electrode, an additional layer of phase change units 13 can be added to the entire memory device. By staggering the upper and lower layers of phase change units 13, a non-overlapping array is formed on the plane, achieving a significant increase in storage density and expanding storage capacity. This invention provides a low-cost and simple-to-process memory expansion solution, enabling the application of embedded phase change memory in process platforms.

[0092] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A memory device, comprising: include: A phase change memory cell disposed on a substrate includes a first electrode, a phase change unit, and a second electrode connected sequentially along a direction away from the substrate surface. The phase change unit is a first annular body. The top end of the first electrode is in direct contact with the bottom surface of the first annular body, and the outer periphery of the top end of the first electrode completely surrounds the inner periphery of the bottom surface of the first annular body. The outer periphery of the bottom surface of the first annular body completely surrounds the outer periphery of the top end of the first electrode, so as to reduce the contact area between the first electrode and the phase change unit.

2. The memory device of claim 1, wherein, The phase change memory unit is a plurality of units, and the first annular body of each phase change memory unit is divided into upper and lower layers in a direction away from the surface of the substrate. In this configuration, the orthographic projections of each of the first annular bodies on the substrate surface form a non-overlapping array distributed in rows and columns. The two first annular bodies corresponding to two adjacent orthographic projections in the same row are located in different layers, and the two first annular bodies corresponding to two adjacent orthographic projections in the same column are located in different layers. In any 2×2 orthographic projections, the two first annular bodies corresponding to every two orthographic projections at diagonal positions are located in the same layer, forming a stacked storage device.

3. The memory device of claim 1, wherein, The second electrode is a second annular body, which is coaxially arranged with the first annular body and together forms an annular body.

4. The memory device of claim 3, wherein, It also includes an electrode lead-out structure connected to the top surface of the second annular body away from the substrate.

5. The memory device of claim 4, wherein, The first electrode and the electrode lead-out structure include contact holes; and / or, a dielectric layer is provided on the surface of the substrate, and the phase change storage unit is disposed in the dielectric layer.

6. A method of manufacturing a memory device, characterized by, include: A phase change memory cell is formed on a substrate. The phase change memory cell includes a first electrode, a phase change unit, and a second electrode connected sequentially in a direction away from the substrate surface. The phase change unit is a first annular body. The top end of the first electrode is in direct contact with the bottom surface of the first annular body, and the outer periphery of the top end of the first electrode completely surrounds the inner periphery of the bottom surface of the first annular body. The outer periphery of the bottom surface of the first annular body completely surrounds the outer periphery of the top end of the first electrode, so as to reduce the contact area between the first electrode and the phase change unit.

7. The method of manufacturing a memory device according to claim 6, wherein When forming a phase change memory cell, the process includes forming a plurality of phase change memory cells, such that the first annular body of each phase change memory cell is divided into upper and lower layers in a direction away from the surface of the substrate. In this configuration, the orthographic projections of each of the first annular bodies on the substrate surface form a non-overlapping array distributed in rows and columns. The two first annular bodies corresponding to two adjacent orthographic projections in the same row are located in different layers, and the two first annular bodies corresponding to two adjacent orthographic projections in the same column are located in different layers. In any 2×2 orthographic projections, the two first annular bodies corresponding to every two orthographic projections at diagonal positions are located in the same layer, forming a stacked storage device.

8. The method of manufacturing a memory device according to claim 7, wherein, Storage devices that form a stacked structure specifically include: A first dielectric layer is formed on the surface of the substrate; A plurality of first contact holes connected to the substrate are formed on the surface of the first dielectric layer, such that each of the first contact holes forms an array distributed in rows and columns on the surface of the substrate; A second dielectric layer is formed on the surface of the first dielectric layer to cover each of the first contact holes; A trench is formed on the surface of the second dielectric layer, exposing the top surface of each of the first contact holes located on the bottom surface of the trench; A lower phase change material layer and an electrode material layer are sequentially formed on the surface of the second dielectric layer, and the trench is filled. The lower phase change material layer and electrode material layer are patterned, and a phase change unit and a second electrode located in the lower layer are formed on the top surface of a portion of the first contact hole at the bottom of the trench, exposing the top surface of the remaining portion of the first contact hole. A third dielectric layer is formed on the surface of the second dielectric layer, covering the second electrode and phase change unit located in the lower layer, as well as the remaining exposed portion of the first contact hole, and forming a flat surface of the third dielectric layer. A second contact hole is formed on the surface of the third dielectric layer, the bottom of which is in contact with the top surface of the remaining portion of the first contact hole. An upper phase change material layer and an electrode material layer are sequentially formed on the surface of the third dielectric layer to cover the second contact hole; The upper phase change material layer and the electrode material layer are patterned, and a phase change unit and a second electrode are formed on the top surface of the second contact hole. The first contact hole connected to the phase change unit located in the lower layer forms the first electrode, and the second contact hole connected to the phase change unit located in the upper layer and the first contact hole together form the first electrode.

9. The method of manufacturing a memory device according to claim 8, wherein, When forming the phase change unit and the second electrode, the phase change unit is formed into a first ring body, the second electrode is formed into a second ring body, and the second ring body and the first ring body are coaxially arranged to form a ring body together.

10. The method of manufacturing a memory device according to Claim 9, wherein, Also includes: A fourth dielectric layer is formed on the surface of the third dielectric layer, covering the second electrode and phase change unit located on the upper layer, and forming a flat surface of the fourth dielectric layer; A third contact hole is formed on the surface of the fourth dielectric layer, with its bottom surface corresponding to the top surface of the second electrode located in the lower layer and the top surface of the second electrode located in the upper layer. The third contact hole serves as an electrode lead-out structure; the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer together form a dielectric layer.

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