Method of manufacturing a semiconductor device

Abstract

This invention provides a method for manufacturing a semiconductor device. Before the active region manufacturing process, trench etching is performed on the substrate region to be fabricated as a high-voltage transistor to form at least a gate oxide trench and a first depth adjustment trench. This allows the depth of the first depth adjustment trench to be used to increase the bottom depth of the shallow trench isolation structure in the high-voltage transistor, thereby increasing the charge path of the high-voltage transistor, increasing its breakdown voltage, and reducing the step height between the high-voltage transistor and other components compared to existing technologies. This reduces the load effect and defects in subsequent processes, improving the performance of the high-voltage transistor. Furthermore, after forming the side trench and before forming the thick gate oxide layer, the surface of the active region's exposed corners is oxidized to form a corner oxide layer. This allows for more favorable growth of the oxide layers on each crystal plane of the active region at the gate oxide trench during the growth of the thick gate oxide layer, solving the problem of the thick gate oxide layer being thin at the active region's corners.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] High-voltage transistors (HVMOS) are devices capable of withstanding higher voltages while ensuring that the gate is not broken down under high-voltage operation. On one hand, the source / drain regions of an HVMOS are isolated from the device channel by a shallow trench isolation (STI) structure to improve the breakdown voltage. This STI structure is typically formed during the active region formation process (AA loop), along with the STI structures of other components (such as low-voltage LVMOS, medium-voltage MVMOS, or core components). The trench depth of the STI structure is limited by the process technology and its stability, making it difficult to deepen further using the AA loop. On the other hand, the gate oxide process in HVMOS involves directly growing the gate oxide layer (HV GOX) on the silicon wafer surface. However, after the HV GOX is grown, a step height (SH) inevitably exists between the HVMOS and other components because the HV GOX... The gate oxide layer (GOX) is much thicker than that formed on other device regions such as LVMOS and MVMOS (e.g., two orders of magnitude thicker). This step height will increase the process loading in subsequent processes, which may affect the performance of HVMOS. For example, this step height may cause insufficient overlap between the drift region and the gate in HVMOS, thus affecting the performance of HV devices.

[0003] Therefore, how to provide a method for manufacturing semiconductor devices that improves the performance of high-voltage transistors without degrading the performance of other components is one of the important technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor device that can improve the performance of a high-voltage transistor without degrading the performance of other components.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0006] A substrate is provided, and trench etching is performed on the substrate region to be fabricated as a high voltage transistor to form at least a gate oxide trench and a first depth adjustment trench located outside the gate oxide trench.

[0007] A hard mask layer is formed covering the substrate having the first depth adjustment trench and the gate oxide trench;

[0008] An active region manufacturing process is performed on the hard mask layer and the substrate it covers to form corresponding shallow trenches in the substrate, wherein a portion of the shallow trenches overlaps with the first depth adjustment trench and communicates with the first depth adjustment trench and the gate oxide trench, and the active region manufacturing process deepens the bottom depth of the portion of the shallow trenches through the first depth adjustment trench.

[0009] Dielectric material is filled into the gate oxide trench, each of the shallow trenches and the first depth adjustment trench to form a shallow trench isolation structure, which buries the hard mask layer in the gate oxide trench.

[0010] The shallow trench isolation structure in the gate oxide trench is etched open, and the shallow trench isolation structure on the sidewall of the gate oxide trench is further etched to form a side trench that exposes the apex corner of the active region in the gate oxide trench. The hard mask layer in the gate oxide trench protects the active region in the gate oxide trench during the formation of the side trench.

[0011] Under the cover of the hard mask layer in the gate oxide trench, the surface of the active region apex exposed by the side trench is oxidized to form an apex oxide layer;

[0012] Remove the hard mask layer in the gate oxide trench and form a thick gate oxide layer on top of the active region of the gate oxide trench and in the side trench.

[0013] Optionally, the step of forming the gate oxide groove and the first depth adjustment groove includes:

[0014] A first pad oxide layer, a first nitride layer, and a first photoresist layer are sequentially formed on the substrate;

[0015] The first photoresist layer is photolithographically lithographically lithographically formed using a first photomask to at least define the formation areas of the gate oxide trench and the first depth adjustment trench;

[0016] Using the first photoresist layer after photolithography as a mask, the first nitride layer, the first pad oxide layer and the substrate are etched sequentially to form the gate oxide trench and the first depth adjustment trench in the substrate;

[0017] Remove the first photoresist layer, the first nitride layer, and the first pad oxide layer.

[0018] Optionally, performing an active region fabrication process on the hard mask layer and the substrate it covers includes the following steps:

[0019] A second photoresist layer is formed on the hard mask layer;

[0020] The second photoresist layer is photolithographically etched using a second photomask to define the formation area of ​​each of the shallow trenches;

[0021] Using the second photoresist layer after photolithography as a mask, the hard mask layer and the substrate are etched to form the corresponding shallow trench;

[0022] Remove the second photoresist layer.

[0023] Optionally, the gate oxide trench is spaced apart from or connected to the first depth adjustment trenches on both sides; and / or, the hard mask layer includes a second pad oxide layer and a second nitride layer sequentially stacked on the substrate.

[0024] Optionally, while performing trench etching on the substrate area to be fabricated as a high-voltage transistor to form the gate oxide trench and the first depth adjustment trench, at least one second depth adjustment trench is also formed at the boundary of the active region of the high-voltage transistor. After performing the active region fabrication process, the second depth adjustment trench overlaps and communicates with the corresponding shallow trench to deepen the bottom depth of the shallow trench and separate the active region of the high-voltage transistor from the active regions of other components. The sidewall of the second depth adjustment trench is aligned with or forms a step between the sidewall of the shallow trench it communicates with.

[0025] Optionally, the method for manufacturing the semiconductor device further includes at least one of the following (1) to (5):

[0026] (1) After the first depth adjustment groove is formed and before the shallow trench is formed, or after the shallow trench is formed and before the dielectric material is filled, at least the top sidewall of the active region in the gate oxide trench is ion implanted to form a first drift region.

[0027] (2) After the shallow trench isolation structure is formed and before the side trench is formed, the active region of the high voltage transistor is ion implanted to form a second drift region.

[0028] (3) Before filling the dielectric material, or after etching open the shallow trench isolation structure in the gate oxide trench to expose the top surface of the hard mask layer in the gate oxide trench, or after forming the side trench, the sidewalls of the hard mask layer in the gate oxide trench are also pulled back and etched to expose and round the top corners of the active region.

[0029] (4) After the formation of the side trench and before the formation of the apex oxide layer, ions for increasing the oxidation rate are first used to implant ions into the apex of the active region;

[0030] (5) After forming the thick gate oxide layer, a thin gate oxide layer is also formed on the active region of the other elements, and a gate is formed together on the thick gate oxide layer and the thin gate oxide layer.

[0031] Optionally, a lightly doped source-drain ion implantation process is used to implant ions into the top sidewall of the active region of the gate oxide trench to form the first drift region; and / or, the ions used to improve the oxidation rate include at least one of oxygen ions, amorphous ions, and halide ions, wherein the amorphous ions include at least one of silicon ions, germanium ions, and argon ions.

[0032] Optionally, the step of forming the first drift region includes:

[0033] A third photoresist layer is formed on the substrate;

[0034] Photolithography is performed on the third photoresist layer to open the third photoresist layer on the gate oxide trench and mask other areas;

[0035] Using the third photoresist layer after photolithography as a mask, and employing a lightly doped source / drain ion implantation process, the top sidewall of the active region of the gate oxide trench is lightly doped with ions to form the first drift region.

[0036] Optionally, after the shallow trenches are formed and before the third photoresist layer is formed on the substrate, a line oxide layer is first formed on the inner surfaces of the gate oxide trench, each of the shallow trenches, and the first depth adjustment trench.

[0037] Optionally, the method for manufacturing the semiconductor device is characterized by further comprising at least one of the following (1) to (3):

[0038] (1) The sidewall of the first depth adjustment groove is aligned with or forms a step with the sidewall of the shallow groove it communicates with;

[0039] (2) Photolithography and trench etching are performed on the substrate area to be fabricated for high voltage transistors using the zero-layer photomask, so as to form the first depth adjustment trench and the gate oxide trench at the same time as forming the zero-layer alignment mark in the substrate.

[0040] (3) After the dielectric material is filled into the gate oxide trench, each of the shallow trenches and the first depth adjustment trench, the top surface of the dielectric material is planarized until the top surface of the hard mask layer on the substrate region surrounding the gate oxide trench is exposed or until the hard mask layer on the substrate region surrounding the gate oxide trench is removed.

[0041] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0042] 1. Before the active region manufacturing process, trench etching is performed on the substrate area to be fabricated as a high-voltage transistor to form at least a gate oxide trench and a first depth adjustment trench on its outer side. After subsequent active region manufacturing processes, the depth of the first depth adjustment trench can be used to increase the bottom depth (STI trench) of the shallow trench isolation structure used to isolate the source / drain region and the channel region of the high-voltage transistor. This increases the charge path of the high-voltage transistor, increases its breakdown voltage, and reduces the step height between the high-voltage transistor and other components compared to existing technologies. This reduces the load effect and defects in subsequent processes and improves the performance of the high-voltage transistor.

[0043] 2. After the formation of the side trench and before the formation of the thick gate oxide layer, the surface of the active region apex exposed by the side trench is oxidized under the cover of the hard mask layer in the gate oxide trench to form a apex oxide layer. This is beneficial for rounding the apex of the active region at the gate oxide trench, and thus makes the growth of the oxide layer on each crystal plane of the active region at the gate oxide trench more favorable when the thick gate oxide layer is subsequently grown. This solves the problem of the thick gate oxide layer being thin at the apex of the active region, thereby reducing the hot carrier (HCI) effect and gate-induced drain leakage (GIDL), and further improving the voltage withstand capability of the high voltage transistor in the semiconductor device of the present invention.

[0044] 3. Under the same voltage withstand capability, the high voltage transistor of the present invention can have a shorter active region length compared with the existing high voltage transistor, which is beneficial to reduce the area of ​​the high voltage transistor, thereby reducing the chip area and improving the integration density.

[0045] 4. Furthermore, before or after the formation of the shallow trench and before filling the shallow trench, ion implantation is performed on the top sidewall of the active region of the gate oxide trench of the high voltage transistor to form a first drift region. This can effectively implant ions into the corners of the regions that should be implanted in the existing LDD (lightly doped source-drain implantation) process. This helps to eliminate the side effect caused by the step height SH of the high voltage transistor and avoids the problem of incomplete implantation caused by the rounded exposure of photoresist corners in the existing LDD (lightly doped drain implantation) process. Attached Figure Description

[0046] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0047] Figure 1 This is a schematic diagram of a semiconductor device manufacturing method according to a specific embodiment of the present invention.

[0048] Figures 2A to 2B This is a schematic cross-sectional view of an example device structure in a specific embodiment of the semiconductor device manufacturing method of the present invention.

[0049] Figures 3 to 10 This is a cross-sectional schematic diagram of other example device structures in the manufacturing method of a semiconductor device according to a specific embodiment of the present invention.

[0050] Figure 11 This is a schematic diagram of the photoresist edge rounding exposure in the existing LDD (lightly doped drain implantation) process. Detailed Implementation

[0051] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0052] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0053] Please refer to Figure 1 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps:

[0054] S1, providing a substrate, and performing trench etching on the substrate region to be fabricated as a high-voltage transistor to form at least a gate oxide trench and a first depth adjustment trench located outside the gate oxide trench;

[0055] S2, forming a hard mask layer covering the substrate having the first depth adjustment trench and the gate oxide trench;

[0056] S3, perform an active region manufacturing process on the hard mask layer and the substrate it covers to form corresponding shallow trenches in the substrate, wherein a portion of the shallow trenches overlaps with the first depth adjustment trench and communicates with the first depth adjustment trench and the gate oxide trench, and the active region manufacturing process deepens the bottom depth of the portion of the shallow trenches through the first depth adjustment trench.

[0057] S4, fill the gate oxide trench, each of the shallow trenches and the first depth adjustment trench with dielectric material to form a shallow trench isolation structure, the shallow trench isolation structure burying the hard mask layer in the gate oxide trench;

[0058] S5, etch open the shallow trench isolation structure in the gate oxide trench, and further etch the shallow trench isolation structure on the sidewall of the gate oxide trench to form a side trench that exposes the apex corner of the active region in the gate oxide trench. The hard mask layer in the gate oxide trench protects the active region in the gate oxide trench during the formation of the side trench.

[0059] S6, under the cover of the hard mask layer in the gate oxide trench, the surface of the active region apex exposed by the side trench is oxidized to form an apex oxide layer;

[0060] S7, remove the hard mask layer in the gate oxide trench and form a thick gate oxide layer on the top of the active region of the gate oxide trench and in the side trench.

[0061] Please refer to Figure 2A In step S1, firstly, the provided substrate 100 can be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC), or silicon-on-insulator (SOI). The substrate 100 can be a bare silicon wafer or a wafer that has undergone appropriate processing. Next, any suitable process can be used to form the required gate oxide trench and the first depth adjustment trench in region HV of the substrate 100 where the high-voltage transistor is to be fabricated. In this example, the gate oxide trench and the first depth adjustment trenches on both sides are connected as a single unit, thereby forming trench 103.

[0062] As an example, please continue to refer to Figure 2A The steps for forming trench 103 include:

[0063] S1.1, a first pad oxide layer 101, a first nitride layer 102 and a first photoresist layer 200 are sequentially formed on the substrate 100. The first pad oxide layer 101 can be formed by any suitable process such as thermal oxidation, the first nitride layer 102 can be formed by any suitable process such as chemical vapor deposition, and the first photoresist layer 200 can be formed by spin coating.

[0064] S1.2, a first photomask (not shown) is used to perform photolithography on the first photoresist layer 200 to define the formation area of ​​the trench 103 in the substrate region HV where the high voltage transistor is to be fabricated, that is, to define the formation area of ​​the gate oxide trench and the first depth adjustment trench on both sides thereof.

[0065] S1.3 Using the first photoresist layer 200 after photolithography as a mask, any suitable etching process, such as dry etching, can be used to sequentially etch the first nitride layer 102, the first pad oxide layer 101, and the substrate 100 to form a trench 103 in the substrate 100. The trench 103 is located between the source and drain regions of the high-voltage transistor, covering the gate oxide trench and the area of ​​the first depth adjustment trench on both sides.

[0066] S1.4, the first photoresist layer 200 is removed by any suitable photoresist removal process such as dry photoresist removal or wet photoresist removal, and the first nitride layer 102 and the first pad oxide layer 101 are removed by any suitable process such as wet etching.

[0067] It should be understood that the depth h of trench 103 needs to meet not only the thickness requirements of the gate oxide layer of the high-voltage transistor, but also the depth requirements of the shallow trench isolation (STI) structure surrounding the gate oxide trench of the high-voltage transistor. As an example, the depth h of trench 103 is approximately... (can be) etc).

[0068] In one example, please refer to Figure 2AIn step S1.2, a first photomask (not shown) is used to perform photolithography on the first photoresist layer 200, defining not only the formation area of ​​the trench 103 but also the formation area of ​​the second depth adjustment trench 104 in the substrate region HV where the high-voltage transistor is to be fabricated. In step S1.3, using the photolithographically rendered first photoresist layer 200 as a mask, the substrate 100 is etched, forming the trench 103 (i.e., the gate oxide trench and the first depth adjustment trench) and the second depth adjustment trench 104 simultaneously in the substrate 100. The trench 103 has a large linewidth, covering not only the active region HVG of the gate oxide trench of the high-voltage transistor, but also the area of ​​the shallow trench 107 that defines the area around the gate oxide trench (which separates the active region HVG of the gate oxide trench of the high-voltage transistor from the source / drain regions HVS / D). The second depth adjustment trench 104 is located at the boundary of the active region of the high-voltage transistor to be fabricated, and is used to achieve device isolation between the high-voltage transistor and other surrounding components together with the shallow trench connected to it. The substrate area between the second depth adjustment trench 104 and the trench 103 is used to fabricate the source / drain regions HVS / D of the high-voltage transistor. The second depth adjustment trench 104 deepens the bottom depth of the subsequently formed shallow trench isolation structure STI2, enhances the isolation performance of the shallow trench isolation structure STI2, and further improves the performance of the high-voltage transistor.

[0069] In one example, please refer to Figure 3In step S1.2, when the substrate 100 provided in step S1.1 is a bare silicon wafer, trenches 103 and second depth adjustment trenches 104 can be formed in the substrate 100 through a zero-loop fabrication process. In this example, the first pad oxide layer 101, the first nitride layer 102, and the photoresist layer 200 sequentially formed on the substrate 100 are the starting layers (also known as the zero layer) formed on the surface of the substrate 100, and have not yet undergone an etching step, so the surface of the substrate 100 has no uneven terrain. Therefore, the first photomask used in step S1.2 is the zero-loop photomask, which is the photomask required in the first photolithography process of substrate fabrication. This zero-loop photomask is usually used to define the formation area of ​​the zero-loop alignment mark ZM0, which is used for alignment in subsequent photolithography processes. Clearly, the zero-layer photomask in this example (i.e., the first photomask), compared to the zero-layer photomask of the prior art, not only defines the formation area of ​​the zero-layer alignment mark ZM0, but also simultaneously defines the formation area of ​​the trench 103, or simultaneously defines the formation areas of the trench 103 and the second depth adjustment groove 104. Therefore, in step S1.3, the trench 103 and the zero-layer alignment mark ZM0 are formed simultaneously, with the depth of the trench 103 being the same as the depth of the zero-layer alignment mark ZM0. The zero-layer alignment mark ZM0 can then be filled with dielectric material in the subsequent step S5.

[0070] Figures 2A to 2B and Figure 3 In the example shown, the trench 103 formed in step S1 is a single trench with a relatively large opening size. The top of the substrate in the trench 103 is flat. The trench 103 covers the gate oxide trench of the high voltage transistor and the formation area of ​​the shallow trench isolation structure around the gate oxide trench (i.e., the area between the gate oxide trench and the source / drain region). The number of first depth adjustment trenches on one side of the gate oxide trench is equivalent to one, but the technical solution of the present invention is not limited to this.

[0071] In another example of this embodiment, please refer to Figure 4 In step S1, the gate oxide trench 103a is not connected to the first depth adjustment trench 103b, and the number of first depth adjustment trenches 103b on one side of the gate oxide trench 103a can be one, two, or more. Therefore, after the subsequent step S3, the shallow trenches 107 formed on both sides of the gate oxide trench 103a are connected to the gate oxide trench 103a and one, two, or more first depth adjustment trenches 103b on the same side. Each first depth adjustment trench 103b causes a deepening groove 107a corresponding to the first depth adjustment trench 103b to be formed at the bottom of the shallow trench 107a.

[0072] Please refer to Figure 5In another example of this embodiment, in step S1.2, when photolithography is performed on the first photoresist layer 200 using a first photomask (not shown), the formation region of the second depth adjustment trench is not defined at the boundary region of the substrate region HV to be fabricated for the high-voltage transistor. In step S1.3, after etching the substrate 100 using the photolithographically rendered first photoresist layer 200 as a mask, the second depth adjustment trench is not formed simultaneously while the trench 103 (i.e., the gate oxide trench and the first depth adjustment trench) is formed in the substrate 100. Therefore, after the subsequent step S3, the bottom depth of the shallow trench 108 formed at the boundary of the substrate region HV to be fabricated for the high-voltage transistor is the same as the bottom depth of the shallow trench 109 formed in the substrate region Other used to fabricate other components.

[0073] Furthermore, it should be understood that in the above examples, the critical dimension CD of the first depth adjustment groove needs to meet the requirements of subsequent processes, such as being at least greater than 80nm, to ensure the process window for forming the second pad oxide layer 105 and the second nitride layer 106 in the subsequent step S2.

[0074] Please continue to refer to this. Figure 2A In step S2, a second pad oxide layer 105 and a second nitride layer 106 are sequentially formed on the surface of the substrate 100 after the trench 103 is formed. The second pad oxide layer 105 covers the inner surface of the trench 103 (i.e., the gate oxide trench and the first depth adjustment trench) and the surface of the substrate 100 surrounding the trench 103. The second pad oxide layer 105 and the second nitride layer 106 constitute the required hard mask layer. The second pad oxide layer 105 can be formed by any suitable process such as thermal oxidation or chemical vapor deposition. It serves as an etch stop layer for etching the second nitride layer 106 and protects the surface of the substrate 100 during the etching of the second nitride layer 106. The second nitride layer 106 can be formed by any suitable process such as chemical vapor deposition, and its material can be any suitable dielectric material such as silicon nitride.

[0075] Please continue to refer to this. Figure 2A In step S3, an active region fabrication process (AA loop) is performed on the hard mask layer and the substrate 100 it covers to form corresponding shallow trenches 107, 108, and 109 in the substrate 100 at trench 103 and in the substrate 100 surrounding trench 103, thereby defining the active regions of high-voltage transistors and other components. The specific process of this active region fabrication process (AA loop) includes:

[0076] S3.1, A second photoresist layer 201 is formed on the second nitride layer 106 by spin coating or other processes;

[0077] S3.2, the second photoresist layer 201 is photolithographically ...

[0078] S3.3, using the second photoresist layer 201 after photolithography as a mask, the second nitride layer 106, the second pad oxide layer 105 and the substrate 100 are etched using any suitable etching process such as dry etching to form the corresponding shallow trenches 107, 108 and 109.

[0079] S3.4, Remove the second photoresist layer 201 by any suitable photoresist removal process, such as dry or wet photoresist removal.

[0080] The shallow trench 107 formed at trench 103 is located on both sides of the gate oxide trench, overlaps with the first depth adjustment trench, and is connected to both the gate oxide trench and the first depth adjustment trench. This separates the active region HVG at the gate oxide trench from the source / drain region HVS / D of the high-voltage transistor. Due to the effect of trench 103, the bottom of the shallow trench 107 formed at trench 103 is deeper than the bottom of the shallow trench 109 in the region of other components. In addition, the shallow trench 108 is formed between the active region (i.e., the HV region) of the high-voltage transistor and the active region (i.e., Other) of other components. On the one hand, it is used to achieve isolation between the active region of the high-voltage transistor and the active region of other components. On the other hand, it is used together with the shallow trench 107 to define the source / drain region HVS / D of the high-voltage transistor.

[0081] In one example, please refer to Figure 2A Since trenches 103 and second depth adjustment trenches 104 of essentially the same depth are simultaneously formed in the substrate region HV of the high-voltage transistor to be fabricated in step S1, in step S3, when performing the above-mentioned active region manufacturing process, a corresponding shallow trench 108 is also formed in the substrate at the second depth adjustment trench 104. The shallow trench 108 formed at the second depth adjustment trench 104 overlaps with and is connected to the second depth adjustment trench 104. At this time, the bottom depth of the shallow trench 108 formed at the second depth adjustment trench 104 is essentially the same as the bottom depth of the shallow trench 107, and is deeper than the bottom of the shallow trench 109 in the region of other components.

[0082] For other examples, please refer to Figure 5 When the second depth adjustment groove is not formed synchronously in step S1, after the above-mentioned active area manufacturing process is performed in step S3, the bottom depth of the shallow trench 108 formed is the same as the bottom depth of the shallow trench 109 in the other component area Other, and is shallower than the bottom depth of the shallow trench 107 formed at trench 103.

[0083] Furthermore, it should be understood that the degree of overlap between the corresponding openings in the second photoresist layer 201 after photolithography and the trench 103 determines the degree of overlap between the shallow trench 107 formed at the trench 103 and the trench 103, and thus determines whether the sidewall of the shallow trench 107 formed at the trench 103 is aligned with the sidewall of the trench 103 or forms a step, or in other words, the degree of overlap between the shallow trench 107 and the first depth adjustment groove, and thus determines whether the sidewall of the shallow trench 107 is aligned with the sidewall of the first depth adjustment groove or has a step.

[0084] In one example, such as Figure 2A and Figure 5 As shown, the corresponding opening in the second photoresist layer 201 after photolithography is aligned with the trench 103, and the sidewall of the shallow trench 107 formed at the trench 103 is aligned with the sidewall of the trench 103.

[0085] In another example, please refer to Figure 4 and Figure 6 The size of the corresponding opening in the second photoresist layer 201 after photolithography is relatively large and offset outward relative to the sidewall of the trench 103. Therefore, a step is formed between the sidewall of the shallow trench 107 formed at the trench 103 and the sidewall of the trench 103 (that is, a step is formed between the sidewall of the shallow trench 107 and the sidewall of the first depth adjustment groove).

[0086] In yet another example, please refer to Figure 7 The size of the corresponding opening in the second photoresist layer 201 after photolithography is relatively small and offset inward relative to the sidewall of the trench 103. Therefore, a step is also formed between the sidewall of the shallow trench 107 formed at the trench 103 and the sidewall of the trench 103 (that is, a step is formed between the sidewall of the shallow trench 107 and the sidewall of the first depth adjustment groove). In this case, the active region surface exposed above the top surface of the step is also covered with a second pad oxide layer 105 and a second nitride layer 106.

[0087] Similarly, when the second depth adjustment groove 104 is formed at the same time as the groove 103 is formed, the overlap between the shallow groove 108 and the second depth adjustment groove 104 at the second depth adjustment groove 104 is different, which can also make the sidewall of the shallow groove 108 at the second depth adjustment groove 104 aligned with the sidewall of the second depth adjustment groove 104 or form a step, which will not be described in detail here.

[0088] It should be understood that, in this embodiment, by utilizing the depth of the first depth adjustment trench (including the portion of trench 103 used as the first depth adjustment trench) and the depth of the second depth adjustment trench 104, the depth of the shallow trench (STI trench) in the substrate region of the high-voltage transistor can be increased, thereby increasing the charge path of the high-voltage transistor and increasing its breakdown voltage. Moreover, under the same breakdown voltage capability, the high-voltage transistor of the present invention can have a shorter active region length compared to existing high-voltage transistors, which is beneficial for reducing the area of ​​the high-voltage transistor, and thus the chip area, and improving integration density. In some examples, the depth of the gate oxide trench is further utilized to reduce the top height of the thick gate oxide layer subsequently formed on the active region HVG, thereby reducing the step height (SH) between the high-voltage transistor and other components.

[0089] Please refer to Figure 2A and Figure 2B In step S4, any suitable process can be used to fill dielectric material into each of the shallow trenches 107, 108, 109 and trench 103 and the second depth adjustment trench 104 to form the desired shallow trench isolation structures STI1, STI2, and STI3. Before or after filling the dielectric material, the hard mask layer (i.e., the second pad oxide layer 105 and the second nitride layer 106) on the active region HVG of the gate oxide trench is retained. At this time, the shallow trench isolation structure STI1 buries the hard mask layer on the active region HVG of the gate oxide trench. Afterwards, the second nitride layer 106 in the hard mask layer of the remaining areas (including the substrate areas of other components and the source / drain regions HVS / D of the substrate area HV of the high voltage transistor) can be removed. The second pad oxide layer 105 in these remaining areas can even be further removed.

[0090] In one example, the process of forming the desired shallow trench isolation structures STI1, STI2, and STI3 in step S4 includes the following steps:

[0091] S4.1 First, use any suitable process such as dry etching to pull back the second nitride layer 106 in the hard mask layer, so that the pattern sidewall of the second nitride layer 106 is pulled back a certain distance.

[0092] S4.2, A linear oxide layer 110 is formed on the inner surface of shallow trenches 107, 108, 109 and trench 103 and second depth adjustment groove 104 by processes such as thermal oxidation;

[0093] S4.3, using a high aspect ratio fill process (HARP) or other suitable process, deposit dielectric material 112 (e.g., silicon oxide) in shallow trenches 107, 108, 109 and trenches 103 and second depth adjustment trenches 104 until the shallow trenches 107, 108, 109 and trenches 103 and second depth adjustment trenches 104 are filled;

[0094] S4.4, using a suitable process such as chemical mechanical polishing, the top surface of the filled dielectric material 112 is planarized until the top surface of the second nitride layer 106 is exposed. This forms a shallow trench isolation structure STI1 in the connected shallow trenches 107 and 103 to isolate the active region HVG of the gate oxide trench from the source / drain region HVS / D of the high-voltage transistor; a shallow trench isolation structure STI2 is formed in the connected shallow trench 108 and the second depth adjustment trench 104 to define the source / drain region HVS / D of the high-voltage transistor and isolate the high-voltage transistor from other components; and a shallow trench isolation structure STI3 is formed in the shallow trench 109 to isolate other components from the high-voltage transistor. At this time, due to the trench 103, the second nitride layer 106 and the second pad oxide layer 105 on the active region HVG of the gate oxide trench are retained and buried within the shallow trench isolation structure STI1.

[0095] S4.5, the second nitride layer 106 exposed by the shallow trench isolation structure STI1 (i.e., the hard mask layer on the area outside the gate oxide trench) is removed by any suitable process such as wet etching, and the second pad oxide layer 105 is retained. The second pad oxide layer 105 protects the surface of the substrate 100 outside the active region HVG of the gate oxide trench in subsequent steps S6 and S7.

[0096] In other examples of this embodiment, in step S4.4, a suitable process such as chemical mechanical polishing can also be used to planarize the top surface of the filled dielectric material 112 until the second nitride layer 106 on the substrate other than the active region HVG of the gate oxide trench is removed, thereby saving one etching process.

[0097] Please continue to refer to this. Figure 2BIn step S5, firstly, a silicon nitride layer 115 is deposited using processes such as chemical vapor deposition; then, photoresist is spin-coated onto the silicon nitride layer 115, and photolithography is performed on the photoresist layer to open the active region HVG of the gate oxide trench, forming a patterned photoresist layer (not shown); then, using the patterned photoresist layer as a mask, the silicon nitride layer 115 is etched to open the silicon nitride layer 115 on the active region HVG of the gate oxide trench; next, the patterned photoresist layer is removed, and using the silicon nitride layer 115 as a mask, the shallow trench isolation structure STI1 on the active region HVG of the gate oxide trench is etched until exposed. A second nitride layer 106 is applied to the active region HVG of the gate oxide trench. Then, under the protection of the second nitride layer 106, the top sidewalls of the shallow trench isolation structure STI1 on both sides of the active region HVG of the gate oxide trench are etched to form a side trench 117 exposing the apex corner of the active region HVG of the gate oxide trench. During this process, the presence of the second nitride layer 106 provides etching protection for the active region HVG of the gate oxide trench, resulting in greater consumption of dielectric material 112 at the side trench 117 and less consumption of the second pad oxide layer 105 below the second nitride layer 106 and the apex corner of the active region. This is beneficial for optimizing the rounding of the apex corner of the active region HVG of the gate oxide trench (e.g., ...). Figure 2B (as shown by the dashed circle in the diagram). The thickness of the silicon nitride layer 115 is generally much thicker than that of the second nitride layer 106. Therefore, when the second nitride layer 106 is subsequently pulled back and etched, and when the second nitride layer 106 is removed in step S7, there will be no adverse effects even if the silicon nitride layer 115 and the second nitride layer 106 are consumed simultaneously.

[0098] Please continue to refer to this. Figure 2B In step S6, under the cover of silicon nitride layer 115 and second nitride layer 106, the apex surface of the active region HVG of the gate oxide trench exposed by the side trench 117 is oxidized to form an apex oxide layer 118a.

[0099] In one example, please refer to Figure 2BTo form a sufficiently thick corner oxide layer 118a, in step S6, before oxidizing the corner surface of the active region HVG of the gate oxide trench exposed by the side trench 117, ions for increasing the oxidation rate can be used to implant ions into the corner of the active region HVG of the gate oxide trench exposed by the side trench 117. This implantation of these ions increases the formation rate and thickness of the corner oxide layer 118a. Optionally, the ions for increasing the oxidation rate can include at least one of oxygen ions, amorphous ions, and halide ions. Oxygen ion implantation can increase the oxygen content in the corner of the active region HVG of the gate oxide trench, thereby increasing the oxidation rate when subsequently oxidizing the corner of the active region HVG of the gate oxide trench. Amorphous ions include, for example, at least one of silicon ions, germanium ions, or argon ions. For instance, when the intrinsic material of the substrate 100 is monocrystalline silicon, the implantation of amorphous ions can transform the monocrystalline silicon at the apex of the active region HVG of the gate oxide trench into amorphous silicon, thereby increasing the oxidation rate at the apex of the active region HVG of the gate oxide trench in subsequent oxidation. Halogen ions include, for example, at least one of chloride ions (Cl), fluoride ions (F), and bromide ions (Br). The implantation of halide ions can act as a catalyst, weakening the Si-O bond energy at the apex of the active region HVG of the gate oxide trench. Therefore, when the apex oxide layer 118a is subsequently formed at the apex of the active region HVG of the gate oxide trench, the Si-O bond energy in the already formed upper apex oxide layer 118a is further weakened, making it easier for oxygen to diffuse in, thereby increasing the oxidation rate at the apex of the active region HVG of the gate oxide trench.

[0100] In another example, in order to ensure the coverage area of ​​the corner oxide layer 118a formed on the corner of the active region HVG of the gate oxide trench, before oxidizing the corner surface of the active region HVG of the gate oxide trench exposed by the side trench 117 in step S6, any suitable etching process such as wet etching can be used to pull back the sidewall of the hard mask layer (i.e., the second nitride layer 106 and the second pad oxide layer 105) to expose more corner surfaces of the active region HVG of the gate oxide trench.

[0101] In other examples of this embodiment, after completing step S3 and before executing step S4, or after etching the shallow trench isolation structure STI1 in the gate oxide trench in step S5 to expose the top surface of the hard mask layer in the gate oxide trench, any suitable etching process such as wet etching can be used to pull back the sidewalls of the hard mask layer (i.e., the second nitride layer 106 and the second pad oxide layer 105) on the top of the active region HVG of the gate oxide trench, thereby exposing more of the apex surface of the active region HVG of the gate oxide trench, thereby ensuring the coverage area of ​​the apex oxide layer 118a formed on the apex of the active region HVG of the gate oxide trench in step S6.

[0102] Please continue to refer to this. Figure 2B In step S7, firstly, the second nitride layer 106 and the second pad oxide layer 105 are removed using any suitable process such as wet etching to expose the top surface of the active region HVG of the gate oxide trench. It should be understood that the silicon nitride layer 115 formed in step S5 needs to be sufficiently thick, allowing it to be thinned entirely during the removal of the second nitride layer 106 while still providing the required masking effect. The corner oxide layer 118a formed in step S6 also needs to be sufficiently thick, allowing it to be thinned entirely during the removal of the second pad oxide layer 105 while still masking the corner surface of the active region HVG of the gate oxide trench. Then, under the masking effect of the silicon nitride 115 and the remaining corner oxide layer 118a, the active region HVG of the gate oxide trench is thermally oxidized to form a thick gate oxide layer 118 of the required thickness.

[0103] On the one hand, because a corner oxide layer 118a is formed at the apex of the active region HVG of the gate oxide trench in step S6, when the thick gate oxide layer 118 is generated in step S7, the thick gate oxide layer 118 grown at the apex of the active region HVG of the gate oxide trench is thicker than that of the prior art, and the apex of the active region is rounded. Therefore, the problem of thin corners of the entire thick gate oxide layer 118 and the problem of sharp corners of the active region can be solved, and the withstand voltage performance of the high voltage transistor can be improved. On the other hand, since the top height of the active region HVG of the gate oxide trench is reduced by the gate oxide trench formed in step S1, after the thick gate oxide layer 118 is formed in step S7, the step height (SH) between the high voltage transistor and other components can be reduced compared with the prior art, thereby reducing the load effect and defects of subsequent processes, improving the performance of the high voltage transistor, and also facilitating the reduction of the device area of ​​the high voltage transistor.

[0104] To further improve device performance, in other examples of this embodiment, after completing step S1 and before executing step S3, or after completing step S3 and before executing step S4, a lightly doped source-drain (LDD) ion implantation process is used to implant ions into the active region HV of the high-voltage transistor to form a first drift region 111. Whether the conductivity type of the ions implanted in this step using the LDD process is n-type or p-type depends on whether the high-voltage transistor is an nMOS or pMOS. The LDD process used in this step is a tilted ion implantation process, and its conditions can be the same as those of the existing LDD process. Therefore, its vertical implantation depth is shallow, and its horizontal implantation depth in the gate oxide region is also shallow, resulting in a low implantation concentration.

[0105] In one example, please refer to Figure 8After completing step S1 and before executing step S3, under the masking of the first pad oxide layer 101 and the first nitride layer 102, a lightly doped source / drain ion implantation process (a tilted ion implantation process) is used to implant ions into the active region HV of the high-voltage transistor to form a first drift region 111. This first drift region 111 extends from the source / drain region HVS / D of the high-voltage transistor to the sidewall of the active region of the gate oxide trench. After step S3 is completed, the active region HVG of the gate oxide trench exposes the first drift region 111 of corresponding thickness near the sidewall of the shallow trench 107, and the first drift region 111 is also retained in the source / drain region HVS / D of the high-voltage transistor.

[0106] In another example, please refer to Figure 9 In step S4, before or after the formation of the online oxide layer 110 and before filling with dielectric material, a third photoresist layer 202 is first formed on a substrate 100 having shallow trenches 107, etc., by a process such as spin coating; then, the third photoresist layer 202 is photolithographically etched to open the third photoresist layer 202 on the active region HVG of the gate oxide trench and mask other areas; next, using the photolithographically etched third photoresist layer 202 as a mask, a lightly doped source / drain ion implantation process (a tilted ion implantation process) is used to implant ions into the top sidewall of the active region HVG of the gate oxide trench to form a first drift region 111, in which case the first drift region 111 is only located in the top sidewall of the active region HVG of the gate oxide trench; then the third photoresist layer 202 is removed.

[0107] Further optional, please refer to Figure 10 In step S4, after photolithography of the third photoresist layer 202, after the growth of the line oxide layer 110 and before the filling of the dielectric material 112, the line oxide layer 110 on the top sidewall of the active region HVG of the gate oxide trench is opened by any suitable etching process under the mask of the third photoresist layer 202. Then, ion implantation is performed on the top sidewall of the active region HVG of the gate oxide trench to form the first drift region 111, thereby ensuring the implantation effect of the first drift region 111.

[0108] In the examples above, whether ion implantation of the first drift region 111 is performed before the shallow trench is formed, or after the shallow trench is formed and before the dielectric material is filled, ions can be effectively implanted to the corners of the area to be implanted in the LDD process. Compared with the prior art (i.e., first filling each shallow trench to form a shallow trench isolation structure, then defining the LDD process implantation area by photolithography of photoresist PR, and then performing the LDD process), the present invention can avoid the need for rounding the corners of the photoresist PR openings (e.g., ...). Figure 11(As shown in the dashed box in the figure) This leads to imperfect corner injection of the active region HVG of the gate oxide trench in the LDD process, thus eliminating the side effect caused by the step height (SH) of the high voltage transistor in the prior art.

[0109] In addition, please refer to Figures 9 to 10 During the ion implantation process that forms the first drift region 111, since the top of the active region HVG of the gate oxide trench is also covered by the second pad oxide layer 105 and the second nitride layer 106, the ions can be implanted into the implantation region required by the LDD process and have a good protection effect on the active region below, without having a negative impact on the threshold voltage regulation of the high voltage transistor.

[0110] In one embodiment of this example, please continue to refer to... Figure 9 After completing step S4 and before executing step S5, a patterned photoresist (not shown) is formed using photolithography to mask the active regions of other components (i.e., the substrate region Other used to form other components) and expose the active region of the high-voltage transistor (i.e., the substrate region HV used to form the high-voltage transistor). Using this patterned photoresist as a mask, ion implantation is performed on the active region of the high-voltage transistor using a suitable process such as vertical ion implantation to form a second drift region 113. The implanted ions are suitable ions such as n-type or p-type ions. Afterward, the patterned photoresist is removed. The ion implantation depth for forming the second drift region 113 is greater than the ion implantation depth for forming the first drift region 111. The second drift region 113 and the first drift region 111 are connected to form the drift region required for the high-voltage transistor.

[0111] As an example, ion implantation to form the second drift region 113 can include two steps: the first step involves slightly deeper ion implantation at a lower energy level, serving as channel conditioning. For pMOS transistors, this step can implant lightweight n-type ions such as phosphorus (P) ions, while for nMOS transistors, it can implant lightweight p-type ions such as boron (B) ions. The second step involves very shallow ion implantation at a very low energy level, serving as threshold voltage conditioning. This step can implant the same ions as the first step or different ions. For example, for pMOS transistors, this step can implant heavy n-type ions such as arsenic (As) or antimony (Sb) ions, which are less prone to diffusion; for nMOS transistors, this step can implant heavy n-type ions such as aluminum (Al), gallium (Ga), or indium (In), which are also less prone to diffusion.

[0112] In addition, it should be noted that after step S7, the silicon nitride layer 115 and the second pad oxide layer 105 covering it are removed first, and then a thin gate oxide layer (not shown) is formed on the active region of other components and the substrate region HV of the high voltage transistor to be fabricated, and the gate (not shown) is formed together on the thick gate oxide layer and the thin gate oxide layer.

[0113] In summary, the semiconductor device manufacturing method of the present invention first performs trench etching on the substrate region to be fabricated as a high-voltage transistor before performing the active region fabrication process, so as to form at least a gate oxide trench and a first depth adjustment trench on its outer side. As a result, after subsequent active region fabrication processes, the depth of the first depth adjustment trench can be used to increase the bottom depth (STI trench) of the shallow trench isolation structure used to isolate the source / drain region and the channel region of the high-voltage transistor, thereby increasing the charge path of the high-voltage transistor, increasing its breakdown voltage, and reducing the step height between the high-voltage transistor and other components compared with the prior art, thereby reducing the load effect and defects of subsequent processes and improving the performance of the high-voltage transistor. Furthermore, after forming the side trench and before forming the thick gate oxide layer, the surface of the active region's apex exposed by the side trench is oxidized under the masking of a hard mask layer in the gate oxide trench to form a apex oxide layer. This facilitates the rounding of the active region's apex at the gate oxide trench, and consequently, during the subsequent growth of the thick gate oxide layer, the growth of oxide layers on each crystal plane of the active region at the gate oxide trench is more favorable, preventing the problem of the thick gate oxide layer being thin at the active region's apex. This further improves the voltage withstand capability of the high-voltage transistor in the semiconductor device of the present invention. Consequently, under the same voltage withstand capability, the high-voltage transistor of the present invention can have a shorter active region length compared to existing high-voltage transistors, thereby reducing the area of ​​the high-voltage transistor, and consequently the chip area, and improving integration density. Furthermore, before filling the shallow trench, ion implantation is performed on the top sidewall of the active region of the gate oxide trench of the high-voltage transistor to form a first drift region. This allows ions to be effectively implanted into the corners of the areas that should be implanted in the existing LDD (lightly doped drain implantation) process. This helps to eliminate the side effect caused by the step height SH of the high-voltage transistor and avoids the problem of incomplete implantation caused by the rounded exposure of photoresist corners in the existing LDD process. The semiconductor device manufacturing method of the present invention is simple, controllable, and effective.

[0114] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, and trench etching is performed on the substrate region to be fabricated as a high voltage transistor to form at least a gate oxide trench and a first depth adjustment trench located outside the gate oxide trench. A hard mask layer is formed covering the substrate having the first depth adjustment trench and the gate oxide trench; An active region manufacturing process is performed on the hard mask layer and the substrate it covers to form corresponding shallow trenches in the substrate, wherein a portion of the shallow trenches overlaps with the first depth adjustment trench and communicates with the first depth adjustment trench and the gate oxide trench, and the active region manufacturing process deepens the bottom depth of the portion of the shallow trenches through the first depth adjustment trench. Dielectric material is filled into the gate oxide trench, each of the shallow trenches and the first depth adjustment trench to form a shallow trench isolation structure, which buries the hard mask layer in the gate oxide trench. The shallow trench isolation structure in the gate oxide trench is etched open, and the shallow trench isolation structure on the sidewall of the gate oxide trench is further etched to form a side trench that exposes the apex corner of the active region in the gate oxide trench. The hard mask layer in the gate oxide trench protects the active region in the gate oxide trench during the formation of the side trench. Under the cover of the hard mask layer in the gate oxide trench, the surface of the active region apex exposed by the side trench is oxidized to form an apex oxide layer; Remove the hard mask layer in the gate oxide trench and form a thick gate oxide layer on top of the active region of the gate oxide trench and in the side trench.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The steps of forming the gate oxide trench and the first depth adjustment trench include: A first pad oxide layer, a first nitride layer, and a first photoresist layer are sequentially formed on the substrate; The first photoresist layer is photolithographically lithographically lithographically formed using a first photomask to at least define the formation areas of the gate oxide trench and the first depth adjustment trench; Using the first photoresist layer after photolithography as a mask, the first nitride layer, the first pad oxide layer and the substrate are etched sequentially to form the gate oxide trench and the first depth adjustment trench in the substrate; Remove the first photoresist layer, the first nitride layer, and the first pad oxide layer.

3. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, Performing an active region fabrication process on the hard mask layer and the substrate it covers includes the following steps: A second photoresist layer is formed on the hard mask layer; The second photoresist layer is photolithographically etched using a second photomask to define the formation area of ​​each of the shallow trenches; Using the second photoresist layer after photolithography as a mask, the hard mask layer and the substrate are etched to form the corresponding shallow trench; Remove the second photoresist layer.

4. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The gate oxide trench is spaced apart from or connected to the first depth adjustment trenches on both sides; and / or, the hard mask layer includes a second pad oxide layer and a second nitride layer sequentially stacked on the substrate.

5. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, While performing trench etching on the substrate area to be fabricated as a high-voltage transistor to form the gate oxide trench and the first depth adjustment trench, at least one second depth adjustment trench is also formed at the boundary of the active region of the high-voltage transistor. After performing the active region fabrication process, the second depth adjustment trench overlaps with and communicates with the corresponding shallow trench to deepen the bottom depth of the shallow trench and separate the active region of the high-voltage transistor from the active regions of other components.

6. The method for manufacturing a semiconductor device according to any one of claims 1-5, characterized in that, It also includes at least one of the following (1) to (5): (1) After the first depth adjustment groove is formed and before the shallow trench is formed, or after the shallow trench is formed and before the dielectric material is filled, at least the top sidewall of the active region in the gate oxide trench is ion implanted to form a first drift region. (2) After the shallow trench isolation structure is formed and before the side trench is formed, the active region of the high voltage transistor is ion implanted to form a second drift region. (3) Before filling the dielectric material, or after etching open the shallow trench isolation structure in the gate oxide trench to expose the top surface of the hard mask layer in the gate oxide trench, or after forming the side trench, the sidewalls of the hard mask layer in the gate oxide trench are also pulled back and etched to expose and round the top corners of the active region. (4) After the formation of the side trench and before the formation of the apex oxide layer, ions for increasing the oxidation rate are first used to implant ions into the apex of the active region; (5) After forming the thick gate oxide layer, a thin gate oxide layer is also formed on the active region of the other elements, and a gate is formed together on the thick gate oxide layer and the thin gate oxide layer.

7. The method for manufacturing a semiconductor device as described in claim 6, characterized in that, The top sidewall of the active region of the gate oxide trench is implanted with ions using a lightly doped source-drain ion implantation process to form the first drift region; and / or, the ions used to improve the oxidation rate include at least one of oxygen ions, amorphous ions, and halide ions, wherein the amorphous ions include at least one of silicon ions, germanium ions, and argon ions.

8. The method for manufacturing a semiconductor device as described in claim 6, characterized in that, The steps for forming the first drift region include: A third photoresist layer is formed on the substrate; Photolithography is performed on the third photoresist layer to at least open the third photoresist layer on the gate oxide trench and mask other areas; Using the third photoresist layer after photolithography as a mask, and employing a lightly doped source / drain ion implantation process, the first drift region is formed.

9. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, After the shallow trenches are formed and before the third photoresist layer is formed on the substrate, a line oxide layer is first formed on the inner surfaces of the gate oxide trench, each of the shallow trenches and the first depth adjustment trench.

10. A method for manufacturing a semiconductor device as described in any one of claims 1-5 or 7-9, characterized in that, It also includes at least one of the following (1) to (3): (1) The sidewall of the first depth adjustment groove is aligned with or forms a step with the sidewall of the shallow groove it communicates with; (2) Photolithography and trench etching are performed on the substrate area to be fabricated for high voltage transistors using the zero-layer photomask, so as to form the first depth adjustment trench and the gate oxide trench at the same time as forming the zero-layer alignment mark in the substrate. (3) After the dielectric material is filled into the gate oxide trench, each of the shallow trenches and the first depth adjustment trench, the top surface of the dielectric material is planarized until the top surface of the hard mask layer on the substrate region surrounding the gate oxide trench is exposed or until the hard mask layer on the substrate region surrounding the gate oxide trench is removed.

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