Semiconductor device and method of forming the same
By selectively forming barrier and adhesive layers on the bottom layer of the interconnect structure, combined with low dielectric constant dielectric plugs, the problem of poor gap filling performance in metallized structures is solved, achieving low contact resistance and high structural integrity, and improving the reliability of the interconnect layer.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2025-08-04
- Publication Date
- 2026-06-02
AI Technical Summary
As the size of integrated circuit devices decreases, the size and spacing between metallization structures in the interconnect layer also decrease, leading to a reduction in the gap-filling performance of the bottom layer of the metallization structure. This can result in voids and discontinuities, increasing contact resistance and causing electrical disconnection.
Barrier and adhesive layers are selectively formed on the bottom layer of the interconnect structure. Self-assembled monolayer films and amorphous adhesive layers are used in combination with low dielectric constant dielectric plugs to form the bottom layer of the metallized structure to reduce contact resistance. A seamless metallized structure is formed by bottom-up deposition technology.
This achieves low contact resistance and higher structural integrity, reduces electrical isolation between the bottom layers of the metallized structure, and improves the reliability and performance of the interconnect layers.
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Figure CN122138684A_ABST