Semiconductor device and method of manufacturing a conductive structure of a metallization structure

Abstract

In one embodiment, a semiconductor device is provided, comprising a semiconductor substrate including a first main surface and a metallization structure on the first main surface. The metallization structure includes one or more conductive structures, each including a metal diffusion barrier layer and a copper layer on the metal diffusion barrier layer. The metal diffusion barrier layer has a thickness t, an upper surface, a lower surface, and a side surface extending between an upper edge formed between the upper surface and the side surface and a lower edge formed between the lower surface and the side surface. The linear distance d between the upper and lower edges is t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t.

Description

Background Technology

[0001] Transistors used in power electronics applications can be fabricated using silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS®, Si power MOSFETs, and Si insulated-gate bipolar transistors (IGBTs). Recently, silicon carbide (SiC) power devices have been considered. III-N group semiconductor devices, such as gallium nitride (GaN) devices, are attractive candidates for carrying high currents, supporting high voltages, and providing very low on-resistance and fast switching times.

[0002] One or more semiconductor devices, such as transistor devices, may be provided in a package. The package includes a substrate or lead frame that includes external contacts for mounting the package on a redistribution board, such as a printed circuit board. The package also includes internal electrical connections from the semiconductor devices to the substrate or lead frame. The housing may include a plastic molding compound covering the semiconductor devices and the internal electrical connections.

[0003] Reliable semiconductor devices and packaged semiconductor devices are desired. US 2018 / 0308927 A1 describes structures and methods for isolating semiconductor devices and improving device reliability under harsh environmental conditions. An isolation region is formed by ion implantation in a semiconductor region surrounding the device. The implanted region can extend into the wafer's channels. A passivation layer is deposited over the implanted region and extends further into the channels than the isolation region to protect the isolation region from environmental conditions that may adversely affect it.

[0004] The goal is to further improve the reliability of the device, even under harsh environmental conditions. Summary of the Invention

[0005] In one embodiment, a semiconductor device is provided, comprising a semiconductor substrate including a first main surface and a metallization structure on the first main surface. The metallization structure includes one or more conductive structures, each including a metal diffusion barrier layer and a copper layer on the metal diffusion barrier layer. The metal diffusion barrier layer has a thickness t, an upper surface, a lower surface, and a side surface extending between an upper edge formed between the upper surface and the side surface and a lower edge formed between the lower surface and the side surface. The linear distance d between the upper and lower edges is t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t.

[0006] In one embodiment, a method for manufacturing a conductive structure with a metallized structure is provided. The method includes forming a metal diffusion barrier layer on a first main surface of a semiconductor substrate, forming a structured copper layer on the metal diffusion barrier layer, wherein a portion of the metal diffusion barrier layer is exposed from the structured copper layer, removing the exposed portion of the metal diffusion barrier layer by plasma etching, and forming one or more conductive structures including the metal diffusion barrier layer and the copper layer.

[0007] Those skilled in the art will recognize the additional features and advantages when reading the following detailed description and when viewing the accompanying drawings. Attached Figure Description

[0008] The elements in the accompanying drawings are not necessarily proportional to each other. Similar reference numerals designate corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the accompanying drawings and described in detail below.

[0009] Figure 1 A cross-sectional view of a semiconductor device including a metallized structure is shown.

[0010] Figure 2 A flowchart illustrating a method for manufacturing a conductive structure with a metallized structure is shown.

[0011] Figure 3, including Figures 3A to 3G This paper illustrates a method for fabricating metallized structures on semiconductor devices. Detailed Implementation

[0012] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description and illustrate, by way of illustration, specific embodiments in which the invention may be practiced. In this regard, directional terms such as “top,” “bottom,” “front,” “back,” “leader,” “tail,” etc., are used with reference to the orientation of the described figures(s). Because components of the embodiments can be positioned in many different orientations, the directional terms are used for illustrative purposes and are by no means limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. The following detailed description is not to be construed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0013] Several exemplary embodiments will now be explained. In this context, the same structural features are identified by the same or similar reference numerals in the figures. In the context of this specification, “lateral” or “lateral direction” should be understood to mean a direction or extent that generally travels parallel to the lateral extent of the semiconductor material or semiconductor carrier. Thus, the lateral direction generally extends parallel to these surfaces or sides. Conversely, the term “vertical” or “vertical direction” is understood to mean a direction that generally travels perpendicular to these surfaces or sides, and therefore perpendicular to the lateral direction. Thus, the vertical direction travels in the thickness direction of the semiconductor material or semiconductor carrier.

[0014] As used in this specification, when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or directly extending onto the other element, or there may be intermediate elements present. Conversely, when an element is referred to as "directly on" or "directly extending onto" another element, there are no intermediate elements present.

[0015] As used in this specification, when an element is referred to as “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, there are no intermediate elements.

[0016] Depletion-type devices, such as high-voltage depletion-type transistors, have a negative threshold voltage, meaning they can conduct current at zero gate voltage. These devices are normally on. Enhancement-type devices, such as low-voltage enhancement-type transistors, have a positive threshold voltage, meaning they cannot conduct current at zero gate voltage and are normally off.

[0017] In some embodiments, the semiconductor device is a group III nitride-based device, such as a transistor, diode, or bidirectional switch.

[0018] As used herein, the phrase "Group III nitride" refers to a compound semiconductor comprising nitrogen (N) and at least one Group III element, including aluminum (Al), gallium (Ga), indium (In), and boron (B), and including but not limited to any alloys thereof, such as, for example, aluminum gallium nitride (Al). x Ga (1-x) N), Indium gallium nitride (In) y Ga (1-y) N), aluminum indium gallium nitride (Al) x In y Ga (1-x-y) N), gallium arsenide phosphorus nitrogen (GaAs) a P b N (1-a-b) ) and AlInGaAsPNi (Alx In y Ga (1-x-y) As a PbN (1-a-b) AlGaN and AlGaN refer to aluminum gallium nitride (AlGaN) produced by the formula AlGaN. x Ga (1-x) N describes the alloy, where 0 <x<1。

[0019] As used herein, various device types and / or doped semiconductor regions may be identified as having n-type or p-type, but this is merely for the convenience of description and not for limitation, and such identification may be replaced by a more general description having a “first conductivity type” or a “second opposite conductivity type”, wherein the first type may be n-type or p-type and the second type may be p-type or n-type.

[0020] In some embodiments, the semiconductor device is a silicon-based device, such as a nitride-based MOSFET (metal-oxide-semiconductor field-effect transistor), an insulated-gate bipolar transistor (IGBT), or a bipolar junction transistor (BJT). The transistor device may be a vertical transistor device having a drift path extending perpendicular to the main surface of the device.

[0021] The electrodes or terminals of a transistor device are referred to herein as source, drain, and gate. As used herein, these terms also cover functionally equivalent terminals of other types of transistor devices, such as insulated-gate bipolar transistors (IGBTs). For example, as used herein, the term "source" covers not only the source of a MOSFET and a superjunction device, but also the emitter of an IGBT and a bipolar junction transistor (BJT); the term "drain" covers not only the drain of a MOSFET or a superjunction device, but also the collector of an IGBT and a BJT; and the term "gate" covers not only the gate of a MOSFET or a superjunction device, but also the gate of an IGBT and a BJT.

[0022] Figure 1 A cross-sectional view of the semiconductor device 10 and an enlarged view of a portion of the semiconductor device 10 are shown.

[0023] Semiconductor device 10 includes a semiconductor substrate 12, the semiconductor substrate 12 including a first main surface 13, and a metallization structure 14 located on the first main surface 13. The metallization structure 14 includes one or more conductive structures 15. Figure 1In this embodiment, the conductive structure 15 has the form of contact pads. The conductive structure 15 can be described as a portion, part, piece, or section, and forms part of the conductive layer of the metallized structure; in some embodiments, the conductive layer is the uppermost conductive layer. The conductive structure 15 can also be referred to as part of power metal. The conductive structure 15 is not limited to the form of contact pads and can have other forms, such as metal interconnects, such as gate channels, or metal interconnects extending between two or more devices formed in the semiconductor substrate 12.

[0024] The contact pad 15 includes a metal diffusion barrier layer 16 and a copper layer 17, the copper layer 17 being disposed on and interfaced with the metal diffusion barrier layer 16. The metal diffusion barrier layer 16 has an upper surface 20 in contact with the copper layer 17 and a lower surface 23 in contact with a portion of the metallized structure 14, in this case, the third sublayer 37-3 of the third electrical insulating layer 37. The metal diffusion barrier layer 16 has a thickness t and a side surface 21, which can also be described as an end face 21, extending between an upper edge 19 and a lower edge 22, the upper edge 19 being formed between the upper surface 20 and the side surface 21 of the metal diffusion barrier layer 16, and the lower edge 22 being formed between the lower surface 23 and the side surface 21 of the metal diffusion barrier layer 16. The length of the side surface 21 extending between the upper edge 19 and the lower edge 22 is such that the linear distance (i.e., the closest distance or spacing) between the upper edge 19 and the lower edge 22 is a distance d.

[0025] Side 21 extends substantially perpendicular to the upper surface 20 and lower surface 23 of the metal diffusion barrier layer 16. Therefore, the length of side 21 and the linear distance d between the upper edge 19 and the lower edge 22 are approximately the same as the thickness t of the metal diffusion barrier layer 16. Side 21 may not extend perfectly perpendicular to the upper surface 20 and lower surface 23, but may be slightly inclined. Therefore, the distance d may be up to 10% larger than the thickness t, or up to 5% larger, such that t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t.

[0026] In some embodiments, such as Figure 1 As shown, the metal diffusion barrier layer 16 has a larger lateral extent than the copper layer 17 of the contact pad 15, such that the metal diffusion barrier layer 16 protrudes from the copper layer 17 and has a peripheral edge portion exposed from the copper layer 17 of the contact pad 15 and not covered by the copper layer 17. As a result, the side surface 24 of the copper layer 17 of the contact pad 15 extends from the upper surface 25 of the copper layer 15 to a position in the middle of the upper surface 20 of the metal diffusion barrier layer 16.

[0027] In some embodiments, such as Figure 1In the illustrated embodiment, the side surface 24 of the copper layer 17 forms an angle α greater than 90° with the metal diffusion barrier layer 16. For example, the angle α can be around 105°. In some embodiments, 90° ≤ α ≤ 145°. This angle can be measured between the tangent at the height center of the copper layer 17 and the upper surface 20 of the metal diffusion barrier layer 16.

[0028] In some embodiments, the semiconductor device 10 further includes an upper dielectric layer 26, which is located at least on the side surface 24 of the contact pad 15, and optionally on the peripheral edge region of the upper surface 25, and also on the region of the metallized structure 14 laterally adjacent to the contact pad 15. The dielectric layer 26 is in direct contact with the peripheral regions of the upper surface 25 and side surface 24 of the copper layer 17 and with the metal diffusion barrier layer 16.

[0029] The central portion of the upper surface 25 of the contact pad 15 remains exposed from the dielectric layer 26 and provides a contact surface, such as a bonding wire 27 or other connector, such as a strip, clip, or solder, which can be attached to provide an electrical connection to one or more semiconductor devices located within the semiconductor substrate 12. Where the conductive structure 15 provides a metal interconnect (also referred to as a trace or line), the entire upper surface 25 of the interconnect can be covered by the dielectric layer 26. Where the conductive structure 15 is an interconnect, the upper surface may also be partially covered or completely uncovered.

[0030] Semiconductor substrate 12 may be formed of silicon. In some embodiments, semiconductor substrate 12 may be formed of an alternative semiconductor material, such as silicon carbide, or may include one or more group III nitride layers. Metal diffusion barrier layer 16 may include a WTi alloy, or may be formed by depositing two or more sublayers, such as Ti / TiN or TaN / Ti. Metal diffusion barrier layer 16 may be deposited, for example, by sputtering. Any metal or alloy or combination of metals and alloys suitable as a diffusion barrier layer for upper copper layer 17 may be used. Copper layer 17 may be formed of copper only, or may include a small fraction of one or more alloying elements, such as Al.

[0031] The upper dielectric layer 26 may be formed of an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). The upper dielectric layer 26 may also include two or more sublayers. In the illustrated embodiment, the upper dielectric layer 26 includes three sublayers. For example, a first sublayer 26-1 formed of a nitride such as silicon nitride is in direct contact with the peripheral edge region of the upper surface 25 of the copper layer 17 and the side surface 24 of the copper layer 17, wherein portions of the metal diffusion barrier layer 16 and the metallization structure 14 laterally surround the contact pad 15 and any other conductive structures 15 present. A second sublayer 26-2 comprising an oxide such as silicon oxide is disposed on the first sublayer 26-1, and a third sublayer 26-3 comprising silicon nitride is formed on the second sublayer 26-2.

[0032] During the operational lifetime of the semiconductor device 10, thermomechanical stress is applied to the passivation structure, including the dielectric layer 26. Due to the shape of the copper layer 17 and the substantially vertical sides of the exposed peripheral region of the metal diffusion barrier layer 16, the upper dielectric layer 26 can be deposited uniformly, continuously, and uninterruptedly onto the conductive structure 15. This arrangement contributes to improved integrity of the dielectric layer 26. The passivation integrity of the dielectric layer 26 is also improved under harsh environmental conditions. The improved integrity of the dielectric layer 26 can help provide protection against mobile ions (e.g., chloride ions) that can leak from the environment and / or from the molding compound used to provide the enclosure in which the semiconductor device 10 is mounted. Therefore, the electrical isolation between the contact pads 15 of the semiconductor device 10 and each other is improved. This is useful, for example, for the source and drain contact pads of transistor devices that are typically connected to ground and high potentials, respectively. For some group III nitride-based HEMTs, the potential difference can reach up to 650V.

[0033] In some embodiments, the transition between the side 24 of the copper layer 17 and the metal diffusion barrier layer 16 may have a concave shape, which may further help to produce a uniform and continuous dielectric layer 26 on the contact pad 15, the metal diffusion barrier layer 16 and the electrically insulating layer provided by the metallization structure 14 in the region adjacent to the contact pad 15, thereby improving the reliability of the semiconductor device 10.

[0034] One or more semiconductor devices are formed in the semiconductor substrate 12. These semiconductor devices are electrically connected to the metallization structure 14 and contact pads 15, as well as one or more additional conductive structures 15. Figure 1 It is not visible in the cross-sectional view. Figure 1In the illustrated embodiment, the semiconductor substrate 12 includes a multilayer group III nitride-based structure 30 and a group III nitride transistor device 30. The group III nitride transistor device has a source electrode 31, a gate electrode 32, and a drain electrode 33 located on a first main surface 13 of the semiconductor substrate 12. The gate electrode 32 is laterally located between the source electrode 31 and the drain electrode 33.

[0035] In some embodiments, the metallization structure 14 includes a multilayer stack, the multilayer stack including a first conductive layer 34, and the terminals of the transistor device 30 are located in the first conductive layer 34. Figure 1 In the semiconductor substrate 12, the source electrode 31, the gate electrode 32, and the drain electrode 33 are formed on the first main surface 13.

[0036] The metallization structure 14 includes a first electrically insulating layer 35 extending over the first main surface 12 and the gate electrode 32, leaving the central portions of the source electrode 31 and the drain electrode 33 uncovered. The first electrically insulating layer 35 includes three sublayers: a lower sublayer 35-1 formed of silicon nitride, a second sublayer 35-2 formed of silicon oxide disposed on the first sublayer 35-1, and a third sublayer 35-3 formed of silicon nitride disposed on the second sublayer 35-2. The second sublayer 35-2 formed of silicon oxide has a greater thickness than the first and third sublayers 35-1 and 35-3 formed of silicon nitride.

[0037] The metallization structure 14 also includes a second electrical insulating layer 36 located on the first electrical insulating layer 35 and a third electrical insulating layer 37 disposed on the second electrical insulating layer 36. The second electrical insulating layer 36 includes two sublayers: a lower first sublayer 36-1 formed of silicon nitride in direct contact with the nitride sublayer 35-3, and a second sublayer 36-2 formed of silicon oxide disposed on the first sublayer 36-1. The second sublayer 36-2 formed of silicon oxide has a greater thickness than the first sublayer 36-1 formed of silicon nitride.

[0038] The third electrical insulating layer 37 comprises three sublayers: a lower sublayer 37-1 formed of silicon nitride directly on the oxide sublayer 36-2; a second sublayer 37-2 formed of silicon oxide disposed on the first sublayer 37-1; and a third sublayer 37-3 formed of silicon nitride disposed on the second sublayer 37-2. The second sublayer 37-2 formed of silicon oxide has a greater thickness than the first and third sublayers 37-1 and 37-3 formed of silicon nitride. The upper surface of the third sublayer 37-3 contacts the metal diffusion barrier layer 16 of the contact pad 15.

[0039] A first redistribution portion 41 is located in the second electrical insulating layer 36 and extends further through the first electrical insulating layer 35 to contact the source electrode 31. A second separate redistribution portion 42 is located in the second electrical insulating layer 36 and extends through the first electrical insulating layer 35 to the drain electrode 33. The first and second redistribution portions 41 and 42 extend through the thickness of the second electrical insulating layer 36.

[0040] exist Figure 1 The cross-sectional view shows a redistribution structure from the drain electrode 33 to the contact pad 15, such that the contact pad 15 provides the drain pad. A conductive via 43 extends through a third electrical insulating layer 37 to electrically connect the contact pad 15 to the redistribution portion 42, which in turn is electrically connected to the drain electrode 33. In some embodiments, an additional metal layer may be formed between the conductive via 43 and the contact 42 to improve adhesion.

[0041] The source and gate contact pads of a transistor device are in Figure 1 It is not visible in the cross-sectional view, but it has a reference. Figure 1 The structure of the drain contact pad 15 is shown and described. For example, the source and gate pads may be located in a plane that is in front of or behind the plane of the drawing.

[0042] The multilayer group III nitride structure of semiconductor substrate 12 is as follows Figure 1 As shown, a group III nitride structure 50 is disposed on a substrate 51. The group III nitride body includes a buffer structure 52 on the substrate 51, a GaN channel layer 53 on the buffer layer, and an AlGaN barrier layer 54 on the GaN channel layer 53, which forms a heterojunction between them to support a two-dimensional charge gas, such as a two-dimensional electron gas (2DEG). The transistor device 30 may be a HEMT (high electron mobility transistor). In this embodiment, the AlGaN barrier layer 54 forms the upper surface 14 of the group III nitride structure 50.

[0043] The substrate 51 includes an upper surface or growth surface 55 capable of supporting the epitaxial growth of one or more group III nitride substrates. In some embodiments, the substrate 51 is a heterogeneous substrate, i.e., formed of a material different from group III nitride materials, which includes an upper surface or growth surface 33 capable of supporting the epitaxial growth of one or more group III nitride substrates. The heterogeneous substrate 51 may be formed of silicon, and may be formed of, for example, monocrystalline silicon or an epitaxial silicon layer or sapphire.

[0044] In some embodiments not shown, the group III nitride-based semiconductor structure 50 may further include a back barrier layer. A GaN channel layer 53 is formed on the back barrier layer and forms a heterojunction with the back barrier layer, and a barrier layer 54 is formed on the channel layer 53. The back barrier layer has a different band gap than the GaN channel layer and may include, for example, AlGaN. The composition of the AlGaN in the back barrier layer may differ from the composition of the AlGaN used in the barrier layer 54.

[0045] A typical transition or buffer structure 52 for a silicon substrate includes an AlN initiation layer on the silicon substrate, which may have a thickness of several hundred nanometers, followed by Al x Ga (1-x) The N-layer sequence, each layer being several hundred nanometers thick, reduces the Al content from approximately 50-75% to 10-25% before growing the GaN layer or AlGaN back barrier layer (if present). Alternatively, a superlattice buffer layer can be used. Again, an AlN initiation layer is used on a silicon substrate. Depending on the chosen superlattice, AlN and Al... x Ga (1-x) N pairs of sequences, where AlN layer and Al x Ga （1-x） The thickness of N ranges from 2 to 25 nm. Depending on the desired breakdown voltage, the superlattice can comprise between 20 and 100 pairs. Alternatively, Al, as described above... x Ga （1-x） The N-layer sequence can be used in conjunction with the superlattice described above.

[0046] The gate electrode 32 may include a p-doped group III nitride layer 44, such as p-doped gallium nitride, and a gate metal layer 45 disposed on the p-doped group III nitride layer 44. This structure of the gate electrode 32 provides an normally-off enhancement-mode device. In other embodiments, the gate electrode 32 may have a recessed structure to form an enhancement-mode device. Alternatively, the group III nitride-based transistor device 30 may be a depletion-mode device.

[0047] In alternative embodiments, the semiconductor substrate 12 may also be formed of other semiconductor materials, such as silicon carbide or silicon. In some embodiments, the semiconductor substrate 12 is formed of an epitaxial silicon layer. For example, the semiconductor device 30 may be a silicon-based MOSFET, IGBT, or BJT.

[0048] In the illustrated embodiment, semiconductor device 10 includes a lateral transistor device. However, semiconductor device 10 may include other types of devices, such as other types of transistor devices, such as vertical transistor devices, bidirectional switches, diodes, two or more semiconductor devices, such as transistor devices and gate driver devices, power devices and logic devices, or two transistor devices electrically connected by a metallization structure to provide a half-bridge circuit or a bootstrap switch (diode).

[0049] Now refer to Figure 2 A method describing the conductive structure of a metallization structure for fabricating semiconductor devices. This method can be used to manufacture... Figure 1 The contact pad 15 is shown.

[0050] Figure 2 A flowchart 100 illustrates a method for manufacturing a conductive structure with a metallized structure.

[0051] In block 101, a metal diffusion barrier layer is formed on a first main surface of the semiconductor substrate. Other layers of the metallization structure may be located between the metal diffusion barrier layer and the first main surface of the semiconductor substrate. In this case, the metal diffusion barrier layer is formed on this segment of the metallization structure, which has already been fabricated and is located on the first main surface of the semiconductor substrate. For example, the metal diffusion barrier layer may be formed directly on an electrically insulating layer of the metallization structure, such as a silicon nitride layer. The metal diffusion barrier layer may include, for example, WTi, Ti / TiN, or TaN / Ta, and can be fabricated by sputtering an alloy or by multilayer stacking.

[0052] In block 102, a structured copper layer is formed on a metal diffusion barrier layer, and a portion of the metal diffusion barrier layer is exposed from the structured copper layer, i.e., from a portion of the copper layer formed on the region of the metal diffusion barrier layer. For example, the copper layer can be deposited by electroplating. In one embodiment, a seed layer is deposited onto the metal diffusion barrier layer, for example by sputtering, a structured mask having one or more openings is deposited onto the seed layer, exposing the seed layer to the substrate at one or more openings, and a copper layer is deposited onto the seed layer and into one or more openings of the mask by electroplating. The seed layer can be formed of copper.

[0053] In block 103, a portion of the metal diffusion barrier layer exposed from the structured copper layer is removed by plasma etching. For example, SF6 and N2 can be used for plasma etching. This forms one or more conductive structures comprising the metal diffusion barrier layer and the copper layer. The conductive structures can provide contact pads or redistributed interconnects. For example, contact pads can be source contact pads, drain contact pads, gate contact pads, anode pads, cathode pads, input / output pads, auxiliary pads such as source sensing pads, current sensing pads, or Kelvin pads or pull-down gate pads. Redistributed interconnects can extend between two semiconductor devices or to contact pads or provide gate channels.

[0054] Figure 3 includes Figures 3A to 3G The diagram illustrates a method for fabricating a conductive structure in the form of contact pads 15 electrically connected to the drain electrode 33 of a lateral group III nitride transistor device 30, particularly a group III nitride HEMT. However, this method can be used to fabricate other types of conductive structures, such as other types of contact pads and interconnects, and is not limited to use with group III nitride-based devices, but can be used for devices formed from other semiconductor materials such as silicon or silicon carbide. In Figure 3, a metallization structure 14 located on the first main surface 13 of the semiconductor substrate 12 is shown having a number of electrically insulating and conductive layers. However, the metallization structure 14 is not limited to the structure shown and can be used for metallization structures having fewer or more conductive and electrically insulating layers than shown. This method can be used for the topmost layer of the conductive layer in the metallization structure of a semiconductor device. The topmost conductive layer can be referred to as a power metal.

[0055] Figure 3 illustrates the fabrication of the conductive structure 15 in the uppermost conductive layer of the metallization structure 14 located on the first main surface 13 of the semiconductor substrate 12. In this embodiment, the partially fabricated metallization structure 14 has been established on the first main surface 13 of the semiconductor device 30 and includes first, second, and third electrically insulating layers 35, 36, and 37, as shown in the reference. Figure 1 The first conductive layer is formed on the source electrode 31, gate electrode 32, and drain electrode 33. The second conductive layer includes a first redistribution portion 41 located in the second electrically insulating layer 36, extending through the first electrically insulating layer 35 to the source electrode 31, and a second redistribution structure 42 located in the second electrically insulating layer 36, extending through the first electrically insulating layer 35 to the drain electrode 32. In this embodiment, the uppermost surface of the partially fabricated metallization layer 14 is provided by an upper nitride layer 37-3.

[0056] refer to Figure 3AThis method is performed by forming a metal diffusion barrier layer 16 on the upper nitride sublayer 37-3. In some embodiments, a seed layer 63, such as a thin copper layer, is deposited on the diffusion metal diffusion barrier layer 16. The seed layer 63 can be used if a copper layer 17 is to be deposited by electroplating. The seed layer 63 serves as an electrode in the electrolytic cell.

[0057] In some embodiments, an opening 44 is formed through the third electrical insulating layer 37, exposing a portion of the second redistribution portion 42. A metal diffusion layer 16 and a seed layer 63 are then deposited such that the seed layer 63 and the metal diffusion barrier layer are formed on the substrate of the opening 44, which is in direct contact with the second redistribution portion 42. Alternatively, an opening 44 is formed extending through the copper seed layer 63, the metal diffusion barrier layer 16, and the third electrical insulating layer 37, such that at least a portion of the second redistribution portion 42 is exposed at the substrate of the opening 44.

[0058] The copper seed layer 63 can be deposited, for example, by sputtering, and can have a thickness of a few nanometers. For example, the metal diffusion barrier layer 16 can have a thickness of about 20 nm to 2 μm, such as about 300 nm.

[0059] refer to Figure 3B A mask 60 is formed on the copper seed layer 63, the mask 60 having at least one opening 61 that exposes the copper seed layer 63 and the via 44. The opening 61 defines the location and lateral dimensions of the conductive structure (e.g., contact pad 15) to be formed in the uppermost conductive layer of the metallized structure 14. For example, the mask 60 may be formed of a photoresist and structured by photolithography.

[0060] refer to Figure 3C Copper 62 is deposited into the opening 61 of the via 44 to form a conductive via 43 between the contact pad 15 and the contact 42, thereby providing a conductive redistribution structure for the drain electrode 33. In some embodiments, copper 62 is deposited by electroplating onto a region of the copper seed layer 63 exposed in the opening 61. The copper seed layer 63 extends under the mask 60 over the entire area of ​​the semiconductor device 10 and thus serves to provide electrodes for the electrolytic cell used in the electroplating process.

[0061] refer to Figure 3D Then, mask 60 is removed. At this stage, copper layer 17 may have the final or near-final dimensions of its contact pads 15 and lies on copper seed layer 63 extending over the entire surface of metallized structure 14. The area of ​​copper seed layer 63 covered by mask 61 is now exposed from copper layer 17 and is not covered by copper layer 17. Metal diffusion barrier layer 16 also extends over the entire surface of metallized structure 14.

[0062] refer to Figure 3EAn enlarged view of the side 24 of the contact pad 15 is shown, and then the exposed area of ​​the copper seed layer 63 covered by the mask 61 is removed, for example, by wet etching. The wet etching selectively removes the copper seed layer 63 above the material of the metal diffusion barrier layer 16. The seed layer 63 remains below the copper layer 17 and forms part of the contact pad 15. Examples of suitable wet etching include H2O2 (8.0%). The area exposing the metal diffusion barrier layer 16, which is also located below the mask 61 and laterally adjacent to the contact pad 15, is then removed by plasma etching, such as... Figure 3E As schematically shown by arrow 64. The plasma etching process can also remove the uppermost portion of the nitride layer 37-3. A portion of the nitride layer 37-3 remains, covering the underlying oxide layer 37-2. After plasma etching, the lateral extents of the metal diffusion barrier layer 16 and the copper layer 17 of the contact pad 15 are substantially the same. Plasma etching conditions utilizing SF6 and N2 gases can be used. For example, the contact pad 15 can have a thickness of 50 nm to 20 µm, or 50 nm to 10 µm, or 50 nm to 7 µm.

[0063] During plasma etching of the exposed areas of the metal diffusion barrier layer 16, portions of the structured electroplated copper layer 17 act as a mask. Removing the exposed areas of the metal diffusion barrier layer 16 using plasma etching allows the sidewalls 21 of the covered or masked portions of the metal diffusion barrier layer 16 remaining beneath the copper layer 17 to have a substantially vertical shape that is substantially perpendicular to both the upper surface 20 and the lower surface 23 of the metal diffusion barrier layer 16, as can be seen more clearly in the enlarged view. Since the sidewalls 21 may not be perfectly perpendicular to the upper surface 20 and the lower surface 23 of the metal diffusion barrier layer 16, variations relative to a precise vertical line are included, such that the linear distance d between the upper edge 19 and the lower edge 22 is at most 10% or at most 5% greater than the thickness t of the metal diffusion barrier layer 16, i.e., t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t.

[0064] Figure 3F An optional process is shown, in which an additional wet etching process is performed. In this optional process, such as... Figure 3F As schematically indicated, the upper surface 25 and side surface 24 of the copper layer 17 of the contact pad 15 are etched. Selective wet etching can be used. As can be more easily seen in the enlarged view, the copper is selectively removed by wet etching, such that the peripheral edge portion of the metal diffusion barrier layer 16 is exposed and laterally protrudes beyond the maximum lateral extent of the copper layer 17. After an optional further wet etching process, the lateral extent of the metal diffusion barrier layer of the contact pad 15 is greater than the lateral extent of the copper layer 17 of the contact pad 15.

[0065] The lowermost surface of copper layer 17 may be laterally larger than the upper surface 25. The side surface 21 of the metal diffusion barrier layer 16 extends laterally beyond the maximum lateral extent of copper layer 17 contacting pad 15. The transition between the thicker and thinner portions of the uppermost nitride layer 37-3 is now also laterally located beyond the maximum lateral extent of copper layer 17 and is substantially coplanar with the side surface 24 of metal diffusion barrier layer 16. Depending on the etching conditions, additional etching processes may provide a concave transition between the protruding peripheral edge portions of copper layer 17 and metal diffusion barrier layer 16, resulting in a smaller angle formed at the interface between copper layer 17 and metal diffusion barrier layer 16. The angle α formed between the center of side surface 24 of copper layer 17 and metal diffusion barrier layer 16 may be greater than 90°, for example, 105°.

[0066] Reference Figure 3G A dielectric layer 26 is then deposited over at least the side surface 24 and the upper surface 13 of the semiconductor substrate 12, such that the protruding portions of the metal diffusion barrier layer 16 not covered by the copper layer 17 are covered by the dielectric layer 26. The dielectric layer 26 may cover the entire metallized structure 14, except for those areas of one or more copper structures 15 that provide external contacts 27, such as solder contacts, bonding wires, metal strips, or clips. In some embodiments, the dielectric layer 26 comprises two or more sublayers, such as three sublayers, such as silicon nitride, silicon oxide, or a silicon nitride stack.

[0067] Typically, two or more conductive structures 15 are formed. These conductive structures 15 may be physically separated from each other and electrically isolated from each other, such as source pads, drain pads, and gate pads of a transistor device. In some embodiments, the two or more conductive structures may be integral, such as a gate pad and an interconnect.

[0068] Although the accompanying drawings show a conductive structure in the form of a drain contact pad 15, the semiconductor device 10 also includes at least one additional structure, such as at least one source contact pad and at least one gate contact pad, and optionally one or more auxiliary pads and one or more interconnects, which can be fabricated using the same process steps as those for the drain contact pad 15 shown in the drawings. The source contact pad, gate contact pad, and any additional auxiliary pads may have… Figure 1 It has the same structure as the contact pad 15 shown in Figure 3, which has a copper layer 17 and a metal diffusion barrier layer 16.

[0069] The passivation integrity of the dielectric layer 26 deposited on the contact pads 15, along with its plasma-etched metal diffusion barrier layer 16 and copper layer 17, is improved, even under harsh environmental conditions. Due to the shape of the copper layer and the fact that the exposed peripheral region of the metal diffusion layer 16 has its substantially vertical sides, the upper dielectric layer 26 can be deposited uniformly, continuously, and uninterruptedly onto the conductive structure 15. This contributes to improved integrity of the dielectric layer 26 throughout the operational lifetime of the semiconductor device 30 when thermomechanical stress is applied to the passivation structure including the dielectric layer 26. The improved integrity of the dielectric layer 26 can help provide protection against mobile ions, such as chloride ions, which can leak from the environment and / or from molding compounds used to provide the housing of the package in which the semiconductor device 10 is mounted. Therefore, the electrical isolation between the contact pads 15 of the semiconductor device 10 and each other is improved, such as the source and drain contact pads of a transistor device 10, which are typically connected to ground potential and high potentials, such as 650V in the case of some group III nitride-based HEMTs.

[0070] While this disclosure is not limited thereto, the examples numbered below illustrate one or more aspects of this disclosure.

[0071] Example 1. A semiconductor device, comprising: The semiconductor substrate includes the first main surface; A metallized structure located on the first main surface, wherein the metallized structure includes one or more conductive structures. The conductive structure includes a metal diffusion barrier layer and a copper layer located on the metal diffusion barrier layer. The metal diffusion barrier layer has a thickness t and a side surface, the side surface extending between an upper edge formed between the upper surface and the side surface and a lower edge formed between the lower surface and the side surface, wherein the linear distance d between the upper edge and the lower edge is t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t.

[0072] 2. The semiconductor device according to Example 1, wherein the side extends substantially perpendicular to the first main surface.

[0073] 3. The semiconductor device according to Example 1 or Example 2, wherein the metal diffusion barrier layer has an upper surface and an opposing lower surface, and the side surfaces extend substantially perpendicular to the upper and lower surfaces of the diffusion barrier layer.

[0074] 4. The semiconductor device according to any one of Examples 1 to 3, wherein the metal diffusion barrier layer has a peripheral edge portion that protrudes from the copper layer and is not covered by the copper layer.

[0075] 5. The semiconductor device according to any one of Examples 1 to 3, wherein the copper layer has an upper surface and a side surface extending from the upper surface to the metal diffusion barrier layer.

[0076] 6. The semiconductor device according to Example 5, wherein the side of the copper layer forms an angle greater than 90° with the upper surface of the metal barrier layer.

[0077] 7. The semiconductor device according to any one of Examples 1 to 6, wherein the transition between the side of the copper layer and the metal barrier layer has a concave shape.

[0078] 8. The semiconductor device according to any one of Examples 1 to 7, wherein the metal diffusion barrier layer comprises one of the group consisting of WTi, Ti / TiN and TaN / Ta.

[0079] 9. The semiconductor device according to any one of Examples 1 to 8 further includes an outer peripheral edge portion disposed on the upper surface of the copper layer and an upper dielectric layer disposed on the side surface of the copper layer.

[0080] 10. The semiconductor device according to Example 9, wherein the upper dielectric layer comprises two or more sublayers.

[0081] 11. The semiconductor device according to Example 10, wherein the upper dielectric layer comprises: a first sublayer comprising a nitride, a second sublayer comprising an oxide on the first sublayer, and a third sublayer comprising a nitride on the second sublayer.

[0082] 12. The semiconductor device according to any one of Examples 1 to 11, wherein the one or more conductive structures comprise at least one of the group consisting of contact pads and redistribution interconnects.

[0083] 13. The semiconductor device according to Example 12, wherein the contact pads are source contact pads, drain contact pads, gate contact pads, anode pads, cathode pads, input / output pads, auxiliary pads such as source sensing pads, current sensing pads, or Kelvin pads or pull-down gate pads, and / or wherein redistribution interconnects extend between or to the contact pads of the two semiconductor devices.

[0084] 14. The semiconductor device according to any one of Examples 1 to 13, wherein the substrate comprises a semiconductor device structure.

[0085] 15. The semiconductor device according to Example 14, wherein the semiconductor device structure is a transistor device structure or a diode structure, or a logic device, or a gate driver or a bootstrap switch (diode).

[0086] 16. The semiconductor device according to any one of Examples 1 to 15, wherein the semiconductor substrate comprises Si or SiC or comprises one or more Group III nitrides.

[0087] 17. The semiconductor device according to any one of Examples 1 to 16, wherein the metallization structure further comprises one or more additional conductive layers and one or more dielectric layers, and the one or more conductive structures are located in the uppermost additional conductive layer.

[0088] 18. A method for manufacturing a conductive structure with a metallized structure, the method comprising: A metal diffusion barrier layer is formed on the first main surface of the semiconductor substrate; A structured copper layer is formed on a metal diffusion barrier layer, wherein a portion of the metal diffusion barrier layer is exposed from the structured copper layer; The exposed portion of the metal barrier layer is removed by plasma etching, and One or more conductive structures are formed, including a metal diffusion barrier layer and a copper layer.

[0089] 19. The method according to Example 18 further includes: A copper seed layer is deposited on the metal diffusion barrier layer, and then... A copper layer is deposited onto a copper seed layer through electroplating.

[0090] 20. The method according to Example 18 or Example 19, wherein depositing a copper layer by electroplating comprises: A mask is formed on a copper seed layer, the mask including at least one opening that exposes the copper seed layer; A copper layer is deposited onto at least one opening and an exposed copper seed layer by electroplating.

[0091] 21. The method according to any one of Examples 18 to 20, further comprising: After forming the structured copper layer, the portion of the copper seed layer exposed from the structured copper layer is removed by wet etching. The exposed metal barrier layer is removed by plasma etching.

[0092] 22. The method according to any one of Examples 18 to 21 further includes: Perform an additional etching process to remove a portion of the upper surface and sides of the conductive structure, as well as the outer edge region of the metal diffusion barrier layer exposed from the copper layer of the conductive structure.

[0093] 23. The method according to Example 22, wherein after a further etching process, the side of the copper layer of the conductive structure forms an angle greater than 90° with the upper surface of the metal barrier layer.

[0094] 24. The method according to Example 22 or Example 23, wherein, after an additional etching process, the transition between the copper layer and the metal barrier layer of the conductive structure has a concave shape.

[0095] 25. The method according to any one of Examples 18 to 24, wherein the metallized structure further comprises one or more additional conductive layers and one or more dielectric layers, and the one or more conductive structures are located in the uppermost additional conductive layer.

[0096] 26. The method according to any one of Examples 18 to 25, wherein after plasma etching, the metal diffusion barrier layer has a thickness t and a side surface extending between an upper edge formed between the upper surface and the side surface and a lower edge formed between the lower surface and the side surface, wherein the linear distance d between the upper edge and the lower edge is t ≤ d ≤ 1.1t or t ≤ d ≤ 1.05t.

[0097] 27. The method according to Example 26, wherein the side of the metal diffusion barrier layer is substantially perpendicular to the first main surface.

[0098] 28. The method according to any one of Examples 22 to 27, wherein the metal diffusion barrier layer has a peripheral edge portion that protrudes from the copper layer and is not covered by the copper layer.

[0099] 29. The method according to any one of Examples 18 to 28, wherein after plasma etching, the copper layer has an upper surface and a side surface extending from the upper surface to the metal diffusion barrier layer.

[0100] 30. The method according to any one of Examples 18 to 29 further includes forming an upper dielectric layer over the peripheral edge portion of the upper surface of the copper layer and over the side surface of the copper layer.

[0101] 31. The method according to Example 30, wherein the upper dielectric layer comprises two or more sublayers.

[0102] 32. The method according to Example 30 or Example 31, wherein forming the upper dielectric layer includes forming a first sublayer comprising a nitride, forming a second sublayer comprising an oxide on the first sublayer, and forming a third sublayer comprising a nitride on the second sublayer.

[0103] 33. The method according to any one of Examples 18 to 32, wherein the metal diffusion barrier layer comprises one of the group consisting of WTi, Ti / TiN and TaN / Ta.

[0104] 34. The method according to any one of Examples 18 to 33, wherein the one or more conductive structures comprise at least one of the group consisting of contact pads and redistribution interconnects.

[0105] 35. The method according to Example 34, wherein the contact pad is a source contact pad, a drain contact pad, a gate contact pad, an anode pad, a cathode pad, an input / output pad, or an auxiliary pad, such as a source sensing pad, a current sensing pad, or a Kelvin pad.

[0106] 36. The method according to any one of Examples 18 to 35, wherein the substrate comprises a semiconductor device structure.

[0107] 37. The method according to Example 36, wherein the semiconductor device structure is a transistor device structure or a diode structure, or a logic device, or a gate driver.

[0108] For ease of description, spatially relative terms such as "below," "below," "down," "above," and "upper" are used to explain the positioning of one element relative to another. These terms are intended to encompass different orientations of the device, in addition to orientations different from those depicted in the figures. Furthermore, terms such as "first" and "second" are also used to describe various elements, regions, segments, etc., and are not intended to be limiting. Throughout the description, similar terms refer to similar elements.

[0109] As used herein, the terms “having,” “comprising,” “including,” “including,” etc., are open-ended terms that indicate the presence of the stated element or feature but do not exclude additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular unless the context clearly indicates otherwise. It should be understood that, unless otherwise specifically indicated, features of the various embodiments described herein can be combined with each other.

[0110] Although specific embodiments have been shown and described herein, those skilled in the art will understand that various alternatives and / or equivalent implementations may be used instead of the shown and described specific embodiments without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

Claims

1. A semiconductor device, comprising: The semiconductor substrate includes the first main surface; A metallized structure located on the first main surface, wherein the metallized structure includes one or more conductive structures. One or more of the conductive structures include a metal diffusion barrier layer and a copper layer located on the metal diffusion barrier layer. The metal diffusion barrier layer has a thickness t and a side surface, the side surface extending between an upper edge formed between the upper surface and the side surface and a lower edge formed between the lower surface and the side surface, wherein the linear distance d between the upper edge and the lower edge is t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t.

2. The semiconductor device of claim 1, wherein the metal diffusion barrier layer has a peripheral edge portion that protrudes from the copper layer and is not covered by the copper layer.

3. The semiconductor device according to claim 1 or claim 2, wherein, The one or more conductive structures include at least one of the group consisting of contact pads and redistributed interconnects.

4. The semiconductor device according to any one of claims 1 to 3, wherein, The semiconductor substrate includes at least one semiconductor device structure, which includes a transistor device structure or a diode structure, or a logic device, or a gate driver or a bootstrap switch.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The semiconductor substrate comprises Si or SiC or one or more group III nitrides.

6. A method for manufacturing a conductive structure with a metallized structure, the method comprising: A metal diffusion barrier layer is formed on the first main surface of the semiconductor substrate; A structured copper layer is formed on a metal diffusion barrier layer, wherein a portion of the metal diffusion barrier layer is exposed from the structured copper layer; The exposed portion of the metal diffusion barrier layer is removed by plasma etching, and One or more conductive structures are formed, including a metal diffusion barrier layer and a copper layer.

7. The method according to claim 6, further comprising: A copper seed layer is deposited on the metal diffusion barrier layer, and then... A copper layer is deposited onto a copper seed layer through electroplating.

8. The method of claim 7, wherein the copper layer is deposited by electroplating comprises: A mask is formed on a copper seed layer, the mask including at least one opening that exposes the copper seed layer; A copper layer is deposited onto at least one opening and an exposed copper seed layer by electroplating.

9. The method according to any one of claims 6 to 8, further comprising: After forming the structured copper layer, the portion of the copper seed layer exposed from the structured copper layer is removed by wet etching. The exposed metal diffusion barrier layer is removed by plasma etching.

10. The method according to any one of claims 6 to 9, further comprising: Perform an additional etching process to remove a portion of the upper surface and sides of the conductive structure, as well as the outer edge region of the metal diffusion barrier layer exposed from the copper layer of the conductive structure.

11. The method of claim 10, wherein after the additional etching process, the side surface of the copper layer of the conductive structure forms an angle greater than 90° with the upper surface of the metal barrier layer.

12. The method according to any one of claims 6 to 11, wherein after plasma etching, the metal diffusion barrier layer has a thickness t and a side surface extending between an upper edge formed between the upper surface and the side surface and a lower edge formed between the lower surface and the side surface, wherein the linear distance d between the upper edge and the lower edge is t ≤ d ≤ 1.1t or t ≤ d ≤ 1.05t.

13. The method according to any one of claims 6 to 12, wherein, After plasma etching, the copper layer has an upper surface and a side extending from the upper surface to the metal diffusion barrier layer.

14. The method according to any one of claims 6 to 13, further comprising forming an upper dielectric layer disposed over a peripheral edge portion of the upper surface of the copper layer of the one or more conductive structures and over the side surface of the copper layer.

15. The method of claim 14, wherein forming the upper dielectric layer comprises forming: a first sublayer comprising a nitride, forming a second sublayer comprising an oxide on the first sublayer, and forming a third sublayer comprising a nitride on the second sublayer.

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