Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a semiconductor substrate having an active region and an isolation region, a gate structure disposed on the active region, a drain electrode and a source electrode, wherein the drain electrode and the source electrode are located on two sides of the gate structure. The semiconductor device includes a dielectric layer, a gate connection pad, a gate plug, and a first field plate. The dielectric layer covers the semiconductor substrate, the gate structure, the drain electrode and the source electrode. The gate connection pad is disposed on the dielectric layer and overlaps the gate structure in a vertical projection. The gate plug is disposed in the dielectric layer and on the active region of the semiconductor substrate to electrically connect the gate connection pad and the gate structure. The first field plate is disposed on the dielectric layer and in the same layer as the gate connection pad and is spaced apart from the gate connection pad, wherein the material of the gate connection pad is the same as the material of the first field plate. Since the first field plate and the gate connection pad are defined by the same patterning process, the use of the number of masks and the process steps can be simplified.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Power semiconductor devices continue to evolve and are widely used in fields such as wireless communication, electronic products, and electric vehicles. However, devices capable of handling high power require high breakdown voltage, and even better devices need high electron mobility and excellent thermal stability. Therefore, a new semiconductor device and its fabrication method are needed to continue the development of this field. Summary of the Invention

[0003] Some embodiments of the present invention provide a semiconductor device comprising a semiconductor substrate, a gate structure, a drain electrode, and a source electrode. The semiconductor substrate includes an active region and an isolation region located on one side of the active region. The gate structure, drain electrode, and source electrode are disposed on the active region of the semiconductor substrate, with the drain electrode and source electrode located on opposite sides of the gate structure. The semiconductor device further includes a dielectric layer covering the semiconductor substrate, the gate structure, the drain electrode, and the source electrode. The semiconductor device further includes gate connection pads and a plurality of gate plugs. The gate connection pads are disposed on the dielectric layer and overlap the gate structure in a vertical projection. The gate plugs are disposed in the dielectric layer and located on the active region of the semiconductor substrate, electrically connecting the gate connection pads and the gate structure. The semiconductor device further includes a first field plate, which is disposed on the dielectric layer, co-layered with, and spaced apart from the gate connection pads. The material of the gate connection pads is the same as the material of the first field plate.

[0004] Other embodiments of the present invention provide a method for fabricating a semiconductor device, comprising: defining an active region and an isolation region located on one side of the active region in a semiconductor substrate; forming a gate structure on the active region of the semiconductor substrate; forming a drain electrode and a source electrode on the active region of the semiconductor substrate and located on both sides of the gate structure; forming a dielectric layer covering the semiconductor substrate, the gate structure, the drain electrode, and the source electrode; forming a plurality of gate plugs in the dielectric layer and the gate plugs being connected to the gate structure; depositing a metal layer on the dielectric layer; and patterning a metal layer to form spaced-apart gate connection pads and a first field plate, wherein the gate connection pads are connected to the gate plugs in the active region.

[0005] In some embodiments of the semiconductor device of the present invention, the first field plate and the gate connection pad are defined using the same patterning process, thereby simplifying the number of masks used and simplifying the process steps. The height of the first field plate differs from the height of the second field plate, thereby allowing for the control of the electric field of the semiconductor device. In addition, the gate structure and the gate connection pad are connected by gate plugs in the active region, which can significantly reduce the gate resistance, thereby reducing switching losses and increasing the switching frequency when the gate control element is switched. Attached Figure Description

[0006] To make the objectives, features, advantages, and embodiments of the present invention more apparent and understandable, the accompanying drawings are described in detail below:

[0007] Figure 1 These are perspective views of some embodiments of the semiconductor device of the present invention.

[0008] Figures 2 to 5 Cross-sectional views of some embodiments of the method for manufacturing a semiconductor device according to the present invention are shown at different manufacturing stages.

[0009] Figure 6 This is a cross-sectional view of some other embodiments of the semiconductor device of the present invention. Detailed Implementation

[0010] Reference Figure 1 The figure shows a perspective view of some embodiments of the semiconductor device of the present invention. The semiconductor device 100 includes a semiconductor substrate 110, which defines an active region A1 and isolation regions A2 located on both sides of the active region A1 (only one side is shown in the figure). The channel layer in the active region A1 is not destroyed, while the channel layer in the isolation region A2 is destroyed by ion bombardment. The semiconductor device 100 includes a gate structure 120, a drain electrode 130, and a source electrode 140 disposed on the active region A1, wherein the gate structure 120, the drain electrode 130, and the source electrode 140 are arranged substantially parallel to each other, and the drain electrode 130 and the source electrode 140 are disposed on both sides of the gate structure 120.

[0011] Semiconductor device 100 includes a gate bus 150 disposed on an isolation region A2 and a gate connection pad 152 connected to the gate bus 150 and extending into an active region A1, wherein the extending direction of the gate bus 150 is perpendicular to the extending direction of the gate connection pad 152. The gate connection pad 152 overlaps the gate structure 120 in a vertical projection. Semiconductor device 100 also includes a plurality of gate plugs 154 disposed on the active region A1 and electrically connecting the gate connection pad 152 and the gate structure 120.

[0012] The semiconductor device 100 further includes a drain bus (not shown) and a source bus (not shown) disposed on an isolation region A2 on the other side, a drain connection pad 162 connected to the drain bus and extending into the active region A1, and a source connection pad 172 connected to the source bus and extending into the active region A1. The extending directions of the drain connection pad 162 and the source connection pad 172 are parallel to the extending direction of the gate connection pad 152. The semiconductor device 100 also includes a plurality of drain plugs 164 and source plugs 174, which are disposed on the active region A1 to electrically connect the drain connection pad 162 to the drain electrode 130 and the source connection pad 172 to the source electrode 140, respectively.

[0013] Semiconductor device 100 includes a first field plate FP1 disposed on active region A1 and located between gate connection pad 152 and drain connection pad 162. The first field plate FP1 is on the same layer as the gate connection pad 152 and the drain connection pad 162, and the first field plate FP1 is not physically connected to any of the gate bus 150, gate connection pad 152, drain connection pad 162 or source connection pad 172.

[0014] Semiconductor device 100 includes a second field plate FP2 disposed on the active region A1 and located between the gate structure 120 and the drain electrode 130, with the height of the second field plate FP2 between the gate structure 120 and the first field plate FP1. In some embodiments, the first field plate FP1 and the second field plate FP2 are not physically connected in the same layer. In some embodiments, depending on different voltage requirements, the second field plate FP2 may be omitted or a multi-layer field plate design may be used to control the electric field.

[0015] Reference Figures 2 to 5 The diagrams depict cross-sectional views of various embodiments of the method for fabricating a semiconductor device according to the present invention at different fabrication stages. The cross-sectional positions can be referenced. Figure 1 Line segment AA in the diagram. For example... Figure 2 As shown, a method for fabricating a semiconductor device includes forming a channel layer 112 on a semiconductor substrate 110 and forming a barrier layer 114 on the channel layer 112. The semiconductor substrate 110 may be a silicon substrate or a silicon carbide substrate, etc., and may contain semiconductor elements, compounds and / or alloys.

[0016] Channel layer 112 provides a channel for carrier flow between the source and drain. Barrier layer 114 helps to form a two-dimensional electron gas (2DEG) layer with high concentration, high electron mobility, and low resistance in channel layer 112 as a carrier flow channel. In some embodiments, the material of channel layer 112 comprises epitaxial gallium nitride. In some embodiments, the material of barrier layer 114 comprises AlGaN, GaN, AlN, InAlGaN, InGaN, etc.

[0017] A gate structure 120 is formed on the barrier layer 114 to control carrier flow in the channel layer 112. In some embodiments, the gate structure 120 includes a patterned doped layer 122 and a gate metal layer 124 on the doped layer 122. For example, in some embodiments, the doped layer 122 includes GaN doped with a p-type dopant. The material of the gate metal layer 124 may include a suitable metallic material, such as titanium nitride, etc.

[0018] Next, a continuously extending first dielectric layer 181 is conformally formed on the barrier layer 114 and the gate structure 120. The first dielectric layer 181 and the barrier layer 114 are in direct contact with the gate structure 120. In some embodiments, the first dielectric layer 181 covers the barrier layer 114 and continuously covers the upper surface and side surface of the gate structure 120.

[0019] Next, as Figure 3 As shown, drain electrode 130 and source electrode 140 are formed on both sides of gate structure 120. The material of drain electrode 130 and source electrode 140 is ohmic contact metal, which can be selected in conjunction with the corresponding barrier layer 114. In some embodiments, the material of the ohmic contact metal of drain electrode 130 and source electrode 140 may include titanium, aluminum, aluminum silicide, copper-aluminum alloy, titanium nitride, nickel, platinum, gold, etc. Drain electrode 130 and source electrode 140 contact the barrier layer 114 through the first dielectric layer 181.

[0020] Next, as Figure 4 As shown, the second dielectric layer 182 covers the drain electrode 130, the source electrode 140, and the first dielectric layer 181. In some embodiments, the materials of the first dielectric layer 181 and the second dielectric layer 182 include SiO2, Si3N4, SiON, or combinations thereof. After the second dielectric layer 182 is formed, a patterned photoresist can be used to cover the semiconductor substrate 110 as the active region A1 (see...). Figure 1 This part will be used as quarantine zone A2 (see) Figure 1 The active region A1 and the isolation region A2 are defined by partially exposing the active region A1 and partially exposing the isolation region A2 by plasma bombardment, which destroys the channel layer 112 in the isolation region A2. Then the patterned photoresist is removed.

[0021] The second field plate FP2 is then formed on the second dielectric layer 182. The step of forming the second field plate FP2 includes depositing a conductor layer on the second dielectric layer 182, followed by patterning the conductor layer. In some embodiments, the material of the second field plate FP2 may be titanium nitride. In some embodiments, depending on different voltage requirements, the second field plate FP2 may be omitted or a multilayer field plate design may be used to control the electric field.

[0022] Next, as Figure 5 As shown, a third dielectric layer 183 is deposited on the second dielectric layer 182, and a planarization process is performed to provide a flat upper surface for the third dielectric layer 183. The first dielectric layer 181, the second dielectric layer 182, and the third dielectric layer 183 can be collectively referred to as dielectric layer 180. Next, dielectric layer 180 is etched to define a plurality of openings OP, and a metal material, such as tungsten, is deposited to fill the openings OP, thereby forming a plurality of gate plugs 154 connected to the gate structure 120, a plurality of drain plugs 164 connected to the drain electrode 130, and a plurality of source plugs 174 connected to the source electrode 140.

[0023] After the gate plug 154, drain plug 164, and source plug 174 are formed on the active region A1, a metal layer M1 is deposited on the dielectric layer 180 and patterned to obtain the gate bus 150 (see...). Figure 1 The metal layer M1 is connected to gate pad 152, drain bus (not shown) and drain pad 162, source bus (not shown) and source pad 172, and a first field plate FP1. In some embodiments, the metal layer M1 is made of a low-resistance metal material, such as AlCu.

[0024] The height H1 between the first field plate FP1 and the semiconductor substrate 110 is greater than the height H2 between the second field plate FP2 and the semiconductor substrate 110, thereby allowing for the control of the gate-source charge (Q). gs and the amount of charge between the gate and drain (Q) gd The ratio of the first field plate FP1 to the gate connection pad 152, drain connection pad 162 and source connection pad 172 is defined by the same patterning process, which simplifies the use of mask quantity and process steps.

[0025] Simultaneously refer to Figure 1 and Figure 5In some embodiments, the gate plug 154, drain plug 164, and source plug 174 are disposed only in the active region A1 and not in the isolation region A2. In some embodiments, optionally, the first field plate FP1 and the second field plate FP2 may be further connected by a conductive plug 190 disposed in the isolation region A2.

[0026] Reference Figure 6 This is a cross-sectional view of some other embodiments of the semiconductor device of the present invention, the cross-sectional position of which can be referred to Figure 1 Line segment AA in the diagram. In some embodiments, as shown in semiconductor device 100A, gate structure 120A may further include gate electrode layer 126 disposed on gate metal layer 124 to reduce the resistance value of gate structure 120A. Gate electrode layer 126 may be a single layer or multiple layers of conductive material. In some embodiments, gate electrode layer 126 may include titanium nitride, titanium, AlCu, or combinations thereof.

[0027] In some embodiments, the gate electrode layer 126 may have a shape that is wider at the top and narrower at the bottom, such that the width W1 of the upper surface of the gate electrode layer 126 is greater than the width W2 of the gate metal layer 124, so as to further increase the contact area between the gate plug 154 and the gate structure 120A, thereby reducing the contact resistance between the gate plug 154 and the gate structure 120A.

[0028] In an embodiment such as semiconductor device 100A, the horizontal plane P2 where the gate electrode layer 126 is located is higher than the horizontal plane P1 where the drain electrode 130 and the source electrode 140 are located, the horizontal plane P3 where the second field plate FP2 is located is different from the horizontal plane P2 where the gate electrode layer 126 is located, and the horizontal plane P4 where the first field plate FP1, gate connection pad 152, drain connection pad 162 and source connection pad 172 are located is higher than the horizontal plane P3 where the second field plate FP2 is located and the horizontal plane P2 where the gate electrode layer 126 is located.

[0029] In summary, in some embodiments of the semiconductor device of the present invention, the first field plate and the gate connection pad are defined using the same patterning process, thereby simplifying the number of masks used and simplifying the process steps. The height of the first field plate differs from the height of the second field plate, thereby allowing for the control of the electric field of the semiconductor device. Furthermore, the gate structure and the gate connection pad are connected in the active region using gate plugs, which significantly reduces the gate resistance, thereby reducing switching losses and increasing the switching frequency when the gate control element is switched.

[0030] [Symbol Explanation]

[0031] 100, 100A: Semiconductor device

[0032] 110: Semiconductor substrate

[0033] 112: Channel Layer

[0034] 114: Barrier Layer

[0035] 120,120A: Gate structure

[0036] 122: Doped layer

[0037] 124: Gate metal layer

[0038] 126: Gate electrode layer

[0039] 130: Drain electrode

[0040] 140: Source electrode

[0041] 150: Gate bus

[0042] 152: Gate connection pad

[0043] 154: Gate plug

[0044] 162: Drain connection pad

[0045] 164: Drain plug

[0046] 172: Source Connector Pad

[0047] 174: Source Plug

[0048] 180: Dielectric layer

[0049] 181: First dielectric layer

[0050] 182: Second dielectric layer

[0051] 183: Third dielectric layer

[0052] 190: Conductive plug

[0053] AA: Line segment

[0054] A1: Active Zone

[0055] A2: Isolation Zone

[0056] FP1: First game rebound

[0057] FP2: Second board

[0058] H1, H2: Height

[0059] M1: Metal layer

[0060] OP: Open

[0061] P1, P2, P3, P4: Horizontal plane

[0062] W1, W2: Width.

Claims

1. A semiconductor device, characterized in that, Include: A semiconductor substrate, comprising an active region and an isolation region located on one side of the active region; A gate structure is disposed on the active region of the semiconductor substrate; The drain electrode and the source electrode are disposed on the active region of the semiconductor substrate and located on both sides of the gate structure; A dielectric layer covering the semiconductor substrate, the gate structure, the drain electrode, and the source electrode; A gate connection pad is disposed on the dielectric layer and overlaps the gate structure in the vertical projection; Multiple gate plugs are disposed in the dielectric layer and located on the active region of the semiconductor substrate to electrically connect the gate connection pad and the gate structure; as well as A first field plate is disposed on the dielectric layer, on the same layer as the gate connection pad and spaced apart from the gate connection pad, wherein the material of the gate connection pad is the same as the material of the first field plate.

2. The semiconductor device according to claim 1, wherein, Also includes: A drain connection pad is disposed on the dielectric layer, on the same layer as the gate connection pad, and overlaps the drain electrode in the vertical projection, wherein the first field plate is located between the gate connection pad and the drain connection pad; as well as Multiple drain plugs are disposed in the dielectric layer and located on the active region of the semiconductor substrate to connect the drain connection pad and the drain electrode.

3. The semiconductor device according to claim 1, wherein, Also includes: A source connection pad is disposed on the dielectric layer, on the same layer as the gate connection pad, and overlaps the source electrode in the vertical projection, wherein the source connection pad is located between the first field plate and the source connection pad; as well as Multiple source plugs are disposed in the dielectric layer and located on the active region of the semiconductor substrate to connect the source connection pad and the source electrode.

4. The semiconductor device according to claim 1, wherein, Also includes: Drain connection pad, disposed on the dielectric layer; and A source connection pad is disposed on the dielectric layer, wherein the first field plate, the drain connection pad, and the source connection pad are made of the same material.

5. The semiconductor device according to claim 1, wherein, Also includes: The second field plate is disposed in the dielectric layer and located on the active region of the semiconductor substrate. The second field plate is located between the gate structure and the drain electrode, and the height of the second field plate is between the first field plate and the gate structure.

6. The semiconductor device of claim 1, wherein the gate structure comprises a doped layer, a gate metal layer on the doped layer, and a gate electrode layer on the gate metal layer.

7. The semiconductor device of claim 6, wherein the width of the upper surface of the gate electrode layer is greater than the width of the gate metal layer.

8. A method for manufacturing a semiconductor device, characterized in that, Include: An active region and an isolation region located on one side of the active region are defined in the semiconductor substrate; A gate structure is formed on the active region of the semiconductor substrate; Drain electrodes and source electrodes are formed on the active region of the semiconductor substrate and located on both sides of the gate structure; A dielectric layer is formed to cover the semiconductor substrate, the gate structure, the drain electrode, and the source electrode; A plurality of gate plugs are formed in the dielectric layer, and the plurality of gate plugs are connected to the gate structure; A metal layer is deposited on the dielectric layer; as well as The metal layer is patterned to form spaced-apart gate connection pads and a first field plate, wherein the gate connection pads are connected to the plurality of gate plugs in the active region.

9. The method of fabricating a semiconductor device according to claim 8, wherein the material of the metal layer comprises AlCu.

10. The method of manufacturing a semiconductor device according to claim 8, wherein, It also includes forming a second field plate in the dielectric layer, wherein the second field plate is located between the gate structure and the drain electrode, and the height of the second field plate is between the first field plate and the gate structure.

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