Semiconductor devices and methods for manufacturing semiconductor devices

Abstract

A semiconductor device includes a first semiconductor chip having a first pad structure and a second semiconductor chip having a second pad structure. The first pad structure and the second pad structure are bonded to each other in a first direction. The first pad structure includes a first filled conductive film and a second filled conductive film. The first filled conductive film includes a first portion overlapping the second filled conductive film in the first direction and a second portion overlapping the second filled conductive film in a second direction intersecting the first direction. A first height of the first portion in the first direction is greater than the thickness of the second portion in the second direction, and the conductivity of the second filled conductive film is greater than the conductivity of the first filled conductive film.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0176202, filed with the Korean Intellectual Property Office on December 2, 2024, and all rights arising therefrom, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices. More specifically, this disclosure relates to semiconductor devices having a bonding structure and methods for manufacturing the semiconductor device. Background Technology

[0003] To improve the integration and performance of semiconductor devices, semiconductor devices with bonding structures have been proposed. A bonding structure refers to a structure that connects an upper chip and a lower chip via a bonding method. A bonding method, for example, can refer to the way bonding pads formed on the topmost metal layer of the upper chip are connected to bonding pads formed on the topmost metal layer of the lower chip.

[0004] Meanwhile, as electronic products require miniaturization, the aspect ratio of bonding pads continues to increase. Therefore, defects such as gaps and voids in the bonding pads can lead to a decrease in yield. Summary of the Invention

[0005] This disclosure provides a semiconductor device with improved yield and performance.

[0006] This disclosure also provides a method for manufacturing semiconductor devices with improved yield and performance.

[0007] However, the aspects of this disclosure are not limited to those set forth herein. The above and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below.

[0008] According to aspects of this disclosure, a semiconductor device is provided, including a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first substrate, a first semiconductor element layer on the first substrate, a first inter-wire insulating film on the first semiconductor element layer, a first wiring structure in the first inter-wire insulating film, and a first pad structure on the first wiring structure. The second semiconductor chip includes a second substrate, a second semiconductor element layer on the second substrate, a second inter-wire insulating film on the second semiconductor element layer, a second wiring structure in the second inter-wire insulating film, and a second pad structure on the second wiring structure. The first pad structure and the second pad structure are bonded to each other in a first direction. The first pad structure includes a first filling conductive film and a second filling conductive film sequentially disposed on the first wiring structure. The first filling conductive film includes a first portion overlapping the second filling conductive film in the first direction and a second portion overlapping the second filling conductive film in a second direction intersecting the first direction. A first height of the first portion in the first direction is greater than the thickness of the second portion in the second direction, and the conductivity of the second filling conductive film is greater than the conductivity of the first filling conductive film.

[0009] According to aspects of this disclosure, a semiconductor device is provided, including a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first substrate, a first semiconductor element layer on the first substrate, a first inter-wire insulating film on the first semiconductor element layer, a first wiring structure in the first inter-wire insulating film, and a first pad structure on the first wiring structure. The second semiconductor chip includes a second substrate, a second semiconductor element layer on the second substrate, a second inter-wire insulating film on the second semiconductor element layer, a second wiring structure in the second inter-wire insulating film, and a second pad structure on the second wiring structure. The first pad structure and the second pad structure are bonded to each other. The first pad structure includes a first filling conductive film and a second filling conductive film sequentially disposed on the first wiring structure. The aspect ratio of the first pad structure is 2 to 10. The ratio of a first height from the lowermost surface of the first filling conductive film to the lowermost surface of the second filling conductive film to a second height from the lowermost surface of the second filling conductive film to the uppermost surface of the second filling conductive film is 1:4 to 3:2. The conductivity of the second filling conductive film is higher than that of the first filling conductive film.

[0010] According to an aspect of this disclosure, a semiconductor device is provided, including a first semiconductor chip and a second semiconductor chip bonded to each other. The first semiconductor chip includes a first substrate, a first semiconductor element layer on the first substrate, a first inter-wire insulating film on the first semiconductor element layer, a first wiring structure in the first inter-wire insulating film connected to the first semiconductor element layer, a first bonding insulating film on the first inter-wire insulating film, and a first pad structure penetrating the first inter-wire insulating film and connected to the first wiring structure. The second semiconductor chip includes a second substrate, a second semiconductor element layer on the second substrate, a second inter-wire insulating film on the second semiconductor element layer, a second wiring structure in the second inter-wire insulating film connected to the second semiconductor element layer, a second bonding insulating film on the second inter-wire insulating film bonded to the first bonding insulating film, and a second pad structure penetrating the second bonding insulating film, connected to the second wiring structure, and bonded to the first pad structure. In the first inter-wire insulating film and the first bonding insulating film, pad trenches extend from the bonding surface between the first semiconductor chip and the second semiconductor chip toward the first wiring structure. The first pad structure includes: a barrier conductive film extending along the contours of the side and bottom surfaces of the pad trench; a first fill conductive film filling a portion of the pad trench on the barrier conductive film; and a second fill conductive film filling another portion of the pad trench on the first fill conductive film. The gap-filling capability of a first metal element contained in the first fill conductive film is superior to the gap-filling capability of a second metal element contained in the second fill conductive film, and the conductivity of the second fill conductive film is higher than the conductivity of the first fill conductive film. Attached Figure Description

[0011] The above and other aspects and features of this disclosure will become clearer from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0012] Figure 1 This is a schematic exploded perspective view of a semiconductor device according to some embodiments.

[0013] Figure 2 It shows Figure 1 A schematic cross-sectional view of a semiconductor device.

[0014] Figure 3 It shows Figure 2 A magnified view of region R.

[0015] Figure 4 It shows Figure 3 A schematic plan view of the first pad structure.

[0016] Figures 5a to 5f It is shown that according to some embodiments Figure 2 A magnified view of the various alternative configurations for region R.

[0017] Figures 6 to 12 This is a diagram of an intermediate structure corresponding to an intermediate step in a method for manufacturing a semiconductor device, according to some embodiments. Detailed Implementation

[0018] In the following text, reference will be made to Figures 1 to 5f A semiconductor device according to an illustrative embodiment is described.

[0019] Figure 1 This is a schematic exploded perspective view used to illustrate a semiconductor device according to some embodiments. Figure 2 It is used to show Figure 1 A schematic cross-sectional view of a semiconductor device. Figure 3 It is used to show Figure 2 A magnified view of region R. Figure 4 It is used to show Figure 3 A schematic plan view of the first pad structure.

[0020] refer to Figures 1 to 4 The semiconductor device according to some embodiments includes a first semiconductor chip 100 and a second semiconductor chip 200.

[0021] The first semiconductor chip 100 and the second semiconductor chip 200 can be bonded to each other in a first direction Z. For example, the first semiconductor chip 100 and the second semiconductor chip 200 can form a bonding surface extending along a horizontal plane (e.g., an XY plane) intersecting the first direction Z. Figure 3 (BS). The first semiconductor chip 100 and the second semiconductor chip 200 can be electrically connected to each other. The first semiconductor chip 100 and the second semiconductor chip 200 can be wafer-level bonded (e.g., wafer-to-wafer bonding or chip-to-wafer bonding), or can be chip-level bonded (e.g., chip-to-chip bonding).

[0022] Each of the first semiconductor chip 100 and the second semiconductor chip 200 can be an integrated circuit (IC), in which hundreds or even millions of semiconductor elements are integrated into a single chip. Integrated circuits can be, for example, but not limited to: logic chips, such as AP (application processor), microprocessor, CPU (central processing unit), controller, ASIC (application-specific integrated circuit), analog components, and digital signal processors; and / or memory chips, such as DRAM chips, SRAM chips, MRAM chips, PRAM chips, flash memory chips, and / or HBM (high-bandwidth memory) chips.

[0023] For example, the second semiconductor chip 200 may be a memory chip including storage cells, such as DRAM or flash memory, and the first semiconductor chip 100 may be a logic chip including peripheral circuitry that controls the operation of the storage cells of the second semiconductor chip 200.

[0024] As another example, the second semiconductor chip 200 may be a sensor chip that captures an image of an object, such as a CMOS (Complementary Metal-Oxide-Semiconductor) image sensor, and the first semiconductor chip 100 may be a logic chip that reads image signals from the second semiconductor chip 200 and performs various signal processing on the read image signals.

[0025] The first semiconductor chip 100 may include a first substrate 110, a first semiconductor element layer 120, a first wiring insulating film 130, a first wiring structure 140, a first bonding insulating film 150, and a first pad structure 160.

[0026] The first substrate 110 may be, for example, bulk silicon or silicon-on-insulator (SOI). The first substrate 110 may be a silicon substrate, or may include other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the first substrate 110 may be a substrate in which an epitaxial layer is formed on a base substrate.

[0027] The first substrate 110 may include a first front side 110a and a first rear side 110b opposite to each other. The first front side 110a may be an active surface on which semiconductor elements are formed. For example, the first front side 110a may include conductive regions, such as a well doped with impurities. The first front side 110a may also include various element separation structures, such as insulating regions separating conductive regions, such as shallow trench isolation (STI).

[0028] The first semiconductor element layer 120 may be formed on the first front side 110a of the first substrate 110. The first semiconductor element layer 120 may include various types of individual devices and / or interlayer insulating films. Individual devices may include various microelectronic devices, such as, but not limited to: MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), such as CMOS transistors (Complementary Metal-Insulator-Semiconductor Transistors); system LSIs (Large-Scale Integrated Circuits); memories, such as flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, and RRAM; image sensors, such as CIS (CMOS Image Sensors); MEMS (Micro-Electro-Mechanical Systems); and / or various other active or passive components, etc.

[0029] The first inter-wiring insulating film 130 may be formed on the first semiconductor element layer 120. The first inter-wiring insulating film 130 may cover the first semiconductor element layer 120. The first inter-wiring insulating film 130 may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, silicon nitride, silicon carbon oxide, silicon boron nitride, silicon boron carbon nitride, silicon carbon nitride, a low dielectric constant material with a dielectric constant lower than silicon oxide, and / or combinations thereof. The low dielectric constant material may include, for example, at least one of FOX (flowable oxide), TOSZ (Toron silazane), USG (undoped silicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), PETEOS (plasma-enhanced tetraethyl orthosilicate), FSG (fluoride silicate glass), CDO (carbon-doped silicon oxide), degel, aerogel, amorphous fluorinated carbon, OSG (organosilicate glass), parylene, BCB (bisbenzocyclobutene), SiLK, polyimide, porous polymer materials, and combinations thereof.

[0030] The first wiring structure 140 may be formed in the first inter-wiring insulating film 130. The first wiring structure 140 is connected to the first semiconductor element layer 120 and may be electrically connected to individual devices in the first semiconductor element layer 120. The first wiring structure 140 may include a multilayer first wiring pattern 140M and a first via pattern 140V that interconnects different layers of the first wiring patterns 140M. The number, quantity, shape, and placement of the layers in the first wiring structure 140 are illustrative only and are not limited to the number, quantity, shape, and placement shown in the drawings.

[0031] In some embodiments, the first wiring structure 140 may include a first wiring barrier conductive film 142 and a first wiring fill conductive film 144 stacked sequentially. The first wiring barrier conductive film 142 may include a metal or a metal nitride to prevent the diffusion of elements included in the first wiring fill conductive film 144. The first wiring fill conductive film 144 may fill the space above the first wiring barrier conductive film 142.

[0032] The first wiring barrier conductive film 142 may include, for example, but not limited to, at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), their alloys, their nitrides, and / or combinations thereof.

[0033] The first wiring filling conductive film 144 may include, for example, but not limited to, at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), ruthenium (Ru) and / or alloys thereof.

[0034] The first bonding insulating film 150 may be formed on the first inter-wiring insulating film 130 and the first wiring structure 140. The first bonding insulating film 150 may extend along the upper surface of the first inter-wiring insulating film 130. The first bonding insulating film 150 may include, for example, but not limited to, films of silicon oxide, silicon nitride, and / or polymers. For example, the first bonding insulating film 150 may include a silicon carbon nitride film (SiCN).

[0035] The first pad structure 160 can be formed on the first inter-wiring insulating film 130 and the first wiring structure 140. The first pad structure 160 penetrates the first bonding insulating film 150 and can be connected to the first wiring structure 140.

[0036] In some embodiments, the aspect ratio of the first pad structure 160 may be from approximately 2 to approximately 10. Here, aspect ratio refers to the ratio of height in a vertical direction (e.g., a first direction Z) to width in a horizontal direction (e.g., a second direction X or a third direction Y). For example, the first pad structure 160 may have a first height H1 in the first direction Z. The first height H1 may be defined as the distance between the lowermost surface and the uppermost surface of the first pad structure 160 in the first direction Z. The first pad structure 160 may also have a first width W1 in the second direction X. The first width W1 may be defined, for example, based on the uppermost surface of the first pad structure 160. In this case, the ratio H1 / W1 of the first height H1 to the first width W1 may be from approximately 2 to approximately 10, or from approximately 3 to approximately 8, or from approximately 4 to approximately 6. The aspect ratio of the first pad structure 160 has been described as being defined based solely on the uppermost surface of the first pad structure 160, but this is merely illustrative, and the aspect ratio of the first pad structure 160 may be defined based on other portions of the first pad structure 160 (e.g., the lowermost surface).

[0037] In some embodiments, the first pad structure 160 may include a first bonding pad 160P and a first pad via 160V.

[0038] The first bonding pad 160P can form the bonding surface BS between the first semiconductor chip 100 and the second semiconductor chip 200. For example, as Figure 3 As shown, a pad trench 160Pt extending from the bonding surface BS between the first semiconductor chip 100 and the second semiconductor chip 200 toward the first wiring structure 140 can be formed in the first bonding insulating film 150 and the first inter-wiring insulating film 130. The first bonding pad 160P can fill the pad trench 160Pt.

[0039] Despite Figure 4In the diagram, the first bonding pad 160P is shown only as a square from a planar perspective, but this is merely illustrative. It goes without saying that, from a planar perspective, the shape of the first pad 160P can take various forms, such as circular, elliptical, or other polygonal shapes.

[0040] A first pad via 160V can extend from the first pad 160P and can be connected to the first wiring structure 140. For example, a via trench 160Vt can be formed in the first inter-wiring insulating film 130, extending from the lower surface of the pad trench 160Pt and connecting to the first wiring structure 140. The first pad via 160V can fill the via trench 160Vt. The first bonding pad 160P can be electrically connected to the first wiring structure 140 through the first pad via 160V.

[0041] Despite Figure 4 In the diagram, from a planar perspective, the first pad via 160V is shown only as a circle, but this is merely illustrative. It goes without saying that from a planar perspective, the shape of the first pad via 160V can take various forms, such as ellipse, square, or other polygons.

[0042] In some embodiments, such as Figure 3 As shown, the first inter-wire insulating film 130 may include a first sub-insulating film 131, a first etch stop film 132, a second sub-insulating film 133, a second etch stop film 134 and a third sub-insulating film 135 stacked in sequence.

[0043] A first wiring structure 140 may be formed in a first sub-insulating film 131. A first etch stop film 132 may extend along the upper surface of the first sub-insulating film 131 and the upper surface of the first wiring structure 140. A second sub-insulating film 133 may cover the upper surface of the first etch stop film 132. A second etch stop film 134 may extend along the upper surface of the second sub-insulating film 133. A third sub-insulating film 135 may cover the upper surface of the second etch stop film 134. A first bonding insulating film 150 may extend along the upper surface of the third sub-insulating film 135.

[0044] The first etch stop film 132 can be provided as an etch stop film in the etch process used to form the first pad via 160V. For example, the via trench 160Vt passes through the second sub-insulating film 133 and the first etch stop film 132, and can be connected to the first wiring structure 140.

[0045] In some embodiments, the width of the first pad via 160V may be reduced toward the first wiring structure 140. This may be due to the characteristics of the etching process used to form the via trench 160Vt.

[0046] The second etch stop film 134 can be provided as an etch stop film in the etch process used to form the first bonding pad 160P. For example, the pad trench 160Pt extends through the first bonding insulating film 150, the third sub-insulating film 135, and the second etch stop film 134, and can be connected to the via trench 160Vt.

[0047] In some embodiments, the width of the first bonding pad 160P may be reduced toward the first wiring structure 140. This may be due to the characteristics of the etching process used to form the pad trench 160Pt.

[0048] Each of the first sub-insulating film 131, the second sub-insulating film 133, and the third sub-insulating film 135 may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, silicon nitride, silicon carbon oxide, silicon boron nitride, silicon boron carbon nitride, silicon carbon nitride, a low dielectric constant material with a dielectric constant smaller than that of silicon oxide, and / or combinations thereof.

[0049] Each of the first etch stop film 132 and the second etch stop film 134 may include, for example, but not limited to, at least one of silicon nitride (SiN), silicon oxide nitride (SiON), silicon carbon oxide nitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxide nitride (SiOBN), silicon carbon oxide (SiOC), silicon carbon nitride (SiCN), aluminum nitride (AlN), aluminum oxide (AlO), and combinations thereof.

[0050] In some embodiments, the width of the first pad via 160V may be smaller than the width of the first bonding pad 160P. For example, based on the interface between the first pad via 160V and the first bonding pad 160P (e.g., the upper surface of the second sub-insulating film 133), the second width W2 of the first pad via 160V may be smaller than the third width W3 of the first bonding pad 160P.

[0051] The first pad structure 160 may include a first barrier conductive film 162, a first fill conductive film 164, and a second fill conductive film 166 that are sequentially stacked (e.g., disposed) in the pad trench 160Pt and the via trench 160Vt.

[0052] The first barrier conductive film 162 may extend along the side and bottom surfaces of the pad trench 160Pt and the via trench 160Vt. For example, the first barrier conductive film 162 may extend conformally along the contours of the pad trench 160Pt and the via trench 160Vt.

[0053] In some embodiments, the first barrier conductive film 162 may form the bonding surface BS between the first semiconductor chip 100 and the second semiconductor chip 200. For example, the uppermost surface of the first barrier conductive film 162 may be configured to be coplanar with the surface (e.g., the upper surface) of the first bonding insulating film 150.

[0054] The first barrier conductive film 162 may include a metal or a metal nitride to prevent the diffusion of elements included in the first filled conductive film 164 and / or the second filled conductive film 166. For example, the first barrier conductive film 162 may include, but is not limited to, at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), their alloys, their nitrides, and / or combinations thereof. For example, the first barrier conductive film 162 may include at least one of titanium nitride film (TiN) and / or tantalum nitride film (TaN).

[0055] A first filler conductive film 164 may be formed on a first barrier conductive film. The first filler conductive film 164 may be located between a first barrier conductive film 162 and a second filler conductive film 166. The first filler conductive film 164 may fill at least a portion of the area where the via trench 160Vt is left after filling the first barrier conductive film 162. For example, the first filler conductive film 164 may fill a portion (e.g., the lower part) of the pad trench 160Pt and the via trench 160Vt.

[0056] A second conductive filler film 166 may be formed on the first conductive filler film 164. The second conductive filler film 166 may fill at least a portion of the region of the via trench 160Vt and / or the region of the pad trench 160Pt, which is left after the first barrier conductive film 162 and the first conductive filler film 164 are filled. For example, the second conductive filler film 166 may fill another portion (e.g., the upper part) of the pad trench 160Pt.

[0057] In some embodiments, the first filled conductive film 164 may include a first portion 164a and a second portion 164b.

[0058] A first portion 164a of the first filled conductive film 164 may overlap with the second filled conductive film 166 in the first direction Z. For example, the first portion 164a of the first filled conductive film 164 may be disposed on the lower surface of the second filled conductive film 166. The first portion 164a of the first filled conductive film 164 may be located between the first blocking conductive film 162 and the second filled conductive film 166 in the first direction Z.

[0059] The second portion 164b of the first filled conductive film 164 may overlap with the second filled conductive film 166 in the second direction X or the third direction Y. For example, the second portion 164b of the first filled conductive film 164 may extend from the first portion 164a of the first filled conductive film 164 and surround the side surface of the second filled conductive film 166. The second portion 164b of the first filled conductive film 164 may be located between the first blocking conductive film 162 and the second filled conductive film 166 in the second direction X or the third direction Y.

[0060] In some embodiments, the thickness of the first portion 164a of the first conductive filler film 164 may be greater than the thickness of the second portion 164b of the first conductive filler film 164. For example, the first portion 164a of the first conductive filler film 164 may have a second height H2 in the first direction Z. The second height H2 may be defined, for example, as the distance between the lowermost surface of the first portion 164a in the first direction Z and the lowermost surface of the second conductive filler film 166. Furthermore, the second portion 164b of the first conductive filler film 164 may have a first thickness TH in the second direction X. In this case, the second height H2 may be greater than the first thickness TH.

[0061] In some embodiments, the first thickness TH of the second portion 164b of the first filled conductive film 164 may be about 10 nm or less. For example, the first thickness TH of the second portion 164b of the first filled conductive film 164 may be from about 0.1 nm to about 10 nm, or from about 1 nm to about 10 nm, or from about 1 nm to about 5 nm.

[0062] In some embodiments, the first conductive filler film 164 may form the bonding surface BS between the first semiconductor chip 100 and the second semiconductor chip 200. For example, the uppermost surface of the second portion 164b may be configured to be coplanar with the surface (e.g., the upper surface) of the first bonding insulating film 150.

[0063] In some embodiments, the second conductive filler film 166 may form the bonding surface BS between the first semiconductor chip 100 and the second semiconductor chip 200. For example, the uppermost surface of the second conductive filler film 166 may be configured to be coplanar with the surface (e.g., the upper surface) of the first bonding insulating film 150.

[0064] The first conductive film 164 may include a first metallic element. The second conductive film 166 may include a second metallic element. The gap-filling capability of the first metallic element may be superior to that of the second metallic element. Here, gap-filling capability refers to the ability of a material to fill a narrow space (e.g., a high aspect ratio trench) without defects such as gaps or voids. Here, a gap refers to a boundary line or interface formed within the material during the filling of a narrow space. Here, a void refers to an empty space or air gap formed within the material during the filling of a narrow space. For example, the second metallic element may be copper (Cu). In this case, the first metallic element may be one of cobalt (Co), ruthenium (Ru), nickel (Ni), molybdenum (Mo), aluminum (Al), and / or tungsten (W), which are known to have better gap-filling capabilities than copper (Cu).

[0065] The conductivity of the second conductive film 166 can be higher than that of the first conductive film 164. For example, the first metal element can be cobalt (Co). In this case, the second metal element can be one of silver (Ag), copper (Cu), gold (Au), aluminum (Al), and / or tungsten (W).

[0066] In some embodiments, the first metallic element may be a metallic element selected from the group consisting of cobalt (Co), ruthenium (Ru), nickel (Ni), molybdenum (Mo), aluminum (Al), and tungsten (W), and the second metallic element may be copper (Cu). For example, the first metallic element may be cobalt (Co), and the second metallic element may be copper (Cu).

[0067] In some embodiments, the first filling conductive film 164 may not include gaps and / or voids. For example, the first blocking conductive film 162 and the first filling conductive film 164 may completely fill the via trench 160Vt.

[0068] In some embodiments, the second filling conductive film 166 may not include gaps and / or voids. For example, the first blocking conductive film 162, the first filling conductive film 164, and the second filling conductive film 166 may completely fill the pad trench 160Pt.

[0069] In some embodiments, the ratio of the thickness of the first portion 164a of the first conductive filler 164 to the thickness of the second conductive filler 166 in the first direction Z can be approximately 1:4 to approximately 3:2. For example, the second conductive filler 166 may have a third height H3 in the first direction Z. For example, the third height H3 can be defined as the distance between the lowermost surface of the second conductive filler 166 and the uppermost surface of the second conductive filler 166 in the first direction Z. In this case, the ratio of the second height H2 to the third height H3 (H2:H3) can be approximately 1:4 to approximately 3:2. Within the above range, defects such as gaps and voids can be prevented from occurring in the first conductive filler 164 and / or the second conductive filler 166. In addition, within the above range, due to the high electrical conductivity of the second conductive filler 166, a first pad structure 160 with excellent electrical properties can be provided.

[0070] In some embodiments, the second height H2 may be less than or equal to the third height H3. For example, the ratio of the second height H2 to the third height H3 (H2:H3) may be approximately 1:4 to approximately 1:1. In this case, a first pad structure 160 with excellent electrical properties can be provided.

[0071] The second semiconductor chip 200 may include a second substrate 210, a second semiconductor element layer 220, a second wiring insulating film 230, a second wiring structure 240, a second bonding insulating film 250, and a second pad structure 260.

[0072] The second substrate 210 may include a second front side 210a and a second rear side 210b opposite to each other. The second front side 210a may be opposite to the first front side 110a of the first substrate 110. The second substrate 210 may be the same as or similar to the first substrate 110, and therefore its detailed description will not be provided.

[0073] The second semiconductor element layer 220 may be formed on the second front side 210a of the second substrate 210. The second semiconductor element layer 220 may be the same as or similar to the first semiconductor element layer 120, and therefore its detailed description will not be provided.

[0074] The second semiconductor element layer 220 may include individual devices of the same type as the first semiconductor element layer 120, or may include individual devices of a different type than the first semiconductor element layer 120.

[0075] For example, the second semiconductor element layer 220 may include a memory such as DRAM or flash memory, and the first semiconductor element layer 120 may include transistors, etc., that control the operation of the second semiconductor element layer 220.

[0076] As another example, the second semiconductor element layer 220 may include an image sensor such as a CIS (CMOS image sensor), and the first semiconductor element layer 120 may include transistors that control the operation of the second semiconductor element layer 220.

[0077] The second inter-wiring insulating film 230 may be formed on the second semiconductor element layer 220. In some embodiments, such as Figure 3 As shown, the second inter-wiring insulating film 230 may include a fourth sub-insulating film 231, a third etch stop film 232, a fifth sub-insulating film 233, a fourth etch stop film 234, and a sixth sub-insulating film 235 stacked in sequence. The second inter-wiring insulating film 230 may be the same as or similar to the first inter-wiring insulating film 130, and therefore its detailed description will not be provided.

[0078] The second wiring structure 240 may be formed in the second wiring inter-insulating film 230. The second wiring structure 240 is connected to the second semiconductor element layer 220 and may be electrically connected to individual devices on the second semiconductor element layer 220. The second wiring structure 240 may include a second wiring pattern 240M having a multilayer structure and second via patterns 240V interconnecting different layers of the second wiring patterns 240M. The number, quantity, shape, and placement of the layers in the second wiring structure 240 are illustrative only and are not limited to the number, quantity, shape, and placement shown in the figures.

[0079] In some embodiments, the second wiring structure 240 may include a second wiring barrier conductive film 242 and a second wiring fill conductive film 244 that are sequentially stacked (e.g., arranged). The second wiring barrier conductive film 242 and the second wiring fill conductive film 244 may be the same as or similar to the first wiring barrier conductive film 142 and the first wiring fill conductive film 144, and therefore their detailed description will not be provided.

[0080] The second bonding insulating film 250 may be formed on the second inter-wiring insulating film 230 and the second wiring structure 240. The second bonding insulating film 250 may be the same as or similar to the first bonding insulating film 150, and therefore its detailed description will not be provided.

[0081] The second bonding insulating film 250 can be bonded to the first bonding insulating film 150 in the first direction Z. For example, the surface of the first bonding insulating film 150 (e.g., the upper surface) and the surface of the second bonding insulating film 250 (e.g., the lower surface) can be bonded to each other to form a bonding surface BS between the first semiconductor chip 100 and the second semiconductor chip 200.

[0082] The second pad structure 260 can be formed on the second inter-wiring insulating film 230 and the second wiring structure 240. The second pad structure 260 penetrates the second bonding insulating film 250 and can be connected to the second wiring structure 240.

[0083] The second pad structure 260 can be bonded to the first pad structure 160 in the first direction Z. For example, the surface of the first pad structure 160 (e.g., the upper surface) and the surface of the second pad structure 160 (e.g., the lower surface) can be bonded to each other to form a bonding surface BS between the first semiconductor chip 100 and the second semiconductor chip 200.

[0084] In some embodiments, the second pad structure 260 may include a second bonding pad 260P and a second pad via 260V. The second bonding pad 260P and the second pad via 260V may be the same as or similar to the first bonding pad 160P and the first pad via 160V, and therefore their detailed description will not be provided.

[0085] The second pad structure 260 may include a second barrier conductive film 262, a third fill conductive film 264, and a fourth fill conductive film 266 stacked in sequence. The second barrier conductive film 262, the third fill conductive film 264, and the fourth fill conductive film 266 may be the same as or similar to the first barrier conductive film 162, the first fill conductive film 164, and the second fill conductive film 166, and therefore their detailed description will not be provided.

[0086] As electronic products require miniaturization, the aspect ratio of bonding pads in bonding structures continues to increase. This leads to defects such as gaps and voids in the bonding pads, resulting in decreased yield. For example, with copper (Cu), which has relatively poor gap-filling ability as a bonding pad material, the risk of defects such as gaps and voids is high during the formation of high aspect ratio bonding pads. Therefore, cobalt (Co), which has relatively better gap-filling ability, has been studied as a pad material; however, materials such as cobalt (Co) have relatively low electrical conductivity.

[0087] According to some embodiments, semiconductor devices can prevent defects in the first pad structure 160 by using a first fill conductive film 164 and a second fill conductive film 166 having different properties from each other. Specifically, as described above, the first fill conductive film 164 has relatively better gap-filling capability, thus preventing defects such as gaps and voids from appearing in the via trench 160Vt and / or pad trench 160Pt. Furthermore, the second fill conductive film 166 has relatively high conductivity, thus compensating for the low conductivity of the first fill conductive film 164 to improve the electrical characteristics of the first pad structure 160.

[0088] Furthermore, as described above, the thickness of the first portion 164a of the first filled conductive film 164 (e.g., Figure 3 H2) can be greater than the thickness of the second portion 164b of the first filled conductive film 164 (e.g., Figure 3 (TH). Therefore, the second filled conductive film 166 on the first filled conductive film 164 can have a relatively low aspect ratio, thus preventing defects such as gaps or voids from appearing in the second filled conductive film 166. As a result, semiconductor devices with improved yield and performance can be provided.

[0089] Figures 5a to 5f It shows Figure 2 Enlarged view of various alternative configurations for region R. For ease of explanation, the above descriptions will be briefly explained or omitted. Figures 1 to 4 Repeated parts of the description are omitted to avoid redundancy.

[0090] refer to Figure 1 , Figure 2 and Figure 5a In a semiconductor device according to some embodiments, the second filled conductive film 166 includes a top end 166C.

[0091] For example, the second portion 164b of the first conductive filler film 164 may include an inner surface 164S1 opposite to the second conductive filler film 166. The inclination of the inner surface 164S1 of the second portion 164b relative to a horizontal plane (e.g., an XY plane) may decrease towards the first wiring structure 140. Furthermore, at the lowermost part of the second portion 164b, the inclination of the inner surface 164S1 of the second portion 164b relative to a horizontal plane (e.g., an XY plane) may not be zero (i.e., the inner surface 164S1 of the second portion 164b may not be parallel to the horizontal plane (e.g., an XY plane). The second conductive filler film 166 may fill the space on the inner surface 164S1 of the second portion 164b. Therefore, the lower part of the second conductive filler film 166 may include a tip 166C pointing towards the first wiring structure 140.

[0092] refer to Figure 1 , Figure 2 and Figure 5b In a semiconductor device according to some embodiments, the upper surface of a first portion 164a of a first filled conductive film 164 includes a concave surface 164S2 that is recessed toward a second filled conductive film 166.

[0093] For example, the inclination of the upper surface of the first portion 164a relative to a horizontal plane (e.g., the XY plane) can decrease as it moves away from the second portion 164b, and can then be zero (i.e., the upper surface of the central portion of the first portion 164a can be parallel to the horizontal plane (e.g., the XY plane)). The second conductive filler 166 can fill the space on the concave surface 164S2 of the first portion 164a. Therefore, the lower portion of the second conductive filler 166 can include a convex surface protruding toward the first wiring structure 140.

[0094] refer to Figure 1 , Figure 2 and Figure 5c In a semiconductor device according to some embodiments, the thickness TH of the second portion 164b of the first filled conductive film 164 decreases toward the bonding surface BS.

[0095] For example, the thickness TH of the second portion 164b adjacent to the surface (e.g., the upper surface) of the first bonding insulating film 150 may be less than the thickness TH of the second portion 164b adjacent to the first portion 164a of the first filling conductive film 164.

[0096] refer to Figure 1 , Figure 2 and Figure 5d In a semiconductor device according to some embodiments, the second filled conductive film 166 includes a third portion 166a and a fourth portion 166b.

[0097] The third portion 166a of the second conductive filler film 166 may be disposed on the inner surface of the first portion 164a and the second portion 164b of the first conductive filler film 164. The second portion 164b of the first conductive filler film 164 may be located between the third portion 166a of the second conductive filler film 166 and the first barrier conductive film 162. The third portion 166a of the second conductive filler film 166 may be spaced apart from the first barrier conductive film 162 in the horizontal direction (e.g., the second direction X or the third direction Y) by the second portion 164b of the first conductive filler film 164.

[0098] The fourth portion 166b of the second conductive filler film 166 may be disposed on the third portion 166a of the second conductive filler film 166. The second portion 164b of the first conductive filler film 164 may not be located between the fourth portion 166b of the second conductive filler film 166 and the first barrier conductive film 162. For example, the fourth portion 166b of the second conductive filler film 166 may be in direct contact with the first barrier conductive film 162 in the horizontal direction (e.g., the second direction X or the third direction Y). The first conductive filler film 164 may be spaced apart from the bonding surface BS between the first semiconductor chip 100 and the second semiconductor chip 200 in the first direction Z.

[0099] refer to Figure 1 , Figure 2 and Figure 5e In a semiconductor device according to some embodiments, the first pad structure 160 further includes a fifth filled conductive film 165.

[0100] The fifth conductive filler 165 may be located between the first conductive filler 164 and the second conductive filler 166. In some embodiments, the fifth conductive filler 165 may include a fifth portion 165a and a sixth portion 165b.

[0101] The fifth portion 165a of the fifth conductive filler film 165 may overlap with the second conductive filler film 166 in the first direction Z. For example, the fifth portion 165a of the fifth conductive filler film 165 may be disposed on the lower surface of the second conductive filler film 166. The fifth portion 165a of the fifth conductive filler film 165 may be located between the first portion 164a of the first conductive filler film 164 and the second conductive filler film 166 in the first direction Z.

[0102] The sixth portion 165b of the fifth conductive filler film 165 may overlap with the second conductive filler film 166 in the second direction X or the third direction Y. For example, the sixth portion 165b of the fifth conductive filler film 165 may extend from the fifth portion 165a of the fifth conductive filler film 165 to surround the side surface of the second conductive filler film 166. The sixth portion 165b of the fifth conductive filler film 165 may be located between the second portion 164b of the first conductive filler film 164 and the second conductive filler film 166 in the second direction X or the third direction Y.

[0103] In some embodiments, the thickness of the fifth portion 165a of the fifth filled conductive film 165 in the first direction Z may be greater than the thickness of the sixth portion 165b of the fifth filled conductive film 165a in the second direction X or the third direction Y.

[0104] The fifth conductive film 165 may include a third metal element. In some embodiments, the gap-filling capability of the first metal element may be superior to that of the third metal element, and the gap-filling capability of the third metal element may be superior to that of the second metal element.

[0105] In some embodiments, the conductivity of the second filled conductive film 166 may be higher than that of the fifth filled conductive film 165, and the conductivity of the fifth filled conductive film 165 may be higher than that of the first filled conductive film 164.

[0106] In some embodiments, the first metal element may be cobalt (Co), the third metal element may be a metal element selected from the group consisting of nickel (Ni), molybdenum (Mo), aluminum (Al) and tungsten (W), and the second metal element may be copper (Cu).

[0107] In some embodiments, the second pad structure 260 may further include a sixth filler conductive film 265. The sixth filler conductive film 265 may be the same as or similar to the fifth filler conductive film 165, and therefore its detailed description will not be provided.

[0108] refer to Figure 1 , Figure 2 and Figure 5f In a semiconductor device according to some embodiments, the second height H2 of the first portion 164a of the first filled conductive film 164 is greater than or equal to the third height H3 of the second filled conductive film 166.

[0109] For example, the ratio of the second height H2 to the third height H3 (H2:H3) can be approximately 1:1 to approximately 3:2. In this case, a first pad structure 160 with excellent gap-filling properties can be provided.

[0110] In the following text, reference will be made to Figures 1 to 12 A method for manufacturing a semiconductor device according to an illustrative embodiment is described.

[0111] Figures 6 to 12 This is a diagram of an intermediate structure corresponding to an intermediate step in a method of manufacturing a semiconductor device, according to some embodiments. For ease of explanation, the above descriptions will be briefly described or omitted. Figures 1 to 5f Repeated parts of the description are omitted to avoid redundancy. For reference, Figure 7 yes Figure 6 A magnified view of region R', which corresponds to Figure 2 The region R.

[0112] refer to Figure 6 and Figure 7 A first semiconductor element layer 120, a first wiring inter-insulating film 130, a first wiring structure 140, and a first bonding insulating film 150 are formed on a first substrate 110.

[0113] A first semiconductor element layer 120 may be formed on a first front side 110a of a first substrate 110. A first inter-wire insulating film 130 and a first wiring structure 140 may be formed on the first semiconductor element layer 120. The first wiring structure 140 may include a first wiring pattern 140M and a first via pattern 140V. A first bonding insulating film 150 may be formed on the first inter-wire insulating film 130 and the first wiring structure 140.

[0114] In some embodiments, the first inter-wire insulating film 130 may include a first sub-insulating film 131, a first etch stop film 132, a second sub-insulating film 133, a second etch stop film 134, and a third sub-insulating film 135 stacked in sequence.

[0115] In some embodiments, the first wiring structure 140 may include a first wiring blocking conductive film 142 and a first wiring filling conductive film 144 stacked in sequence.

[0116] refer to Figure 8 This forms 160Pt pad trenches and 160Vt via trenches.

[0117] For example, an etching process using a second etch stop film 134 as an etch stop film can be performed. This forms a pad trench 160Pt that penetrates the first bonding insulating film 150, the third sub-insulating film 135, and the second etch stop film 134, exposing the upper surface of the second sub-insulating film 133. Next, an etching process using a first etch stop film 132 as an etch stop film can be performed. This forms a via trench 160Vt that penetrates the second sub-insulating film 133 and the first etch stop film 132, exposing the upper surface of the first wiring structure 140.

[0118] refer to Figure 9 A first barrier conductive film 162 is formed in the via trench 160Vt and the pad trench 160Pt.

[0119] The first barrier conductive film 162 may extend along the side and bottom surfaces of the pad trench 160Pt and the via trench 160Vt. The first barrier conductive film 162 may extend along the upper surface of the first bonding insulating film 150. The first barrier conductive film 162 may be formed by, for example, but not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, etc.

[0120] refer to Figure 10 The first filling conductive film 164 is formed on the first blocking conductive film 162.

[0121] The first conductive filler film 164 may fill at least a portion of the via trench 160Vt and a portion of the pad trench 160Pt. The first conductive filler film 164 may be formed by, for example, but not limited to, chemical vapor deposition, atomic layer deposition, electroplating, etc.

[0122] In some embodiments, the first filled conductive film 164 can be formed by electroplating using a bottom-up filling method. A bottom-up filling method refers to sequentially filling a narrow space (e.g., a high aspect ratio trench) with conductive metal from bottom to top. Inhibitors such as polymers can be used, but are not limited to, in a bottom-up filling method. By using a bottom-up filling method, the second height H2 of the first portion 164a of the first filled conductive film 164 can be greater than the thickness TH of the second portion 164b of the first filled conductive film 164.

[0123] refer to Figure 11 The second filled conductive film 166 is formed on the first filled conductive film 164.

[0124] The second conductive filler film 166 can fill the via trench 160Vt and the pad trench 160Pt. The second conductive filler film 166 can be formed by, for example, but not limited to, chemical vapor deposition, atomic layer deposition, electroplating, etc. In some embodiments, the second conductive filler film 166 can be formed by electroplating.

[0125] refer to Figure 12 A planarization process is performed on the first barrier conductive film 162, the first fill conductive film 164, and the second fill conductive film 166.

[0126] By performing a planarization process, the upper surface of the first bonding insulating film 150 can be exposed. Furthermore, a first pad structure 160, including a first bonding pad 160P and a first pad via 160V, can be formed. The planarization process may include, for example, but not limited to, a chemical mechanical polishing (CMP) process. Thus, a first semiconductor chip 100 including the first pad structure 160 can be manufactured.

[0127] Next, refer to Figure 3 The first semiconductor chip 100 and the second semiconductor chip 200 are joined together.

[0128] The first bonding insulating film 150 of the first semiconductor chip 100 can be bonded to the second bonding insulating film 250 of the second semiconductor chip 200. The first pad structure 160 of the first semiconductor chip 100 can be bonded to the second pad structure 260 of the second semiconductor chip 200. The manufacturing process of the second semiconductor chip 200 can be the same as or similar to that of the first semiconductor chip 100, and therefore its detailed description will not be provided. Therefore, the above-described application can be manufactured. Figures 1 to 4 Explanation of semiconductor devices.

[0129] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the embodiments described above, but can be implemented in various different forms. Those skilled in the art will understand that the present disclosure can be practiced in other specific forms without changing the technical spirit or essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are not limiting in any respect, but rather illustrative.

[0130] This document uses the term "approximately" to provide literal support for exact figures that follow it, as well as figures that are close to or approximate to those that are close to or approximate to a specifically stated figure. In determining whether a figure is close to or approximate to a specifically stated figure, an unstated close or approximate figure may be a figure substantially equivalent to the specifically stated figure in its context of existence. It should be understood that all numerical values ​​and ranges disclosed herein are approximate values ​​and ranges, whether or not they are used in conjunction with "approximately". It should also be understood that, as used herein, the term "approximately" in conjunction with a numerical value means that the value may be ±0.01%, ±0.1%, ±0.5%, ±1%, ±2%, ±3%, ±5%, ±10%, or ±15% of that value. It should also be understood that when a numerical range is disclosed herein, any value falling within that range is also specifically disclosed.

Claims

1. A semiconductor device, comprising: The first semiconductor chip includes a first substrate, a first semiconductor element layer on the first substrate, a first inter-wire insulating film on the first semiconductor element layer, a first wiring structure in the first inter-wire insulating film, and a first pad structure on the first wiring structure. as well as The second semiconductor chip includes a second substrate, a second semiconductor element layer on the second substrate, a second inter-wire insulating film on the second semiconductor element layer, a second wiring structure in the second inter-wire insulating film, and a second pad structure on the second wiring structure. The first pad structure and the second pad structure are joined to each other in a first direction. The first pad structure includes a first filling conductive film and a second filling conductive film sequentially disposed on the first wiring structure. The first conductive filler film includes a first portion that overlaps with the second conductive filler film in the first direction, and a second portion that overlaps with the second conductive filler film in a second direction intersecting the first direction. The first height of the first portion in the first direction is greater than the thickness of the second portion in the second direction, and The conductivity of the second filled conductive film is greater than that of the first filled conductive film.

2. The semiconductor device according to claim 1, wherein, The first semiconductor chip also includes a first bonding insulating film on the first inter-wire insulating film. The second semiconductor chip also includes a second bonding insulating film on the second inter-wire insulating film, and The first bonding insulating film and the second bonding insulating film are bonded to each other in the first direction.

3. The semiconductor device according to claim 1, in, The first pad structure further includes a barrier conductive film extending along the side and lower surfaces of the first portion and the outer surface of the second portion.

4. The semiconductor device according to claim 1, wherein, The first inter-wiring insulating film includes: pad trenches extending from the bonding surface between the first semiconductor chip and the second semiconductor chip toward the first wiring structure, and Via trenches extend from the lower surface of the pad trenches and connect to the first wiring structure. The first portion of the first conductive film fills a portion of the pad trench and the via trench, and The second portion of the first conductive filler film and the second conductive filler film fill another portion of the pad trench.

5. The semiconductor device according to claim 1, in, The gap-filling ability of the first metal element contained in the first filled conductive film is better than that of the gap-filling ability of the second metal element contained in the second filled conductive film.

6. The semiconductor device according to claim 5, wherein, The first metallic element is selected from the group consisting of cobalt (Co), ruthenium (Ru), nickel (Ni), molybdenum (Mo), aluminum (Al), and tungsten (W). The second metallic element is copper (Cu).

7. The semiconductor device according to claim 1, in, The aspect ratio of the first pad structure is 2 to 10.

8. The semiconductor device according to claim 7, in, The width of the first pad structure at the junction between the first semiconductor chip and the second semiconductor chip is 10 nm to 120 nm.

9. The semiconductor device according to claim 1, in, The ratio of the first height of the first portion of the first filled conductive film to the second height of the second filled conductive film in the first direction is 1:4 to 3:

2.

10. The semiconductor device according to claim 1, in, The thickness of the second portion of the first filled conductive film in the second direction is 10 nm or less.

11. A semiconductor device, comprising: The first semiconductor chip includes a first substrate, a first semiconductor element layer on the first substrate, a first inter-wire insulating film on the first semiconductor element layer, a first wiring structure in the first inter-wire insulating film, and a first pad structure on the first wiring structure. as well as The second semiconductor chip includes a second substrate, a second semiconductor element layer on the second substrate, a second inter-wire insulating film on the second semiconductor element layer, a second wiring structure in the second inter-wire insulating film, and a second pad structure on the second wiring structure. The first pad structure and the second pad structure are joined together. The first pad structure includes a first filling conductive film and a second filling conductive film sequentially disposed on the first wiring structure. The aspect ratio of the first pad structure is 2 to 10. The ratio of the first height from the lowest surface of the first filled conductive film to the lowest surface of the second filled conductive film to the second height from the lowest surface of the second filled conductive film to the highest surface of the second filled conductive film is 1:4 to 3:2, and The conductivity of the second filled conductive film is higher than that of the first filled conductive film.

12. The semiconductor device according to claim 11, in, The width of the first pad structure at the junction between the first semiconductor chip and the second semiconductor chip is 10 nm to 120 nm.

13. The semiconductor device according to claim 11, in, The gap-filling ability of the first metal element contained in the first filled conductive film is better than that of the gap-filling ability of the second metal element contained in the second filled conductive film.

14. The semiconductor device according to claim 13, wherein, The first metallic element is selected from the group consisting of cobalt (Co), ruthenium (Ru), nickel (Ni), molybdenum (Mo), aluminum (Al), and tungsten (W). The second metallic element is copper (Cu).

15. The semiconductor device according to claim 11, wherein, The first semiconductor chip and the second semiconductor chip are bonded to each other in a first direction. The first conductive filler film includes a first portion overlapping the second conductive filler film in the first direction, and a second portion overlapping the second conductive filler film in a second direction intersecting the first direction. The height of the first part in the first direction is greater than the thickness of the second part in the second direction.

16. A semiconductor device, comprising: The first semiconductor chip and the second semiconductor chip are joined together, wherein The first semiconductor chip includes: First substrate; A first semiconductor element layer is disposed on the first substrate; A first wiring inter-insulation film is disposed on the first semiconductor element layer; A first wiring structure is connected to the first semiconductor element layer in the first wiring inter-insulating film; A first bonding insulating film, on the first inter-wire insulating film; and A first pad structure extends through the first bonding insulating film and connects to the first wiring structure. The second semiconductor chip includes: Second substrate; A second semiconductor element layer is disposed on the second substrate; A second inter-wire insulating film is disposed on the second semiconductor element layer; The second wiring structure is connected to the second semiconductor element layer in the insulating film between the second wirings; A second bonding insulating film is bonded to the first bonding insulating film on the second inter-wire insulating film; and The second pad structure extends through the second bonding insulating film, connects to the second wiring structure, and bonds to the first pad structure. In the first inter-wiring insulating film and the first bonding insulating film, the pad trenches extend from the bonding surface between the first semiconductor chip and the second semiconductor chip toward the first wiring structure. The first pad structure includes: a barrier conductive film extending along the contours of the side and bottom surfaces of the pad trench; a first fill conductive film filling a portion of the pad trench on the barrier conductive film; and a second fill conductive film filling another portion of the pad trench on the first fill conductive film. The gap-filling ability of the first metal element contained in the first filled conductive film is better than that of the gap-filling ability of the second metal element contained in the second filled conductive film, and The conductivity of the second filled conductive film is higher than that of the first filled conductive film.

17. The semiconductor device according to claim 16, wherein, The first semiconductor chip and the second semiconductor chip are bonded to each other in a first direction. The first conductive filler film includes a first portion overlapping the second conductive filler film in the first direction, and a second portion overlapping the second conductive filler film in a second direction intersecting the first direction. The height of the first part in the first direction is greater than the thickness of the second part in the second direction.

18. The semiconductor device according to claim 16, wherein, In the first inter-wiring insulating film, via trenches extend from the lower surface of the pad trenches and connect to the first wiring structure, and The barrier conductive film and the first filling conductive film fill the via trench.

19. The semiconductor device according to claim 16, in, The aspect ratio of the first pad structure is 2 to 10.

20. The semiconductor device according to claim 16, wherein, The first conductive film comprises cobalt (Co), and The second conductive film comprises copper (Cu).

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