Heat dissipation structure, semiconductor device and preparation method thereof

Abstract

This invention provides a heat dissipation structure, a semiconductor device, and a method for fabricating the same. The heat dissipation structure includes: a substrate, wherein at least one chip embedding region is defined on the upper surface of the substrate; and a first heat dissipation channel disposed around the outer periphery of the chip embedding region, and the first heat dissipation channel being integrally connected for filling with a heat dissipation medium. This invention uses the chip embedding region as the area where the chip is subsequently placed. By using the first heat dissipation channel disposed around this region, the chip can dissipate heat evenly from all sides, improving heat dissipation efficiency, avoiding uneven local heat dissipation, and simultaneously improving integration density.

Description

Technical Field

[0001] This invention relates to semiconductor device manufacturing, and in particular to a heat dissipation structure, a semiconductor device, and a method for fabricating the same. Background Technology

[0002] With the continued advancement of Moore's Law, chip manufacturing technology has achieved a new leap, reaching the angstrom scale. This advanced manufacturing technology allows for the integration of more transistors into chips, thereby increasing transistor density and total number, and enhancing chip functionality and performance. However, the increase in the number of transistors also leads to higher demands for heat dissipation and power consumption. If heat cannot be effectively dissipated to keep the chip temperature within a safe range, it may lead to performance degradation or even chip damage, severely limiting the development of high-performance computers. Therefore, developing more efficient chip heat dissipation and packaging technologies is of great significance for both scientific research and practical applications.

[0003] Current chip heat dissipation technologies mainly involve adding heat sinks or liquid cooling devices to the vertical surface of the chip after packaging, which leads to various problems such as poor heat dissipation and low integration.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a heat dissipation structure, a semiconductor device and a method for fabricating the same, to solve the problems of poor heat dissipation and low integration caused by external heat dissipation devices such as adding heat sinks to vertical surfaces or adding liquid heat dissipation devices in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a heat dissipation structure, comprising: a substrate, wherein at least one chip embedding region is defined on the upper surface of the substrate;

[0007] A first heat dissipation channel is arranged around the outer periphery of the chip to be embedded area, and the first heat dissipation channel is integrally connected to fill the heat dissipation medium.

[0008] Optionally, the substrate is made of a metallic material.

[0009] Optionally, a preset distance is provided between the chip to be embedded area and the first heat dissipation channel.

[0010] Optionally, a second heat dissipation channel is further provided on the outer periphery of the first heat dissipation channel; the inlet of the first heat dissipation channel is connected to the inlet of the second heat dissipation channel, and the outlet of the first heat dissipation channel is connected to the outlet of the second heat dissipation channel.

[0011] Optionally, both the first and second heat dissipation channels include heat dissipation channels and metal covers; the top of the heat dissipation channel has an opening, and inlets and outlets are respectively provided at both ends; the metal cover seals and covers the opening; the heat dissipation channel and the metal cover together form a flow channel for the heat dissipation medium to circulate.

[0012] A semiconductor device includes at least one chip and the above-described heat dissipation structure; the chip is disposed in a corresponding chip embedding area, and the first heat dissipation channel is used to circulate a heat dissipation medium.

[0013] Optionally, a plastic encapsulation structure is provided between the chip and the first heat dissipation channel for isolation.

[0014] Optionally, the upper surface of the chip is further provided with an electrical lead-out structure; the electrical lead-out structure includes a redistribution layer.

[0015] To achieve the above and other related objectives, the present invention provides a method for preparing a heat dissipation structure, comprising: providing a substrate;

[0016] At least one chip embedding region is defined on the upper surface of the substrate;

[0017] A first heat dissipation channel is provided on the outer periphery of the chip to be embedded area, and the first heat dissipation channel is integrally connected to fill the heat dissipation medium.

[0018] Optionally, a second heat dissipation channel is further provided on the outer periphery of the first heat dissipation channel; the inlet of the first heat dissipation channel is connected to the inlet of the second heat dissipation channel, and the outlet of the first heat dissipation channel is connected to the outlet of the second heat dissipation channel.

[0019] Optionally, the preparation method for forming the corresponding heat dissipation channel includes:

[0020] Laser etching or wet etching is performed on the upper surface of the substrate to form a corresponding heat dissipation channel with a top opening, and an inlet and an outlet are respectively provided at both ends of the corresponding heat dissipation channel; a metal cover plate is covered by vacuum diffusion welding, and the heat dissipation channel and the metal cover plate together form a flow channel for the heat dissipation medium to flow.

[0021] To achieve the above and other related objectives, the present invention provides a semiconductor device fabrication method, comprising: fabricating the heat dissipation structure based on the above-described heat dissipation structure fabrication method; providing at least one chip; placing the chip in a corresponding chip embedding region, wherein the first heat dissipation channel is used for the flow of heat dissipation medium.

[0022] Optionally, the lower surface of the substrate is etched to form a vertically penetrating channel at the location where the chip is to be embedded, and the chip is placed within the vertically penetrating channel.

[0023] As described above, the heat dissipation structure, semiconductor device, and fabrication method of the present invention have the following beneficial effects:

[0024] 1. The present invention uses the chip to be embedded area as the area where the chip is subsequently set, and sets the first heat dissipation channel around the area, so that the chip can dissipate heat evenly from all sides, which improves the heat dissipation efficiency and avoids uneven local heat dissipation.

[0025] 2. The heat dissipation channel of the present invention is formed directly on the substrate and then directly packaged into a chip, which has better integration and greatly reduces the size of the device.

[0026] 3. The heat dissipation channel of the present invention also has the function of supporting and fixing, preventing the substrate from warping and deforming during the subsequent plastic sealing process. Attached Figure Description

[0027] Figure 1 The diagram shown is a schematic of the first type of semiconductor structure.

[0028] Figure 2 This is a schematic diagram of the second type of semiconductor structure.

[0029] Figure 3 The diagram shown illustrates the third type of semiconductor structure.

[0030] Figure 4 The diagram shown is a schematic representation of the heat dissipation structure of the present invention.

[0031] Figure 5 The diagram shown is a structural schematic of the first heat dissipation channel of the present invention.

[0032] Figure 6 The diagram shown is a structural schematic of the second heat dissipation channel of the present invention.

[0033] Figure 7 The diagram shows the process steps for preparing the heat dissipation structure of the present invention.

[0034] Figure 8 The image shown is a top view of the base of this invention.

[0035] Figure 9 The image shown is a side view of the base of the present invention.

[0036] Figure 10 The diagram shows the location of the chip to be embedded region according to the present invention.

[0037] Figure 11The image shown is a side view of the first heat dissipation channel etched according to the present invention.

[0038] Figure 12 The image shown is a top view of the first heat dissipation channel etched according to the present invention.

[0039] Figure 13 The diagram shows the structure of the present invention after the metal cover plate is applied.

[0040] Figure 14 The diagram shown is a schematic representation of the structure of the semiconductor device of the present invention.

[0041] Figure 15 The diagram shown is a schematic of a semiconductor device with a plastic encapsulation structure according to the present invention.

[0042] Figure 16 The diagram shown illustrates another semiconductor device with a plastic encapsulation structure according to the present invention.

[0043] Figure 17 The diagram shown is a schematic diagram of a semiconductor device structure with an electrical lead-out structure according to the present invention.

[0044] Figure 18 The diagram shows the structure of the chip after etching the area to be embedded according to the present invention.

[0045] Figure 19 The diagram shows the position of the chip on the pad of the present invention.

[0046] Figure 20 The diagram shown is a schematic diagram of the semiconductor device with an electrically led-out structure prepared according to the present invention.

[0047] Component designation explanation

[0048] 1. Semiconductor Structure

[0049] 11 chips

[0050] 12 Metal heat sinks

[0051] 13 First Liquid Cooling Heatsink

[0052] 14 Second liquid cooling heat sink

[0053] 2 Semiconductor devices

[0054] 20 chips

[0055] 201 Pad

[0056] 21 Heat dissipation structure

[0057] 210 base

[0058] 210a heat dissipation channel

[0059] 210b Flat section

[0060] 210c channel

[0061] 2101 Chip Embedding Area

[0062] 2102 First heat dissipation channel

[0063] 2103 Second heat dissipation channel

[0064] 211 Metal Cover Plate

[0065] 212 Molded Structure

[0066] 213 Dielectric layer

[0067] 214 Rewiring Layer

[0068] 215 Convex structure Detailed Implementation

[0069] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0070] Please see Figures 1 to 20 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0071] like Figures 1 to 3 Semiconductor structure 1, which involves attaching a heat sink or adding an external heat dissipation device such as a liquid cooling system to the vertical surface of the chip after packaging: Figure 1 A metal heat sink 12 is directly mounted on the back of chip 11 for heat dissipation; Figure 2 Multiple chips 11 are arranged on the same plane, and the upper surface of each chip 11 shares a first liquid cooling heat sink 13 for heat dissipation; Figure 3 Each chip 11 located on the same plane is equipped with its own corresponding second liquid cooling heat sink 14 for heat dissipation.

[0072] However, all of the above heat dissipation measures require independent heat dissipation devices to be installed on the chip surface, which will affect the miniaturization and thinning process of the product. Furthermore, the connection between the chip and the corresponding heat dissipation device typically requires the use of adhesive materials with poor thermal conductivity. This not only affects heat dissipation efficiency but also results in a relatively long distance between the chip and the heat dissipation device, leading to delayed chip heat dissipation and impacting the heat dissipation efficiency of the external heat dissipation device. In addition, these heat dissipation measures need to be implemented separately after chip packaging, thus adding extra process steps and costs.

[0073] To address the above issues, this embodiment provides a heat dissipation structure 21, which optimizes heat dissipation, improves the overall integration of the device, and does not introduce additional process steps or costs by setting heat dissipation channels on the outer periphery of the chip 20.

[0074] like Figure 4 As shown, the heat dissipation structure 21 provided in this embodiment includes: a substrate 210.

[0075] Specifically, in this embodiment, the substrate 210 is made of a metallic material. To avoid wafer warping and improve thermal conductivity, a metallic material with good thermal conductivity and a low coefficient of thermal expansion (CTE) is selected for processing. The metallic material refers to a material composition containing at least one metal, such as copper, Kovar alloy, stainless steel, etc. Kovar alloy, also known as an iron-nickel-cobalt alloy, is a special alloy with a coefficient of linear expansion similar to hard glass within a specific temperature range. In this embodiment, Kovar alloy is combined with oxygen-free copper, resulting in a final metallic material with anisotropic thermal conductivity. When the heat flow direction is parallel to the axial direction, the thermal conductivity and electrical conductivity are 4-5 times higher than those of Kovar alloy alone.

[0076] It should be noted that different metal materials can be selected based on actual heat dissipation requirements and industrial cost considerations. The actual selection and mixing of metal materials are not limited to this embodiment. Based on the above metal materials, 8-inch metal wafers with a thickness of 100-150um can be manufactured. Various sizes such as 6 / 8 / 12 inches and different thicknesses can also be set, and are not limited to this embodiment.

[0077] Specifically, at least one chip embedding region 2101 is defined on the upper surface of the substrate 210. A first heat dissipation channel 2102 is disposed around the outer periphery of the chip embedding region 2101, and the first heat dissipation channel 2102 is integrally connected to fill the heat dissipation medium (not shown in the figure).

[0078] As an example, such as Figures 4-6As shown, the chip embedding area 2101 serves as the region where the chip will be subsequently embedded, and the first heat dissipation channel 2102 is arranged around this region. Because it is evenly distributed around the perimeter of the chip embedding area 2101, heat dissipation efficiency is improved and uneven local heat dissipation is avoided.

[0079] In this embodiment, a preset distance h is provided between the chip embedding area 2101 and the first heat dissipation channel 2102. For example... Figure 5 As shown, the chip embedding region 2101 is surrounded by a preset spacing h. Setting the preset spacing h ensures adequate operating space for subsequent process steps. In addition, setting the preset spacing h avoids problems such as uneven temperature damage to the chip caused by localized rapid cooling due to direct contact between the heat dissipation channel and the chip.

[0080] In another embodiment, a second heat dissipation channel 2103 is further provided on the outer periphery of the first heat dissipation channel 2102; the inlets of the first heat dissipation channel 2102 and the second heat dissipation channel 2103 are connected, and the outlets of the first heat dissipation channel 2102 and the second heat dissipation channel 2103 are connected to each other to allow the heat dissipation medium to flow together. The first heat dissipation channel 2102 and the second heat dissipation channel 2103 can be considered as concentric structures with the same center and shape but different sizes. In this embodiment, compared to directly increasing the size of the first heat dissipation channel 2102, the addition of the second heat dissipation channel 2103 increases the structural strength of the substrate 2101 by adding a new metal framework, thus preventing wafer surface warping and other issues.

[0081] As an example, both the first heat dissipation channel 2102 and the second heat dissipation channel 2103 include a heat dissipation channel 210a and a metal cover plate 211. The top of the heat dissipation channel 210a has an opening, and inlets and outlets are respectively provided at both ends. The metal cover plate 211 seals and covers the opening, and the heat dissipation channel 210a and the metal cover plate 211 together form a flow channel for the heat dissipation medium to circulate. In this embodiment, the heat dissipation channel 210a and the metal cover plate 211 cooperate to form an internally hollow cavity, and the internally through-cavities are connected and filled with heat dissipation medium to form corresponding heat dissipation channels.

[0082] It should be noted that, in this embodiment, in order to ensure that multiple chips with heat dissipation channels can be assembled simultaneously on a single substrate 210, at least multiple chip embedding regions 2101 are provided. Furthermore, to facilitate the filling of each first heat dissipation channel 2102, it is preferable that each first heat dissipation channel 2102 is integrally connected (as shown by line m in the figure) to facilitate filling with the same heat dissipation medium. In some embodiments, different heat dissipation channels can also be filled with different heat dissipation media to meet more diverse needs; in this case, the heat dissipation channels filled with different heat dissipation media are respectively configured to be integrally connected.

[0083] In this embodiment, the heat dissipation channels (including the first heat dissipation channel 2102 and the second heat dissipation channel 2103) are formed directly on the substrate 210, rather than being fabricated using additional heat dissipation devices after the substrate 210 and the chip to be designed are packaged or assembled. This results in better integration and significantly reduces the size of the final device. Furthermore, the heat dissipation channels can be considered as a "skeleton" that supports and fixes the substrate 210, preventing warping or deformation during subsequent molding. Similarly, in this embodiment, the added heat dissipation channels are evenly distributed, effectively increasing the area of ​​the metal with a small CTE, thus improving the warping problem of the substrate 210.

[0084] like Figure 7 As shown, this embodiment also provides a method for fabricating a heat dissipation structure, including:

[0085] S1, Provide a substrate 210.

[0086] Specifically, in this embodiment, the thickness of the substrate 210 is greater than or equal to 30 μm, such as 50 μm, 100 μm, 150 μm, etc. It should be noted that the substrate 210 must at least be greater than or equal to the thickness of the chip to be designed.

[0087] S2. At least one chip embedding region 2101 is defined on the upper surface of the substrate 210.

[0088] S3. A first heat dissipation channel 2102 is provided on the outer periphery of the chip to be embedded region 2101, and the first heat dissipation channel 2102 is integrally connected to fill the heat dissipation medium.

[0089] Specifically, in another embodiment, a second heat dissipation channel 2103 is further provided on the outer periphery of the first heat dissipation channel 2102; the inlets of the first heat dissipation channel 2102 and the second heat dissipation channel 2103 are connected, and the outlets of the first heat dissipation channel 2102 and the second heat dissipation channel 2103 are connected to each other to allow the heat dissipation medium to flow together.

[0090] In this embodiment, the method for forming the corresponding heat dissipation channel includes: performing laser etching or wet etching on the upper surface of the substrate 210 to form a corresponding heat dissipation channel with a top opening, and providing an inlet and an outlet at both ends of the corresponding heat dissipation channel; covering the opening with a metal cover plate by vacuum diffusion welding; the heat dissipation channel and the metal cover plate together form a flow channel for the heat dissipation medium to circulate.

[0091] It should be noted that in this embodiment, the wet etching process employs a framework wet etching process (including lamination, exposure, development, etching, and film removal) to etch the substrate 210 according to a specific pattern to form a single-channel or multi-channel heat dissipation structure 21. Considering the heat dissipation requirements and the warpage of the substrate 210, the width of the heat dissipation channels is set through algorithm simulation. In this embodiment, a single channel is set to be less than or equal to 200µm, such as 75µm, 100µm, or 150µm. The specific width can be set according to actual needs and is not limited to this embodiment. Simultaneously, based on the above simulation algorithm, the chip thickness + 30µm is calculated. Here, taking a chip thickness of 100µm as an example, the channel depth is 130µm.

[0092] It should be further explained that vacuum diffusion welding is a method of joining two or more metals by heating them in a vacuum environment to allow them to directly contact and diffuse into each other. In this embodiment, the contact portion between the metal cover plate 211 and the flat portion 210b is welded by vacuum diffusion welding to form a flow channel. In this embodiment, the metal cover plate 211 is configured as any structure containing metallic materials; for better anti-warping properties, a metal with a small CTE is preferred. It is also preferred that the material be the same as that of the underlying substrate 210. Furthermore, in this embodiment, the thickness of the metal cover plate 211 is set to 50µm-100µm, such as 60µm, 80µm, or 90µm, and is not limited to this embodiment.

[0093] The following is combined with, for example Figures 8 to 14 The fabrication process of the first heat dissipation channel 2102 is described in detail below. The fabrication process of the second heat dissipation channel 2103 is similar and will not be described in detail here.

[0094] First, a substrate 210 is provided for subsequent fabrication. In this embodiment, as... Figure 8 and Figure 9 As shown, a substrate 210 made of a metallic material and in accordance with Figure 10 The diagram shows the configuration of multiple chip regions to be embedded 2101.

[0095] Secondly, heat dissipation channels 210a are manufactured. For example... Figure 11 and Figure 12 As shown, heat dissipation channels 210a are manufactured around the chip embedding area 2101. In this embodiment, heat dissipation channels 210a are obtained by laser etching, and the unetched portion is referred to as the flat portion 210b.

[0096] Next, a metal cover plate 211 is used to form a heat dissipation channel 2102. The cover plate is directly applied to the etched substrate 210. Due to the presence of the flat portion 210b, a first heat dissipation channel 2102 is formed between the metal cover plate 211 and the heat dissipation channel 210a. In this embodiment, it is preferable to use a metal with the same shape and size as the upper surface of the substrate 210 for the cover. Vacuum diffusion bonding technology is also used.

[0097] Finally, the first heat dissipation channel 2102 is filled with a heat dissipation medium to ensure subsequent heat dissipation effect. In this embodiment, the heat dissipation medium includes, but is not limited to, deionized water, alcohol-based solutions, mineral oil, silicone oil, etc.

[0098] It should be noted that, since the heat dissipation structure of this embodiment is manufactured in one step using the above preparation method to create a micron-level liquid flow channel, it greatly reduces the length, volume and area required by previous liquid cooling heat dissipation devices while effectively improving heat dissipation performance, and has good application prospects.

[0099] like Figures 14-17 As shown, this embodiment also provides a semiconductor device 2, including at least one chip 20 and the aforementioned heat dissipation structure 21. The chip is disposed within a corresponding chip embedding region 2101, and the first heat dissipation channel is used for the flow of heat dissipation medium.

[0100] Specifically, a plastic encapsulation structure 212 is provided between the chip 20 and the first heat dissipation channel 211 for isolation, such as... Figure 16 As shown. In fact, in this embodiment, the molding structure 212 is also covered by a metal cover plate 211 to facilitate subsequent encapsulation.

[0101] An electrical lead-out structure is also provided on the upper surface of the chip 20; the electrical lead-out structure includes at least a redistribution layer 214. The chip 20 is electrically led out through the redistribution layer 214 to ensure signal transmission.

[0102] In this embodiment, the relationship between chip 20 and heat dissipation structure 21 is parallel rather than perpendicular. At the same time, the process setting of redistribution layer 214 is adopted to ensure that heat dissipation is carried out in the parallel direction of chip 20 and signal transmission is carried out in the vertical direction. This can maximize the integration of the finished product after chip 20 and improve the heat dissipation effect of chip 20.

[0103] like Figure 18 As shown in the figure, this embodiment also provides a method for fabricating a semiconductor device, including fabricating a heat dissipation structure 21 based on the above-described heat dissipation structure fabrication method.

[0104] Specifically, after the heat dissipation structure 21 is prepared, at least one chip 20 is provided; the chip 20 is placed in the corresponding chip embedding area 2101 and dissipates heat at least through the first heat dissipation channel 2102.

[0105] As an example, the lower surface of the substrate 210 is etched to etch the chip embedding area 2101 and form a channel 210c that runs vertically through the chip, and the chip 20 is placed in the channel 210c.

[0106] In this embodiment, if the substrate 210 is etched with heat dissipation channel 210a but not etched through the substrate 210 (e.g. Figure 18 (As shown), then it is necessary to continue using machining or etching processes to allow 210 to penetrate while keeping 210a from penetrating.

[0107] In this embodiment, the original thickness of the wafer edge 5mm is maintained to ensure the rigidity of the substrate 210 in the subsequent molding process and to avoid wafer warping, and no structural etching is performed at this point.

[0108] Meanwhile, in this embodiment, the method of placing chip 20 within channel 210c includes: as follows Figure 19 As shown, firstly, a carrier board 201 is set up, and each chip 20 is attached to its corresponding position on the carrier board 201. Then, the carrier board 201 with each chip 20 is placed below the substrate 210, and each chip 20 is aligned with its corresponding channel 210c. The carrier board 201 is then brought into contact with the lower surface of the substrate 210, so that the chip 20 is positioned within the channel 210c. Because there is a certain gap between the chip embedding area 2101 and the first heat dissipation channel 2102, there is sufficient space for the chip 20 when it is positioned within the channel 210c, preventing damage caused by contact during chip movement.

[0109] As an example, the semiconductor device fabrication method also includes a chip injection molding and curing step, which includes: after the chip 20 is disposed in the channel 210c, removing the carrier board 201 and setting a molding structure 212 between the chip 20 and the first heat dissipation channel 211 for isolation.

[0110] In this embodiment, during the thinning process, a perforation is machined on the back side of the substrate 210 at a location without the channel 210c to obtain a molding injection port. Epoxy resin is injected through this molding injection port, and a molding machine is used to perform epoxy resin molding and baking curing on the substrate 210, on which the chip and heat dissipation structure 21 have already been attached. Figure 16 As shown.

[0111] As an example, the semiconductor device fabrication method also includes a chip stripping and electrical lead-out step, including: an electrical lead-out structure is provided on the upper surface of the encapsulated chip 20.

[0112] In this embodiment, the semiconductor devices after molding are first thermally peeled off to form molding wafers. On the upper surface of these molding wafers, a bumping process is used to fabricate a dielectric layer 213, a redistribution layer 214, and a bump structure 215, as follows: Figure 20 As shown.

[0113] As an example, the semiconductor device fabrication method also includes a chip packaging and dicing step. After electrical leads are made on the upper surface of the aforementioned molded wafer, the back side of the substrate 210 is encapsulated with epoxy resin, and then diced to form the aforementioned chip package.

[0114] In summary, this invention provides a heat dissipation structure, a semiconductor device, and a method for fabricating the same. The heat dissipation structure includes: a substrate, wherein at least one chip embedding region is defined on the upper surface of the substrate; and a first heat dissipation channel disposed around the outer periphery of the chip embedding region, and integrally connected to provide a heat dissipation medium. This invention uses the chip embedding region as the area where the chip is subsequently placed, and by using the first heat dissipation channel disposed around this region, the chip can dissipate heat evenly from all sides, avoiding uneven local heat dissipation and improving integration density. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0115] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A heat dissipation structure, characterized in that, The heat dissipation structure includes at least: A substrate, wherein at least one chip embedding region is defined on the upper surface of the substrate; A first heat dissipation channel is arranged around the outer periphery of the chip to be embedded area, and the first heat dissipation channel is integrally connected to fill the heat dissipation medium.

2. The heat dissipation structure according to claim 1, characterized in that: The substrate is made of a metallic material.

3. The heat dissipation structure according to claim 1, characterized in that: A preset distance is provided between the chip to be embedded area and the first heat dissipation channel.

4. The heat dissipation structure according to claim 1, characterized in that: A second heat dissipation channel is also provided on the outer periphery of the first heat dissipation channel; the inlet of the first heat dissipation channel is connected to the inlet of the second heat dissipation channel, and the outlet of the first heat dissipation channel is connected to the outlet of the second heat dissipation channel.

5. The heat dissipation structure according to claim 3 or 4, characterized in that: Both the first and second heat dissipation channels include heat dissipation channels and metal cover plates; the top of the heat dissipation channel has an opening, and inlets and outlets are respectively provided at both ends; the metal cover plate seals and covers the opening; the heat dissipation channel and the metal cover plate together form a flow channel for the heat dissipation medium to circulate.

6. A semiconductor device, characterized in that, The semiconductor device includes at least one chip and a heat dissipation structure as described in any one of claims 1 to 5; the chip is disposed in a corresponding chip embedding area, and the first heat dissipation channel is used to circulate heat dissipation medium.

7. The semiconductor device according to claim 6, characterized in that: A plastic encapsulation structure is provided between the chip and the first heat dissipation channel for isolation.

8. The semiconductor device according to claim 7, characterized in that: The chip's upper surface is also provided with an electrical lead-out structure; The electrical lead-out structure includes a redistribution layer.

9. A method for preparing a heat dissipation structure, characterized in that, The method for preparing the heat dissipation structure includes at least the following: Provide a base; At least one chip embedding region is defined on the upper surface of the substrate; A first heat dissipation channel is provided on the outer periphery of the chip to be embedded area, and the first heat dissipation channel is integrally connected to fill the heat dissipation medium.

10. The method for preparing the heat dissipation structure according to claim 9, characterized in that: A second heat dissipation channel is also provided on the outer periphery of the first heat dissipation channel; the inlet of the first heat dissipation channel is connected to the inlet of the second heat dissipation channel, and the outlet of the first heat dissipation channel is connected to the outlet of the second heat dissipation channel.

11. The method for preparing a heat dissipation structure according to claim 9 or 10, characterized in that: The methods for forming the corresponding heat dissipation channels include: Laser etching or wet etching is performed on the upper surface of the substrate to form a corresponding heat dissipation channel with a top opening, and an inlet and an outlet are respectively provided at both ends of the corresponding heat dissipation channel; a metal cover plate is covered by vacuum diffusion welding, and the heat dissipation channel and the metal cover plate together form a flow channel for the heat dissipation medium to flow.

12. A method for fabricating a semiconductor device, characterized in that, The semiconductor device fabrication method includes fabricating the heat dissipation structure based on the heat dissipation structure fabrication method according to any one of claims 9 to 11; Provide at least one chip; place the chip in the corresponding chip embedding area, and use the first heat dissipation channel for the flow of heat dissipation medium.

13. The semiconductor device fabrication method according to claim 12, characterized in that: The lower surface of the substrate is etched to form a vertically penetrating channel at the location where the chip is to be embedded, and the chip is placed within the vertically penetrating channel.

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