Semiconductor structure and method of forming the same

Abstract

This application provides a semiconductor structure and a method for forming the same; wherein, the semiconductor structure includes: a substrate including an alignment region; a first alignment layer located on the surface of the alignment region and including a first alignment pattern; the first alignment pattern is used for pattern positioning; at least one barrier layer located on one side of the first alignment layer along a first direction, including a barrier pattern disposed on one side of the alignment pattern along the first direction; the barrier pattern has multiple sub-patterns arranged in an array, and the maximum distance between adjacent sub-patterns is a preset distance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor chip manufacturing layout design, alignment marks and overlay error marks commonly employ a front-layer clearance design, which avoids placing other patterns directly above them to ensure the mark can be monitored. This results in a metal density in this area that is significantly lower than the surrounding logic circuits or memory areas, leading to micro-loading effects during the manufacturing process, significantly increasing the difficulty of process control and the likelihood of process defects. Summary of the Invention

[0003] This application provides a semiconductor structure and a method for forming the same.

[0004] The technical solution of this application embodiment is implemented as follows: In a first aspect, embodiments of this application provide a semiconductor structure, including: The substrate, including the alignment area; A first alignment layer, located on the surface of the alignment area, includes a first alignment pattern; the first alignment pattern is used for graphic positioning. At least one blocking layer is located on one side of the first alignment layer along the first direction, including a blocking pattern disposed on the side of the alignment pattern along the first direction; the blocking pattern has a plurality of sub-patterns arranged in an array, and the maximum distance between adjacent sub-patterns is a preset distance. The first direction is perpendicular to the plane in which the base lies.

[0005] In some embodiments, the preset distance is less than the Rayleigh interval that the detection system can recognize; the detection system is used to locate the pattern of the first alignment pattern.

[0006] In some embodiments, the preset distance ranges from 50 nanometers to 1000 nanometers.

[0007] In some embodiments, the sub-pattern includes a rectangle, a bar, a triangle, or a cross.

[0008] In some embodiments, the semiconductor structure includes: At least two of the barrier layers, wherein the projections of the barrier patterns in adjacent barrier layers onto the substrate are complementary or overlap.

[0009] In some embodiments, the first alignment layer further includes: virtual metal disposed around the alignment pattern.

[0010] In some embodiments, the first alignment pattern includes alignment marks or overlay marks.

[0011] In some embodiments, the substrate includes a slit region and a main chip region; the alignment region is disposed in the slit region and / or the main chip region.

[0012] In some embodiments, the first alignment layer further includes a first dielectric layer, wherein the first alignment pattern and the virtual metal are disposed in the first dielectric layer; The barrier layer further includes a second dielectric layer, and the barrier pattern is disposed in the second dielectric layer.

[0013] Secondly, embodiments of this application provide a method for forming a semiconductor structure, the method comprising: A substrate is provided, the substrate including an alignment region; A first alignment layer is formed on the surface of the alignment region, and at least one barrier layer is formed on one side of the first alignment layer along a first direction. The first alignment layer includes a first alignment pattern for graphic positioning; the blocking layer includes a blocking pattern disposed on one side of the alignment pattern along the first direction; the blocking pattern has multiple sub-patterns arranged in an array, and the maximum distance between adjacent sub-patterns is a preset distance; the first direction is perpendicular to the plane where the substrate is located.

[0014] This application provides a semiconductor structure and a method for forming the same; wherein, the semiconductor structure includes: a substrate, a first alignment layer and at least one barrier layer; the substrate includes an alignment region; the first alignment layer is located on the surface of the alignment region and includes a first alignment pattern; the first alignment pattern is used for pattern positioning; at least one barrier layer is located on one side of the first alignment layer along a first direction and includes a barrier pattern disposed on one side of the alignment pattern along the first direction; the barrier pattern has multiple sub-patterns arranged in an array, the maximum distance between adjacent sub-patterns is a preset distance, and the first direction is perpendicular to the plane where the substrate is located.

[0015] Here, because the barrier layer contains a barrier pattern, one side of the first alignment layer along the first direction is a non-clear layer. This allows the metal density of this area to remain similar to that of the surrounding circuitry, thereby reducing micro-load effects during the manufacturing process. In other words, it reduces potential thickness inhomogeneities, stress, or morphological changes in subsequent processes, improving the yield of the semiconductor structure and reducing production costs. Furthermore, since the maximum distance between the sub-patterns in the barrier pattern is a preset distance, this preset distance prevents the barrier pattern from being recognized by the measuring instrument, ensuring the positioning accuracy of the first alignment pattern. Attached Figure Description

[0016] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0017] Figure 1 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 1 ; Figure 2 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 2 ; Figure 3 A schematic diagram of the substrate provided in the embodiments of this application; Figure 4 Schematic diagram of the barrier layer provided in the embodiments of this application Figure 1 ; Figure 5 This is a schematic diagram of the detection system provided in the embodiments of this application; Figure 6 A schematic diagram of the barrier layer provided in the embodiments of this application. Figure 2 ; Figure 7 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 3 ; Figure 8 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 4 ; Figure 9 A schematic diagram of the barrier layer provided in the embodiments of this application. Figure 3 ; Figure 10 A schematic diagram of the structure of the first alignment layer provided in the embodiments of this application. Figure 1 ; Figure 11 A schematic diagram of the structure of the first alignment layer provided in the embodiments of this application. Figure 2 ; Figure 12 A schematic diagram of the structure of the first alignment layer provided in the embodiments of this application. Figure 3 ; Figure 13 A schematic diagram of the structure of the first alignment layer provided in the embodiments of this application. Figure 4 ; Figure 14 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 5 ; Figure 15 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 6; Figure 16 A schematic flowchart illustrating the semiconductor structure fabrication method provided in this application embodiment; Figures 17 to 20 This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this application; Figure 21 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0018] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0019] In the following description, numerous details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0020] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0021] In the following description, the terms "first," "second," and "third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first," "second," and "third" may be interchanged in a specific order or sequence where permissible, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein. In the drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0022] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0024] Currently, in semiconductor chip manufacturing layout design, alignment marks and overlay error marks are typically placed within the dicing channels to maximize the utilization of the wafer's effective area. However, on the one hand, to control defects in the dicing channels, an etching process is usually used to pre-cut the chip. This process requires the dicing channel area to remain clear, resulting in a lower metal density in this area compared to other areas, which can easily lead to defects and stress problems during the process. On the other hand, to obtain more precise and accurate positioning during the process, alignment marks need to be placed in various local areas of the chip to enable monitoring of local areas of a large-size chip. For example, the chip can be divided into 1×2, 2×1, 2×2, etc. arrays, with each area having a corresponding alignment mark.

[0025] Furthermore, alignment marks and overlay error marks commonly employ a front-layer clearance design to improve monitoring accuracy during alignment. However, this results in a metal density in this area being significantly lower than that of the surrounding logic circuits or memory areas. Consequently, during global planarization processes such as Chemical Mechanical Polishing (CMP), uneven density can lead to depressions or defects, damaging the mark morphology and signal integrity. Therefore, alignment marks and similar markings cannot meet the fabrication rules of semiconductor structures, making reliable integration into the chip impossible.

[0026] Based on this, embodiments of this application provide a semiconductor structure and a method for forming the same; the semiconductor structure and method for forming the same in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0027] Before introducing the embodiments of this application, let's define three directions that may be used in the following embodiments to describe the three-dimensional structure. These three directions may include the X-axis, Y-axis, and Z-axis (first) direction. The Z-axis direction can be a direction perpendicular to the plane where the base is located; the X-axis and Y-axis directions are two perpendicular directions on the plane where the base is located.

[0028] This application provides a semiconductor structure; please refer to [reference needed]. Figure 1 The semiconductor structure 100 includes: a substrate 110 including an alignment region A; a first alignment layer 120 located on the surface of the alignment region A, including a first alignment pattern 121; the first alignment pattern is used for pattern positioning; at least one barrier layer 130 located on one side of the first alignment layer 120 along the Z-axis direction, including a barrier pattern 131 disposed on one side of the alignment pattern 121 along the Z-axis direction; the barrier pattern 131 has a plurality of sub-patterns 131a arranged in an array, and the maximum distance between adjacent sub-patterns 131a is a preset distance d.

[0029] In this embodiment of the application, the substrate 110 may include a substrate, and a device layer and a metal layer (not shown) located on the substrate; wherein, the substrate may be a silicon substrate, or the substrate may include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0030] In this embodiment, alignment area A is an area for arranging graphic positioning marks; the position and size of alignment area A can be set according to actual needs. For example, alignment area A can be set in the cutting channel area or in the chip area.

[0031] In this embodiment, the first alignment pattern 121 is a physical structure for identification and positioning. The first alignment pattern 121 can be identified by a detection system (such as an optical alignment system or an electron beam measurement system) to achieve pattern overlay alignment or overall position positioning during the manufacturing process. The first alignment pattern 121 can be a metallic pattern composed of materials such as titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum (Al), and copper (Cu). The high reflectivity of the metal generates a strong optical contrast signal, facilitating the identification of the first alignment pattern 121 by the detection system. In other embodiments, the first alignment pattern 121 can also be a high-refractive-index dielectric pattern (such as silicon nitride) or a semiconductor pattern (such as polycrystalline silicon).

[0032] In this embodiment of the application, the blocking pattern 131 can be a metallic pattern made of materials such as titanium, titanium nitride, tungsten, aluminum, and copper; it should be noted that... Figure 1 The diagram only shows a schematic structure of semiconductor structure 100 including a single barrier layer 130; in reality, the number of barrier layers can be set according to actual needs, for example, two layers (e.g., Figure 7 As shown), 3 layers (as shown) Figure 8 (as shown) etc.

[0033] It should be noted that, Figure 1 The diagram only shows a schematic structure of the semiconductor structure 100, including a barrier layer 130 located below the first alignment layer 120 along the Z-axis; for actual details, please refer to [reference needed]. Figure 2 The barrier layer 130 can also be located above the first alignment layer along the Z-axis.

[0034] In this embodiment, because the barrier layer contains a barrier pattern, one side of the first alignment layer along the Z-axis is a non-clear layer. This allows the region to maintain a similar metal density to the surrounding circuitry, thereby reducing micro-load effects during the manufacturing process. In other words, it reduces potential thickness inhomogeneities, stress, or morphological changes in subsequent processes, improving the yield of the semiconductor structure and reducing production costs. Furthermore, since the maximum distance between the sub-patterns in the barrier pattern is a preset distance, this preset distance prevents the barrier pattern from being recognized by the measuring instrument, ensuring the positioning accuracy of the first alignment pattern.

[0035] Next, please refer to Figures 1 to 15 The semiconductor structure 100 will be described in detail.

[0036] In some embodiments, please refer to Figure 1 The first alignment layer 120 further includes a first dielectric layer 122, wherein the first alignment pattern 121 is disposed in the first dielectric layer 122; the barrier layer 130 further includes a second dielectric layer 132, wherein the barrier pattern 131 is disposed in the second dielectric layer 132.

[0037] In this embodiment, the first dielectric layer 122 is an insulating material layer carrying the first alignment pattern 121, typically composed of a low dielectric constant material such as silicon oxide or silicon nitride. Similarly, the second dielectric layer 132 is an insulating material layer carrying the blocking pattern 131. The materials of the second dielectric layer 132 and the first dielectric layer 122 can be the same or different. For example, both the second dielectric layer 132 and the first dielectric layer 122 can be made of silicon oxide.

[0038] In some embodiments, please refer to Figure 3 The substrate 110 includes a dicing region 111 and a main chip region 112; the alignment region A is disposed in the dicing region 111 and / or the main chip region 112.

[0039] In the embodiments of this application, please refer to Figure 3 The dicing region 111 is the dicing area on the semiconductor structure 100, and parts that do not participate in the actual circuit function, such as virtual metal, overlay marks, test structures, and process control monitoring, can be formed on its surface. The main chip region 112 is the core region used to form integrated circuit functional devices, and actual circuits or devices can be formed on its surface.

[0040] In this embodiment, the position of alignment area A can be set according to requirements. For example, as... Figure 3 As shown in (a), the alignment region A can be set in the dicing region 111, thus allowing the semiconductor structure 100 to be positioned without occupying the area of ​​the main chip region 112. For example, as... Figure 3 As shown in (b), the alignment region A can be set in the main chip region 112. Thus, when forming the actual circuit on the surface of the main chip region 112, alignment is performed using the first alignment pattern 121 on the alignment region A, making the mask alignment for fabricating each circuit layer more precise. Additionally, please refer to... Figure 3 (b) When the size of the main chip region 112 is large, it can be divided into multiple regions (four in the figure). By setting the alignment region A in the local region (two alignment regions A are diagonally placed in the four local regions in the figure), the alignment accuracy of the local region can be improved, thereby improving the alignment accuracy of the main chip region 112. For example, ... Figure 3As shown in (c), the alignment area A can be set in the dicing area 111 and the main chip area 112, so that alignment can be performed not only in the dicing area 111 but also in the main chip area 112, thus improving the alignment accuracy.

[0041] In some embodiments, please refer to Figure 1 and Figure 4 ,or Figure 2 and Figure 4 This is a top view of the blocking layer 130 in this embodiment; the maximum preset distance d between the sub-patterns 131a is less than the Rayleigh interval that the detection system can recognize; the detection system is used to locate the pattern of the first aligned pattern 121.

[0042] In this embodiment, since the Rayleigh interval is the smallest resolvable distance in the optical system (detection system), setting a preset distance d less than the Rayleigh interval can ensure that the detection light of the detection system passes through the blocking layer 130. In other words, since the preset distance d is less than the Rayleigh interval that the detection system can recognize, the detection system cannot recognize the blocking pattern 131, thereby realizing the recognition and measurement of only the first alignment pattern 121.

[0043] Specifically, when the maximum preset distance d between adjacent sub-patterns 131a is less than the Rayleigh interval that the optical system can recognize, the detection system cannot resolve a single independent sub-pattern 131a in the blocking pattern 131. Therefore, the entire blocking layer 130 exhibits an extremely low equivalent extinction coefficient and an equivalent refractive index that matches the surrounding medium at the measurement wavelength, resulting in a high transmittance of the measurement light in the detection system. In other words, the blocking pattern 131 cannot be recognized by the detection system, thus avoiding interference of the blocking pattern 131 with the measurement light. This allows the detection system to more stably recognize the first alignment pattern 121, improving alignment accuracy.

[0044] Additionally, please combine Figure 5 Here, the value of the Ruili interval needs to be calculated and designed based on the optical parameters of the detection system; the Ruili interval is calculated using the following formula 1: R=0.61λ / NA formula 1; In the formula, λ is the wavelength of the detection system, NA is the numerical aperture of the detection system; in addition, 0.61 is the standard optical theoretical value, taken from the first minimum position of the Airy pattern.

[0045] The numerical aperture (NA) of the detection system is calculated using the following formula 2: NA=n*sinθ Formula 2; In the formula, n is the refractive index in image space, and θ is the maximum half-angle of the objective lens in image space; the maximum half-angle depends on the equivalent aperture of the objective lens and lens parameters. The medium in image space is air or vacuum, the refractive index n is close to or equal to 1.0, and the numerical aperture NA is sinθ. Therefore, the larger the angle of the objective lens in image space, the larger the NA of the optical system, and the smaller the Rayleigh spacing R.

[0046] The following are two exemplary methods for calculating the Ruili interval:

[0047] In some embodiments, the preset distance d ranges from 50 nanometers (nm) to 1000 nanometers.

[0048] For example, the preset distance d can be a value between 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, or any combination thereof.

[0049] Specifically, when using extreme ultraviolet (EUV) lithography with a working wavelength λ of 13.5 nm as the detection system, the minimum preset distance d is approximately 50 nm; when using visible light with a working wavelength λ of 550 nm as the detection system, the preset distance d is approximately 500 nm; and when using visible light with a working wavelength λ greater than 700 nm as the detection system, the maximum preset distance d is approximately 1000 nm.

[0050] In some embodiments, such as Figure 6 (a) to Figure 6 As shown in (d), the sub-pattern 131a in the barrier layer 130 includes rectangles, stripes, triangles or crosses.

[0051] In this embodiment of the application, the shape of the sub-pattern 131a can be set according to actual needs. For example, Figure 6 (a) The rectangular sub-pattern 131a is easy to design and fabricate, and at the same time, the pattern density of the sub-pattern 131a is uniform, which helps to reduce local stress concentration caused by uneven pattern distribution, thereby reducing the risk of pattern warping or cracking; such as Figure 6 As shown in (b), the strip subpattern 131a can further increase the pattern density; as Figure 6 (c) shows a triangular sub-pattern 131a that has a similar effect to the rectangular sub-pattern 131a, which will not be described in detail here.

[0052] In addition, and such Figure 6(d) shows that the multiple cross-shaped sub-patterns 131a form a mesh structure, which can improve the structural stability and mechanical strength of the semiconductor structure.

[0053] In some embodiments, the semiconductor structure 100 includes at least two barrier layers 130, wherein the projections of the barrier patterns in adjacent barrier layers 130 onto the substrate 110 are complementary or overlap.

[0054] In this embodiment, the number of blocking layers 130 can be set according to actual needs; for example, in Figure 1 Based on the attached diagram, Figure 7 Two blocking layers 130 are provided below the first alignment layer 120 along the Z-axis direction; Figure 8 Three blocking layers 130 are provided below the first alignment layer 120 along the Z-axis direction.

[0055] In this embodiment, the projections of the blocking patterns in two adjacent blocking layers 130 onto the substrate 110 can be complementary; for example, Figure 7 and Figure 8 Both barrier layers 130a and 130b are made of Figure 6 (a) and Figure 6 (d) shows the sub-pattern 131a; for example, Figure 8 The patterns of the barrier layers 130b and 130c are respectively made by Figure 9 (a) and Figure 9 (b) The striped sub-pattern 131a shown constitutes the structure, where, Figure 9 (a) and Figure 9 (b) The structure of the bar sub-pattern 131a shown is the same, the difference being that Figure 9 (a) and Figure 9 (b) The projections of the subpattern 131a onto the substrate are complementary. This allows for a more uniform metal density in the vertical direction within the semiconductor structure.

[0056] In this embodiment, the projections of the blocking patterns in two adjacent blocking layers 130 onto the substrate 110 can overlap; for example, Figure 7 and Figure 8 The barrier layers 130a and 130b in the middle, or Figure 8 The patterns of barrier layers 130b and 130c are both made by Figure 6 (a) Figure 6 (b) Figure 6 (c) or Figure 6 The sub-pattern 131a shown in (d) is formed. This reduces the shading of the upper blocking layer by the lower blocking layer, increasing the light transmittance of all blocking layers. Furthermore, Figure 8The projections of the barrier layers 130a and 130b onto the substrate 110 can be complementary, for example, by respectively... Figure 6 (a) and Figure 6 (d) shows the sub-pattern 131a; Figure 8 The projections of the barrier layers 130b and 130c onto the substrate 110 can overlap, for example, both being made of... Figure 6 (d) shows the sub-pattern 131a.

[0057] It should be noted that, in other embodiments, the projections of the blocking patterns in two adjacent blocking layers 130 onto the substrate 110 may also partially overlap.

[0058] In some embodiments, the first alignment pattern 121 includes alignment marks (such as...) Figure 10 (as shown) or overprinted markings (such as) Figure 11 (As shown).

[0059] In this embodiment, the first alignment pattern 121 can be configured as an alignment mark or an overlay mark depending on its measurement task within the semiconductor structure. The alignment mark is used during the semiconductor structure fabrication process to ensure that subsequent photolithographic patterns are accurately aligned with preceding patterns; the alignment mark has a pattern with a large feature size and period, for example... Figure 10 (c) shows a one-dimensional coarse grating. Figure 10 (a) and Figure 10 (b) The two-dimensional coarse grating, etc., shown can be identified in subsequent measurement equipment and used to adjust the position of the lithography machine through alignment marks, thereby achieving high-precision alignment.

[0060] In addition, overlay marks are used to evaluate the alignment accuracy between different process layers. Overlay marks usually appear in pairs, located on two different alignment layers; for example, such as Figure 11 (a) Located in the first alignment layer 120, Figure 11 (b) Located in the second alignment layer 140 (location can be referenced) Figure 14 ),pass Figure 11 (a) and Figure 11 (b) The overlay marks formed by measuring the offset between the two alignment layers can directly and quantitatively obtain the overlay error value between the alignment layers.

[0061] In this embodiment, the semiconductor structure may have multiple alignment regions A, and the alignment pattern 121 in different alignment regions may be an alignment mark or an overlay mark. For example, Figure 3 The two alignment areas A shown can both be set as alignment marks or overlay marks; or they can be set as alignment marks and overlay marks respectively.

[0062] In some embodiments, please refer to Figure 12and Figure 13 The first alignment layer 120 further includes: a virtual metal 123 disposed around the first alignment pattern 121; the virtual metal 123 is disposed in the first dielectric layer 122.

[0063] In this embodiment, the virtual metal 123 is disposed in the peripheral region of the first alignment pattern 121 and formed on the same layer as the first alignment pattern 121, but it does not directly participate in the signal generation for pattern positioning. The virtual metal 123 is typically made of the same material as the first alignment pattern 121 to simplify the process steps. For example, both the first alignment pattern 121 and the virtual metal 123 are made of copper.

[0064] Here, by adding virtual metal 123 around the first alignment pattern 121, the metal pattern density of the first alignment layer 120 in the alignment area A can be adjusted, reducing depressions or defects caused by uneven density.

[0065] In the embodiments of this application, please refer to Figure 14 and Figure 15 The semiconductor structure 100 further includes a second alignment layer 140 disposed on the surface of the first alignment layer 120 along the Z-axis direction relative to the other side of the first alignment layer 120, at least one barrier layer 130 (i.e., 130a and 130b). The structure of the second alignment layer 140 is similar to that of the first alignment layer 120; please refer to the first alignment layer 120 for understanding. For example, please refer to... Figure 15 The second alignment layer 140 includes a second alignment pattern 141 and a third dielectric layer 142; for example, please refer to Figure 14 The second alignment layer 140 includes a second alignment pattern 141, a third medium layer 142, and a virtual metal 143 disposed around the second alignment pattern 141.

[0066] It should be noted that, Figure 14 and Figure 15 The diagram shows that the first alignment layer 120 is located below at least one barrier layer 130 (i.e., 130a and 130b) along the Z-axis direction, and correspondingly, the second alignment layer 140 is located above at least one barrier layer 130 along the Z-axis direction; similarly, when the first alignment layer 120 is located above at least one barrier layer 130 along the Z-axis direction, the second alignment layer 140 is located below at least one barrier layer 130 along the Z-axis direction.

[0067] In this embodiment, on the one hand, by setting a blocking pattern 131 in the blocking layer 130, and since the maximum distance between the sub-patterns in the blocking pattern is a preset distance (less than the Rayleigh pitch), not only can the blocking pattern be prevented from being recognized by the measuring instrument, enhancing the detection system's recognition of the first alignment pattern, but the blocking pattern can also shield the interference of the previous layer pattern (i.e., the metal layer on the other side of the blocking layer relative to the first alignment pattern) on the first alignment pattern. On the other hand, by adding virtual metal in the alignment layer, the metal density in the alignment layer can be kept consistent with the peripheral circuit, fundamentally avoiding defects caused by uneven density in processes such as chemical mechanical polishing, resulting in fewer defects in the semiconductor structure. In addition, in test items directly related to overlay accuracy, the semiconductor structure (i.e., the blocking pattern 131) provided in this embodiment can improve the signal-to-noise ratio by increasing the transmittance of the test light, thereby reducing the measurement error of the alignment pattern and achieving the effectiveness of high-precision alignment.

[0068] In addition, embodiments of this application also provide a method for forming a semiconductor structure. Figure 16 This is a schematic flowchart of the semiconductor structure fabrication method provided in the embodiments of this application, as shown below. Figure 16 As shown, the method for forming a semiconductor structure includes the following steps: steps S110 to S130.

[0069] Step S110, providing a substrate 110, the substrate 110 including an alignment region A.

[0070] Step S120: A first alignment layer 120 is formed on the surface of the alignment region A, and at least one blocking layer 130 is formed on one side of the first alignment layer 120 along the Z-axis direction; wherein, the first alignment layer 120 includes a first alignment pattern 121, which is used for graphic positioning; the blocking layer 130 includes a blocking pattern 131 disposed on one side of the alignment pattern along the Z-axis direction; the blocking pattern 131 has a plurality of sub-patterns 131a arranged in an array, and the maximum distance between adjacent sub-patterns 131a is a preset distance d.

[0071] In this embodiment, because the barrier layer contains a barrier pattern, the side of the first alignment layer with the barrier pattern along the Z-axis is not a clear layer. This allows the region to maintain a similar metal density to the surrounding circuitry, thereby reducing micro-load effects during the manufacturing process. In other words, it reduces potential thickness inhomogeneities, stress, or morphological changes in subsequent processes, improving the yield of the semiconductor structure and reducing production costs. Furthermore, since the maximum distance between the sub-patterns in the barrier pattern is a preset distance, setting this preset distance prevents the barrier pattern from being recognized by the measuring instrument, ensuring the positioning accuracy of the first alignment pattern.

[0072] Next, to form Figure 14 Taking semiconductor structures as an example, this paper provides a detailed explanation of the methods for forming semiconductor structures.

[0073] Step S110, provide as follows Figure 17 The substrate 110 includes an alignment region A.

[0074] Here, the substrate 110 includes a dicing region 111 and a main chip region 112; wherein, the alignment region A is located within the dicing region 111 and / or the main chip region 112 (see above for location). Figure 3 (To understand).

[0075] Step S120, forming as follows Figure 18 The first alignment layer 120 located on the surface of alignment region A is shown, and as shown in the figure. Figure 20 The diagram shows at least one blocking layer 130 located on one side of the first alignment layer 120 along the Z-axis direction; wherein, the first alignment layer 120 includes a first alignment pattern 121, which is used for graphic positioning; the blocking layer 130 includes a blocking pattern 131 disposed on one side of the alignment pattern along the Z-axis direction; the blocking pattern 131 has a plurality of sub-patterns 131a arranged in an array, and the maximum distance between adjacent sub-patterns 131a is a preset distance d.

[0076] In some embodiments, step S120 includes steps S121 to S122.

[0077] Step S121, forming as follows Figure 18 The first alignment layer 120 is located on the surface of the alignment region A. The first alignment layer 120 includes a first alignment pattern 121, which is used for graphic positioning.

[0078] In implementation, firstly, in situations such as Figure 17 A first initial dielectric layer (not shown) is formed on the surface of the substrate 110; next, the first initial dielectric layer is etched through a mask with an alignment pattern to form a first etched hole, and the remaining first initial dielectric layer is configured as follows: Figure 18 The first dielectric layer 122 is shown; finally, a metallic material (such as titanium, titanium nitride, etc.) is deposited in the first etched hole to form a layer as shown. Figure 18 The first alignment pattern 121 is shown.

[0079] In addition, in this embodiment of the application, the method for forming a semiconductor structure, while forming the first etched hole, further includes: etching the first initial dielectric layer through a mask with a virtual metal pattern to form a second etched hole located around the first etched hole. While forming the first alignment pattern 121, a pattern is formed in the second etched hole as shown in the image. Figure 18 The virtual metal 123 shown.

[0080] It should be noted that during the formation of the first alignment pattern 121 and the virtual metal 123 in the first and second etched holes, some metal material is often deposited on the surface of the first dielectric layer 122. This metal material is then removed by chemical mechanical polishing (CMP). By adding virtual metal 123 around the first alignment pattern 121, the metal pattern density of the first alignment layer 120 in the alignment region A can be adjusted, reducing depressions or defects caused by uneven density during the CMP process.

[0081] The etching processes described in the embodiments of this application include, but are not limited to, dry etching, wet etching, and combinations thereof.

[0082] The deposition processes involved in the embodiments of this application include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.

[0083] Step S122: Form at least one barrier layer 130. The barrier layer 130 includes a barrier pattern 131 disposed on one side of the alignment pattern along the Z-axis direction. The barrier pattern 131 has a plurality of sub-patterns 131a arranged in an array, and the maximum distance between adjacent sub-patterns 131a is a preset distance d.

[0084] In practice, the following example illustrates the formation of barrier layers 130a and 130b, with barrier layers 130a and 130b located above the first alignment layer along the Z-axis. Barrier layer 130a is formed through the following steps: First, in such Figure 18 A second initial dielectric layer (not shown) is formed on the surface of the first alignment pattern 121, the first dielectric layer 122, and the virtual metal 123; next, the second initial dielectric layer is etched through a mask with a blocking pattern to form a third etch hole, and the remaining second initial dielectric layer is configured as follows. Figure 19 The second dielectric layer 132 is shown; finally, a metallic material (such as titanium, titanium nitride, etc.) is deposited in the third etched hole to form a layer as shown. Figure 19 The blocking pattern 131 is shown. (As shown) Figure 20The steps for forming the barrier layer 130b shown are similar to those for forming the barrier layer 130a, and will not be described again here.

[0085] In this embodiment of the application, after forming the barrier layer 130b, the method for forming the semiconductor structure 100 further includes: forming a second alignment layer 140 on the surface of the barrier layer 130b; wherein, the formation steps of the second alignment layer 140 are similar to those of the first alignment layer 120, and will not be described again here.

[0086] It should be noted that the order of the description of steps S121 and S122 is only to illustrate the process flow of one embodiment and does not limit the order of the two in the actual process. That is, the barrier layer can be located above or below the first alignment layer along the Z-axis. In actual implementation, the above embodiment can be referred to for understanding.

[0087] In this embodiment, the semiconductor structure formation method typically requires multi-layer photolithography steps, and a certain overlay accuracy is needed between layers to align each layer. Taking a subsequent metal wiring process as an example, suppose N+1 metal layers need to be fabricated from bottom to top along the Z-axis to meet wiring requirements. The current process has reached the N+1th layer, and the previous N metal layers have been fabricated. Therefore, when performing photolithography on the N+1th metal pattern, the alignment pattern already formed in the Nth metal layer (i.e., the first alignment layer 120) needs to be used. At this time, a blocking pattern is formed in the N-1th metal layer (i.e., the blocking layer 130). This blocking pattern can shield the interference of the previous layer (e.g., layers 1 to N-2) metal patterns on the first alignment pattern, and the blocking pattern of the N-1th layer will not be recognized by the optical system, thus avoiding interference. The positions of the first alignment layer 120 and the blocking layer 130 can be combined... Figure 1 To understand.

[0088] Furthermore, during the patterning process on the back side of the substrate (the bottom surface along the positive Z-axis), and since the back side pattern needs to be aligned with the front side pattern (the top surface along the positive Z-axis), the alignment pattern already formed on the front side (i.e., the first alignment layer 120) is required. A blocking pattern has already been formed on the first metal layer (i.e., the blocking layer 130) above this pattern (i.e., on the side along the positive Z-axis) to shield the alignment pattern from interference from the previous layer pattern (e.g., the 2nd to 10th metal layers), and the first blocking pattern will not be recognized by the optical system, thus avoiding interference. The positions of the first alignment layer 120 and the blocking layer 130 can be combined... Figure 2 To understand.

[0089] In summary, this application provides a semiconductor structure 100. By providing at least one barrier layer 130 (such as barrier layer 130a and barrier layer 130b) on one side of the first alignment pattern 121 in the alignment region A along the Z-axis direction, since the barrier layer 130 contains a barrier pattern 131, and the preset distance d between adjacent sub-patterns 131a in the barrier pattern 131 is less than the Rayleigh interval that the detection system can recognize, the barrier pattern can be prevented from being recognized by the measuring instrument. At the same time, the barrier layer can also shield the interference of patterns in the adjacent other metal layers along the Z-axis direction on the recognition of the first alignment pattern, thereby enhancing the recognition of the first alignment pattern by the detection system. On the other hand, by adding virtual metal in the alignment layer, the metal density in the alignment layer can be kept consistent with that of the peripheral circuit, fundamentally avoiding defects caused by uneven density during chemical mechanical polishing, thus reducing defects in the semiconductor structure.

[0090] The semiconductor structure provided in this application embodiment is similar to the semiconductor structure in the above embodiments in terms of preparation method. For technical features not disclosed in detail in this application embodiment, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0091] This application also provides an electronic device. Figure 21 This is a schematic diagram of the structure of an electronic device 200 provided in an embodiment of this application, as shown below. Figure 21 As shown, the electronic device 200 includes any of the semiconductor structures 100 described in the above embodiments.

[0092] It should be noted that for electronic devices, this can be such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate SDRAM (DDRSDRAM), etc., and no specific limitation is made here.

[0093] Furthermore, in some embodiments, the electronic device may include a DRAM chip. The DRAM chip may conform to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, as well as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6; no specific limitation is made here.

[0094] In the several embodiments provided in this application, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0095] The features disclosed in the several method or structural embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0096] The above are merely some embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the above-described scope.

Claims

1. A semiconductor structure, characterized in that, include: The substrate, including the alignment area; A first alignment layer, located on the surface of the alignment area, includes a first alignment pattern; The first alignment pattern is used for graphic positioning; At least one barrier layer is located on one side of the first alignment layer along the first direction, including a barrier pattern disposed on the side of the alignment pattern along the first direction. The blocking pattern has multiple sub-patterns arranged in an array, and the maximum distance between adjacent sub-patterns is a preset distance; The first direction is perpendicular to the plane in which the base lies.

2. The semiconductor structure according to claim 1, characterized in that, The preset distance is less than the Rayleigh interval that the detection system can recognize; the detection system is used to locate the graphic of the first alignment pattern.

3. The semiconductor structure according to claim 1 or 2, characterized in that, The preset distance ranges from 50 nanometers to 1000 nanometers.

4. The semiconductor structure according to claim 1 or 2, characterized in that, The sub-patterns include rectangles, bars, triangles, or crosses.

5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes: At least two of the barrier layers, wherein the projections of the barrier patterns in adjacent barrier layers onto the substrate are complementary or overlap.

6. The semiconductor structure according to claim 1, characterized in that, The first alignment layer further includes: a virtual metal disposed around the alignment pattern.

7. The semiconductor structure according to claim 1, characterized in that, The first alignment pattern includes alignment marks or overlay marks.

8. The semiconductor structure according to claim 1, characterized in that, The substrate includes a dicing region and a main chip region; the alignment region is located in the dicing region and / or the main chip region.

9. The semiconductor structure according to claim 6, characterized in that, The first alignment layer further includes a first dielectric layer, wherein the first alignment pattern and the virtual metal are disposed in the first dielectric layer; The barrier layer further includes a second dielectric layer, and the barrier pattern is disposed in the second dielectric layer.

10. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided, the substrate including an alignment region; A first alignment layer is formed on the surface of the alignment region, and at least one barrier layer is formed on one side of the first alignment layer along a first direction. The first alignment layer includes a first alignment pattern for graphic positioning; the blocking layer includes a blocking pattern disposed on one side of the alignment pattern along the first direction; the blocking pattern has multiple sub-patterns arranged in an array, and the maximum distance between adjacent sub-patterns is a preset distance; the first direction is perpendicular to the plane where the substrate is located.

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