A wafer level packaging preparation method of a GaAs chip based on 3D printing

Abstract

This invention belongs to the field of wafer-level packaging technology, and specifically relates to a wafer-level packaging fabrication method for GaAs chips based on 3D printing. The method includes: encapsulating several GaAs chips to form a resin-based encapsulation; depositing around the bridge structure of the GaAs chips using 3D printing to form a dam structure; depositing a dielectric layer on the surface of the resin-based encapsulation using 3D printing; depositing a redistribution layer on the surface of the dielectric layer using 3D printing; thinning the back side of the resin-based encapsulation to expose the back gold layer of the GaAs chips, and dicing it as needed to form a single packaged chip; and depositing a conductive transition structure on the edge region of the single packaged chip using 3D printing. This invention achieves local protection, redistribution, and low-cost back gold layer-to-chip front-side conductivity, thereby simplifying the process and improving packaging reliability.

Description

Technical Field

[0001] This invention belongs to the field of wafer-level packaging technology, and specifically relates to a wafer-level packaging fabrication method for GaAs chips based on 3D printing. Background Technology

[0002] With the rapid development of radio frequency devices, millimeter-wave devices, and high-performance microwave devices, GaAs chips are widely used in communications, radar, and high-performance microelectronic systems due to their excellent high-frequency performance, high electron mobility, and low noise characteristics. At the same time, GaAs chip packaging is gradually evolving towards wafer-level packaging (WLP), fan-out wafer-level packaging (FOWLP), and multi-chip heterogeneous integration to meet the requirements of high integration, miniaturization, and high reliability.

[0003] In the wafer-level packaging process of GaAs chips, the following key structures are usually required: 1) chip surface or peripheral protection structure to protect GaAs chip bridge structure, floating structure or edge sensitive area; 2) redistribution layer (RDL) to redistribute chip electrodes to meet external interconnection requirements.

[0004] In existing technologies, the above-mentioned structures are typically formed using different processes. While these traditional processes are relatively mature, they have the following shortcomings: 1) Traditional RDL fabrication relies on multiple processes such as photolithography, electroplating, development, and etching, which are lengthy, require large equipment investment, and have a long manufacturing cycle.

[0005] 2) If the wiring structure, solder ball size or local protection structure needs to be adjusted, the mask usually needs to be redesigned, which increases the development cycle and cost.

[0006] 3) Traditional planar photolithography electroplating processes are more suitable for uniform thickness and uniform material systems, and it is difficult to flexibly realize complex structures such as local thickening, material gradient, and functional partitioning in the same manufacturing process.

[0007] 4) GaAs chip bridge structures are typically characterized by being suspended, slender, or having local protrusions, making them prone to failure during the packaging process due to mechanical collisions, packaging material flow, thermal stress concentration, or particulate contamination.

[0008] 5) Traditional back-gold connection methods often rely on flip-chip structures, through-holes, or complex metallization processes, which are not conducive to flexible packaging design. Existing back-gold lead structures are difficult to be compatible with the advanced packaging requirements of small-batch, frequently changing, and rapidly iterating designs.

[0009] In recent years, 3D printing technology has received increasing attention in the fields of electronic manufacturing and microstructure construction. Compared with traditional subtractive manufacturing and photolithography processes, 3D printing has advantages such as no need for masks, flexible design, and high structural freedom, and is expected to replace some traditional process steps in advanced packaging. However, currently, when using 3D printing for GaAs chip wafer-level packaging, there is still a lack of an integrated packaging solution that can simultaneously take into account bridge structure protection, RDL construction, low-cost back gold backing, and front-side chip conductivity.

[0010] Therefore, this invention urgently needs to propose a wafer-level packaging fabrication method for GaAs chips based on 3D printing to solve the above-mentioned technical defects. Summary of the Invention

[0011] The purpose of this invention is to provide a wafer-level packaging fabrication method for GaAs chips based on 3D printing. This invention can simultaneously achieve local protection, redistribution, and low-cost back gold and front-side conduction of the chip through an integrated 3D printing fabrication method, thereby simplifying the process flow and improving packaging reliability.

[0012] To address the aforementioned technical problems, this invention provides a wafer-level packaging fabrication method for GaAs chips based on 3D printing, comprising: Several GaAs chips are encapsulated to form a resin-based encapsulation. A dam structure is formed by depositing material around a bridge structure on a GaAs chip using 3D printing. A dielectric layer is formed by deposition on the surface of a resin-based molding compound using 3D printing. A redistribution layer is formed by depositing material on the surface of a dielectric layer using 3D printing. The back side of the resin-based molding compound is thinned to expose the back gold layer of the GaAs chip, and then diced as needed to form a single packaged chip. A conductive transition structure is formed by depositing a conductive layer on the edge region of a single packaged chip using 3D printing. The conductive transition structure leads the back gold layer to the interconnect region on the front side of the single packaged chip. The conductive transition structure extends from the back side to the front side along the edge region of the single packaged chip. The bottom end of the conductive transition structure is electrically connected to the back gold layer, and the top end is connected to the interconnect pads of the single packaged chip.

[0013] Preferably, when the plurality of GaAs chips are encapsulated, the plurality of GaAs chips are arranged in an array as required and encapsulated with encapsulation material to form a 12-inch wafer resin-based encapsulation body.

[0014] Preferably, the dam structure includes one of a continuous ring structure, a segmented discontinuous ring structure, and a closed or non-closed local barrier structure.

[0015] Preferably, the material of the dam structure is a pure metal slurry, a metal powder resin composite slurry, or a multilayer slurry with conductive and buffering functions.

[0016] Preferably, the dielectric layer is made of polyimide, epoxy resin, or PBO.

[0017] Preferably, the redistribution layer includes one of single-layer conductive wiring, multi-layer conductive wiring, planar wiring, or three-dimensional wiring with height difference; the conductive material of the redistribution layer is pure metal paste, metal powder resin composite paste, or layered conductive paste.

[0018] Preferably, the redistribution layer forms an electrical connection with the pads, dam structures, or subsequent metal pillars of the GaAs chip.

[0019] Preferably, between forming the redistribution layer and thinning the back side of the resin-based encapsulant, the method further includes: forming conductive bumps on the interconnect pads of the redistribution layer by 3D printing, and performing post-processing on the 3D-printed dam structure, redistribution layer, and conductive bumps; the conductive bumps are microbumps or solder balls.

[0020] Preferably, the post-treatment includes one or more of curing, sintering, electroplating thickening, annealing, or surface metallization.

[0021] The present invention also provides a wafer-level packaging structure for a GaAs chip based on 3D printing, which is prepared by using a wafer-level packaging fabrication method for a GaAs chip based on 3D printing as described above.

[0022] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention integrates bridge structure protection and packaging functions; by printing a dam around the GaAs chip bridge structure, the bridge structure can be effectively protected from the effects of packaging material flow, particulate contamination, and mechanical impact.

[0023] 2. This invention simplifies the RDL fabrication process; RDLs are formed directly through 3D printing, eliminating the need for traditional photolithography masks, electroplating, and etching processes, significantly simplifying the process and reducing costs.

[0024] 3. This invention can realize local functional gradient design; the dam structure, RDL and welding ball can adopt different material systems and different hierarchical structures, so as to take into account interface adhesion, printing stability, stress buffering and conductivity.

[0025] 4. This invention is adapted to the brittleness and thermomechanical properties of GaAs chips; this invention provides local protection design for GaAs bridge structures and stress-sensitive areas, which is beneficial to improving thermal cycling, mechanical shock and long-term reliability.

[0026] 5. The process of this invention is flexible and suitable for rapid iteration; compared with the traditional mask process, 3D printing is more suitable for small-batch, frequently changing, and highly complex packaging designs.

[0027] 6. This invention constructs conductive paths along the chip edge using 3D printing, eliminating the need to form through-holes inside the GaAs chip, greatly reducing costs and avoiding mechanical damage to the chip caused by traditional processing methods. It is more suitable for GaAs and similar brittle semiconductor materials. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the GaAs chip provided in an embodiment of the present invention.

[0029] Figure 2 This is a schematic diagram of forming a resin-based encapsulation body from several GaAs chips, provided in an embodiment of the present invention.

[0030] Figure 3 This is a schematic diagram of the formation of a dam structure provided in an embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram of the formation of a dielectric layer provided in an embodiment of the present invention.

[0032] Figure 5 This is a schematic diagram of the formation of a redistribution layer provided in an embodiment of the present invention.

[0033] Figure 6 This is a schematic diagram of forming conductive bumps provided in an embodiment of the present invention.

[0034] Figure 7 This is a schematic diagram of forming a single packaged chip provided in an embodiment of the present invention.

[0035] Figure 8 This is a schematic diagram of the formation of a conductive transition structure provided in an embodiment of the present invention.

[0036] In the diagram: 1-GaAs chip, 2-resin-based molding compound, 3-dam structure, 4-dielectric layer, 5-rewiring layer, 6-back gold layer, 7-conductive transition structure, 8-pad, 9-interconnect pad, 10-conductive bump. Detailed Implementation

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0038] This invention specifically provides a wafer-level packaging fabrication method for GaAs chips based on 3D printing, comprising the following steps: Step 1: Provide a GaAs chip of a certain thickness, wherein the GaAs chip has a front functional area and a back gold layer, such as... Figure 1 As shown.

[0039] Step 2: Arrange several GaAs chips in an array as required, and encapsulate them with molding compound to form a resin-based encapsulation. This is achieved using a 12-inch resin-based wafer as the resin substrate. Figure 2 As shown.

[0040] Step 3: Print a dam structure around the bridge structure. Using 3D printing, deposit dam material around the GaAs chip bridge structure to form a ring of dam material, such as... Figure 3 As shown; the dam structure can be a continuous ring structure, a segmented discontinuous ring structure, or a closed or non-closed local blocking structure.

[0041] The dam structure is preferably printed using pure metal paste, a composite paste formed by mixing metal powder and epoxy resin, or a multi-layer paste with conductive and buffering functions. The dam structure can be used for mechanical protection, thermal stress buffering, preventing particle or moisture intrusion, limiting the diffusion of encapsulation materials, and as a grounding or shielding structure.

[0042] Step 4: Form a dielectric layer on the surface and surrounding area of ​​the GaAs chip. This dielectric layer can be formed using 3D printing. The dielectric layer material can be polyimide, epoxy resin, PBO, or other insulating polymer materials, such as... Figure 4 As shown.

[0043] Step 5: Deposit conductive material on the substrate, chip surface, or dielectric layer surface using 3D printing to form a redistribution layer (RDL). The RDL can be: single-layer conductive wiring, multi-layer conductive wiring, planar wiring, or three-dimensional wiring with height differences. The conductive material can be: pure metal paste, a composite paste formed by mixing metal powder and epoxy resin, or a layered conductive paste system. Preferably, the RDL forms an electrical connection with chip pads, dam structures, or subsequent metal pillars, such as... Figure 5 As shown.

[0044] Step 6: On the RDL or the predetermined interconnect area, i.e., the interconnect pad, conductive bumps containing microbumps or solder balls are formed using 3D printing. Figure 6 As shown. The printed dam structure, RDL, and micro-bump or solder ball structure undergo post-processing, which includes one or more of the following: curing, sintering, electroplating thickening, annealing, or surface metallization.

[0045] Step 7: Thin the GaAs chip to expose the back gold layer as required, then dice it to form a single packaged chip, such as... Figure 7 As shown.

[0046] Step 8: Lead the back gold layer to the front of the chip. At the edge of the packaged chip, form a conductive transition structure using 3D printing. The conductive transition structure extends from the back to the front along the chip edge, with its bottom end electrically connected to the back gold layer and its top end connected to the interconnect pads on the front of the chip, such as... Figure 8 As shown.

[0047] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A wafer-level packaging fabrication method for GaAs chips based on 3D printing, characterized in that, include: Several GaAs chips are encapsulated to form a resin-based encapsulation. A dam structure is formed by depositing material around a bridge structure on a GaAs chip using 3D printing. A dielectric layer is formed by deposition on the surface of a resin-based molding compound using 3D printing. A redistribution layer is formed by depositing material on the surface of a dielectric layer using 3D printing. The back side of the resin-based molding compound is thinned to expose the back gold layer of the GaAs chip, and then diced as needed to form a single packaged chip. A conductive transition structure is formed by depositing a conductive layer on the edge region of a single packaged chip using 3D printing. The conductive transition structure leads the back gold layer to the interconnect region on the front side of the single packaged chip. The conductive transition structure extends from the back side to the front side along the edge region of the single packaged chip. The bottom end of the conductive transition structure is electrically connected to the back gold layer, and the top end is connected to the interconnect pads of the single packaged chip.

2. The wafer-level packaging fabrication method for GaAs chips based on 3D printing as described in claim 1, characterized in that, When the GaAs chips are encapsulated, the GaAs chips are arranged in an array as required and encapsulated with encapsulation material to form a 12-inch wafer resin-based encapsulation body.

3. The wafer-level packaging fabrication method for GaAs chips based on 3D printing as described in claim 1, characterized in that, The dam structure includes one of the following: a continuous ring structure, a segmented discontinuous ring structure, and a closed or non-closed local barrier structure.

4. The wafer-level packaging fabrication method for GaAs chips based on 3D printing as described in claim 1, characterized in that, The materials used for the dam structure include pure metal slurry, metal powder resin composite slurry, or multi-layer slurry with conductive and buffering functions.

5. The wafer-level packaging fabrication method for GaAs chips based on 3D printing as described in claim 1, characterized in that, The dielectric layer is made of polyimide, epoxy resin, or PBO.

6. The wafer-level packaging fabrication method for GaAs chips based on 3D printing as described in claim 1, characterized in that, The redistribution layer includes one of single-layer conductive wiring, multi-layer conductive wiring, planar wiring, or three-dimensional wiring with height difference; the conductive material of the redistribution layer is pure metal paste, metal powder resin composite paste, or layered conductive paste.

7. The wafer-level packaging fabrication method for GaAs chips based on 3D printing as described in claim 1, characterized in that, The redistribution layer forms an electrical connection with the pads, dam structures, or subsequent metal pillars of the GaAs chip.

8. The wafer-level packaging fabrication method for GaAs chips based on 3D printing as described in claim 1, characterized in that, Between forming the redistribution layer and thinning the back side of the resin-based encapsulant, the method further includes: forming conductive bumps on the interconnect pads of the redistribution layer by 3D printing, and performing post-processing on the 3D-printed dam structure, redistribution layer, and conductive bumps; the conductive bumps are micro-bumps or solder balls.

9. The wafer-level packaging fabrication method for GaAs chips based on 3D printing as described in claim 8, characterized in that, The post-treatment includes one or more of the following: curing, sintering, electroplating thickening, annealing, or surface metallization.

10. A wafer-level packaging structure for a 3D-printed GaAs chip, characterized in that, It is prepared by using a wafer-level packaging method for GaAs chips based on 3D printing as described in any one of claims 1 to 9.

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