Smart IC substrate, smart IC module, and IC card including the smart IC module

Abstract

The smart IC substrate according to an embodiment includes: a substrate including a first surface and a second surface opposite to the first surface; a first bonding layer disposed on the first surface; a first metal layer disposed on the first bonding layer; a second bonding layer disposed on the second surface; a second metal layer disposed on the second bonding layer; a first plating layer disposed on one surface of the first metal layer; a second plating layer disposed on another surface of the first metal layer; and a third plating layer disposed on one surface of the second metal layer, wherein the second bonding layer includes a first region and a second region, the second bonding layer has a surface contacting the second metal layer and another surface contacting the substrate, the first region includes a bonding region, the second region overlaps with at least one of the second metal layer and the third plating layer, and the surface roughness of one surface of the first region is greater than the surface roughness of one surface of the second region.

Description

Technical Field

[0001] The embodiments relate to a smart IC substrate, a smart IC module, and an IC card including the smart IC module. Background Technology

[0002] An IC card is a plastic card with an embedded integrated circuit chip that can store and process information. An IC card contains an IC that stores the necessary information for the card and transmits that information to a reader in the form of electrical signals.

[0003] IC cards are manufactured by inserting a smart IC module into the body of the card.

[0004] Based on the arrangement of the metal layers, smart IC modules are classified into single-type or dual-type. Single-type modules have metal layers and plating on only one surface of the substrate. Dual-type modules have metal layers and plating on both surfaces of the substrate.

[0005] Furthermore, based on how the card is used, smart IC modules are classified into contact cards, contactless cards, hybrid cards, and combination cards. Contact cards send and receive information through physical contact. Contactless cards send and receive information without physical contact. Hybrid and combination cards combine both contact and contactless functions.

[0006] Therefore, the smart IC module includes a contact surface and a bonding surface. The contact surface contacts external devices, and the chip is mounted on the bonding surface. The bonding surface is inserted into the interior of the card body.

[0007] The card body includes a housing for a smart IC module. Adhesive material is disposed inside the housing. The bonding surfaces and the card body are bonded together by the adhesive material.

[0008] When the adhesive force between the bonding surface and the card body decreases, the smart IC module may separate from the interior of the receiving portion. This reduces the reliability of the smart card.

[0009] Therefore, there is a need for a smart IC substrate, a smart IC module, and an IC card including the smart IC module, all with a new structure capable of solving the above problems.

[0010] As prior art relating to smart IC substrates, Korean Patent Publication (KR10-2022-0110247) has been disclosed. Summary of the Invention

[0011] Technical issues

[0012] The embodiments provide a smart IC substrate with improved reliability, a smart IC module, and an IC card including the smart IC module.

[0013] Technical solution

[0014] The smart IC substrate according to an embodiment includes: a substrate including a first surface and a second surface opposite to the first surface; a first bonding layer disposed on the first surface; a first metal layer disposed on the first bonding layer; a second bonding layer disposed on the second surface; a second metal layer disposed on the second bonding layer; a first plating layer disposed on one surface of the first metal layer; a second plating layer disposed on another surface of the first metal layer; and a third plating layer disposed on one surface of the second metal layer, wherein the second bonding layer includes a first region and a second region, the second bonding layer has a surface contacting the second metal layer and another surface contacting the substrate, the first region includes a bonding region, the second region overlaps with at least one of the second metal layer and the third plating layer, and the surface roughness of one surface of the first region is greater than the surface roughness of one surface of the second region.

[0015] In addition, the surface free energy of one surface in the first region is greater than the surface free energy of one surface in the second region.

[0016] In addition, the first region does not overlap with the second metal layer and the third plating layer, while the second region overlaps with the second metal layer and the third plating layer.

[0017] In addition, the first region overlaps with the third coating, and the second region overlaps with the second metal layer.

[0018] In addition, the area of ​​the first region is larger than the area of ​​the second region.

[0019] In addition, the surface roughness and surface free energy of one surface in the first region are greater than those of the other surface in the first region.

[0020] In addition, the surface roughness and surface free energy of one surface in the first region increase from the center region of the second bonding layer toward the edge region.

[0021] In addition, the surface roughness and surface free energy of the joint region are greater than those of the regions other than the joint region.

[0022] In addition, the surface free energy of one surface in the first region is 25 dyn / cm to 60 dyn / cm.

[0023] Beneficial effects

[0024] The smart IC substrate according to an embodiment includes a second bonding layer. A second metal layer and a third plating layer for forming wiring patterns are disposed on the second bonding layer.

[0025] The second bonding layer is divided into a first region and a second region. The first region does not overlap with at least one of the second metal layer and the third plating layer.

[0026] The second bonding layer is bonded to the card body. Specifically, the first region is bonded to the card body.

[0027] The surface roughness of the second bonding layer is related to the surface roughness of the second metal layer to be patterned. Specifically, after the second metal layer is patterned, the surface roughness of the second bonding layer is formed to be similar to that of the second metal layer. Therefore, when the surface roughness of the second metal layer is small, the surface roughness of the second bonding layer also becomes small. Consequently, the bonding force between the smart IC substrate and the card body may decrease.

[0028] Therefore, the first region has undergone surface treatment, while the second region has not. Consequently, the surface roughness and surface free energy of the first region increase. Therefore, the surface roughness and surface free energy of the first region are greater than those of the second region.

[0029] Therefore, the bonding force between the second bonding layer and the card body can be improved. This, in turn, improves the bonding force between the smart IC module and the card body. Consequently, the reliability of the IC card can be enhanced. Attached Figure Description

[0030] Figure 1 This is a plan view of the first surface of the smart IC substrate according to an embodiment.

[0031] Figure 2 This is a plan view of the second surface of the smart IC substrate according to an embodiment.

[0032] Figure 3 It is along Figure 2 A sectional view taken by line A-A'.

[0033] Figure 4 It is along Figure 2 The sectional view taken by line B-B'.

[0034] Figure 5 It is along Figure 2 A sectional view taken by line C-C'.

[0035] Figure 6 yes Figure 5 Enlarged views of regions A and B.

[0036] Figure 7 yes Figure 5 Scanning electron microscope images of regions A and B.

[0037] Figure 8 This is a plan view of the second surface of the smart IC module according to an embodiment.

[0038] Figure 9 It is along Figure 5 A sectional view taken by line D-D'.

[0039] Figure 10 It is along Figure 5 A sectional view taken from line E-E'.

[0040] Figure 11 It is along Figure 5 A sectional view taken from line E-E'.

[0041] Figure 12 This is an exploded perspective view of the IC card according to an embodiment. Detailed Implementation

[0042] In the following description, embodiments of the present disclosure will be illustrated in detail with reference to the accompanying drawings. However, the spirit and scope of the present disclosure are not limited to the portion of the described embodiments, and may be implemented in various other forms. Furthermore, one or more elements of the embodiments may be selectively combined and rearranged within the spirit and scope of the present disclosure.

[0043] Furthermore, unless otherwise explicitly defined and described, the terms (including technical and scientific terms) used in the embodiments of this disclosure may be interpreted as having the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains, and terms such as those defined in common dictionaries may be interpreted as having a meaning consistent with their meaning in the context of the relevant field.

[0044] Furthermore, the terminology used in the embodiments of this disclosure is for describing embodiments and is not intended to limit this disclosure. In this specification, unless specifically stated in the phrase, the singular form may also include the plural form, and when described as “at least one (or more) of A (and), B and C”, it may include at least one of all combinations that can be combined among A, B and C.

[0045] Furthermore, in describing the elements of embodiments of this disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are used only to distinguish elements from other elements, and these terms are not limited to the nature, order, or sequence of the elements.

[0046] In addition, when an element is described as being “connected,” “joined,” or “in contact” with another element, it can include not only cases where the element is directly “connected,” “joined,” or “in contact” with another element, but also cases where the element is “connected,” “joined,” or “in contact” with another element through which the element is connected, joined, or “in contact” with another element.

[0047] Additionally, when described as being formed or positioned “above” or “below” each element, “above” or “below” can include not only cases where two elements are directly connected to each other, but also cases where one or more other elements are formed or positioned between the two elements.

[0048] Furthermore, when expressed as "above" or "below", it can include not only the upward direction based on a single element, but also the downward direction based on a single element.

[0049] In the following description, a smart IC substrate, a smart IC module, and a smart IC card including the smart IC module according to an embodiment will be described with reference to the accompanying drawings.

[0050] Reference Figures 1 to 7 According to the embodiment, the smart IC substrate 1000 includes a substrate 100, bonding layers 210 and 220, metal layers 310 and 320, and a plating layer.

[0051] The substrate 100 includes a first surface 1S and a second surface 2S. The first surface 1S and the second surface 2S are surfaces opposite to each other.

[0052] The first surface 1S is a contact surface. Specifically, the first surface 1S is a surface capable of identifying information of the smart IC module through direct or indirect contact. Additionally, the second surface 2S is a bonding surface. Specifically, the second surface 2S is a surface on which the chip is mounted and bonded to the body of the IC card.

[0053] The substrate 100 comprises a resin material. The substrate 100 may include a prepreg containing glass fibers. Specifically, the substrate 100 may comprise a material in which glass fibers and silicone fillers are dispersed within an epoxy resin.

[0054] Alternatively, substrate 100 may be rigid or flexible. For example, substrate 100 may comprise glass or plastic. Specifically, substrate 100 may comprise chemically strengthened or semi-strengthened glass such as soda-lime glass or aluminosilicate glass. Alternatively, substrate 100 may comprise polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or sapphire.

[0055] Alternatively, substrate 100 may include an optically anisotropic film. For example, substrate 100 may include cyclic olefin copolymer (COC), cyclic olefin polymer (COP), optically anisotropic polycarbonate (PC), or optically anisotropic polymethyl methacrylate (PMMA).

[0056] Alternatively, the substrate 100 may be bent and partially have a curved surface. That is, the substrate 100 may be bent and partially have a flat surface and partially have a curved surface. Specifically, the ends of the substrate 100 may be bent and have curved surfaces. Alternatively, the substrate 100 may be bent and have a random curvature.

[0057] The substrate 100 can have a thickness within a set range. For example, the thickness of the substrate 100 can be 80 μm to 150 μm, 90 μm to 140 μm, or 100 μm to 120 μm. If the thickness of the substrate 100 is less than 80 μm, the supporting force of the substrate 100 decreases. If the thickness of the substrate 100 exceeds 150 μm, the thickness of the smart IC substrate may increase. Therefore, the size of the IC card increases.

[0058] The substrate 100 has insulating properties. Therefore, the substrate 100 prevents short circuits between circuits. In addition, the substrate 100 is used to support the circuits during the circuit formation process.

[0059] The substrate 100 includes holes. Specifically, the substrate 100 includes a plurality of holes H.

[0060] At least one of the multiple holes is a region where wire bonding is performed. For example, all of the multiple holes may be in a region where wire bonding is performed. Alternatively, a portion of the multiple holes may be in a region where wire bonding is performed. The chip C and the plating are wire bonded through hole H.

[0061] The aperture H has a width within a defined range. The width of aperture H can be defined as the diameter of the aperture or the minimum distance between the inner surfaces of the aperture. For example, the width of aperture H can be 500 μm to 1000 μm, 600 μm to 900 μm, or 700 μm to 800 μm. If the width of aperture H is less than 500 μm, wire bonding through aperture H becomes difficult. If the width of aperture H exceeds 1000 μm, the support strength of substrate 100 decreases.

[0062] Bonding layers 210 and 220 are disposed on the substrate 100. The bonding layers include a first bonding layer 210 and a second bonding layer 220. The first bonding layer 210 is disposed on a first surface 1S. The second bonding layer 220 is disposed on a second surface 2S.

[0063] Bonding layers 210 and 220 comprise a resin material. For example, bonding layers 210 and 220 may comprise at least one selected from epoxy resin, acrylic resin, and polyimide resin. Additionally, bonding layers 210 and 220 may comprise at least one additive selected from natural rubber, plasticizer, curing agent, and phosphorus-based flame retardant. Therefore, the flexibility of bonding layers 210 and 220 is improved.

[0064] Bonding layers 210 and 220 can have thicknesses within a defined range. For example, the thicknesses of bonding layers 210 and 220 can be 15 μm to 35 μm, 20 μm to 30 μm, or 22 μm to 28 μm. If the thickness of bonding layers 210 and 220 is less than 15 μm, the adhesive strength of bonding layers 210 and 220 decreases. Therefore, the metal layer on bonding layer 200 may peel off. Additionally, if the thickness of bonding layers 210 and 220 exceeds 35 μm, the thickness of the smart IC substrate may increase. Therefore, the size of the IC card increases.

[0065] Metal layers 310 and 320 are disposed on the substrate 100. The metal layers include a first metal layer 310 and a second metal layer 320. The first metal layer 310 is disposed on the first bonding layer 210. The second metal layer 320 is disposed on the second bonding layer 220.

[0066] Metal layers 310 and 320 comprise a metallic material. For example, metal layers 310 and 320 may comprise at least one material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, metal layers 310 and 320 comprise copper.

[0067] Metal layers 310 and 320 can have thicknesses within a defined range. For example, the thicknesses of metal layers 310 and 320 can be 30 μm to 75 μm, 40 μm to 65 μm, or 50 μm to 60 μm. If the thickness of metal layers 310 and 320 is less than 30 μm, the resistance of metal layers 310 and 320 increases. Conversely, if the thickness of metal layers 310 and 320 exceeds 75 μm, the thickness of the smart IC substrate may increase. Therefore, the size of the IC card increases. Additionally, process efficiency may decrease.

[0068] Metal layers 310 and 320 form a conductive pattern P and a wiring pattern 500.

[0069] The first metal layer 310 forms multiple conductive patterns P. The conductive patterns P are formed by patterning the metal layer 300.

[0070] A conductive pattern P is disposed on the first surface 1S. A conductive pattern P is disposed on the first bonding layer 210. A conductive pattern P is disposed on the contact surface.

[0071] The conductive patterns P are spaced apart from each other. Holes H are located in the regions corresponding to each conductive pattern P.

[0072] The second metal layer 320 forms a wiring pattern 500.

[0073] Wiring pattern 500 is disposed on second surface 2S, and wiring pattern 500 is disposed on second bonding layer 220. Wiring pattern 500 is disposed on bonding surface.

[0074] Wiring pattern 500 connects to an external antenna pattern. Therefore, the smart IC module can be driven in a non-contact manner.

[0075] The wiring pattern 500 may include a wiring portion 510 and a connecting portion 520.

[0076] The wiring section 510 may include a first wiring section 511, a second wiring section 512, and a third wiring section 513. The first wiring section 511 and the connecting section 520 are disposed inside the molding area MA. The second wiring section 512 and the third wiring section 513 are disposed outside the molding area MA.

[0077] The first wiring section 511 and the third wiring section 513 can be connected by the second wiring section 512.

[0078] The first wiring section 511, the second wiring section 512, and the third wiring section 513 can have different line widths. For example, the line width of the second wiring section 512 can be greater than the line width of the first wiring section 511. Therefore, after the molding section M is provided inside the molding area MA, damage to the wiring sections provided outside the molding section M can be prevented.

[0079] The linewidth of the third wiring section 513 can be greater than that of the first wiring section 511 and the second wiring section 512. The third wiring section 513 is the area connected to the antenna pattern. Because the linewidth of the third wiring section 513 is larger, the smart IC substrate and the antenna pattern can be easily connected.

[0080] The connecting portion 520 may include a first connecting portion 521 and a second connecting portion 522. Specifically, at least one of the plurality of wiring patterns may include the first connecting portion 521 and the second connecting portion 522.

[0081] The dimensions of the first connecting portion 521 and the second connecting portion 522 can be smaller than the dimension of the hole H. Furthermore, the dimension of the second connecting portion 522 can be smaller than the dimension of the third wiring portion 513. For example, the area of ​​the second connecting portion 522 can be smaller than the area of ​​the third wiring portion 513. Therefore, a wider space can be ensured for the chip mounting area, and the package size can be reduced.

[0082] Furthermore, either the first connection portion 521 or the second connection portion 522 is wire-bonded to the chip. The connection portion includes two or more connection portions. Therefore, when a problem occurs in the wire bonding at one connection portion, the problem can be solved by additionally performing wire bonding on another connection portion. For example, when a problem occurs in the wire bonding of the first connection portion 521, additional wire bonding can be performed on the second connection portion 522.

[0083] The plating layer is disposed on the metal layer 300. The plating layer may include a first plating layer 410, a second plating layer 420, and a third plating layer 430.

[0084] The first plating layer 410, the second plating layer 420, and the third plating layer 430 are distinguished by their positions. The first plating layer 410, the second plating layer 420, and the third plating layer 430 are located in different positions from each other.

[0085] A first plating layer 410 is disposed on one surface 311 of the first metal layer 310. A second plating layer 420 is disposed on the other surface 312 of the first metal layer 310. The second plating layer 420 is disposed in the region overlapping with the via H. The second plating layer 420 may be a pad portion for wire bonding. A third plating layer 430 is disposed on one surface 321 of the second metal layer 320. The wiring pattern 500 is formed by the second metal layer 320 and the third plating layer 430. The third plating layer 430 may be a pad portion for wire bonding.

[0086] The first plating layer 410 includes a first-1 layer 411 and a first-2 layer 412. The first-1 layer 411 contacts the first metal layer 310. The first-2 layer 412 contacts the first-1 layer 411. Therefore, the first-1 layer 411 is disposed between the first metal layer 310 and the first-2 layer 412.

[0087] Although not shown in the accompanying drawings, an organic coating may be applied to the first and second layers 412. The organic coating protects the first and second layers 412. Therefore, corrosion of the first and second layers 412 can be prevented.

[0088] The second plating layer 420 includes a second-1 layer 421 and a second-2 layer 422. The second-1 layer 421 contacts the first metal layer 310. The second-2 layer 422 contacts the second-1 layer 421. Therefore, the second-1 layer 421 is disposed between the first metal layer 310 and the second-2 layer 422.

[0089] The third plating layer 430 includes a third-first layer 431 and a third-second layer 432. The third-first layer 431 contacts the second metal layer 320. The third-second layer 432 contacts the third-first layer 431. Therefore, the third-first layer 431 is disposed between the second metal layer 320 and the third-second layer 432.

[0090] Layer 1-1 411 and Layer 2-1 421 may contain the same material. Specifically, Layer 1-1 411 and Layer 2-1 421 may contain the same metal. For example, Layer 1-1 411 and Layer 2-1 421 may contain nickel.

[0091] Layer 1-2 412 and Layer 2-2 422 may contain the same material. Specifically, Layer 1-2 412 and Layer 2-2 422 may contain the same metal. For example, Layer 1-2 412 and Layer 2-2 422 may contain gold (Au) or palladium (Pd).

[0092] The first plating layer 410 and the second plating layer 420 can have different dimensions. Specifically, the thickness T1 of the first plating layer 410 and the thickness T2 of the second plating layer 420 can be different.

[0093] The thickness T2 of the second plating layer 420 is greater than the thickness T1 of the first plating layer 410. The thickness T1-1 of the first-1 layer 411 and the thickness T2-1 of the second-1 layer 421 can be different. Specifically, the thickness T1-1 of the first-1 layer 411 can be less than the thickness T2-1 of the second-1 layer 421. Furthermore, the thickness T1-2 of the first-2 layer 412 and the thickness T2-2 of the second-2 layer 422 can be different. Specifically, the thickness T1-2 of the first-2 layer 412 can be less than the thickness T2-2 of the second-2 layer 422. Therefore, the thickness T2 of the second plating layer 420 is greater than the thickness T1 of the first plating layer 410.

[0094] The third plating layer 430 may contain the same material as the second plating layer 420. For example, the third-first layer 431 may contain nickel. In addition, the third-second layer 432 may contain gold (Au) or palladium (Pd).

[0095] Reference Figure 5 The second bonding layer 220 can be divided into a first region 1A and a second region 2A. The first region 1A and the second region 2A are divided by a wiring pattern 500. The wiring pattern 500 is formed by a second metal layer 320 and a third plating layer 430.

[0096] The first region 1A is the region in which no wiring pattern 500 is provided. The second region 2A is the region in which the wiring pattern 500 is provided. The second region 2A overlaps with at least one of the second metal layer 320 and the third plating layer 430.

[0097] The first region 1A includes a joining region CA. The joining region CA may be located at the edge of the second joining layer 220. For example, the joining region CA may be located at two edges facing each other, or the joining region CA may extend along the edge of the second joining layer 220.

[0098] The area of ​​the first region 1A is different from the area of ​​the second region 2A. For example, the area of ​​the first region 1A can be larger than the area of ​​the second region 2A.

[0099] Region 1A is a surface that has undergone surface treatment. Region 2A is a surface that has not undergone surface treatment.

[0100] The second bonding layer 220 has one surface 221 and another surface 222 opposite to the first surface 221. One surface 221 contacts the wiring pattern 500. The other surface 222 contacts the substrate 100.

[0101] The surface roughness of the other surface 222 can be uniformly the same or similar. Furthermore, the surface free energy of the other surface 222 can be uniformly the same or similar.

[0102] The surface roughness of a surface 221 can vary depending on the region. Additionally, the surface free energy of a surface 221 can vary depending on the region.

[0103] The first region 1A may have different surface roughnesses on one surface and another surface. Specifically, the surface roughness of one surface of the first region 1A may be greater than the surface roughness of the other surface of the first region 1A. Additionally, the first region 1A may have different surface free energies on one surface and another surface. Specifically, the surface free energy of one surface of the first region 1A may be greater than the surface free energy of the other surface of the first region 1A.

[0104] The second region 2A can have the same or similar surface roughness on one surface and another surface. Additionally, the second region 2A can have the same or similar surface free energy on one surface and another surface.

[0105] The surface roughness of the other surface of the first region 1A and the other surface of the second region 2A can be the same or similar. The surface free energy of the other surface of the first region 1A and the other surface of the second region 2A can be the same or similar.

[0106] The surface roughness of a surface in the first region 1A and a surface in the second region 2A can be different. The surface roughness of a surface in the first region 1A can be greater than the surface roughness of a surface in the second region 2A.

[0107] The surface free energies of a surface in the first region 1A and a surface in the second region 2A can be different. The surface free energy of a surface in the first region 1A can be greater than the surface free energy of a surface in the second region 2A.

[0108] For example, the surface free energy of a surface of the first region 1A may be 25 dyn / cm or more. Specifically, the surface free energy of a surface of the first region 1A may be 25 to 60 dyn / cm, 30 to 50 dyn / cm, or 35 to 45 dyn / cm.

[0109] Furthermore, the surface free energy of one surface in the second region 2A can be less than 25 dyn / cm. Specifically, the surface free energy of one surface in the second region 2A can be greater than 0 and less than 25 dyn / cm.

[0110] The surface free energy was measured using a DSA305 instrument. The surface free energy was calculated using OWRK.

[0111] A second metal layer 320 is disposed on a surface 221. The second metal layer 320 is patterned to form a wiring pattern 500. Subsequently, a third plating layer 430 is formed on the outer surface of the patterned second metal layer 320.

[0112] When the process is carried out in this manner, the first region 1A is defined as the region that does not overlap with the second metal layer 320 and the third plating layer 430.

[0113] Subsequently, a surface 221 can be pretreated. For example, a wet treatment can be performed on a surface 221. For example, a decontamination process can be used to treat a surface 221.

[0114] Therefore, the first region 1A undergoes surface treatment. Consequently, the surface roughness of the first region 1A increases. Additionally, the surface free energy of the first region 1A increases.

[0115] The first region 1A includes the joining region CA. The surface roughness and surface free energy of the joining region CA are also increased. Therefore, when the joining region CA and the receiving part of the card body are joined, the bonding force between the second joining layer 220 and the receiving part increases.

[0116] The process sequence on a surface 221 can be different. For example, a second metal layer 320 may be formed on a surface 221. The second metal layer 320 may be patterned to form a wiring pattern 500. Subsequently, a surface 221 may be pretreated. For example, a wet treatment may be performed on a surface 221. For example, a decontamination process may be used to treat a surface 221. Afterward, a third plating layer 430 is formed on the outer surface of the patterned second metal layer 320.

[0117] When the process is performed in this manner, the first region 1A is defined as a region that does not overlap with the second metal layer 320. Additionally, the first region 1A overlaps with the third plating layer 430.

[0118] The first region 1A includes the joining region CA. The surface roughness and surface free energy of the joining region CA are also increased. Therefore, when the joining region CA and the receiving part of the card body are joined, the bonding force between the second joining layer 220 and the receiving part increases.

[0119] Furthermore, the second bonding layer 220 is non-metallic, while the third plating layer 430 is metallic. Therefore, the bonding strength between the second bonding layer 220 and the third plating layer 430 may be reduced.

[0120] A third plating layer 430 is disposed on the first region 1A. Therefore, the third plating layer 430 is disposed on the surface-treated second bonding layer 220. Therefore, the bonding force between the third plating layer 430 and the second bonding layer 220 can be increased.

[0121] The surface roughness and surface free energy of a surface 221 in the first region 1A can vary for each region. For example, the surface roughness and surface free energy of a surface 221 can be maximum in the bonding region CA. For example, the surface roughness and surface free energy of a surface 221 can increase as it extends from the central region of the second bonding layer 220 toward the edge region.

[0122] Therefore, the surface roughness and surface free energy of one surface 221 in the bonding region CA become greater than those of other regions. This increases the bonding force between the second bonding layer 220 and the card body.

[0123] The first region 1A may optionally include regions with large surface roughness and surface free energy.

[0124] For example, the surface roughness and surface free energy of one surface 221 of the joining region CA can be greater than the surface roughness and surface free energy of one surface 221 of the first region other than the joining region CA and one surface 221 of the second region. That is, the surface roughness and surface free energy of one surface of the first region other than the joining region CA can be the same as or similar to the surface roughness and surface free energy of one surface of the second region.

[0125] Therefore, the surface roughness and surface free energy of the bonding region CA become greater than those of other regions. This increases the bonding force between the second bonding layer 220 and the card body.

[0126] Figure 6 and Figure 7 It is a diagram of a surface 221 used to compare the first region 1A and the second region 2A.

[0127] Figure 6 (a) and Figure 7(a) is a diagram of the first region 1A. Figure 6 (b) and Figure 7 (b) is a diagram of the second region 2A.

[0128] Reference Figure 6 and Figure 7 The first region 1A undergoes surface treatment. Therefore, the surface roughness and surface free energy of surface 221 of the first region 1A increase. Conversely, the second region 2A is not surface treated. Therefore, the surface roughness and surface free energy of surface 221 of the second region 2A are less than those of the first region 1A.

[0129] The smart IC substrate according to an embodiment includes a second bonding layer. A second metal layer and a third plating layer for forming wiring patterns are disposed on the second bonding layer.

[0130] The second bonding layer is divided into a first region and a second region. The first region does not overlap with at least one of the second metal layer and the third plating layer.

[0131] The second bonding layer is bonded to the card body. Specifically, the first region is bonded to the card body.

[0132] The surface roughness of the second bonding layer is related to the surface roughness of the second metal layer to be patterned. Specifically, after the second metal layer is patterned, the surface roughness of the second bonding layer is formed to be similar to that of the second metal layer. Therefore, when the surface roughness of the second metal layer is small, the surface roughness of the second bonding layer also becomes small. Consequently, the bonding force between the smart IC substrate and the card body may decrease.

[0133] Therefore, the first region undergoes surface treatment, while the second region remains untreated. Consequently, the surface roughness and surface free energy of the first region increase. Consequently, the surface roughness and surface free energy of the first region become greater than those of the second region.

[0134] Therefore, the bonding force between the second bonding layer 220 and the card body is increased. Consequently, the bonding force between the smart IC module and the card body is increased. Therefore, the reliability of the IC card can be improved.

[0135] The invention will be described in detail below with reference to examples and comparative examples.

[0136] Example

[0137] The above-mentioned smart IC substrate is manufactured.

[0138] Subsequently, the surface of the second bonding layer is surface treated. Specifically, the surface of the second bonding layer is surface treated through a decontamination process.

[0139] Subsequently, the second bonding layer and the card body are joined. Specifically, the adhesive layer is disposed inside the receiving portion of the card body. The second bonding layer and the card body are joined by the adhesive layer.

[0140] Subsequently, the adhesion between the second bonding layer and the card body was measured using a BFG-200N device.

[0141] Adhesive force was measured at a peel speed of 10 mm / min, a 90-degree angle, and a maximum peel load of 20 kgf.

[0142] Comparative example

[0143] The second bonding layer and the card body are joined without surface treatment of the second bonding layer.

[0144] Subsequently, the adhesive force between the second bonding layer and the card body was measured using the same method as in the example.

[0145] Table 1

[0146] Referring to Table 1, it can be seen that the surface free energy of the example is greater than that of the comparative example. Furthermore, it can be seen that the adhesive force of the example is greater than that of the comparative example.

[0147] In this example, the second bonding layer undergoes surface treatment. Therefore, the surface free energy of the second bonding layer increases. Consequently, the adhesion between the smart IC substrate and the card body can be increased due to the improved adhesion to the bonding layer.

[0148] In the following text, reference will be made to Figures 8 to 10 A smart IC module according to an embodiment is described.

[0149] Reference Figures 8 to 10 The smart IC module 2000 includes the aforementioned smart IC substrate 1000 and chip C.

[0150] Chip C is disposed on the second bonding layer 220.

[0151] Chip C is connected to the second plating layer 420 and the third plating layer 430. Specifically, chip C and the second plating layer 430 are wire-bonded via wiring W. Therefore, chip C is electrically connected to the conductive pattern P. Additionally, chip C and the third plating layer 430 are wire-bonded via wiring W. Therefore, chip C is electrically connected to the antenna pattern via wiring pattern 500.

[0152] A molded component M is provided on chip C. The molded component M is configured to cover chip C and wiring W. Therefore, damage to the wiring due to external impact can be prevented.

[0153] In the following text, reference will be made to Figure 11 and Figure 12 Describes an IC card according to an embodiment.

[0154] Reference Figure 11 and Figure 12 The IC card 3000 may include a main body 3100, an upper layer 3210, and a lower layer 3220.

[0155] The main body 3100 includes a receiving section 3110. The intelligent IC module 2000 is disposed inside the receiving section 3110.

[0156] IC cards can be driven in various modes. For example, an IC card can be driven as a contact card.

[0157] Alternatively, an antenna pattern (not shown) may be provided on the main body 3100. Specifically, the antenna pattern may be provided in the shape of a coil at the edge of the main body 3100. Therefore, the IC card can be driven as a contactless card, a combination card, or a hybrid card.

[0158] The smart IC module 2000 is inserted into the housing portion 3110. The smart IC module 2000 and the main body portion 3100 are joined by the adhesive layer 3500. Therefore, the smart IC module 2000 is inserted into and fixed in the housing portion 3110.

[0159] Specifically, the main body 3100 is bonded to the second bonding layer 220. The main body 3100 is bonded to the first region 1A. The first region 1A has undergone surface treatment. Therefore, the adhesion between the smart IC module 2000 and the main body 3100 is improved.

[0160] The upper layer 3210 is disposed on the upper part of the main body 3100. The upper layer 3210 may contain a transparent material. The upper layer 3210 may contain a transparent resin material. The upper layer 3210 may be configured as at least one layer. That is, the upper layer 3210 may include multiple layers.

[0161] The lower layer 3220 is disposed at the lower part of the main body 3100. A magnetic strip can be disposed on the lower layer 3220. The lower layer 3220 may contain a transparent material. The lower layer 3220 may contain a transparent resin material. The lower layer 3220 may be configured as at least one layer. That is, the lower layer 3220 may include multiple layers.

[0162] The features, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. Furthermore, those skilled in the art to which the embodiments pertain can combine or modify the features, structures, and effects shown in each embodiment with respect to other embodiments. Therefore, it should be understood that such combinations and modifications are included within the scope of the embodiments.

[0163] The description focuses on embodiments, but is illustrative only and does not limit the embodiments. Those skilled in the art will understand that various modifications and applications not shown above are possible without departing from the essential characteristics of the embodiments. For example, various components specifically represented in the embodiments can be modified and implemented. Furthermore, it should be understood that differences involving such changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A smart IC substrate, comprising: A substrate, the substrate including a first surface and a second surface opposite to the first surface; A first bonding layer is disposed on the first surface; A first metal layer is disposed on the first bonding layer; A second bonding layer is disposed on the second surface; A second metal layer is disposed on the second bonding layer; A first coating is disposed on one surface of the first metal layer; A second coating is disposed on another surface of the first metal layer; as well as A third plating layer is disposed on one surface of the second metal layer. The second bonding layer includes a first region and a second region. The second bonding layer has one surface that contacts the second metal layer and another surface that contacts the substrate. The first region includes a bonding region. Wherein, the second region overlaps with at least one of the second metal layer and the third plating layer, and The surface roughness of one surface in the first region is greater than the surface roughness of one surface in the second region.

2. The smart IC substrate according to claim 1, wherein, The surface free energy of a surface in the first region is greater than the surface free energy of a surface in the second region.

3. The smart IC substrate according to claim 1, wherein, The first region does not overlap with the second metal layer and the third plating layer, and The second region overlaps with the second metal layer and the third plating layer.

4. The smart IC substrate according to claim 1, wherein, The first region overlaps with the third coating, and The second region overlaps with the second metal layer.

5. The smart IC substrate according to claim 1, wherein, The area of ​​the first region is larger than the area of ​​the second region.

6. The smart IC substrate according to claim 1, wherein, The surface roughness and surface free energy of one surface in the first region are greater than the surface roughness and surface free energy of the other surface in the first region.

7. The smart IC substrate according to claim 1, wherein, The surface roughness and surface free energy of the first region increase from the center region of the second bonding layer toward the edge region.

8. The smart IC substrate according to claim 1, wherein, The surface roughness and surface free energy of the joint region are greater than those of the regions other than the joint region.

9. The smart IC substrate according to claim 1, wherein, The surface free energy of one surface in the first region is 25 dyn / cm to 60 dyn / cm.

10. A smart IC module, comprising: The smart IC substrate according to any one of claims 1 to 9; as well as A chip, wherein the chip is disposed on the second surface or the other surface of the first metal layer. The chip leads are bonded to the second or fourth plating layer.

Images