Hybrid clocking scheme for serdes physical layer circuitry
By using inverters and tunable capacitors to generate multiphase clock signals in SERDES, the data error problem caused by the drift of clock signal frequency and phase relationship is solved, realizing low-power and high-efficiency clock generation and calibration, and improving the reliability of data transmission.
CN122139300APending Publication Date: 2026-06-02QUALCOMM INC
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- QUALCOMM INC
- Filing Date
- 2024-10-29
- Publication Date
- 2026-06-02
AI Technical Summary
Technical Problem
In high-speed serial links, drift in the frequency and phase relationship of the SERDES clock signal leads to data errors, and existing technologies struggle to provide reliable, low-power clock generation and calibration circuits.
Method used
A clock generation circuit including a first inverter, a second inverter, and a tunable capacitor is used. Multiphase clock signals are generated by configuring driver slices and tunable capacitors. Differential enable signals are used to control the switching on and off of transistors to achieve the generation of quadrature clock signals.
Benefits of technology
It effectively reduces power consumption while ensuring the reliability and accuracy of the clock signal, thereby improving the reliability and efficiency of data transmission.
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Figure CN122139300A_ABST
Abstract
The clock generation circuit includes a first inverter coupled to an input clock signal and having multiple driver slices. Each driver slice includes a first transistor with a gate coupled to the input clock signal and a second transistor with a source coupled to a rail of power supply. Each of the second transistors has a drain coupled to the source of one of the first transistors. The second transistors are turned on or off based on the signaling state of a differential enable signal. A tuning resistor is coupled to the drain of the first transistor and further coupled to the output of the first inverter. The second inverter outputs a quadrature version of the input clock signal and has an input coupled to the output of the first inverter. A first tunable capacitor is coupled to the output of the first inverter.
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