Electrical apparatus

Abstract

This invention relates to an electrical device. An embodiment of the electrical device includes: a first circuit board having a first signal processing device; and a second circuit board having a second signal processing device. The first signal processing device has a processor, a main communication interface, and a peripheral device communication interface. The main communication interface is used for data communication with the second signal processing device. The second signal processing device has a slave communication interface and a second peripheral device communication interface. The slave communication interface is used for data communication with the first signal processing device. The main communication interface transmits a first interrupt to the processor, and the second peripheral device communication interface transmits a second interrupt to the slave communication interface. Thus, stable and scalable data communication can be performed.

Description

Technical Field

[0001] This invention relates to electrical equipment, and more specifically, to electrical equipment capable of reliably performing scalable data communication. Background Technology

[0002] Electrical equipment can be electrical equipment used in the home, such as washing machines, refrigerators, and air conditioners.

[0003] As electrical equipment becomes more sophisticated, various functions are being added to it.

[0004] Therefore, multiple signal processing devices are used within the electrical equipment, and data communication is performed between the various signal processing devices.

[0005] For example, in the case of data communication between signal processing devices, when using UART (Universal Asynchronous Serial Receiver and Transmitter), which is an example of serial communication, data communication becomes less smooth as the number of signal processing devices increases because data is transmitted in a cascade manner. Summary of the Invention

[0006] The problem the invention aims to solve

[0007] The purpose of this invention is to provide an electrical device capable of stably performing scalable data communication.

[0008] On the other hand, another object of the present invention is to provide an electrical device capable of stably performing scalable data communication between signal processing devices or between circuit boards.

[0009] On the other hand, another object of the present invention is to provide an electrical device that can apply general data communication to various types of electrical devices.

[0010] means for solving problems

[0011] An electrical device according to an embodiment of the present invention for solving the above-mentioned problems includes: a first circuit board having a first signal processing device; and a second circuit board having a second signal processing device; the first signal processing device includes: a processor, a main communication interface, and a peripheral device communication interface, the main communication interface being used for data communication with the second signal processing device, the second signal processing device including: a slave communication interface and a second peripheral device communication interface, the slave communication interface being used for data communication with the first signal processing device, the main communication interface transmitting a first interrupt to the processor, and the second peripheral device communication interface transmitting a second interrupt to the slave communication interface.

[0012] On the other hand, the main communication interface can transmit control commands, and the secondary communication interface can receive control commands.

[0013] On the other hand, the main communication interface can output serialized data or deserialize received serialized data.

[0014] On the other hand, the first signal processing device may also have a bus for a peripheral device communication interface, which can exchange data with the processor or the main communication interface.

[0015] On the other hand, the main communication interface can control communication with the bus or generate data based on the communication protocol.

[0016] On the other hand, the second signal processing device may also have a second bus for a second peripheral device communication interface, the second bus being able to exchange data with the communication interface.

[0017] On the other hand, the communication interface can control communication with the second bus or generate data based on the communication protocol.

[0018] On the other hand, the first signal processing device may also have a clock signal generator that generates clock signals, and the main communication interface may output data signals and clock signals.

[0019] On the other hand, the first signal processing device can deserialize the received serialized data based on the clock signal from the clock signal generator.

[0020] On the other hand, the main communication interface can control the data communication to stop within a specified time when the data communication line occupancy rate exceeds a baseline value.

[0021] On the other hand, the control commands received from the main communication interface can be transmitted from the communication interface to the second peripheral device communication interface. If the second peripheral device communication interface does not respond within a set time, the generated error response signal and the second interrupt from the second peripheral device communication interface are transmitted to the main communication interface.

[0022] On the other hand, the general address data output from the main communication interface may include key information, register indicator information, slave indicator information, and address information.

[0023] On the other hand, the transmission address data output from the main communication interface may include transmission address information, receiving address information, and monitoring information.

[0024] On the other hand, the received data from the main communication interface may include error information and interrupt information.

[0025] On the other hand, the master communication interface or slave communication interface may include a differential end interface.

[0026] On the other hand, the master communication interface or slave communication interface may include a single-end interface.

[0027] On the other hand, an electrical device according to an embodiment of the present invention includes: a third circuit board having a third signal processing device, the third signal processing device having a second slave communication interface and a third peripheral device communication interface, the second slave communication interface being used for data communication with a first signal processing device, and the third peripheral device communication interface being able to transmit a third interrupt to the second slave communication interface.

[0028] On the other hand, the main communication interface can transmit control commands, while the slave communication interface and the second slave communication interface can receive control commands.

[0029] On the other hand, the second slave communication interface can transmit the control commands received from the master communication interface to the third peripheral device communication interface. If the third peripheral device communication interface does not respond within a second set time, it will transmit the generated second error response signal and the third interrupt from the third peripheral device communication interface to the master communication interface.

[0030] In another embodiment of the present invention, an electrical device includes a first signal processing device, a second signal processing device, and a third signal processing device. The first signal processing device has a processor and a main communication interface, the main communication interface being used for data communication with the second signal processing device. The second signal processing device has a slave communication interface, the slave communication interface being used for data communication with the first signal processing device. The third signal processing device has a second slave communication interface, the second slave communication interface being used for data communication with the first signal processing device. The main communication interface transmits control commands, and the slave communication interface and the second slave communication interface receive control commands.

[0031] The effects of the invention

[0032] An embodiment of the present invention provides an electrical device comprising: a first circuit board having a first signal processing device; and a second circuit board having a second signal processing device. The first signal processing device includes a processor, a main communication interface, and a peripheral device communication interface. The main communication interface is used for data communication with the second signal processing device. The second signal processing device includes a slave communication interface and a second peripheral device communication interface. The slave communication interface is used for data communication with the first signal processing device. The main communication interface transmits a first interrupt to the processor, and the second peripheral device communication interface transmits a second interrupt to the slave communication interface. This enables stable and scalable data communication. In particular, it enables stable and scalable data communication between circuit boards. Furthermore, it allows general-purpose data communication to be applied to various types of electrical devices.

[0033] On the other hand, the main communication interface can transmit control commands, and the slave communication interface can receive control commands. This enables stable and scalable data communication.

[0034] On the other hand, the main communication interface can output serialized data or deserialize received serialized data. This enables stable and scalable data communication.

[0035] On the other hand, the first signal processing device also has a bus for peripheral device communication interfaces, which can exchange data with the processor or the main communication interface. This enables stable and scalable data communication.

[0036] On the other hand, the main communication interface can control the communication between the main communication interface and the bus or generate data based on the communication protocol. This enables stable and scalable data communication.

[0037] On the other hand, the second signal processing device also has a second bus for a second peripheral device communication interface, which can exchange data with the communication interface. This enables stable and scalable data communication.

[0038] On the other hand, the communication interface can control communication with the second bus or generate data based on the communication protocol. This enables stable and scalable data communication.

[0039] On the other hand, the first signal processing device also has a clock signal generator for generating clock signals, and the main communication interface can output data signals and clock signals. Therefore, stable and scalable data communication can be performed.

[0040] On the other hand, the first signal processing device can deserialize the received serialized data based on the clock signal from the clock signal generator. This enables stable and scalable data communication.

[0041] On the other hand, the main communication interface can control data communication to stop within a specified time when the data communication line occupancy rate exceeds a baseline value. This enables stable and scalable data communication.

[0042] On the other hand, the communication interface can transmit control commands received from the main communication interface to the second peripheral device communication interface. If the second peripheral device communication interface does not respond within a set time, it will transmit a generated error response signal and a second interrupt from the second peripheral device communication interface to the main communication interface. This enables stable and scalable data communication.

[0043] On the other hand, the general address data output from the main communication interface can include key information, register indicator information, slave indicator information, and address information. This enables stable and scalable data communication.

[0044] On the other hand, the transmission address data output from the main communication interface can include transmission address information, receiving address information, and monitoring information. This enables stable and scalable data communication.

[0045] On the other hand, the received data at the main communication interface can include error messages and interrupt messages. This enables stable and scalable data communication.

[0046] On the other hand, the master or slave communication interface may include a differential end interface. This enables stable and scalable data communication.

[0047] On the other hand, the master or slave communication interface can include a single-end interface. This enables stable and scalable data communication.

[0048] On the other hand, an electrical device according to an embodiment of the present invention includes: a third circuit board having a third signal processing device, the third signal processing device having a second slave communication interface and a third peripheral device communication interface, the second slave communication interface being used for data communication with the first signal processing device, and the third peripheral device communication interface transmitting a third interrupt to the second slave communication interface. Thus, stable and scalable data communication can be performed.

[0049] On the other hand, the main communication interface can transmit control commands, while the slave communication interface and the second slave communication interface can receive control commands. This enables stable and scalable data communication.

[0050] On the other hand, the second slave communication interface can transmit control commands received from the master communication interface to the third peripheral device communication interface. If the third peripheral device communication interface does not respond within a second set time, it will transmit a generated second error response signal and a third interrupt from the third peripheral device communication interface to the master communication interface. This enables stable and scalable data communication.

[0051] Another embodiment of the electrical device of the present invention includes a first signal processing device, a second signal processing device, and a third signal processing device. The first signal processing device has a processor and a main communication interface for data communication with the second signal processing device. The second signal processing device has a slave communication interface for data communication with the first signal processing device. The third signal processing device has a second slave communication interface for data communication with the first signal processing device. The main communication interface transmits control commands, and the slave and second slave communication interfaces receive the control commands. This enables stable and scalable data communication. In particular, it enables stable and scalable data communication between circuit boards. Furthermore, it allows the application of general-purpose data communication to various types of electrical devices. Attached Figure Description

[0052] Figure 1 This is an example of an electrical equipment system structure diagram that includes an electrical device according to an embodiment of the present invention.

[0053] Figures 2a to 2e To show Figure 1 Diagrams showing various examples of electrical equipment.

[0054] Figure 3a This is an example of an internal block diagram of an electrical device related to the present invention.

[0055] Figure 3b for Figure 3a The diagram referenced in the description.

[0056] Figure 4 This is an example of an internal block diagram of an electrical device according to an embodiment of the present invention.

[0057] Figures 5 to 11 for Figure 4 The diagram referenced in the description. Detailed Implementation

[0058] The present invention will now be described in more detail with reference to the accompanying drawings.

[0059] The suffixes “module” and “section” used in the following description for the purpose of ease of writing this specification are merely assigned and do not inherently possess any particularly important meaning or function. Therefore, the terms “module” and “section” can be used interchangeably.

[0060] Figure 1 This is an example of an electrical equipment system structure diagram that includes an electrical device according to an embodiment of the present invention.

[0061] Referring to the accompanying drawings, an electrical equipment system 10 according to an embodiment of the present invention may include electrical equipment 200, mobile terminal 600, and server 500.

[0062] In addition, the electrical equipment system 10 may also have an access point (AP) device (not shown) for connecting the electrical equipment 200 to an external network.

[0063] The electrical equipment 200 has displays such as LEDs and LCDs, sensors, and multiple signal processing devices, and can operate based on sensor signals from the sensors.

[0064] For example, electrical equipment 200 may also include a motor, magnetron, or heater for load control, etc.

[0065] On the other hand, the electrical equipment 200 may have an inverter that converts DC power to AC power in order to effectively control a motor, magnetron, or heater.

[0066] On the other hand, the mobile terminal 600 performs wireless communication with the electrical equipment 200, and can remotely control the wirelessly connected electrical equipment 200 or receive monitoring data from the electrical equipment 200.

[0067] On the other hand, server 500 can provide data to electrical equipment 200 connected via a network or the like.

[0068] For example, server 500 can provide updated information to electrical equipment 200 based on a request from mobile terminal 600.

[0069] As another example, server 500 can provide updated information to electrical device 200 when necessary, even without a request from mobile terminal 600 or electrical device 200.

[0070] On the other hand, update information can include firmware update information, software update information, etc.

[0071] An embodiment of the present invention provides an electrical device 200 having a first signal processing device ( Figure 4 410) and the second signal processing device ( Figure 4 420), the first signal processing device 410 has a processor ( Figure 5 518), main communication interface ( Figure 5 410b) and peripheral device communication interface 512, the main communication interface being used for data communication with the second signal processing device 420, the second signal processing device 420 having a slave communication interface ( Figure 5 420b) and the second peripheral device communication interface ( Figure 5 The second peripheral communication interface 532 (532) is used for data communication with the first signal processing device 410, the main communication interface 410b transmits a first interrupt to the processor 518, and the second peripheral device communication interface 532 transmits a second interrupt to the slave communication interface 420b. This enables stable and scalable data communication. In particular, it enables stable and scalable data communication between circuit boards. Furthermore, it enables the application of universal data communication to various types of electrical equipment.

[0072] On the other hand, there may be various examples of the electrical device 200 used in this invention. This can be achieved through... Figures 2a to 2e Example provided.

[0073] Figures 2a to 2e To show Figure 1 Diagrams showing various examples of electrical equipment.

[0074] Figure 2a An example of a washing machine 200a as an electrical device is given.

[0075] In the case where the electrical equipment 200 is a washing machine 200a, the washing machine 200a may have a washing tub motor (not shown) and an inverter (not shown) for rotating the washing tub motor in order to rotate the washing tub.

[0076] Figure 2b The refrigerator 200b is shown as an example of an electrical device.

[0077] In the case where the electrical equipment 200 is a refrigerator 200b, in order to supply cold air into the refrigerator, the refrigerator 200b may have a compressor (not shown), a compressor motor (not shown) for operating the compressor, and an inverter (not shown) for controlling the compressor motor.

[0078] Figure 2c An example of an air conditioner 200c as an electrical device is given.

[0079] In the case where the electrical equipment 200 is an air conditioner 200c, in order to supply cooling air from the air conditioner, the air conditioner 200c may have a compressor (not shown), a compressor motor (not shown) for operating the compressor, and an inverter (not shown) for controlling the compressor motor.

[0080] Figure 2dThe cooking machine 200d is shown as an example of an electrical device.

[0081] In the case where the electrical equipment 200 is a cooking machine 200d, in order to heat the items inside the cooking machine, the cooking machine 200d may have a magnetron (not shown) or a light wave heater (not shown) and an inverter (not shown) for controlling the magnetron or the light wave heater.

[0082] Figure 2e The vacuum cleaner 200e is shown as an example of an electrical device.

[0083] In the case where the electrical device 200 is a vacuum cleaner 200e, in order to suck up foreign objects inside the cooking machine, the vacuum cleaner 200e may have a fan motor (not shown) and an inverter (not shown) for controlling the fan motor.

[0084] On the other hand, the electrical equipment 200 in the embodiments of the present invention can be, in addition to washing machine 200a, refrigerator 200b, air conditioner 200c, cooking machine 200d, vacuum cleaner 200e, dryer, clothes care machine, robot vacuum cleaner, air purifier, television (TV), monitor, laptop computer, mobile terminal, vehicle display device, electric vehicle, robot, drone and other various examples.

[0085] Figure 3a This is an example of an internal block diagram of an electrical device related to the present invention.

[0086] Referring to the accompanying drawings, the electrical device 200x related to the present invention may include: a first circuit board BDax having a first microcomputer 417, a second circuit board BDbx having a second microcomputer 427, and a third circuit board BDcx having a third microcomputer 437.

[0087] The first circuit board BDax may also include a display 415, a light-emitting diode 410, and a touch input device 413.

[0088] The second circuit board BDbx may also include a switch 421, a touch key 422, a touch input device 423, an IR receiver 424, and a sensor device 426.

[0089] The third circuit board BDcx may include a switch 431, a light-emitting diode 433, and a sensor device 436.

[0090] On the other hand, UART (Universal Asynchronous Serial Receiver and Transmitter) communication can be performed between the first microcomputer 417 and the second microcomputer 427, as well as between the first microcomputer 417 and the second microcomputer 427.

[0091] On the other hand, as shown in the figure, when UART communication is performed between a plurality of microcomputers 417, 427, and 437, data must be transmitted via the second microcomputer 427 when transmitting data from the first microcomputer 417 to the third microcomputer 437. That is, as shown in the figure, data must be transmitted in a cascade manner.

[0092] As a result, the input / output burden for data bypass increases, and there are problems such as the data transmission speed decreasing significantly as the number of microcomputers increases.

[0093] Furthermore, since each circuit board requires its own microcomputer, there is a drawback that the operation of the microcomputer needs to be programmed separately.

[0094] To address this issue, the present invention proposes a scheme capable of stably performing data communication. In particular, it proposes a scheme capable of stably performing scalable data communication between signal processing devices or between circuit boards. (See attached...) Figure 5 The following diagrams will be described.

[0095] Figure 3b for Figure 3a The diagrams referenced in the description. In particular, Figure 3b A diagram illustrating various examples of configurations for a plurality of microcomputers.

[0096] Refer to the attached diagram, as follows Figure 3b As shown in (a), a plurality of microcomputers 467, 477, 487, 497 can be mounted on various circuit boards BDax, BDbx, BDcx, BDdx.

[0097] Or, such as Figure 3b As shown in (b), some of the plurality of microcomputers 467, 477, 487, 497 are mounted on the circuit board BDex, while others 487, 497 may not be mounted on the circuit board.

[0098] Or, such as Figure 3b As shown in (c), some of the plurality of microcomputers 467, 477, 487, and 497, 477 and 487, are mounted on the circuit board BDfx, while the other 467 and 497 may not be mounted on the circuit board.

[0099] Or, such as Figure 3b As shown in (d), a portion of the plurality of microcomputers 467, 477, 487, 497, 467, 487 are mounted on the first circuit board BDgx, and another portion of 487, 497 can be mounted on the second circuit board BDjx.

[0100] on the other hand, Figure 3b (a) to Figure 3b Data communication between the plurality of microcomputers 467, 477, 487, and 497 in (d) can be performed in a cascade manner. This increases the input / output load for data bypass and results in a significant decrease in data transmission speed as the number of microcomputers increases.

[0101] Figure 4 This is an example of an internal block diagram of an electrical device according to an embodiment of the present invention.

[0102] Referring to the accompanying drawings, an electrical device 200 according to an embodiment of the present invention includes: a first circuit board BDa having a first signal processing device 410 and a second circuit board BDb having a second signal processing device 420.

[0103] On the other hand, the first signal processing device 410 has a processor ( Figure 5 518), main communication interface 410b and peripheral device communication interface ( Figure 5 (512), the main communication interface 410b is used for data communication with the second signal processing device 420.

[0104] On the other hand, the second signal processing device 420 has a communication interface 420b and a second peripheral device communication interface ( Figure 5 (532), the communication interface 420b is used for data communication with the first signal processing device 410.

[0105] On the other hand, the main communication interface 410b transmits the first interrupt to the processor 518, and the second peripheral device communication interface 532 transmits the second interrupt to the slave communication interface 420b.

[0106] This enables stable and scalable data communication. In particular, it enables stable and scalable data communication between circuit boards. Consequently, it allows general-purpose data communication to be applied to various types of electrical equipment.

[0107] On the other hand, an electrical device 200 according to an embodiment of the present invention may have a third circuit board BDc, the third circuit board BDc having a third signal processing device 430.

[0108] The third signal processing device 430 may have a second slave communication interface 430b and a third peripheral device communication interface, wherein the second slave communication interface 430b is used for data communication with the first signal processing device 410. Figure 5 (452).

[0109] On the other hand, the main communication interface 410b can transmit control commands, and the slave communication interface 420b or the second slave communication interface 430b can receive control commands. This enables stable and scalable data communication.

[0110] On the other hand, the main communication interface 410b can output serialized data to the slave communication interface 420b or the second slave communication interface 430b, or deserialize the serialized data received by the slave communication interface 420b or the second slave communication interface 430b.

[0111] The communication method between the main communication interface 410b and the slave communication interface 420b or the second slave communication interface 430b is a serial communication method, which can be a communication method based on the chip extensible architecture.

[0112] Therefore, the communication method between the main communication interface 410b and the slave communication interface 420b or the second slave communication interface 430b can be named CEALINK (Chip Scalable Architecture Link) communication method.

[0113] On the other hand, the first circuit board BDa may also have a display 415, a light-emitting diode 410, and a touch input device 413.

[0114] The second circuit board BDb may also include a switch 421, a touch key 422, a touch input device 423, an IR receiver 424, and a sensor device 426.

[0115] The third circuit board BDc may include a switch 431, a light-emitting diode 433, and a sensor device 436.

[0116] On the other hand, the first signal processing device 410 in the first circuit board BDa can perform SPI (Serial Peripheral Interface) communication with the display 415, and the first signal processing device 410 can perform I2C (Inter-Integrated Circuit) communication with the touch input device 413.

[0117] On the other hand, I2C communication can be performed between the second signal processing device 420 and the touch input device 413, or between the second signal processing device 420 and the IR receiving device 424, or between the second signal processing device 420 and the sensor device 426 within the second circuit board BDb, and GPIO (General Purpose Input Output) communication can be performed between the second signal processing device 420 and the switch 421.

[0118] On the other hand, I2C communication can be performed between the third signal processing device 430 and the sensor device 436 in the third circuit board BDc, and GPIO communication can be performed between the third signal processing device 430 and the switch 421 or between the third signal processing device 430 and the light-emitting diode 433.

[0119] On the other hand, the above-mentioned CEALINK communication can be performed between the first signal processing device 410 and the second signal processing device 420, and between the first signal processing device 410 and the second signal processing device 420.

[0120] On the other hand, as shown in the figure, when CEALINK communication is performed between a plurality of signal processing devices 410, 420, and 430, when the first signal processing device 410 transmits data to the third signal processing device 430, fast data communication can be performed without going through the second signal processing device 420.

[0121] Furthermore, even if the number of signal processing devices increases, with Figure 3a In comparison, it also has the advantage of fast and stable data transmission. Furthermore, due to the universal design of the signal processing device, it has the advantage of not requiring separate programming for the operation of the signal processing device.

[0122] Figures 5 to 11 for Figure 4 The diagram referenced in the description.

[0123] first, Figure 5 for Figure 4 An example of an internal block diagram of each signal processing device.

[0124] Referring to the accompanying drawings, the first signal processing device 410 has a main communication interface 410b and a peripheral device communication interface 512. The main communication interface 410b is used for data communication with the second signal processing device 420.

[0125] On the other hand, the peripheral device communication interface 512 can exchange signals with peripheral devices 511 such as sensor devices, light-emitting diodes, or switches.

[0126] On the other hand, the processor 518 can be housed together with the ROM 516, RAM 517, and processor bus 515 within the processor package 410a.

[0127] On the other hand, the first signal processing device 410 may also have a bus 514 for a peripheral device communication interface 512.

[0128] On the other hand, bus 514 can exchange data with processor 518 or main communication interface 410b.

[0129] On the other hand, the main communication interface 410b can control the communication between the main communication interface 410b and the bus 514 or generate data based on the communication protocol.

[0130] On the other hand, the first signal processing device 410 may also have a clock signal generator 513 for generating clock signals.

[0131] On the other hand, the main communication interface 410b can output data signals and clock signals.

[0132] On the other hand, the first signal processing device 410 can deserialize the received serialized data based on the clock signal from the clock signal generator 513.

[0133] On the other hand, the main communication interface 410b can control the data communication to stop within a specified time when the occupancy rate of the data communication line is above a baseline value.

[0134] On the other hand, the main communication interface 410b may include a CEALINK physical layer processing unit 528, a data serialization or deserialization unit 526, a buffer 524, a bus controller 522, and a register 531.

[0135] The CEALINK physical layer processing unit 528 can output or receive data to the outside based on the physical layer processing used for CEALINK communication.

[0136] The bus controller 522 can control the communication between the bus controller 522 and the bus 514 or generate signals that apply the protocol for CEALINK communication.

[0137] On the other hand, buffer 524 operates for asynchronous communication between bus controller 522 and data serialization or deserialization unit 526.

[0138] On the other hand, the data serialization or deserialization unit 526 can serialize the data to be transmitted or deserialize the received data.

[0139] On the other hand, the second signal processing device 420 has a slave communication interface 420b and a second peripheral device communication interface 532, wherein the slave communication interface 420b is used to perform data communication with the first signal processing device 410.

[0140] On the other hand, the second peripheral device communication interface 532 can exchange signals with peripheral devices 531 such as sensor devices, light-emitting diodes, or switches.

[0141] On the other hand, the second signal processing device 420 differs from the first signal processing device 410 in that it does not have a processor package.

[0142] That is, the second signal processing device 420 does not have a processor, ROM, RAM, or processor bus.

[0143] On the other hand, the second signal processing device 420 may also have a second bus 534 for the second peripheral device communication interface 532.

[0144] On the other hand, the second bus 534 can exchange data with the communication interface 420b.

[0145] On the other hand, control commands can be received from the main communication interface 410b via the communication interface 420b.

[0146] On the other hand, the control commands received from the main communication interface 410b from the communication interface 420b are transmitted to the second peripheral device communication interface 532. If the second peripheral device communication interface 532 does not respond within a set time, the generated error response signal and the second interrupt from the second peripheral device communication interface 532 can be transmitted to the main communication interface 410b.

[0147] On the other hand, the communication interface 420b can control the communication between the device communication interface 420b and the second bus 534 or generate data based on the communication protocol.

[0148] On the other hand, the second signal processing device 420 may also have a second clock signal generator 533 for generating clock signals.

[0149] On the other hand, data signals and clock signals can be output from the communication interface 420b.

[0150] On the other hand, the second signal processing device 420 can deserialize the received serialized data based on the clock signal from the second clock signal generator 533.

[0151] On the other hand, the communication interface 420b can control the data communication to stop within a specified time when the occupancy rate of the data communication line exceeds a reference value.

[0152] On the other hand, the communication interface 420b may include a second CEALINK physical layer processing unit 548, a second data serialization or deserialization unit 546, a second buffer 544, a second bus controller 542, and a second register 531.

[0153] The second CEALINK physical layer processing unit 548 can output or receive data to the outside according to the physical layer processing used for CEALINK communication.

[0154] The second bus controller 542 can control the communication between the second bus controller 542 and the second bus 534 or generate signals that apply the protocol for CEALINK communication.

[0155] On the other hand, the second buffer 544 operates for asynchronous communication between the second bus controller 542 and the second data serialization or deserialization unit 546.

[0156] On the other hand, the second data serialization or deserialization unit 546 can serialize the data to be transmitted or deserialize the received data.

[0157] On the other hand, the third signal processing device 430 has a second slave communication interface 430b and a third peripheral device communication interface 552, wherein the second slave communication interface 430b is used to perform data communication with the first signal processing device 410.

[0158] On the other hand, the third peripheral device communication interface 552 can exchange signals with peripheral devices 551 such as sensor devices, light-emitting diodes, or switches.

[0159] On the other hand, the third signal processing device 430 differs from the first signal processing device 410 in that it does not have a processor package.

[0160] That is, the third signal processing device 430 does not have a processor, ROM, RAM, or processor bus.

[0161] On the other hand, the third signal processing device 430 may also have a third bus 554 for a third peripheral device communication interface 552.

[0162] On the other hand, the third bus 554 can exchange data with the second slave communication interface 430b.

[0163] On the other hand, the second slave communication interface 430b can receive control commands from the master communication interface 410b.

[0164] On the other hand, the second slave communication interface 430b transmits the control commands received from the master communication interface 410b to the third peripheral device communication interface 552. If the third peripheral device communication interface 552 does not respond within a second set time, it can transmit the generated error response signal and the third interrupt from the third peripheral device communication interface 552 to the master communication interface 410b.

[0165] On the other hand, the second slave communication interface 430b can control the communication between the second slave communication interface 430b and the third bus 554 or generate data based on the communication protocol.

[0166] On the other hand, the third signal processing device 430 may also have a third clock signal generator 553 for generating clock signals.

[0167] On the other hand, the second communication interface 430b can output data signals and clock signals.

[0168] On the other hand, the third signal processing device 430 can deserialize the received serialized data based on the clock signal from the third clock signal generator 553.

[0169] On the other hand, the second slave communication interface 430b can control the data communication to stop within a specified time when the data communication line occupancy rate is above a reference value.

[0170] On the other hand, the second slave communication interface 430b may have a third CEALINK physical layer processing unit 568, a third data serialization or deserialization unit 566, a third buffer 564, a third bus controller 562, and a third register 561.

[0171] The third CEALINK physical layer processing unit 568 can output or receive data to the outside based on the physical layer processing used for CEALINK communication.

[0172] The third bus controller 562 can control the communication between the third bus controller 562 and the third bus 554 or generate signals that apply the protocol for CEALINK communication.

[0173] On the other hand, the third buffer 564 operates for asynchronous communication between the third bus controller 562 and the third data serialization or deserialization unit 566.

[0174] On the other hand, the third data serialization or deserialization unit 566 can serialize the data to be transmitted or deserialize the received data.

[0175] On the other hand, in another embodiment of the present invention, the electrical device 200 has a first signal processing device 410, a second signal processing device 420, and a third signal processing device 430. The first signal processing device 410 has a processor 518 and a main communication interface 410b, which is used to communicate with the second signal processing device 420. The second signal processing device 420 has a slave communication interface 420b, which is used to communicate with the first signal processing device 410. The third signal processing device 430 has a second slave communication interface 430b, which is used to communicate with the first signal processing device 410.

[0176] At this time, the main communication interface 410b transmits control commands and receives control commands from the communication interface 420b and the second slave communication interface 430b. This enables stable and scalable data communication. In particular, it enables stable and scalable data communication between circuit boards. Furthermore, it allows general-purpose data communication to be applied to various types of electrical equipment.

[0177] Figure 6 for Figure 4 Another example of the internal block diagram of each signal processing device.

[0178] Referring to the accompanying drawings, the first signal processing device 410 and Figure 5 It is the same as the first signal processing device 410.

[0179] On the other hand, the second signal processing device 420 and Figure 5 They are almost identical, but differ in that they also have a storage unit 549 for storing system setting information such as SUBID and an oscillator 539 for the second clock signal generator 533.

[0180] On the other hand, the third signal processing device 430 and Figure 5 They are almost identical, but differ in that they also have a storage unit 569 for storing system setting information such as SUBID and an oscillator 559 for the third clock signal generator 553.

[0181] Figure 7 for Figure 4 An example of a detailed block diagram of the first signal processing device.

[0182] Referring to the accompanying drawings, the first signal processing device 410 has a processor 518, a main communication interface 410b, and a peripheral device communication interface 512. The main communication interface 410b is used for data communication with the second signal processing device 420.

[0183] On the other hand, the first signal processing device 410 may also have a bus 514 for a peripheral device communication interface 512, a processor bus 515 between the bus 514 and the processor 518, and a clock signal generator 513 for generating clock signals.

[0184] On the other hand, the figure shows that the oscillator 509 for the clock signal generator 513 is disposed outside the first signal processing device 410, but unlike the figure, it may also be disposed inside the first signal processing device 410.

[0185] On the other hand, the main communication interface 410b may include a bus controller 522a for data transmission, a buffer 524a for data transmission, a data serialization unit 726a for data transmission, and a physical layer processing unit 528a for data transmission.

[0186] On the other hand, the bus controller 522a for data transmission may have an instruction detector 716 and a header inserter 718, which inserts a header according to a CEALINK-based communication protocol.

[0187] On the other hand, the data serialization unit 726a may have a data serialization processor 526a and a link busy detector 515a, which detects whether the occupancy rate of the data communication line is above a reference value.

[0188] On the other hand, the main communication interface 410b may include a bus controller 522b for data reception, a buffer 524b for data reception, a data deserialization unit 726b for data reception, and a physical layer processing unit 528b for data reception.

[0189] On the other hand, the data deserialization unit 726b may include a header detector 525b for detecting the header of the received data and a data deserialization processor 526b.

[0190] On the other hand, the bus controller 522b for receiving data may include a header decoder 715 for decoding the header of the received data, an interrupt signal generator 711 for generating an interrupt signal, and an automatic ready controller 713 for automatically controlling the standby state during data communication.

[0191] On the other hand, the main communication interface 410b may also have a physical layer processing unit 528c, which is used to transmit the clock signal generated in the clock signal generator 513 to the outside.

[0192] On the other hand, the clock signal generated in the clock signal generator 513 is also transmitted to the buffer 524b used for data reception and is used during data reception.

[0193] Figure 8 for Figure 4 An example of a detailed block diagram of the second signal processing device.

[0194] Referring to the accompanying drawings, the second signal processing device 420 has a slave communication interface 420b and a second peripheral device communication interface 532, wherein the slave communication interface 420b is used for data communication with the first signal processing device 410.

[0195] On the other hand, the second signal processing device 420 may also have a second bus 534 for a second peripheral device communication interface 532, a second clock signal generator 533 for generating a second clock signal, and a storage unit 549 for storing system setting information such as SUBID.

[0196] On the other hand, the figure shows that the second oscillator 539 for the second clock signal generator 533 is disposed inside the second signal processing device 420, but unlike the figure, it can also be disposed outside the second signal processing device 420.

[0197] On the other hand, the communication interface 420b may include a second bus controller 542a for data reception, a second buffer 544a for data reception, a second data deserialization unit 746a for data reception, and a second physical layer processing unit 548a for data reception.

[0198] On the other hand, the second bus controller 542a for receiving data may have a header decoder 813 for decoding the header of the received data and a bus signal generator 811 for generating bus signals.

[0199] On the other hand, the second data deserialization unit 746b may have a header detector 545a for detecting the header of the received data and a data deserialization processor 546a.

[0200] On the other hand, the communication interface 420b may include a second bus controller 542b for data transmission, a second buffer 544b for data transmission, a second data serialization unit 746b for data transmission, and a second physical layer processing unit 548b for data transmission.

[0201] On the other hand, the second bus controller 542b for data transmission may have a bus monitor 815 for monitoring the second bus 534, a controller 817 for controlling interruptions or errors, and a header inserter 718 for inserting headers according to the CEALINK-based communication protocol.

[0202] On the other hand, the second data serialization unit 726a may have a data serialization processor 546b and a link busy detector 545b, which detects whether the occupancy rate of the data communication line is above a reference value.

[0203] On the other hand, the communication interface 420b may also have a second physical layer processing unit 548c, which is used to receive clock signals received from the main communication interface 410b.

[0204] On the other hand, the second clock signal generated in the second clock signal generator 533 is transmitted to the second buffer 544b and the second bus controller 542b for data transmission and used when transmitting data.

[0205] On the other hand, control commands received from the main communication interface 410b can be transmitted from the communication interface 420b to the second peripheral device communication interface 532. If the second peripheral device communication interface 532 does not respond within a set time, a generated error response signal and a second interrupt from the second peripheral device communication interface 532 can be transmitted to the main communication interface 410b. Thus, stable and scalable data communication can be performed.

[0206] Figure 9 This is an example in Figure 4 Diagrams showing various examples of data transmitted within electrical equipment.

[0207] Referring to the attached diagram, Figure 9 (a) illustrates general address data 910 based on the CEALINK communication protocol output from the main communication interface 410b, the slave communication interface 420b, or the second slave communication interface 430b.

[0208] The general address data 910 may include key information, register indicator information, slave indicator information, and address information.

[0209] For example, the key information (CEAKEY) is 8 bits and may include key data stored in registers (521, 541, or 561).

[0210] On the other hand, the indicator information SUBID is 2 bits and may include an identifier ID representing either the signal processing device (420 or 430) or the communication interface (420b or 430b).

[0211] On the other hand, the register indicator information REGID is 6 bits and may include an identifier ID representing a register (521, 541, or 561) within the communication interface (410b, 420b, or 430b).

[0212] For example, when the register indicator information REGID is “111111”, it can represent register 521 in the main communication interface 410b; when the register indicator information REGID is “111110”, it can represent the second register 541 in the slave communication interface 420b.

[0213] On the other hand, the address information (PERI register Address) is 16 bits, which can represent the address information of the register.

[0214] Referring to the attached diagram, Figure 9 (b) illustrates the transmission address data 920 based on the CEALINK communication protocol output from the main communication interface 410b, the slave communication interface 420b, or the second slave communication interface 430b.

[0215] The transmission address data 920 may include transmission address information, receiving address information, and monitoring information.

[0216] As shown in the figure, the transmission address data 920 may include a 4-bit transmission header (Tx Header), a 2-bit slave indicator information (SUBID), a 6-bit PERI information (PERID), and a 16-bit PERI register address information (PERI registeraddress).

[0217] On the other hand, the transmission header (Tx Header) may include reset information, bus monitoring information, transmission address information, receive address information, idle status information, etc.

[0218] For example, a Tx Header of "11xx" can indicate reset information; a Tx Header of "101x" can indicate bus monitoring information; a Tx Header of "1001" can indicate write address information; and a Tx Header of "1000" can indicate read address information.

[0219] Referring to the attached diagram, Figure 9 (c) illustrates the transmission data 930 based on the CEALINK communication protocol output from the main communication interface 410b, the slave communication interface 420b, or the second slave communication interface 430b.

[0220] The transmitted data 930 may include a 3-bit write header (Wdata Header) and 32 bits of write data (Wdata).

[0221] Referring to the attached diagram, Figure 9 Example (d) illustrates received data 940 based on the CEALINK communication protocol output from the main communication interface 410b, the slave communication interface 420b, or the second slave communication interface 430b.

[0222] The received data 940 may include a 3-bit read header (Wread Header) and a 32-bit write information (Rinfo).

[0223] For example, if the Wread Header is "001", it can indicate an error message; if the Wread Header is "010", it can indicate an interrupt message; and if the Wread Header is "011", it can indicate that data Rdata has been read.

[0224] On the other hand, when the communication data is a transmission command, the main communication interface 410b, the slave communication interface 420b, or the second slave communication interface 430b can apply automatic ready, such as automatic control of standby state during data communication, within the allowable range of the buffer.

[0225] On the other hand, if the main communication interface 410b, the slave communication interface 420b, or the second slave communication interface 430b receives a receive instruction for the same address after the transmission instruction has been transmitted, it can immediately apply auto-ready.

[0226] On the other hand, the main communication interface 410b, the slave communication interface 420b, or the second slave communication interface 430b may not apply auto-ready when it is a random access read instruction.

[0227] Figure 10a This diagram illustrates an example of signaling transmission during data communication.

[0228] Referring to the attached diagram, D+ represents a positive voltage signal, D- represents a negative voltage signal, and GND represents the ground voltage.

[0229] On the other hand, Vp represents the high level of a positive or negative voltage signal, and Vn represents the high level of a positive or negative voltage signal.

[0230] V single-end can represent the reference voltage for a signal based on a single-ended interface.

[0231] Vd(1) and Vd(0) can represent the high and low levels of signals based on the differential interface, respectively.

[0232] Vs(1) and Vs(0) can represent the high and low levels of a signal based on a single-ended interface, respectively.

[0233] On the other hand, the signals output from the main communication interface 410b, the secondary communication interface 420b, or the second secondary communication interface 430b can be signals based on a differential end interface or signals based on a single end interface.

[0234] For example, signals based on the differential end interface can be output as D+ and D-.

[0235] As another example, a signal based on a single-end interface can be either D+ or D-.

[0236] On the other hand, the signal output from the main communication interface 410b, the secondary communication interface 420b, or the second secondary communication interface 430b can be a data signal or a clock signal. The data signal or clock signal can be a signal based on a differential end interface or a signal based on a single end interface.

[0237] On the other hand, the main communication interface 410b, the slave communication interface 420b, or the second slave communication interface 430b may include, for example: Figure 10b The differential end interface is shown.

[0238] On the other hand, the main communication interface 410b, the slave communication interface 420b, or the second slave communication interface 430b may include, for example: Figure 10c The single-end interface shown is shown.

[0239] Figure 10b An example of a differential interface system is given.

[0240] Referring to the accompanying drawings, the differential interface system 1000 may include a transmitter 1003 and a receiver 1007 respectively connected to the na node and the nb node.

[0241] Such a differential interface system 1000 is useful for long-distance data communication and for environments with high noise.

[0242] Figure 10c An example of a single-ended interface system is given.

[0243] Referring to the accompanying drawings, the single-ended interface system 1010 may include a transmitter 1016 and a receiver 1017, each connected at one end to an nc node.

[0244] On the other hand, the other ends of the transmitter 1016 and the receiver 1017 can be connected to the nd node and the ne node, respectively.

[0245] Such a single-ended interface system 1010 is useful for short-distance data communication and for environments with low noise.

[0246] Figure 11 The figures illustrate various examples of the configuration of a plurality of signal processing devices according to embodiments of the present invention.

[0247] Refer to the attached diagram, as follows Figure 11 As shown in (a), the plurality of signal processing devices 467, 477, 487, 497 of the present invention can be installed on each circuit board BDax, BDbx, BDcx, BDd.

[0248] Or, such as Figure 11 As shown in (b), some of the signal processing devices 467 and 487 are mounted on the circuit board BDe, while other signal processing devices 487 and 497 may not be mounted on the circuit board.

[0249] Or, such as Figure 11 As shown in (c), some of the signal processing devices 477 and 487 are mounted on the circuit board BDf, while other signal processing devices 467 and 497 may not be mounted on the circuit board.

[0250] Or, such as Figure 11 As shown in (d), some of the signal processing devices 467 and 487 are mounted on the first circuit board BDg, and the other part of the signal processing devices 487 and 497 can be mounted on the second circuit board BDj.

[0251] on the other hand, Figure 11 (a) to Figure 11 Data communication between the plurality of signal processing devices 467, 477, 487, 497 in (d) can be as follows: Figure 4As described in the following diagrams, it is executed via CEALINK communication.

[0252] This communication method enables stable and scalable data communication. In particular, it enables stable and scalable data communication between circuit boards. This, in turn, allows general-purpose data communication to be applied to various types of electrical equipment.

[0253] While the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above. Various modifications can be made by those skilled in the art without departing from the spirit of the invention as claimed in the claims, and these modifications should not be understood solely from the technical concept or vision of the present invention.

Claims

1. An electrical device, wherein, have: A first circuit board having a first signal processing device; and A second circuit board having a second signal processing device; The first signal processing device has: The system includes a processor, a main communication interface, and peripheral device communication interfaces. The main communication interface is used for data communication with the second signal processing device. The second signal processing device has: The secondary communication interface is used for data communication with the first signal processing device, and the secondary communication interface is used for data communication with the first peripheral device. The main communication interface transmits a first interrupt to the processor. The second peripheral device communication interface transmits a second interrupt to the slave communication interface.

2. The electrical equipment according to claim 1, wherein, The main communication interface transmits control commands. The control command is received from the communication interface.

3. The electrical equipment according to claim 1, wherein, The main communication interface outputs serialized data or deserializes received serialized data.

4. The electrical equipment according to claim 1, wherein, The first signal processing device also has a bus for the communication interface of the peripheral device. The bus exchanges data with the processor or the main communication interface.

5. The electrical equipment according to claim 4, wherein, The main communication interface controls the communication between the main communication interface and the bus or generates data based on the communication protocol.

6. The electrical equipment according to claim 1, wherein, The second signal processing device also has a second bus for the communication interface of the second peripheral device. The second bus exchanges data with the communication interface.

7. The electrical equipment according to claim 6, wherein, The slave communication interface controls the communication between the slave communication interface and the second bus or generates data based on the communication protocol.

8. The electrical equipment according to claim 1, wherein, The first signal processing device further includes a clock signal generator for generating clock signals. The main communication interface outputs data signals and clock signals.

9. The electrical equipment according to claim 8, wherein, The first signal processing device deserializes the received serialized data based on the clock signal from the clock signal generator.

10. The electrical equipment according to claim 1, wherein, When the occupancy rate of the data communication line exceeds a baseline value, the main communication interface is controlled to stop data communication within a specified time.

11. The electrical equipment according to claim 1, wherein, The slave communication interface transmits the control commands received from the master communication interface to the second peripheral device communication interface. If the second peripheral device communication interface does not respond within a set time, the generated error response signal and the second interrupt from the second peripheral device communication interface are transmitted to the main communication interface.

12. The electrical equipment according to claim 1, wherein, The general address data output from the main communication interface includes key information, register indicator information, slave indicator information, and address information.

13. The electrical equipment according to claim 1, wherein, The transmission address data output from the main communication interface includes transmission address information, receiving address information, and monitoring information.

14. The electrical equipment according to claim 1, wherein, The received data from the main communication interface includes error information and interrupt information.

15. The electrical equipment according to claim 1, wherein, The main communication interface or the slave communication interface includes a differential interface.

16. The electrical equipment according to claim 1, wherein, The main communication interface or the slave communication interface includes a single-ended interface.

17. The electrical equipment according to claim 1, wherein, have: A third circuit board having a third signal processing device; The third signal processing device has a second slave communication interface and a third peripheral device communication interface. The second slave communication interface is used for data communication with the first signal processing device. The third peripheral device communication interface transmits a third interrupt to the second slave communication interface.

18. The electrical equipment according to claim 17, wherein, The main communication interface transmits control commands. The control command is received by the slave communication interface and the second slave communication interface.

19. The electrical equipment according to claim 17, wherein, The second slave communication interface transmits the control commands received from the master communication interface to the third peripheral device communication interface. If the third peripheral device communication interface does not respond within a second set time, the generated second error response signal and the third interrupt from the third peripheral device communication interface are transmitted to the main communication interface.

20. An electrical device, wherein, have: First signal processing device; Second signal processing device; as well as Third signal processing device; The first signal processing device has a processor and a main communication interface, the main communication interface being used for data communication with the second signal processing device. The second signal processing device has a slave communication interface for data communication with the first signal processing device. The third signal processing device has a second slave communication interface, which is used for data communication with the first signal processing device. The main communication interface transmits control commands. The control command is received by the slave communication interface and the second slave communication interface.

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