Semiconductor device, method for manufacturing semiconductor device, and power conversion device

Abstract

The aim is to provide a technology that can improve the insulation reliability of a semiconductor device. The semiconductor device includes a terminal well region surrounding an active region when viewed from above, and an FLR region surrounding the terminal well region when viewed from above. The FLR region includes multiple floating wells with floating potentials that surround the terminal well region when viewed from above and are arranged in a nested manner, each having a floating potential. The number of floating wells is VR / 100 or more relative to the rated voltage VR[V] of the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a power conversion device. Background Technology

[0002] Various techniques have been proposed to ensure breakdown voltage performance in vertical semiconductor devices such as Schottky Barrier Diodes (SBDs) used in power semiconductor devices. For example, Patent Document 1 proposes a technique of providing a guard ring region (also called a terminal well region) composed of multiple p-type semiconductor layers in the outer periphery, i.e., the terminal region, of an n-type semiconductor layer. According to this structure, the electric field generated inside the semiconductor layer when a reverse voltage is applied to the main electrode of the semiconductor device is mitigated by the depletion layer formed by the pn junction between the n-type semiconductor layer and the p-type guard ring region.

[0003] On the other hand, even if the electric field generated inside the semiconductor layer in the guard ring region is effectively mitigated, it can sometimes become a high electric field outside the semiconductor layer. Therefore, for example, in Patent Document 2, the guard ring region is covered with a surface protective film such as polyimide, or sealed with a sealing material such as gel. Such surface protective films and sealing materials are not limited to SBDs, but can also be applied to other semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0004] Patent Document 1: Japanese Patent Application Publication No. 2009-94433

[0005] Patent Document 2: Japanese Patent Application Publication No. 2013-211503 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] Surface protective films such as polyimide and sealing materials such as gels are prone to containing moisture under high humidity conditions, which can potentially have adverse effects on semiconductor devices. Specifically, if the semiconductor layer, which becomes a high electric field, reacts with moisture, insulating materials such as oxides are formed, leading to the peeling of the surface protective film, or moisture remains at the interface between the surface protective film and the sealing material. As a result, the following problems exist: leakage paths are formed in the semiconductor device that differ from the usual ones, potentially compromising the insulation reliability of the semiconductor device.

[0008] Therefore, this disclosure was made in view of the problems described above, and its purpose is to provide a technique that can improve the insulation reliability of semiconductor devices.

[0009] Solution for solving the problem

[0010] The semiconductor device disclosed herein is a semiconductor device having an active region and a terminal region surrounding the active region when viewed from above, comprising: a semiconductor substrate of a first conductivity type made of silicon carbide; a terminal well region of a second conductivity type selectively disposed on the upper part of the semiconductor substrate of the terminal region, surrounding the active region when viewed from above, and having an outer peripheral end; an FLR region selectively disposed on the upper part of the semiconductor substrate of the terminal region, surrounding the terminal well region when viewed from above; and a field insulating film disposed on the upper surface of the semiconductor substrate, covering a portion of the terminal well region. The FLR region comprises: a surface electrode disposed on the semiconductor substrate on the side closer to the active region than the field insulating film; an upper surface film disposed on the field insulating film, covering the end of the surface electrode on the terminal region side; and a back electrode disposed on the lower surface of the semiconductor substrate. The FLR region includes a plurality of floating wells of a second conductivity type, which surround the terminal well region when viewed from above and are arranged in a nested manner, having a floating potential. The number of the plurality of floating wells is VR / 100 or more relative to the rated voltage VR[V] of the semiconductor device.

[0011] The effects of the invention

[0012] According to this disclosure, the number of multiple floating wells is VR / 100 or more relative to the rated voltage VR[V] of the semiconductor device. This structure improves the insulation reliability of the semiconductor device.

[0013] The purpose, features, aspects, and advantages of this disclosure become clearer from the following detailed description and accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a partial cross-sectional view showing the structure of the semiconductor device involved in Embodiment 1.

[0015] Figure 2 This is a top view showing the structure of the semiconductor device involved in Embodiment 1.

[0016] Figure 3 This is a partial cross-sectional view showing the structure of the semiconductor device involved in Embodiment 1.

[0017] Figure 4 This is a partial cross-sectional view showing the structure of the semiconductor device involved in Embodiment 1.

[0018] Figure 5 This is a graph showing the lifetime of a sample of the semiconductor device according to Embodiment 1.

[0019] Figure 6 This is a graph showing the lifetime of a sample of the semiconductor device according to Embodiment 1.

[0020] Figure 7 Figures (a) to (c) are diagrams showing the appearance of the upper surface of a sample of a semiconductor device.

[0021] Figure 8 This is a diagram showing the simulation results in the semiconductor device involved in Embodiment 1.

[0022] Figure 9 This is a diagram showing the simulation results in the semiconductor device involved in Embodiment 1.

[0023] Figure 10 This is a partial cross-sectional view showing the structure of the semiconductor device involved in Embodiment 1.

[0024] Figure 11 This is a graph showing the calculated results of the electric field strength in the semiconductor device according to Embodiment 1.

[0025] Figure 12 This is a graph showing the calculated results of the electric field strength in the semiconductor device according to Embodiment 1.

[0026] Figure 13 This is a partial cross-sectional view showing the structure of the semiconductor device involved in Embodiment 2.

[0027] Figure 14 This is a top view showing the structure of the semiconductor device involved in Embodiment 2.

[0028] Figure 15 This is a partial cross-sectional view showing the structure of the semiconductor device involved in Embodiment 2.

[0029] Figure 16 This is a block diagram that schematically represents the structure of the power conversion system involved in Embodiment 3. Detailed Implementation

[0030] Hereinafter, embodiments will be described with reference to the accompanying drawings. In this specification, the "active region" of a semiconductor device is defined as the region through which the main current flows when the semiconductor device is in the ON state, and the "terminal region" of a semiconductor device is defined as the region surrounding the active region when viewed from above. Furthermore, the "outer side" of a semiconductor device refers to the direction from the center of the semiconductor device toward the outer periphery when viewed from above, and the "inner side" of a semiconductor device refers to the direction opposite to the "outer side". Regarding the conductivity type of the impurities, it is assumed that the "first conductivity type" is n-type and the "second conductivity type" is p-type, but it is also possible that the "first conductivity type" is p-type and the "second conductivity type" is n-type.

[0031] Here, the term "MOS" was historically used to refer to a metal-oxide-semiconductor (MOS) stack-up structure, derived from the first letters of Metal-Oxide-Semiconductor. However, particularly in field-effect transistors with a MOS structure (hereinafter referred to simply as "MOS transistors"), from the perspective of recent integration and improvements in manufacturing processes, materials other than metals and oxides are sometimes used as the gate electrode and gate insulating film. For example, primarily from the viewpoint of forming the source and drain of a MOS transistor in a self-aligned manner, polysilicon is sometimes used instead of metal as the gate electrode material. Furthermore, from the viewpoint of improving electrical characteristics, materials with high dielectric constants other than oxides are sometimes used as the gate insulating film.

[0032] Therefore, the term "MOS" is not necessarily limited to metal-oxide-semiconductor stacked structures. That is, based on common technical knowledge, "MOS" is defined not only as a stacked structure represented by the abbreviation Metal-Oxide-Semiconductor, but also as a conductor-insulator-semiconductor stacked structure, which is also the case in this specification.

[0033] Furthermore, in the following descriptions, even if it is written as "~above" or "covering~", it does not preclude the existence of intervening elements between structural elements. For example, even if it is written as "B set on A" or "B covering A", there may still be other structural elements placed between A and B. In addition, in the following descriptions, terms such as "above", "below", "side", "bottom", "top", or "inside" are sometimes used to indicate specific positions or directions, but these terms are used for ease of explanation and are unrelated to the actual direction in use.

[0034] Furthermore, the diagrams used in the following description are illustrative. Therefore, the dimensions, positions, and relationships of the elements shown in the diagrams may not be accurate and may be modified accordingly. Additionally, the dimensions and relationships of elements shown in different diagrams may also be inaccurate and may be modified accordingly.

[0035] In each figure, structural elements with the same names and functions as those shown in other figures are given the same reference symbols. Therefore, descriptions of structural elements that are the same as those previously described in other figures are sometimes omitted to avoid lengthy explanations.

[0036] <Implementation Method 1>

[0037] <Device Structure>

[0038] Figure 1This is a partial cross-sectional view showing the structure of the Schottky barrier diode (SBD) 100, which is a semiconductor device according to Embodiment 1. Figure 2 This is a top view of the SBD100, along... Figure 2 The AA line's directional section view is equivalent to Figure 1 . Figure 1 The left side is the active region through which the main current flows when the SBD100 is turned on. Figure 1 The right-hand portion is the terminal region, which is located outside the active region of SBD100. Hereinafter, the region corresponding to the active region will sometimes be referred to as "inner region RI", and the region corresponding to the terminal region will sometimes be referred to as "outer region RO".

[0039] like Figure 1 Thus, the SBD100 according to Embodiment 1 is composed of an epitaxial substrate 30 including a single-crystal substrate 31 and an epitaxial layer 32 disposed thereon. The single-crystal substrate 31 is an n-type (first conductivity type) substrate, for example, made of silicon carbide (SiC). The epitaxial layer 32 is made of n-type SiC and includes a semiconductor layer epitaxially grown on the single-crystal substrate 31. In this configuration, the SBD100 according to Embodiment 1 is a SiC-SBD.

[0040] The semiconductor substrate involved in this embodiment 1 is an epitaxial substrate 30 comprising a single-crystal substrate 31 and an epitaxial layer 32, but it is not limited to this; for example, it can be either the single-crystal substrate 31 or the epitaxial layer 32. Furthermore, in this embodiment 1, the epitaxial substrate 30 is a polytype substrate having a 4H layer. Figure 1 The upper and lower sides of the epitaxial substrate 30 are defined as "surface side" and "back side" respectively. Hereinafter, the main surface of the back side of the epitaxial substrate 30, i.e. the lower surface, is sometimes referred to as "back side S1" and the main surface of the surface side, i.e. the upper surface, is referred to as "surface S2".

[0041] A p-type (second conductivity type) terminal well region 2 is selectively disposed on the upper part of the epitaxial layer 32, which serves as the outer region RO, the active region. The n-type epitaxial layer 32, which serves as the inner region RI, includes an n-type drift layer 1 through which current flows via drift. The impurity concentration of the drift layer 1 is lower than that of the single-crystal substrate 31. Therefore, the single-crystal substrate 31 has a lower resistivity compared to the drift layer 1. The impurity concentration of the drift layer 1 is, for example, 1 × 10⁻⁶. 14 / cm 3 Above and 1×10 17 / cm 3 the following.

[0042] Terminal trap region 2 is a frame-shaped (ring-shaped) region that surrounds the active region and has an outer peripheral end when viewed from above, functioning as a so-called protective ring. Figure 2 In the diagram, the outer periphery of the terminal trap region 2 is shown by dashed lines. Furthermore, the "outer periphery end" refers to the end portion of the annular structural element, such as the terminal trap region 2, located on the outer side of the SBD 100. Conversely, the "inner periphery end" refers to the end portion of the annular structural element, such as the terminal trap region 2, located on the inner side of the SBD 100.

[0043] In this embodiment 1, as Figure 1 As shown, with the inner periphery of the terminal well region 2 as the boundary, the portion inside the SBD100 closer to this boundary is the active region (i.e., the inner region RI), and the portion outside the SBD100 closer to this boundary is the terminal region (i.e., the outer region RO). In this embodiment 1, the outer region RO is a frame-shaped region that surrounds the inner region RI when viewed from above. It has straight regions along each side of the semiconductor chip, i.e., straight portions, and curved regions connecting the two straight portions that extend in different directions, i.e., corner portions.

[0044] like Figure 1 Thus, an FLR (Field Limiting Ring) region 3, which surrounds the terminal well region 2 when viewed from above, is selectively provided on the upper part of the epitaxial layer 32 of the outer region RO, which serves as the terminal region. The FLR region 3 includes a plurality of p-type floating wells 3a with floating potentials. The plurality of floating wells 3a are separately provided on the outer periphery of the terminal well region 2, and are nested together and separated from each other when viewed from above.

[0045] In the FLR region 3, the region with floating traps 3a and the region of the epitaxial layer 32 without floating traps 3a are alternately arranged from the inside to the outside of the SBD 100. Furthermore, the inner periphery of the FLR region 3 corresponds to the inner periphery of the innermost floating trap 3a among the plurality of floating traps 3a, and the outer periphery of the FLR region 3 corresponds to the outer periphery of the outermost floating trap 3a among the plurality of floating traps 3a.

[0046] In FLR region 3, the desired outcome is as follows: Figure 3 As shown, the spacing between the floating traps 3a increases from the inside to the outside of the SBD100. For example, it is desirable that... Figure 4 As shown, the interval between the x-th (x=1, 2, ..., n) floating trap 3a and the (x-1)-th floating trap 3a, counting from the inner perimeter, is set as S. x As the value of x increases, S x The value increases. Figure 4 In the diagram, the 0th floating sink 3a corresponds to the terminal sink region 2. Alternatively, it could be that not all S... x All of them increase monotonically relative to x.

[0047] Alternatively, it can be as follows: Figure 3 As shown, the width of the x-th floating trap 3a, counting from the inside of SBD100, is set to L. x L x The value of decreases as the value of x increases, can also increase locally, or can be set to the same value regardless of the value of x. However, from the perspective of cost reduction, as long as the required avalanche voltage can be obtained, S is preferred. x +L x The value is small, and it is desirable to set it to a value of, for example, 3μm to 10μm.

[0048] A field insulating film 4, a surface electrode 5, and a surface protective film 6 are disposed on the surface S2 of the epitaxial substrate 30. Furthermore, Figure 2 In the top view, the field insulating film 4 and other components are omitted, and the position of the end of the surface protective film 6, i.e. the outline of the surface protective film 6, is shown with solid lines.

[0049] The field insulating film 4 covers a portion of the terminal well region 2 and the FLR region 3, extending beyond the outer periphery of the FLR region 3. The field insulating film 4 is made of insulating materials such as SiO2 or SiN, and preferably has a thickness of, for example, 10 nm or more. For example, a SiO2 film with a thickness of 1 μm can also be used as the field insulating film 4.

[0050] A surface electrode 5 is disposed on the surface S2 of the epitaxial substrate 30 on the side closer to the active region than the field insulating film 4, and at least a portion of the surface S2 of the epitaxial substrate 30 is disposed in the inner region RI. In this embodiment 1, the surface electrode 5 includes a Schottky electrode 5a disposed on the surface S2 of the epitaxial substrate 30 and an electrode pad 5b disposed on the Schottky electrode 5a. Furthermore, the outer peripheral ends of the Schottky electrode 5a and the electrode pad 5b rest on the field insulating film 4.

[0051] Thus, the surface electrode 5 rests on the upper part of the field insulating film 4. When viewed from above, the outer peripheral end of the surface electrode 5 is located inside the SBD100, closer to the outer peripheral end of the terminal well region 2, and does not extend beyond the outer peripheral end of the terminal well region 2 but is positioned above the FLR region 3.

[0052] The Schottky electrode 5a is in contact with the remaining portion of the drift layer 1 in the inner region RI and the terminal well region 2 in the outer region RO, which is exposed from the field insulating film 4. Thus, the surface electrode 5 is electrically connected to the terminal well region 2. The material of the Schottky electrode 5a can be any metal that forms the Schottky junction with the drift layer 1, which is an n-type SiC semiconductor, such as Ti (titanium), Mo (molybdenum), Ni (nickel), Au (gold), or W (tungsten). The thickness of the Schottky electrode 5a is preferably, for example, 30 nm or more and 300 nm or less. For example, a Ti film with a thickness of 100 nm can also be used as the Schottky electrode 5a.

[0053] The material for the electrode pad 5b can be, for example, a metal containing one or more of Al (aluminum), Cu (copper), Mo, Ni, or an Al alloy such as Al-Si (silicon). The thickness of the electrode pad 5b is preferably 300 nm or more and 10 μm or less. For example, an Al film with a thickness of 3 μm can also be used as the electrode pad 5b.

[0054] The surface protective film 6 is an upper surface film disposed on the field insulating film 4 and covering the outer RO side end of the surface electrode 5. Specifically, the surface protective film 6 covers the end and end face (side) of the upper surface of the electrode pad 5b and the end face (side) of the Schottky electrode 5a. Therefore, the outer peripheral end of the upper surface of the electrode pad 5b is covered by the surface protective film 6.

[0055] However, the central portion of the electrode pad 5b protrudes from the surface protective film 6 to function as an external connection terminal. That is, the surface protective film 6, as... Figure 1 That way, the inner region RI has an opening that exposes the upper surface of the electrode pad 5b. Additionally, Figure 1 The surface protective film 6 completely covers the outer peripheral end of the field insulating film 4 and covers at least a portion of the surface S2 of the epitaxial substrate 30 in the outer region RO. However, the surface protective film 6 can also expose the outer peripheral end of the field insulating film 4 without contacting the surface S2 of the epitaxial substrate 30, as long as it is in contact with the field insulating film 4 on the upper side of the FLR region 3.

[0056] The material of the surface protective film 6 may be, for example, polyimide, which serves as a resin-based insulator to mitigate external stress, or silicon nitride (SiN), which has high resistance and can discharge external charges generated in the gel of the sealing resin 41 to the outside of the gel via electrodes. Alternatively, the surface protective film 6 may be a multilayer film formed by stacking a polyimide film and a SiN film.

[0057] A back electrode 8 is provided on the back side S1 of the epitaxial substrate 30. The material of the back electrode 8 may be, for example, a metal containing one or more of Ti, Ni, Al, Cu, and Au. A sealing resin 41 covers a surface protective film 6. The sealing resin 41 may be a gel-like sealing resin or a thermosetting sealing resin.

[0058] In the above structure, the overall length of the FLR region 3 and the number of floating traps 3a vary depending on the required withstand voltage of the SBD100. Typically, the withstand voltage of the SBD100 varies depending on the application and conditions, for example, specified as 1.2kV, 1.7kV, 3.3kV, or 6.5kV ratings. From the viewpoint of increasing the rated voltage (withstand voltage) of the SBD100, it is preferable to extend the overall length of the FLR region 3 or increase the number of floating traps 3a. On the other hand, from the viewpoint of cost reduction, it is preferable to shorten the overall length of the FLR region 3 as much as possible or reduce the number of floating traps 3a.

[0059] Furthermore, when using SBD100 under high temperature and high humidity conditions, high voltage is sometimes applied to SBD100 while it contains some moisture. According to the inventors' research, in order to improve insulation reliability under such conditions, it is necessary to extend the overall length of the FLR region 3 or increase the number of multiple floating traps 3a compared to the structure of SBD100 used under normal operating conditions.

[0060] Based on the survey results, in the SBD100 according to Embodiment 1, the number of multiple floating wells 3a relative to the rated voltage VR[V] of the SBD100 is VR÷100 or more, preferably VR÷85 or more, and more preferably VR÷65 or more. With this structure, an SBD100 with high insulation reliability can be obtained. Furthermore, in Embodiment 1, the length from the outer periphery of the terminal well region 2 to the outer periphery of the FLR region 3 is VR×0.08μm or more, preferably VR×0.09μm or more, and more preferably VR×0.1μm or more. With this structure, an SBD100 with even higher insulation reliability can be obtained. Moreover, by appropriately changing the combination of the number of multiple floating wells 3a and the length from the outer periphery of the terminal well region 2 to the outer periphery of the FLR region 3, a desired SBD100 can be obtained from the viewpoint of withstand voltage and cost.

[0061] Furthermore, in this embodiment 1, the outer peripheral end of the surface electrode 5 is disposed on the field insulating film 4, and when viewed from above, it is located inside the SBD100 compared to the outer peripheral end of the terminal well region 2. With this structure, high electric fields can be suppressed on the upper surface of the epitaxial layer 32 and the upper surface of the surface protective film 6.

[0062] Furthermore, in this embodiment 1, SiC is used as the material for the epitaxial substrate 30. SiC has a wider bandgap than Si, and SiC semiconductor devices exhibit superior voltage withstand capability, higher allowable current density, and higher heat resistance compared to Si semiconductor devices, thus enabling high-temperature operation. However, the material of the epitaxial substrate 30 is not limited to SiC, especially in cases where the termination region is prone to a high electric field; for example, other wide-bandgap semiconductors such as gallium nitride (GaN) and gallium oxide (Ga2O3) can also be used. Additionally, the semiconductor device involved in this embodiment 1 can also be a diode other than an SBD, such as a pn junction diode or a junction barrier Schottky (JBS) diode.

[0063] <Manufacturing Method>

[0064] Next, the manufacturing method of the SBD100 according to Embodiment 1 will be described.

[0065] First, prepare to use a relatively high concentration (i.e., n) + The single-crystal substrate 31 contains n-type impurities and has low resistance. In this embodiment 1, a SiC substrate with a polytype of 4H and an offset angle of 4 degrees or 8 degrees is used as the single-crystal substrate 31.

[0066] Next, SiC epitaxial growth is performed on the single-crystal substrate 31, thereby forming an n-type epitaxial layer 32 on the single-crystal substrate 31. The impurity concentration of the n-type in the epitaxial layer 32 is lower than that of the n-type in the single-crystal substrate 31, for example, 1 × 10⁻⁶. 14 / cm 3 Above and 1×10 17 / cm 3 Therefore, an epitaxial substrate 30 comprising a single-crystal substrate 31 and an epitaxial layer 32 is formed.

[0067] Next, a photolithography process is used to form a resist mask on the epitaxial layer 32, which has a pattern that opens the formation regions of the terminal well region 2 and the FLR region 3. Then, using this resist mask as an implantation mask, p-type impurities (acceptors), such as Al or B (boron), are ion implanted into the epitaxial layer 32, thereby forming a p-type terminal well region 2 on the upper part of the epitaxial layer 32. The terminal well region 2 and the FLR region 3 can be formed simultaneously, and the preferred dosage of the p-type impurity is 1.0 × 10⁻⁶. 13 / cm 2 Above and 3.0×10 13 / cm 2 The following, for example, could also be 2.0 × 10 13 / cm 2Alternatively, the terminal well region 2 and the FLR region 3 can be formed through separate processes by repeating the formation of the implantation mask (patterning of the resist mask) and ion implantation multiple times.

[0068] Regarding the ion implantation energy in FLR region 3, it is, for example, above 100 keV and below 700 keV when the p-type impurity is Al. In this case, according to the above dose [cm -2 The calculated peak impurity concentration of floating trap 3a is 1 × 10⁻⁶. 17 / cm 3 Above and 1×10 19 / cm 3 Furthermore, even when implantation is performed at high energies above 300 keV, and the upper surface of the epitaxial layer 32 is etched due to various manufacturing processes, the p-type impurity concentration on the upper surface of the multiple floating traps 3a can still be 1.0 × 10⁻⁶. 17 cm -3 the following.

[0069] After forming the terminal well region 2 and the FLR region 3, annealing is performed using a heat treatment apparatus at a temperature of 1300°C or higher and 1900°C or lower for 30 seconds to 1 hour in an inert gas atmosphere such as argon (Ar). Through this annealing, impurities added to the epitaxial layer 32 by ion implantation are activated.

[0070] Next, a material layer, such as a SiO2 film with a thickness of 1 μm, is formed on the surface S2 of the epitaxial substrate 30 using, for example, CVD (Chemical Vapor Deposition). Then, the material layer of the field insulating film 4 is patterned using photolithography and etching processes, thereby forming the field insulating film 4. At this time, the field insulating film 4 is patterned in such a way that it covers at least a portion of the terminal well region 2 and the FLR region 3 and extends beyond the outer periphery of the FLR region 3.

[0071] Subsequently, on the epitaxial layer 32 and the field insulating film 4, the material layer of the Schottky electrode 5a and the material layer of the electrode pad 5b are stacked in this order, for example by sputtering. As the material layer of the Schottky electrode 5a, for example, a Ti film with a thickness of 100 nm is used, and as the material layer of the electrode pad 5b, for example, an Al film with a thickness of 3 μm is used.

[0072] Next, a photoresist mask with a pattern of the surface electrode 5 is formed on the material layer of the electrode pad 5b using a photolithography process. Then, using this photoresist mask as an etching mask, the material layers of the electrode pad 5b and the Schottky electrode 5a are patterned, thereby forming the surface electrode 5 including the Schottky electrode 5a and the electrode pad 5b. At this time, the outer peripheral end of the surface electrode 5 is patterned in a position that is inside the SBD100, closer to the outer peripheral end of the terminal well region 2 connected to the surface electrode 5, and is not positioned above the FLR region 3.

[0073] Dry etching or wet etching can be used in the etching of the material layer of electrode pad 5b and the material layer of Schottky electrode 5a. In the case of wet etching, an etchant such as hydrofluoric acid (HF) or phosphoric acid-based etchant can be used.

[0074] Furthermore, the patterning of the Schottky electrode 5a and the patterning of the electrode pad 5b can also be performed separately. In this case, it is also possible to... Figure 1 The position of the end of the Schottky electrode 5a in the left-right direction (also called the planar direction) is offset from the position of the end of the electrode pad 5b. For example, the electrode pad 5b can be made to protrude beyond the end of the Schottky electrode 5a, so that the electrode pad 5b completely covers the Schottky electrode 5a. Alternatively, the end of the Schottky electrode 5a can be made to protrude beyond the end of the electrode pad 5b, so that the end of the Schottky electrode 5a is not covered by the electrode pad 5b.

[0075] Next, a material layer such as a resin layer, is formed on the surface S2 of the epitaxial substrate 30 to cover the outer region RO side of the field insulating film 4 and the surface electrode 5. For example, this resin layer is formed by coating photosensitive polyimide. Then, the resin layer is patterned by a photolithography process, thereby forming the surface protective film 6. At this time, the surface protective film 6 on the central portion of the surface electrode 5, which becomes an external connection terminal, is removed. Furthermore, in this embodiment 1, the resin layer of the surface protective film 6 is patterned in the outer region RO to cover the outer region RO side of the surface electrode 5 and at least a portion of the epitaxial substrate 30 in the outer region RO.

[0076] Furthermore, in the outer region RO, the resin layer of the surface protective film 6 can be patterned such that its outer peripheral end is exposed on the field insulating film 4 without being in contact with the surface S2 of the epitaxial substrate 30. However, the resin layer of the surface protective film 6 is patterned such that the surface protective film 6 is in contact with the field insulating film 4 above the FLR region 3.

[0077] Finally, on the back side S1 of the epitaxial substrate 30, a back electrode 8 is formed, for example, by sputtering, thereby forming... Figure 1 The SBD100 is shown. Furthermore, the formation of the back electrode 8 can be performed before or after the formation of the material layer of the Schottky electrode 5a and the material layer of the electrode pad 5b. As the material of the back electrode 8, for example, a metal containing one or more of Ti, Ni, Al, Cu, and Au can be used. Additionally, the thickness of the back electrode 8 is preferably, for example, 50 nm or more and 2 μm or less. For example, a Ti / Au bilayer film with a thickness of 1 μm can also be used as the back electrode 8.

[0078] <Action>

[0079] Next, the operation of the SBD100 according to Embodiment 1 will be explained. In addition, in the following description, the regions that function as p-type regions that combine the terminal trap region 2 and the FLR region 3 will sometimes be referred to as "p-type functional regions 2 and 3".

[0080] When a negative voltage is applied to the back electrode 8 with reference to the potential of the surface electrode 5, the SBD100 becomes a state where current flows from the surface electrode 5 to the back electrode 8, i.e., a conducting state (on state). Conversely, when a positive voltage is applied to the back electrode 8 with reference to the potential of the surface electrode 5, the SBD100 becomes a non-conducting state (off state).

[0081] When the SBD100 is in the off state, a large electric field is applied near the upper surface of the drift layer 1 in the inner region RI (active region) and near the interface of the pn junction between the drift layer 1 and the p-type functional regions 2 and 3. The voltage applied to the back electrode 8 when this electric field reaches the critical electric field and avalanche breakdown occurs is defined as the maximum voltage (avalanche voltage) of the SBD100. Typically, the rated voltage VR [V] of the SBD100 is specified in a manner that allows the SBD100 to be used in a voltage range where avalanche breakdown does not occur.

[0082] When SBD100 is in the off state, the depletion layer is located on the upper surface of the drift layer 1 in the active region and the pn junction interface between the drift layer 1 in the active region and the p-type functional regions 2 and 3, in the direction towards the single crystal substrate 31. Figure 1 (downward direction) and the direction from drift layer 1 toward the outer periphery ( Figure 1 The depletion layer extends to the right (direction). Additionally, the depletion layer extends from the pn junction interface between drift layer 1 and p-type functional regions 2 and 3 into the p-type functional regions 2 and 3. The extent of this extension largely depends on the impurity concentrations in the terminal well region 2 and the floating well 3a. That is, when the impurity concentrations in the terminal well region 2 and the floating well 3a are increased, the extension of the depletion layer within the p-type functional regions 2 and 3 is suppressed, and the top of the depletion layer becomes located near the boundary between the terminal well region 2 and the drift layer 1.

[0083] For example, the dose in terminal trap region 2 and floating trap 3a is set to 1.0 × 10⁻⁶. 13 / cm 2 Under the above conditions, the depletion layer does not expand significantly within the p-type functional regions 2 and 3, and a potential gradient is mainly generated between the floating wells 3a in the FLR region 3. A potential gradient is generated on the upper surface of the epitaxial layer 32 between the floating wells 3a in a direction perpendicular to this upper surface (planar direction), and the potential increases from the inner periphery to the outer periphery of the FLR region 3. On the upper surface of the epitaxial layer 32, the portion with the largest potential gradient between the floating wells 3a is the peripheral portion of the pn junction on the outer periphery side of each floating well 3a, where a high electric field is formed.

[0084] However, depending on the fabrication process of SBD100, or the electric field generated when a high voltage is applied, the fixed charge trapped in a portion of the epitaxial layer 32 near the upper surface of FLR region 3 may affect the propagation mode of the depletion layer in that portion. Considering this, a dose of 1.5 × 10⁻⁶ is desired for terminal well region 2. 13 / cm 2 above.

[0085] Here, we consider the case where SBD100 is in a cutoff state under high humidity. The sealing resin 41, which is provided in a manner that covers the surface protective film 6, sometimes contains moisture. For example, if the surface protective film 6 is made of a resin material with high hygroscopicity, such as polyimide, under high humidity, the surface protective film 6 contains a large amount of moisture, which may reach the upper surface of the epitaxial layer 32. In addition, if the surface protective film 6 is made of a material such as SiN with high resistance, cracks can easily enter the surface protective film 6 due to stress generated during the process, and the upper surface of the epitaxial layer 32 may be exposed to moisture through the cracks. In these cases, when the epitaxial layer 32 of the FLR region 3 acts as an anode by applying a voltage to the SBD100 in the cutoff state, a SiO2 generation reaction occurs, particularly around the p-type terminal well region 2, where Si atoms and moisture generate SiO2. The following formula (1) is the chemical formula representing the SiO2 generation reaction.

[0086] Si + 2H₂O + 4h + →SiO2+4H + ……(1)

[0087] When the SiO2 formation reaction occurs on the upper surface of the epitaxial layer 32 in the FLR region 3, sometimes the upper part of the region where SiO2 is formed, namely the field insulating film 4 and the surface protective film 6, is lifted and peeled off. In this case, a leakage path different from the usual one is formed in the SBD100, which may impair the insulation reliability of the SBD100.

[0088] The inventors discovered that the SiO2 formation reaction depends on the electric field around the pn junction on the outer periphery between the floating wells 3a. For example, the reliability guidelines for power semiconductor devices specified by ECPE (European Center for Power Electronics), namely AQG324, stipulate a test in which a voltage of 0.8 times the rated voltage of SBD100 is applied for an extended period at 85°C and 85% RH. Considering this, in this embodiment 1, the electric field strength on the upper surface of the epitaxial layer 32 of the FLR region 3 is configured such that when a voltage of 0.8 times the rated voltage VR[V] of SBD100 is applied to the back electrode 8 with reference to the surface electrode 5, the electric field strength is 1MV / cm or less. That is, the electric field strength on the upper surface of the epitaxial substrate 30, which is located outside the outer periphery of the terminal well region 2 relative to the SBD100, is 1MV / cm or less. The inventors discovered that with this structure, the SiO2 formation reaction can be significantly suppressed even under the high temperature and high humidity environment described above.

[0089] In addition, the dose in each floating trap 3a is greater than 3.0 × 10⁻⁶. 13 / cm 2 In some cases, holes (h) sometimes appear around the periphery of the pn junction on the outer periphery of the floating trap 3a. + As the supply of SiO2 increases, the SiO2 formation reaction expressed by equation (1) above is accelerated. Therefore, it is expected that even when the electric field strength on the upper surface of the epitaxial layer 32 in the FLR region 3 is suppressed to below 1 MV / cm, the dose of each floating well 3a will be 3.0 × 10⁻⁶. 13 / cm 2 Below. Furthermore, in order to reduce the number of holes (h) on the upper surface of the epitaxial layer 32 in the FLR region 3. + The supply of ion implantation energy is expected to be above 300 keV when forming terminal trap region 2 and FLR region 3.

[0090] Especially in high-voltage ratings where the n-type concentration on the upper surface of the epitaxial layer 32 is low, such as ratings with an avalanche voltage of 1.7 kV or higher, it is desirable to have an ion implantation energy of 500 keV or higher when forming the terminal well region 2 and the FLR region 3. By forming the terminal well region 2 and the FLR region 3 at high energy, it is possible to achieve a p-type impurity concentration of 1.0 × 10⁻⁶ on the upper surface of multiple floating wells 3a. 17 cm -3 Therefore, the SiO2 formation reaction represented by the above formula (1) can be suppressed.

[0091] Furthermore, when the SBD100 is exposed to a high-humidity environment, moisture may sometimes remain at the interface between the semiconductor chip and the sealing resin 41, which may have peeled off due to stress, or moisture may be trapped and retained at the interface between the semiconductor chip and the sealing resin 41. For example, if the sealing resin 41 is made of a thermosetting material such as epoxy, the sealing resin 41 may expand due to the presence of moisture, causing minor peeling at the interface between the semiconductor chip and the sealing resin 41, thereby easily trapping moisture at the interface between the surface protective film 6 and the sealing resin 41. Additionally, if the sealing resin 41 is made of a gel-like material such as silicone, moisture that has permeated through the sealing resin 41 may easily remain at the interface between the surface protective film 6 and the sealing resin 41.

[0092] When the SBD100 is in the off state, especially on the upper surface of the surface protective film 6 above the FLR region 3 which becomes a high electric field, the ionization of retained moisture is accelerated, easily forming a leakage path different from the usual one. The central portion of the opening in the surface protective film 6 in the electrode pad 5b acts as a cathode through this leakage path, and corrosion of the electrode pad 5b develops at the inner peripheral end of the surface protective film 6. Therefore, if the electrode pad 5b expands, cracks may form in the Schottky electrode 5a, or the surface protective film 6 may peel off from the surface electrode 5, potentially compromising the insulation reliability of the SBD100.

[0093] The inventors discovered that the corrosion of the electrode pad 5b depends on the electric field of the upper surface of the surface protective film 6 above the FLR region 3. Therefore, in this embodiment 1, when a voltage of 0.8 times the rated voltage VR[V] of the SBD100 is applied to the back electrode 8 based on the surface electrode 5, the electric field strength of the upper surface of the surface protective film 6 on the FLR region 3, i.e., the surface protective film 6 located outside the SBD100 beyond the outer periphery of the terminal well region 2, is configured to be 0.1 MV / cm or less. The inventors discovered that, according to this structure, even under high temperature and high humidity conditions specified in the reliability guidelines, the formation of leakage paths at the interface between the surface protective film 6 and the sealing resin 41 can be suppressed, and corrosion of the electrode pad 5b exposed from the surface protective film 6 can be suppressed. In other words, the inventors discovered that the insulation reliability of the SBD100 can be improved.

[0094] The electric field strength on the upper surface of the epitaxial layer 32 of such FLR region 3, or the electric field strength on the upper surface of the surface protective film 6 above FLR region 3, depends on at least one of the number of floating traps 3a and the overall width of FLR region 3. Furthermore, in this specification, for example, at least one of A, B, C, ... and Z refers to any one of all combinations obtained by selecting one or more from the group of A, B, C, ... and Z.

[0095] Here, it is explained that the insulation reliability of SBD100 can be improved by making the electric field strength of the upper surface of the epitaxial substrate 30, which is located on the outer side of the outer periphery of the terminal well region 2, less than 1 MV / cm, and the electric field strength of the upper surface of the surface protective film 6, which is located on the outer side of the outer periphery of the terminal well region 2, less than 0.1 MV / cm.

[0096] Figure 5 This graph represents the results of applying voltages to five SBD100 samples under different electric field conditions A to C at high temperature and high humidity, and using the Weibull distribution to determine the time when the failure probability is 50% based on the resulting measurement results. Figure 6 It is a graph representing the time when the failure probability of conditions A to C is 50%.

[0097] like Figure 5 As shown, differences in lifetime (i.e., time with a 50% failure probability) arise due to the differences in the surface electric field of SiC (i.e., the electric field strength on the upper surface of the epitaxial substrate 30) and the surface electric field of the protective film (i.e., the electric field strength on the upper surface of the surface protective film 6).

[0098] For example in Figure 5 In the comparison of the lifetimes under conditions A and B (SiC surface electric field greater than 1MV / cm) and condition C (SiC surface electric field less than 1MV / cm), it can be seen that the lifetime increases when the SiC surface electric field becomes below 1.0MV / cm. Furthermore, Figure 6 The curve represents the baseline of the data. For example... Figure 6 As shown, it is believed that when the surface electric field of SiC is suppressed to below 1.0 MV / cm, the time to failure 50% increases significantly, i.e., the lifetime is extended. If this is extended, it is believed that the lifetime increases as the surface electric field of SiC becomes 1 MV / cm, 0.9 MV / cm, and 0.8 MV / cm.

[0099] Additionally, for example in Figure 5 Based on the comparison of the lifetimes under conditions A and B (where the surface electric field of the protective film is greater than 0.1 MV / cm) and condition C (where the surface electric field of the protective film is less than 0.1 MV / cm), it can be seen that the lifetime is extended when the surface electric field of the protective film is below 0.1 MV / cm. Extending this point, it is assumed that the lifetime extends as the surface electric field of the protective film becomes 0.1 MV / cm, 0.09 MV / cm, and 0.08 MV / cm.

[0100] Figure 7 (a) is a figure showing the appearance of the upper surface of the sample after 753 hours of applying an electric field of 1.1 MV / cm on the SiC surface. Figure 7(b) is a diagram showing the appearance of the upper surface of the sample after 2166 hours of applying an electric field C with a surface electric field of 0.9 MV / cm on SiC. Figure 7 (c) is a graph showing the appearance of the upper surface of the sample after an electric field of 0.8 MV / cm was applied to the SiC surface for 939 hours. According to... Figure 7 The appearance of (a) and Figure 7 A comparison of the appearances in (b) and (c) shows that when the surface electric field of SiC is below 1.0 MV / cm, the degradation of the FLR region 3 on the upper surface of the epitaxial layer 32 caused by the SiO2 formation reaction is suppressed. It is believed that the lifetime is extended by suppressing the degradation of the FLR region 3 in this way.

[0101] Furthermore, in this embodiment 1, in order to suppress the electric field strength on the surface of the epitaxial layer 32 of the FLR region 3 to below 1 MV / cm, the number of floating wells 3a is increased within the range of achieving an avalanche voltage higher than the rated voltage. In this structure, although it substantially does not contribute to reducing the electric field strength inside the epitaxial layer 32 of the FLR region 3, i.e., increasing the avalanche voltage, it can reduce the electric field strength on the upper surface of the epitaxial layer 32 of the FLR region 3. Furthermore, from the viewpoint of cost reduction, it is desirable to reduce the number of floating wells 3a within the range of achieving an avalanche voltage higher than the rated voltage of the SBD100.

[0102] Furthermore, in this embodiment 1, the number of floating traps 3a is somewhat large, and the concentration of p-type impurities per unit area of ​​the floating traps 3a, i.e., the dose, is 1.0 × 10⁻⁶. 13 cm -2 The preferred value is 1.5 × 10⁴. 13 cm -2 That's all. Based on this structure, the peak electric field intensity on the upper surface of the epitaxial layer 32 in the FLR region 3 is almost unaffected by the spacing S of the individual floating wells 3a. x and width L x The only change is in the peak position of the electric field intensity. Specifically, the peak position of the electric field intensity shifts towards the outer periphery of FLR region 3 when the dose increases, and shifts towards the inner periphery of FLR region 3 when the dose decreases. Furthermore, the peak positions of the electric field intensity are spaced S apart from each floating trap 3a. x In the case of a small displacement, it tends to move towards the outer periphery of FLR region 3, at intervals of S. x In large cases, it tends to move towards the inner periphery of FLR region 3.

[0103] Figure 8 This is a graph showing the TCAD simulation results for a 3.3kV-rated semiconductor chip using the SBD100, which is particularly prone to the aforementioned problems due to its high voltage rating (e.g., avalanche voltage above 1.7kV). Figure 8 If the number of floating wells 3a is 33 or more (=3.3kV (rated voltage VR) ÷ 100), the electric field strength on the upper surface of the epitaxial layer 32 of the FLR region 3 when a voltage of 0.8 times the rated voltage VR is applied can be suppressed to 1MV / cm or less. Similarly, if the number of floating wells is 39 or more (=3.3kV (rated voltage VR) ÷ 85), the electric field strength can be suppressed to 0.9MV / cm or less. If the number of floating wells is 51 or more (=3.3kV (rated voltage VR) ÷ 65), the electric field strength can be suppressed to 0.8MV / cm or less.

[0104] Figure 9 This is a graph showing the TCAD simulation results of a semiconductor chip at the 6.5kV level. If... Figure 9 If the number of floating wells 3a is 65 or more (=6.5kV (rated voltage VR) ÷ 100), the electric field strength on the upper surface of the epitaxial layer 32 of the FLR region 3 when a voltage of 0.8 times the rated voltage VR is applied can be suppressed to 1MV / cm or less. Although not shown, if the number of floating wells is 77 or more (=6.5kV (rated voltage VR) ÷ 85), the electric field strength can be suppressed to 0.9MV / cm or less, and if the number of floating wells is 100 or more (=6.5kV (rated voltage VR) ÷ 65), the electric field strength can be suppressed to 0.8MV / cm or less.

[0105] Considering the above, by setting the floating well 3a to be VR÷100 or more relative to the rated voltage VR[V], the electric field strength on the upper surface of the epitaxial layer 32 of the FLR region 3 when a voltage of 0.8 times the rated voltage VR is applied can be suppressed to below 1MV / cm. As a result, SBD100 with high insulation reliability can be obtained.

[0106] Furthermore, in practical applications, a voltage of rated voltage VR[V]×0.8 or higher is sometimes applied to the back electrode 8 with reference to the surface electrode 5. In order to suppress the formation reaction of SiO2 on the upper surface of the epitaxial layer 32 of the FLR region 3 even in this case, the number of floating traps 3a is preferably VR÷80 or more, and more preferably VR÷65 or more.

[0107] On the other hand, in order to suppress the electric field intensity on the upper surface of the surface protective film 6 above the FLR region 3 to below 0.1 MV / cm, the width of the FLR region 3 becomes important. The upper surface of the surface protective film 6 has an electric field intensity distribution that flattens the electric field intensity distribution on the upper surface of the epitaxial layer 32 of the FLR region 3. Specifically, the upper surface of the surface protective film 6 has an electric field intensity distribution such as… Figure 10 In the case of a rectangular electric field intensity distribution as shown, the electric field intensity can be minimized.

[0108] The theoretical minimum value E of the electric field strength on the surface of the protective film 6, when the electric field applied to the back electrode 8 relative to the surface electrode 5 is set as V, is relative to the length W from the outer periphery of the terminal well region 2 to the outer periphery of the FLR region 3. FLR The equation E=V / W holds true. FLR In addition, the length W FLR Corresponds to the width of FLR region 3.

[0109] Figure 11 This is a graph showing the calculated electric field strength when a rated voltage VR[V]×0.8 (2640V) is applied to an SBD100 at a voltage level of 3.3kV. (See figure below.) Figure 11 As shown, in order to suppress the electric field intensity on the upper surface of the surface protective film 6 above the FLR region 3 to below 0.1 MV / cm, theoretically, it is only necessary to reduce the length W FLR Set it to 264μm, which is above the rated voltage VR[V]×0.08μm.

[0110] Figure 12 This is a graph showing the calculated electric field strength when a rated voltage VR[V]×0.8 (5200V) is applied to a 6.5kV SBD100. (For example...) Figure 12 As shown, in order to suppress the electric field intensity on the upper surface of the surface protective film 6 above the FLR region 3 to below 0.1 MV / cm, theoretically, it is only necessary to reduce the length W FLR Set it to 520μm, which is above the rated voltage VR[V]×0.08μm.

[0111] Considering the above, in order to suppress the electric field intensity on the upper surface of the surface protective film 6 above the FLR region 3 to below 0.1 MV / cm, it is only necessary to reduce the electric field intensity from the outer periphery of the terminal well region 2 to the outer periphery of the FLR region 3 by a length W. FLR Set it to a value above the rated voltage VR×0.08μm. Here, according to... Figure 11 and Figure 12 As can be seen from the plotted portion, in length W FLR With a rated voltage VR×0.09μm or higher, the electric field strength can be reduced to below 0.09MV / cm, and within a length W FLR When the rated voltage is above VR×0.1μm, the electric field strength can be reduced to below 0.08MV / cm.

[0112] On the upper surface of the surface protective film 6 above the FLR region 3, the number of floating traps 3a is increased or the width L of the floating traps 3a is increased. xThe value of can reduce the electric field strength. On the other hand, the electric field strength distribution on the upper surface of the surface protective film 6 above the FLR region 3, which becomes the upper surface of the epitaxial layer 32 of the FLR region 3, is smoothed out, so there is a peak in the electric field strength distribution at a certain position on the upper surface of the surface protective film 6 above the FLR region 3.

[0113] Therefore, as long as the length W is made FLR It can be longer than theoretically required to suppress the electric field strength on the upper surface of the surface protective film 6 above the FLR region 3 to below 0.1 MV / cm. In other words, it only requires a distance longer than the length W. FLR Setting it to VR[V]×0.08μm is acceptable, preferably VR×0.09μm or higher, and more preferably VR×0.1μm or higher. With this structure, corrosion of the electrode pad 5b in the area where the surface protective film 6 opens in the center of the electrode pad 5b can be suppressed even under high temperature and high humidity environments.

[0114] Furthermore, in the structure where the surface electrode 5 protrudes outward beyond the terminal well region 2, a region with a low potential is formed above the FLR region 3. Therefore, this sometimes leads to an increase in the electric field intensity on the upper surface of the epitaxial layer 32 of the FLR region 3 and the upper surface of the surface protective film 6 above the FLR region 3. In contrast, in this embodiment 1, the outer peripheral end of the surface electrode 5 is located inside the SBD 100 when viewed from above, compared to the outer peripheral end of the terminal well region 2, thus suppressing the increase in electric field intensity.

[0115] <Summary of Implementation Method 1>

[0116] As described above, the SBD100 according to Embodiment 1 can suppress the formation of leakage paths that are different from those of the norm when high voltage is applied in a high temperature and high humidity environment, thereby improving the insulation reliability of the SBD100.

[0117] <Implementation Method 2>

[0118] <Device Structure>

[0119] Figure 13 This is a partial cross-sectional view showing the structure of the MOSFET 200, which is the semiconductor device according to Embodiment 2. Figure 14 This is a top view of the MOSFET200, along... Figure 14 The view section of the BB line is equivalent to Figure 13 .in addition, Figure 15 This is a cross-sectional view showing the structure of the smallest unit structure, i.e., the unit cell UC, of ​​the MOSFET 200 located in the inner region RI, which is the active region. Multiple MOSFETs are arranged in the inner region RI of the MOSFET 200. Figure 15 The unit cell UC shown is in Figure 13 The left-hand portion shows the outermost unit cell UC. Furthermore, in... Figures 13-15 In the middle, for those with Figure 1 and Figure 2 The structural elements of the SBD100 involved in Embodiment 1 shown have the same function as those in Embodiment 1, and the following descriptions that are repeated in Embodiment 1 are omitted.

[0120] Similar to implementation method 1, the configuration is as follows: Figure 13 The semiconductor substrate of the MOSFET 200 involved in this embodiment 2 is an epitaxial substrate 30 including a single crystal substrate 31 and an epitaxial layer 32.

[0121] Above the epitaxial layer 32, which serves as the inner region RI of the active region, a p-type (second conductivity type) element well region 9 is selectively provided. Above the element well region 9, an n-type source region 11 and a p-type contact region 19, which has a higher impurity concentration than the p-type, are selectively provided.

[0122] Above the epitaxial layer 32 of the outer region RO, which serves as the terminal region, a p-type boundary region 20 is selectively provided, which surrounds the active region when viewed from above. The inner peripheral end of the boundary region 20 corresponds to the boundary between the inner region RI and the outer region RO. The boundary region 20 includes a low-concentration portion 20a with a relatively low p-type impurity concentration and a high-concentration portion 20b with a relatively high p-type impurity concentration, selectively provided above the low-concentration portion 20a. Furthermore, the conductivity type of the high-concentration portion 20b is not limited to p-type, but can also be n-type.

[0123] Above the epitaxial layer 32, which serves as the outer region RO of the terminal region, a terminal well region 2, which surrounds the boundary region 20 when viewed from above, is selectively provided. Furthermore, the impurity concentration of the p-type in the terminal well region 2 is lower than that of the p-type in the boundary region 20.

[0124] The portion of the n-type epitaxial layer 32, which is the inner region RI of the active region, excluding the element well region 9, the source region 11, and the contact region 19, includes a drift layer 1 through which current flows by drift. This drift layer 1 is the same as the drift layer 1 described in Embodiment 1.

[0125] Similar to embodiment 1, the terminal trap region 2 is a frame-shaped (ring-shaped) region that surrounds the active region and has an outer peripheral end when viewed from above, functioning as a so-called protective ring. Figure 14 In the diagram, the outer perimeter of the terminal trap region 2 is shown by dashed lines.

[0126] like Figure 13Thus, similar to Embodiment 1, an FLR region 3, which surrounds the terminal trap region 2 when viewed from above, is selectively provided on the upper part of the epitaxial layer 32 of the outer region RO, serving as the terminal region. The FLR region 3, like in Embodiment 1, includes a plurality of p-type floating traps 3a with floating potentials. The spacing and width of the floating traps 3a can also be the same as the spacing S described in Embodiment 1. x and width L x same.

[0127] On the surface S2 of the epitaxial substrate 30 of the active region, i.e., on the epitaxial substrate 30 of the field insulating film 4 on the side of the active region, a gate insulating film 12 is provided, which includes a source region 11, a device well region 9, and a drift layer 1. Furthermore, a gate electrode 13 is provided on the gate insulating film 12. The portion of the upper part of the device well region 9, covered by the gate insulating film 12 and the gate electrode 13, between the source region 11 and the drift layer 1, forms a channel region where an inversion channel is formed when the MOSFET 200 is turned on.

[0128] An interlayer insulating film 14 covers the gate electrode 13, and a source electrode 51 is disposed on the interlayer insulating film 14. The source electrode 51 and the gate electrode 13 are electrically insulated from each other by the interlayer insulating film 14. The source electrode 51 is electrically connected to the source region 11 and the contact region 19 through a contact hole disposed in the interlayer insulating film 14. The source electrode 51 and the contact region 19 form an ohmic contact. A back electrode 8, which functions as a drain electrode, is formed on the back side S1 of the epitaxial substrate 30.

[0129] like Figure 13 Thus, the gate insulating film 12, the gate electrode 13, the interlayer insulating film 14, and a portion of the source electrode 51 extend beyond the boundary between the inner region RI and the outer region RO to the outer region RO, arranged in a manner spanning both the inner region RI and the outer region RO. The source electrode 51 disposed in the outer region RO is electrically connected to the high-concentration portion 20b of the boundary region 20 through a contact hole disposed in the interlayer insulating film 14, forming an ohmic contact or a Schottky contact. In addition, the gate electrode 13 disposed in the outer region RO is disposed on the high-concentration portion 20b of the boundary region 20 through the gate insulating film 12, and extends in a frame shape when viewed from above, similar to the high-concentration portion 20b.

[0130] On the surface S2 of the epitaxial substrate 30 in the terminal region, in addition to the aforementioned structural elements arranged across the inner region RI and the outer region RO, a field insulating film 4, a gate wiring electrode 52, and a surface protective film 6 are also provided. Furthermore, Figure 14 In the top view, the field insulating film 4 and other components are omitted, and the position of the end of the surface protective film 6, i.e. the outline of the surface protective film 6, is shown with solid lines.

[0131] Similar to Embodiment 1, the field insulating film 4 covers a portion of the terminal well region 2 and the FLR region 3, extending beyond the outer periphery of the FLR region 3. A gate wiring electrode 52 is disposed on the interlayer insulating film 14 covering the gate electrode 13 disposed in the outer region RO. Furthermore, the gate wiring electrode 52 is electrically connected to the gate electrode 13 through a contact hole disposed in the interlayer insulating film 14. The gate wiring electrode 52 functions as an electrode receiving a gate signal (control signal) for controlling the electrical path between the source electrode 51 and the back electrode 8. The gate wiring electrode 52 is separate from and electrically insulated from the source electrode 51.

[0132] The gate wiring electrode 52, like the gate electrode 13 disposed in the outer region RO, extends in a frame shape when viewed from above. In this embodiment 2, the gate wiring electrode 52 is as follows: Figure 14 This includes a gate wiring 52w surrounding the source electrode 51 and a gate pad 52p positioned to enter a recess in a straight portion located on one side of the generally rectangular source electrode 51. The gate wiring 52w and the gate pad 52p are interconnected. Figure 13 The gate wiring electrode 52 shown is Figure 14 The gate wiring 52w corresponds to this. The gate pad 52p functions as an external connection terminal for inputting gate signals. Furthermore, in... Figure 14 In the middle, the gate pad 52p is disposed in the straight part of the generally rectangular source electrode 51, but it can also be disposed in the corner.

[0133] The surface electrode 5 according to Embodiment 2 includes a source electrode 51 and a gate wiring electrode 52. The source electrode 51 and the gate wiring electrode 52 are disposed on the epitaxial substrate 30 with the interlayer insulating film 14 as a separator, and are separated on the interlayer insulating film 14. The surface electrode 5 is disposed on the surface S2 of the epitaxial substrate 30 on the active region side of the field insulating film 4, and is disposed on at least a portion of the surface S2 of the epitaxial substrate 30 in the inner region RI. The surface electrode 5 is disposed throughout the entire inner region RI, and a portion of it extends beyond the boundary between the inner region RI and the outer region RO to the outer region RO. In addition, a portion of the surface electrode 5 is disposed such that it rests on the interlayer insulating film 14.

[0134] exist Figure 13In this example, the inner peripheral end of the field insulating film 4 is connected to the outer peripheral end of the interlayer insulating film 14, and the gate electrode 13 and the surface electrode 5 are disposed at a position closer to the inside of the MOSFET 200 than the inner peripheral end of the field insulating film 4. However, the interlayer insulating film 14, the gate electrode 13, and the surface electrode 5 can also be disposed on top of the field insulating film 4. Moreover, the source electrode 51 can also be connected to the high-concentration portion 20b of the boundary region 20 through a contact hole penetrating both the interlayer insulating film 14 and the field insulating film 4. However, when viewed from above, the outer peripheral ends of the surface electrode 5 and the gate electrode 13 are located closer to the inside of the MOSFET 200 than the outer peripheral end of the terminal well region 2, and are disposed above the FLR region 3 without extending beyond the outer peripheral end of the terminal well region 2.

[0135] The surface protective film 6 is an upper surface film disposed on the field insulating film 4 and covering the outer region RO side end of the surface electrode 5. In this embodiment 2, the surface protective film 6 covers the source electrode 51 and the gate wiring electrode 52, and at least a portion of the surface S2 of the epitaxial substrate 30 covering the outer region RO. The surface protective film 6 is as follows: Figure 14 Thus, openings are provided in the central portion of the source electrode 51 and the central portion of the gate pad 52p. Therefore, the source electrode 51 and the gate pad 52p function as external connection terminals.

[0136] In the above structure, the overall length of the FLR region 3 and the number of multiple floating wells 3a are varied according to the required withstand voltage of the semiconductor device, just as in Embodiment 1. That is, in the MOSFET 200 according to Embodiment 2, the number of multiple floating wells 3a is VR÷100 or more relative to the rated voltage VR[V] of the MOSFET 200, preferably VR÷85 or more, and more preferably VR÷65 or more. According to this structure, a MOSFET 200 with high insulation reliability can be obtained.

[0137] Furthermore, in this embodiment 2, the length from the outer periphery of the terminal well region 2 to the outer periphery of the FLR region 3 is VR×0.08μm or more, preferably VR×0.09μm or more, and more preferably VR×0.1μm or more. With this structure, a MOSFET 200 with higher insulation reliability can be obtained.

[0138] Furthermore, in this Embodiment 2, similarly to Embodiment 1, SiC is used as the material for the epitaxial substrate 30. Additionally, the semiconductor device involved in this Embodiment 2 can also be a transistor other than a MOSFET, such as a JFET (Junction FET) or an IGBT (Insulated Gate Bipolar Transistor). Furthermore, while the semiconductor device involved in this Embodiment 2 is a planar transistor, it can also be a trench transistor.

[0139] <Manufacturing Method>

[0140] Next, the manufacturing method of the MOSFET 200 according to Embodiment 2 will be described. First, similar to Embodiment 1, an epitaxial substrate 30 including a single crystal substrate 31 and an epitaxial layer 32 is formed.

[0141] Then, the following steps are repeated: a photolithography step to form a resist mask; and an ion implantation step to form an impurity region on the upper part of the epitaxial layer 32 by using the resist mask as an implantation mask. Thus, a terminal well region 2, an FLR region 3, a device well region 9, a source region 11, a contact region 19, and a boundary region 20 are formed on the epitaxial layer 32. For example, N (nitrogen) is used as an n-type impurity, and Al or B is used as a p-type impurity. The terminal well region 2 and the FLR region 3 can also be formed together in the same ion implantation step. The low-concentration portion 20a of the device well region 9 and the boundary region 20 can also be formed together in the same ion implantation step. Furthermore, the high-concentration portion 20b of the contact region 19 and the boundary region 20 can also be formed together in the same ion implantation step.

[0142] The impurity concentration in the low-concentration portion 20a of the element trap region 9 and the boundary region 20 is preferably, for example, 1.0 × 10⁻⁶. 18 / cm 3 Above and 1.0×10 20 / cm 3 The impurity concentration in the high-concentration portion 20b of the source region 11, contact region 19, and boundary region 20 is higher than the impurity concentration in the element well region 9, preferably 1.0 × 10⁻⁶. 19 / cm 3 Above and 1.0×10 21 / cm 3 the following.

[0143] The dosage and formation conditions of the p-type impurity in FLR region 3 are the same as those in Embodiment 1. When the implanted N impurity is an n-type impurity, the ion implantation energy is preferably 20 keV or higher and 300 keV or lower. Afterwards, annealing is performed using a heat treatment apparatus at a temperature of 1500°C or higher. Thus, the impurity added to the epitaxial layer 32 by ion implantation is activated.

[0144] Next, for example, by CVD, a material layer such as a SiO2 film with a thickness of 0.5 μm or more and 2 μm or less is formed on the surface S2 of the epitaxial substrate 30 as the field insulating film 4, and the material layer is patterned to form the field insulating film 4. The field insulating film 4 is patterned in such a way that it covers at least a portion of the terminal well region 2 and the FLR region 3 and extends beyond the outer peripheral end of the FLR region 3.

[0145] Next, the surface of the epitaxial layer 32 not covered by the field insulating film 4 is thermally oxidized to form, for example, a SiO2 film as the gate insulating film 12. Then, a conductive polysilicon film is formed on the gate insulating film 12 by a reduced-pressure CVD method, for example, and the polysilicon film is patterned by photolithography and etching processes to form the gate electrode 13. At this time, the gate electrode 13 can also be formed by placing it on the field insulating film 4.

[0146] Subsequently, a SiO2 film is formed as an interlayer insulating film 14 using a CVD method, for example. Then, a contact hole is formed by passing through the gate insulating film 12 and the interlayer insulating film 14 through a photolithography and etching process, reaching each of the high-concentration portions 20b of the contact region 19, the source region 11, and the boundary region 20. In addition, in the terminal region, a contact hole is formed that passes through the interlayer insulating film 14 and reaches the gate electrode 13, and the interlayer insulating film 14 on the field insulating film 4 and the interlayer insulating film 14 on the outer periphery of the field insulating film 4 are removed.

[0147] Next, a material layer for the surface electrode 5 is formed on the surface S2 of the epitaxial substrate 30 by sputtering or vapor deposition. Similarly, a material layer for the back electrode 8 is formed on the back side S1 of the epitaxial substrate 30. The material for the surface electrode 5 can be, for example, a metal containing at least one of Ti, Ni, Al, Cu, and Au, or an Al alloy such as Al-Si. The material for the back electrode 8 can be, for example, a metal containing one or more of Ti, Ni, Al, Cu, and Au. Furthermore, a silicide film can be formed in advance on the portion of the epitaxial substrate 30 that is in contact with the surface electrode 5 or the back electrode 8 by heat treatment. Additionally, the formation of the back electrode 8 can be performed at the end of all processes.

[0148] Next, the material layer of the surface electrode 5 is patterned through photolithography and etching processes to form the separated source electrode 51 and gate wiring electrode 52.

[0149] Finally, a surface protective film 6 is formed covering the outer region RO side end of the surface electrode 5 and the field insulating film 4. The surface protective film 6 is formed, for example, by coating and exposing a photosensitive polyimide to a desired shape. In this embodiment 2, the surface protective film 6 is formed in the outer region RO in such a way that it covers the outer region RO side end of the surface electrode 5 and at least a portion of the epitaxial substrate 30 covering the outer region RO. Through the above, a surface protective film is formed... Figure 13 The MOSFET200 shown.

[0150] <Action>

[0151] Next, the operation of the MOSFET 200 according to Embodiment 2 will be described in two states. Furthermore, in the following description, the regions that function as the p-type regions that combine the terminal well region 2 and the FLR region 3 will be referred to as p-type functional regions 2 and 3.

[0152] The first state is when a positive voltage above the threshold voltage is applied to the gate electrode 13; this state is hereinafter referred to as the "on state". When the MOSFET 200 is in the on state, an inversion channel is formed in the channel region. The inversion channel becomes the path for electrons, which act as charge carriers, to flow between the source region 11 and the drift layer 1. When a high voltage is applied to the back electrode 8 with reference to the potential of the source electrode 51, the on state is achieved, and current flows through the single-crystal substrate 31 and the drift layer 1. At this time, the voltage between the source electrode 51 and the back electrode 8 is called the "on voltage", and the current flowing between the source electrode 51 and the back electrode 8 is called the "on current". The on current only flows through the active region where the channel exists and does not flow through the terminal region.

[0153] The second state is when a voltage less than the threshold voltage is applied to the gate electrode 13; this state is hereinafter referred to as the "off state". When the MOSFET 200 is in the off state, no inversion channel is formed in the channel region, and therefore no on-current flows. Therefore, when a high voltage is applied between the source electrode 51 and the back electrode 8, this high voltage is maintained. At this time, the voltage between the gate electrode 13 and the source electrode 51 is very small relative to the voltage between the source electrode 51 and the back electrode 8, thus a high voltage is applied between the gate electrode 13 and the back electrode 8.

[0154] In the off state, a high voltage is also applied between the gate wiring electrode 52 and the gate electrode 13 and the back electrode 8 in the termination region. However, similar to the electrical contact formed between the element well region 9 and the source electrode 51 in the active region, an electrical contact between the boundary region 20 and the source electrode 51 is formed in the termination region. Therefore, a high electric field is applied to suppress the gate insulating film 12 and the interlayer insulating film 14.

[0155] The termination region of MOSFET 200 functions similarly to the off state of SBD 100 as described in Embodiment 1. That is, a large electric field is applied near the interface of the pn junction between drift layer 1 and the p-type functional regions 2 and 3. The voltage applied to the back electrode 8 when avalanche breakdown occurs due to this electric field reaching a critical field is defined as the maximum voltage (avalanche voltage) of MOSFET 200. Typically, the rated voltage VR [V] of MOSFET 200 is specified in such a way that it can be used within a voltage range where avalanche breakdown does not occur.

[0156] When MOSFET200 is in the off state, the depletion layer extends from the pn junction interface between the drift layer 1 of the active region and the device well region 9, the boundary region 20, and the p-type functional regions 2 and 3 toward the single crystal substrate 31. Figure 13 (downward direction) and the direction toward the outer periphery of drift layer 1 ( Figure 13 (To the right) it expands. Thus, when MOSFET200 is in the off state, the depletion layer expands in the same way as the off state of SBD100 described in Embodiment 1, and a high electric field is formed in the peripheral portion of the pn junction on the outer periphery of each floating well 3a. Moreover, especially around the p-type terminal well region 2, a SiO2 generation reaction, represented by the chemical formula (1) above, occurs, which involves the generation of SiO2 from Si atoms and water.

[0157] Therefore, in this second embodiment, similar to the first embodiment, the electric field strength on the upper surface of the epitaxial layer 32 in the FLR region 3 is set to 1 MV / cm or less when a voltage of 0.8 times the rated voltage VR[V] of the MOSFET 200 is applied to the back electrode 8 based on the surface electrode 5. In other words, the electric field strength on the upper surface of the epitaxial substrate 30, which is located outside the MOSFET 200 at the outer periphery of the terminal well region 2, is set to 1 MV / cm or less. The inventors have discovered that, according to this structure, the SiO2 formation reaction can be significantly suppressed even under high temperature and high humidity conditions, similar to the first embodiment.

[0158] Furthermore, in order to reduce the number of holes (h) on the upper surface of the epitaxial layer 32 in the FLR region 3 + The supply of ion implantation energy is expected to be above 300 keV when forming terminal trap region 2 and FLR region 3.

[0159] Especially in high-voltage ratings where the n-type concentration on the upper surface of the epitaxial layer 32 is low, such as ratings with an avalanche voltage of 1.7 kV or higher, it is desirable to have an ion implantation energy of 500 keV or higher when forming the terminal well region 2 and the FLR region 3. By forming the terminal well region 2 and the FLR region 3 at high energy, it is possible to achieve a p-type impurity concentration of 1.0 × 10⁻⁶ on the upper surface of multiple floating wells 3a. 17 cm -3 Therefore, the SiO2 formation reaction represented by the above formula (1) can be suppressed.

[0160] Furthermore, when the MOSFET200 is exposed to a high-humidity environment, the ionization of trapped moisture on the upper surface of the surface protective film 6 above the FLR region 3 is accelerated, easily forming leakage paths that differ from the norm. Therefore, corrosion of the surface electrode 5 develops at the inner periphery of the surface protective film 6, potentially compromising the insulation reliability of the MOSFET200.

[0161] Therefore, in this embodiment 2, when a voltage of 0.8 times the rated voltage VR[V] of the MOSFET 200 is applied to the back electrode 8 with reference to the surface electrode 5, the electric field strength of the surface protective film 6 on the FLR region 3, that is, the surface protective film 6 located on the outer side of the MOSFET 200 from the outer periphery of the terminal well region 2, is 0.1 MV / cm or less. The inventors have discovered that, according to this structure, even under the high temperature and high humidity environment specified in the reliability guidelines, the formation of leakage paths at the interface between the surface protective film 6 and the sealing resin 41 and the corrosion of the electrode pad 5b can be suppressed, thereby improving the insulation reliability of the MOSFET 200.

[0162] Furthermore, in this embodiment 2, similarly to embodiment 1, the number of floating traps 3a is increased to a certain extent, and the concentration of p-type impurities per unit area of ​​the floating traps 3a, i.e., the dose, is 1.0 × 10⁻⁶. 13 cm -2 The preferred value is 1.5 × 10⁴. 13 cm -2 above.

[0163] Furthermore, in the MOSFET 200 of this embodiment 2, similarly to the SBD 100 of embodiment 1, a... Figure 8 and Figure 9As a result, if the number of floating wells 3a is 100 or more times the rated voltage VR, the electric field strength on the upper surface of the epitaxial layer 32 of the FLR region 3 when a voltage of 0.8 times the rated voltage VR is applied can be suppressed to 1 MV / cm or less. Similarly, if the number of floating wells is 85 or more times the rated voltage VR, the electric field strength can be suppressed to 0.9 MV / cm or less, and if the number of floating wells is 65 or more times the rated voltage VR, the electric field strength can be suppressed to 0.8 MV / cm or less.

[0164] Furthermore, in the MOSFET 200 of this embodiment 2, similarly to the SBD 100 of embodiment 1, a... Figure 11 and Figure 12 The result. Therefore, if the length W from the outer periphery of the terminal trap region 2 to the outer periphery of the FLR region 3 is... FLR If the rated voltage VR[V]×0.08μm or higher, the electric field strength on the upper surface of the surface protective film 6 above the FLR region 3 can be suppressed to below 0.1MV / cm. Similarly, if the length W FLR If the rated voltage VR[V]×0.09μm is above, the above electric field strength can be suppressed to below 0.09MV / cm. If the length W FLR If the rated voltage VR[V]×0.1μm is above, the above electric field strength can be suppressed to below 0.08MV / cm.

[0165] Furthermore, the gate electrode 13 can also be placed on the field insulating film 4. However, in a structure where the gate electrode 13 protrudes outward beyond the terminal well region 2, a low-potential region is created above the FLR region 3. Therefore, this sometimes leads to an increase in the electric field strength on the upper surface of the epitaxial layer 32 of the FLR region 3 and the upper surface of the surface protective film 6 above the FLR region 3. In contrast, in this embodiment 2, the outer peripheral end of the gate electrode 13 is located inside the MOSFET 200 when viewed from above, compared to the outer peripheral end of the terminal well region 2, thus suppressing the increase in electric field strength.

[0166] <Summary of Implementation Method 2>

[0167] As described above, the MOSFET 200 according to Embodiment 2 can suppress the formation of leakage paths that are different from those of the norm when high voltage is applied in a high temperature and high humidity environment, thereby improving the insulation reliability of the MOSFET 200.

[0168] <Implementation Method 3>

[0169] This embodiment 3 describes the power conversion device and its manufacturing method. In this embodiment 3, the semiconductor device described in embodiments 1 and 2 above is applied to the power conversion device. Therefore, in the following description, the same structural elements as those described in embodiments 1 and 2 are illustrated with the same reference numerals, and detailed descriptions are omitted as appropriate.

[0170] <Structure>

[0171] The power conversion device described in Embodiment 3 is not limited to a specific application; the following describes its application to a three-phase inverter.

[0172] Figure 16 This is a block diagram that schematically represents the structure of a power conversion system including the power conversion device 2200 according to Embodiment 3.

[0173] Figure 16 The power conversion system shown includes a power source 2100, a power conversion device 2200, and a load 2300. The power source 2100 is a DC power source that supplies DC power to the power conversion device 2200. The power source 2100 can be composed of various power sources, such as a DC system, solar cells, or batteries. Alternatively, the power source 2100 can be composed of a rectifier circuit or an AC-DC converter connected to an AC system. Furthermore, the power source 2100 can also be composed of a DC-DC converter that converts DC power output from a DC system into a predetermined power.

[0174] The power conversion device 2200 is a three-phase inverter connected between the power source 2100 and the load 2300. The power conversion device 2200 converts the DC power supplied from the power source 2100 into AC power and supplies the AC power to the load 2300.

[0175] In addition, such as Figure 16 As shown, the power conversion device 2200 includes: a conversion circuit 2201 that converts DC power into AC power and outputs it; a drive circuit 2202 that outputs drive signals for driving each switching element of the conversion circuit 2201; and a control circuit 2203 that outputs control signals for controlling the drive circuit 2202 to the drive circuit 2202.

[0176] The load 2300 is a three-phase motor driven by AC power supplied from the power conversion device 2200. Furthermore, the load 2300 is not limited to a specific application; it is a motor mounted on various electrical equipment, such as those used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning systems.

[0177] The details of the power conversion device 2200 are described below. The conversion circuit 2201 includes a switching element and a freewheeling diode (not shown). Furthermore, by performing a switching operation by the switching element, the conversion circuit 2201 converts the DC power supplied from the power source 2100 into AC power and supplies the AC power to the load 2300.

[0178] Various circuit structures can be conceived for the specific circuit structure of the conversion circuit 2201. The conversion circuit 2201 involved in this embodiment 3 is a 2-level three-phase full-bridge circuit, and can be composed of 6 switching elements and 6 freewheeling diodes connected in anti-parallel with each switching element.

[0179] At least one of the switching elements and freewheeling diodes in the conversion circuit 2201 is employed, using a semiconductor device as described in either Embodiment 1 or 2 above. Six switching elements are connected in series in pairs to form upper and lower arms, each upper and lower arm constituting a phase (U phase, V phase, and W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower arm, i.e., the three output terminals of the conversion circuit 2201, are connected to the load 2300.

[0180] The drive circuit 2202 generates drive signals for driving the switching elements of the conversion circuit 2201, and supplies the drive signals to the control electrodes of the switching elements of the conversion circuit 2201. Specifically, based on the control signals output from the control circuit 2203 (described later), the drive circuit 2202 outputs drive signals that turn the switching elements on and drive signals that turn the switching elements off to the control electrodes of each switching element.

[0181] When the switching element is kept in the ON state, the drive signal is a voltage signal above the threshold voltage of the switching element (ON signal); when the switching element is kept in the OFF state, the drive signal is a voltage signal below the threshold voltage of the switching element (OFF signal).

[0182] Control circuit 2203 controls the switching elements of converter circuit 2201 to supply the desired power to load 2300. Specifically, control circuit 2203 calculates the on-time (on-state) of each switching element of converter circuit 2201 based on the power to be supplied to load 2300. For example, converter circuit 2201 can be controlled by pulse width modulation (PWM) control, which modulates the on-time of the switching elements according to the voltage to be output.

[0183] Furthermore, the control circuit 2203 outputs control commands (control signals) to the drive circuit 2202, causing it to output turn-on signals to the switching elements that should be in the on state and turn-off signals to the switching elements that should be in the off state at each time point. Based on this control signal, the drive circuit 2202 outputs turn-on or turn-off signals to the control electrodes of each switching element as drive signals.

[0184] Typically, semiconductor devices are embedded in gels or epoxy resins, but these materials cannot completely block moisture, thus compromising the insulation reliability of the semiconductor device. In contrast, in the power conversion device 2200 according to Embodiment 3, at least one of the switching element and freewheeling diode in the conversion circuit 2201 is a semiconductor device from either Embodiment 1 or 2, which improves insulation reliability. Therefore, the reliability of the power conversion device 2200 can be improved.

[0185] Furthermore, in this embodiment 3, an example of applying the semiconductor devices of embodiments 1 and 2 to a 2-level three-phase inverter has been described, but the semiconductor devices of embodiments 1 and 2 can be applied to various power conversion devices.

[0186] Furthermore, while a two-level power conversion device has been described in this embodiment 3, the semiconductor devices of embodiments 1 and 2 can be applied to three-level or multi-level power conversion devices. Additionally, when supplying power to a single-phase load, the semiconductor devices of embodiments 1 and 2 can be applied to a single-phase inverter. Furthermore, when supplying power to a DC load, the semiconductor devices of embodiments 1 and 2 can be applied to a DC-DC converter or an AC-DC converter.

[0187] Furthermore, the power conversion device according to Embodiment 3 is not limited to applications where the load is an electric motor. For example, it can also be used as a power supply device for electrical discharge machining (EDM), laser processing machines, induction heating cookers, or contactless power supply systems. Additionally, the power conversion device according to Embodiment 3 can also be used as a power regulator in solar power generation systems or energy storage systems.

[0188] <Manufacturing Method>

[0189] Next, a method for manufacturing the power conversion device related to Embodiment 3 will be described. First, a semiconductor device is manufactured using the manufacturing methods described in Embodiments 1 and 2. Then, a conversion circuit 2201 having the semiconductor device is embedded in the power conversion device 2200. The conversion circuit 2201 is a circuit for converting and outputting input power.

[0190] Then, a drive circuit 2202 is embedded in the power conversion device 2200. The drive circuit 2202 is a circuit that outputs a drive signal for driving a semiconductor device to the semiconductor device. Then, a control circuit 2203 is embedded in the power conversion device 2200. The control circuit 2203 is a circuit that outputs a control signal for controlling the drive circuit 2202 to the drive circuit 2202.

[0191] The semiconductor devices described in Embodiments 1 and 2 show examples made of SiC semiconductors, but can be made of other wide-bandgap semiconductors such as gallium nitride (GaN) and gallium oxide (Ga2O3) as switching elements. Switching elements made of wide-bandgap semiconductors can be used in high-voltage regions where unipolar operation is difficult with Si switching elements, significantly reducing switching losses during switching operation. Therefore, a significant reduction in power loss can be achieved.

[0192] Furthermore, switching elements made of wide-bandgap semiconductors have low power losses and high heat resistance. Therefore, when constructing a power module with a cooling section, the heat sink fins can be miniaturized, thus enabling further miniaturization of the semiconductor module.

[0193] Furthermore, switching elements made of wide-bandgap semiconductors are suitable for high-frequency switching operations. Therefore, in the case of converter circuits with high frequency requirements, increasing the switching frequency also enables the miniaturization of reactors or capacitors connected to the converter circuit.

[0194] In the above embodiments, the physical properties, materials, dimensions, shapes, relative configurations, or implementation conditions of each structural element are sometimes described; however, these are illustrative in all respects, and this disclosure is not limited to the described contents. Therefore, numerous variations not illustrated are conceivable within the scope of this disclosure.

[0195] For example, this includes cases where arbitrary structural elements are modified, added to, or omitted, as well as cases where at least one structural element in at least one embodiment is extracted and combined with structural elements in other embodiments.

[0196] Furthermore, as long as no contradiction arises, the structural element described as having "one" in the above embodiments can also have "more than one". Moreover, the structural element constituting this disclosure is a conceptual unit; one structural element may include multiple structures, or one structural element may correspond to a part of a certain structure. Additionally, as long as they perform the same function, the structural elements of this disclosure can include structures with other structures or shapes.

[0197] Furthermore, it is possible to freely combine the various embodiments and variations, or to appropriately modify or omit the various embodiments and variations.

[0198] The above description is illustrative in all respects, not limiting. It should be understood that countless variations not illustrated can be conceived.

[0199] (Explanation of reference numerals in the attached image)

[0200] 2: Termination well region; 3: FLR region; 3a: Floating well; 4: Field insulating film; 5: Surface electrode; 6: Surface protective film; 8: Back electrode; 12: Gate insulating film; 13: Gate electrode; 14: Interlayer insulating film; 30: Epitaxial substrate; 41: Sealing resin; 51: Source electrode; 52: Gate wiring electrode; 100: SBD; 200: MOSFET; 2201: Conversion circuit; 2202: Drive circuit; 2203: Control circuit; W FLR :length.

Claims

1. A semiconductor device, having defined an active region and a terminal region surrounding the active region when viewed from above, comprising: A semiconductor substrate of the first conductivity type made of silicon carbide; A second type of conductive terminal well region is selectively disposed on the upper part of the semiconductor substrate of the terminal region, surrounds the active region when viewed from above, and has an outer peripheral end; The FLR region is selectively disposed on the upper part of the semiconductor substrate of the terminal region, and surrounds the terminal well region when viewed from above. A field insulating film is disposed on the upper surface of the semiconductor substrate, covering a portion of the terminal well region and the FLR; A surface electrode is disposed on the semiconductor substrate on the side closer to the active region than the field insulating film; An upper surface film, disposed on the field insulating film, covers the end portion of the surface electrode on the terminal region side; and The back electrode is disposed on the lower surface of the semiconductor substrate. The FLR region includes multiple floating wells of a second conductivity type, which surround the terminal well region when viewed from above, and are arranged in a nested manner, each having a floating potential. The number of the plurality of floating wells is greater than or equal to VR / 100 relative to the rated voltage VR[V] of the semiconductor device.

2. The semiconductor device according to claim 1, wherein, The distance from the outer periphery of the terminal trap region to the outer periphery of the FLR region is VR×0.08μm or more.

3. A semiconductor device, having defined an active region and a terminal region surrounding the active region when viewed from above, comprising: A semiconductor substrate of the first conductivity type made of silicon carbide; A second type of conductive terminal well region is selectively disposed on the upper part of the semiconductor substrate of the terminal region, surrounding the active region when viewed from above; The FLR region is selectively disposed on the upper part of the semiconductor substrate of the terminal region, and surrounds the terminal well region when viewed from above. A field insulating film is disposed on the semiconductor substrate, covering a portion of the terminal well region and the FLR; A surface electrode is disposed on the semiconductor substrate on the side closer to the active region than the field insulating film; An upper surface film, disposed on the field insulating film, covers the end portion of the surface electrode on the terminal region side; and The back electrode is disposed on the back side of the semiconductor substrate. The FLR region includes multiple floating wells of a second conductivity type, which surround the terminal well region when viewed from above, and are arranged in a nested manner, each having a floating potential. When a voltage of 0.8 times the rated voltage VR[V] of the semiconductor device is applied to the back electrode with reference to the surface electrode, the electric field strength on the upper surface of the semiconductor substrate on the outer side of the semiconductor device, relative to the outer periphery of the terminal well region, is less than 1 MV / cm.

4. The semiconductor device according to claim 3, wherein, When a voltage of 0.8 times the rated voltage VR[V] of the semiconductor device is applied to the back electrode with reference to the surface electrode, the electric field strength of the upper surface film of the upper surface film on the outer side of the semiconductor device, which is closer to the outer periphery of the terminal well region, is less than 0.1 MV / cm.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The outer peripheral end of the surface electrode is disposed on the field insulating film and, when viewed from above, is located on the inner side of the semiconductor device than the outer peripheral end of the terminal well region.

6. The semiconductor device according to any one of claims 1 to 5, wherein, It also has: A gate insulating film is disposed on the semiconductor substrate on the side closer to the active region than the field insulating film; A gate electrode is disposed on the gate insulating film; as well as An interlayer insulating film covers the gate electrode. The surface electrode includes a source electrode and a gate wiring electrode disposed on the semiconductor substrate through the interlayer insulating film and divided on the interlayer insulating film. When viewed from above, the source electrode, the gate wiring electrode, and the outer peripheral end of the gate electrode are located inside the semiconductor device than the outer peripheral end of the terminal well region.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The impurity concentration of the second conductivity type per unit area of ​​the plurality of floating wells is 1.5 × 10⁻⁶. 13 cm -2 above.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The impurity concentration of the second conductivity type on the upper surface of the plurality of floating wells is 1.0 × 10⁻⁶. 17 cm -3 the following.

9. The semiconductor device according to any one of claims 1 to 8, wherein, The avalanche voltage of the semiconductor device is above 1.7kV.

10. The semiconductor device according to any one of claims 1 to 9, wherein, It also has a gel-like sealing resin covering the upper surface film.

11. The semiconductor device according to any one of claims 1 to 9, wherein, It also contains a thermosetting sealing resin that covers the upper surface film.

12. A method for manufacturing a semiconductor device, as described in claim 8. The FLR region is formed using ion implantation energies of 300 keV or higher.

13. A power conversion device, comprising: A conversion circuit having a semiconductor device according to any one of claims 1 to 11, the conversion circuit converting and outputting input power; The driving circuit outputs a driving signal to the semiconductor device. as well as The control circuit outputs control signals to the drive circuit.

Images