Fully functional back power protection (BPP) input / output (I / O) circuit with overvoltage protection including electrostatic discharge

Abstract

An apparatus includes: an overvoltage detector configured to generate an overvoltage indication signal indicating whether a first voltage at an input / output (I / O) port is higher than an overvoltage threshold; control circuitry configured to generate a control signal based on the overvoltage indication signal; a dummy power supply coupled to the I / O port and configured to provide a supply voltage to the control circuitry; and a clamping circuitry configured to generate a shunt current from the I / O port via an electrostatic discharge (ESD) protection diode, wherein the shunt current is enabled or disabled based on the control signal.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to pending U.S. nonprovisional application No. 18 / 508,052, filed November 13, 2023, which has been assigned to the assignee of this application and is expressly incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0003] Various aspects of this disclosure generally relate to multi-point bus input / output (I / O) circuits, and more specifically, to fully functional reverse power protection (BPP) input / output (I / O) circuits with overvoltage protection including electrostatic discharge (ESD). Background Technology

[0004] A multipoint bus can be coupled to a group of integrated circuits (ICs) (or other components) to facilitate data / clock communication between the ICs in that group. In some cases, one or more ICs in the group may be turned off. It may be desirable to keep the multipoint bus in use to facilitate data / clock communication between the ICs that are turned on, without affecting or being affected by the one or more ICs that are turned off. Summary of the Invention

[0005] The following is a simplified overview of one or more specific implementations to provide a basic understanding of such implementations. This overview is not an exhaustive summary of all envisioned implementations, nor is it intended to identify key or essential elements of all implementations, nor to depict the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] One aspect of this disclosure relates to an apparatus. The apparatus includes: an overvoltage detector including an input terminal coupled to an input / output (I / O) port; a control circuit including an input terminal coupled to an output terminal of the overvoltage detector; a dummy power supply including an input terminal and an output terminal, the input terminal coupled to the I / O port and the output terminal coupled to the control circuit; and a clamping circuit coupled between the I / O port and a voltage rail via a diode, wherein the clamping circuit includes an input terminal coupled to the output terminal of the control circuit.

[0007] Another aspect of this disclosure relates to an apparatus. The apparatus includes: an overvoltage detector configured to generate an overvoltage indication signal indicating whether a first voltage at an input / output (I / O) port exceeds an overvoltage threshold; a control circuit configured to generate a control signal based on the overvoltage indication signal; a dummy power supply coupled to the I / O port and configured to provide a supply voltage to the control circuit; and a clamping circuit configured to generate a shunt current from the I / O port via a diode, wherein the shunt current is enabled or disabled based on the control signal.

[0008] Another aspect of this disclosure relates to a method. The method includes: generating an overvoltage indication signal indicating whether a voltage at an input / output (I / O) port is higher than an overvoltage threshold; generating a control signal based on the overvoltage indication signal; and enabling or disabling the shunting of current generated by the voltage from the I / O port to a voltage rail based on the control signal.

[0009] Another aspect of this disclosure relates to an apparatus. The apparatus includes: means for generating an overvoltage indication signal indicating whether the voltage at an input / output (I / O) port is higher than an overvoltage threshold; means for generating a control signal based on the overvoltage indication signal; and means for enabling or disabling the shunting of current generated by the voltage from the I / O port to a voltage rail based on the control signal.

[0010] To achieve the foregoing and related objectives, one or more embodiments include the features fully described below and specifically pointed out in the claims. The following description and accompanying figures illustrate certain exemplary aspects of one or more embodiments in detail. However, these aspects are merely indications of a number of ways in which the principles of the various embodiments may be employed, and the description of the embodiments is intended to include all such aspects and their equivalents. Attached Figure Description

[0011] Figure 1 A block diagram of an example data communication system according to one aspect of this disclosure is illustrated.

[0012] Figure 2 A block diagram of another example data communication system according to another aspect of this disclosure is illustrated.

[0013] Figure 3 A block diagram / schematic representation of an example input / output (I / O) circuit according to another aspect of this disclosure is illustrated.

[0014] Figure 4 A block diagram of another example input / output (I / O) circuit according to another aspect of this disclosure is illustrated.

[0015] Figure 5 A schematic diagram illustrating an example overvoltage detector and associated operating diagram according to another aspect of this disclosure is shown.

[0016] Figure 6 A schematic diagram of an example resistor-capacitor (RC) clamping control circuit according to another aspect of this disclosure is illustrated.

[0017] Figure 7 A schematic diagram illustrating an example pseudo-power source according to another aspect of this disclosure is shown.

[0018] Figure 8 A schematic diagram of an example resistor-capacitor (RC) clamp according to another aspect of this disclosure is illustrated.

[0019] Figure 9 A block diagram of an example integrated circuit (IC) according to another aspect of this disclosure is illustrated.

[0020] Figure 10 A block diagram of another example input / output (I / O) circuit according to another aspect of this disclosure is illustrated.

[0021] Figure 11 A block diagram of another example input / output (I / O) circuit according to another aspect of this disclosure is illustrated.

[0022] Figure 12 A flowchart illustrating an example method for providing overvoltage protection to input / output (I / O) circuits according to another aspect of this disclosure is provided. Detailed Implementation

[0023] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0024] As described in the specification, it may be desirable to keep multiple bus points available to facilitate data / clock communication between powered-on ICs, while not affecting or being unaffected by one or more powered-off ICs. For this purpose, the input / output (I / O) circuitry needs to provide reverse power protection (BPP) and electrostatic discharge (ESD) protection. For example, as... Figure 3The I / O circuit 300 shown not only provides this type of protection but also has a relatively small footprint and low current leakage. However, the I / O circuit 300 may not be able to distinguish between normal data / clock bus signaling and ESD events, therefore it is not fully functional for multi-point buses because it cannot be used for data / clock communication.

[0025] In some specific embodiments of the invention, the I / O circuit includes an overvoltage detector coupled between the I / O port and a lower voltage rail Vssx. The clamping circuit can be enabled by disabling the clamping circuit when the overvoltage indication signal CLP_CTL generated by the overvoltage detector indicates that the voltage Vbus at the I / O port is consistent with data / clock communication signaling, and by enabling the clamping circuit when the overvoltage indication signal CLP_CTL generated by the overvoltage detector indicates that the voltage Vbus at the I / O port is higher than an overvoltage threshold (e.g., consistent with an ESD event or other overvoltage event). This enables the full functionality of the multipoint bus (e.g., for data / clock signaling).

[0026] Furthermore, further improvements to the above-mentioned inventive concept are proposed. In some specific embodiments, a dummy power supply is used to generate a supply voltage for the control circuit when the I / O circuit is de-energized and there is no supply voltage at the higher voltage rail Vddpx.

[0027] Figure 1 A block diagram of an example data communication system 100 according to one aspect of this disclosure is illustrated. The data communication system 100 includes a first integrated circuit (IC) 110, a second IC 120, and a third IC 130, all coupled to a multipoint bus 140. It should be understood that other ICs, circuits, and components may also be coupled to the multipoint bus 140. Components (e.g., ICs 110, 120, and 130) may use access arbitration available for use by the multipoint bus 140 to access the multipoint bus 140 for transmitting data or clock communication signaling to one or more other components on the multipoint bus 140.

[0028] In this example, the first IC 110 includes a transmit (Tx) driver 112, which is configured to receive and process the input data signal D. i (For example, amplification, voltage level conversion, etc.) to generate output data signal D o The Tx driver 112 can be coupled to a first higher voltage rail Vddpx1 and a lower voltage rail Vssx (e.g., ground) and receive power (e.g., supply voltage / current) from them. The Tx driver 112 includes an output terminal (e.g., where an output data signal D is generated). oThe output is coupled to an input / output (I / O) port (e.g., an IC pin) 114, which in turn is coupled to a bus pad 142 on a multipoint bus 140. As discussed in more detail herein, the first IC 110 is powered on, as indicated by the first higher voltage rail Vddpx1 designated as "on". Furthermore, according to this example, the output data signal D... o The destination is IC 130.

[0029] The second IC 120 also includes a transmit (Tx) driver 122 comprising a first field-effect transistor (FET) MP (e.g., a p-channel FET) and a second FET MN (e.g., an n-channel FET) series coupled between a second higher voltage rail Vddpx2 and a lower voltage rail Vssx (e.g., ground). In this example, IC 120 can be turned off, as indicated by the second higher voltage rail Vddpx2 being designated as "off". The first FET MP includes a source and body region coupled to the second higher voltage rail Vddpx2, a gate coupled to the gate of the second FET MN, and a drain coupled to the drain of the second FET MN. The second MN includes a source and body region coupled to the lower voltage rail Vssx. The gates of the first FET MP and the second FET MN serve as inputs to the Tx driver 122; however, in this example, since IC 120 is off, no data signal is shown as being applied to the input of the Tx driver 122. The drains of the first FET MP and the second FET MN are used as the output of the Tx driver 122 and coupled to an I / O port (e.g., an IC pin) 124, which in turn is coupled to a bus pad 144 on a multipoint bus 140.

[0030] The second IC 120 also includes electrostatic discharge (ESD) protection diodes D1 and D2. The first ESD protection diode D1 includes an anode coupled to I / O port 124 and a cathode coupled to a second higher voltage rail Vddpx2. The second ESD protection diode D2 includes a cathode coupled to I / O port 124 and an anode coupled to a lower voltage rail Vssx. For reverse power protection (BPP) further described herein, a third (parasitic) diode D3 is shown between the p-type doped drain and the n-type doped body region of the first FET MP.

[0031] In this example, the second IC 120 does not have reverse power protection (BPP). That is, when the Tx driver 112 of the first IC 110 provides the output data signal D to the multipoint bus 140... o When used to send data to IC 130, it is related to the output data signal D. oThe high logic level associated currents flow to the second higher voltage rail Vddpx2 via ESD protection diode D1 and drain-body diode D3 of the first FET MP, as indicated by the dashed arrows. If the second higher voltage rail Vddpx2 is pulled down to Vssx (e.g., grounded) when the second IC 120 is turned off, the current flowing to Vssx via diodes D1 / D3 and Vddpx2 is relatively large; thereby disrupting the output data signal D on the multipoint bus 140. o This makes it difficult, or even impossible, for IC 130 to receive and detect the output data signal D. o If the second higher voltage rail Vddpx2 floats when the second IC 120 is off, the current flowing through diodes D1 / D3 will charge the second higher voltage rail Vddpx2 to an unknown voltage, and may unintentionally and / or unpredictably turn on other circuitry on the second higher voltage rail Vddpx2, potentially causing system malfunctions (e.g., enabling system reset circuitry). The charging of floating Vddpx2 may also consume power and may corrupt the output data signal D. o .

[0032] Figure 2 A block diagram illustrating another example of a data communication system 200 according to another aspect of this disclosure is shown. The data communication system 200 is similar to the data communication system 100 discussed above. Specifically, the data communication system 200 includes a first IC 210, which includes a Tx driver 212 configured to process an input data signal D. i To generate output data signal D o A Tx driver 212 is coupled to and receives power from a first higher voltage rail Vddpx1 (on) and a lower voltage rail Vssx (e.g., ground). The output of Tx driver 212 is coupled to an I / O port (e.g., an IC pin) 214, which in turn is coupled to a bus pad 242 on a multipoint bus 240. The multipoint bus 240 is also coupled to a second IC 220 and a third IC 230. The second IC 220 includes a Tx driver 222 (e.g., FET MP and FET MN, connected to the body region of an MP via a custom well contact), coupled between a second higher voltage rail Vddpx2 (off) and a lower voltage rail Vssx (e.g., ground). The output of Tx driver 222 is coupled to an I / O port (e.g., an IC pin) 224, which in turn is coupled to a bus pad 244 on the multipoint bus 240.

[0033] In this example, the second IC 220 is configured with reverse power protection (BPP) to prevent or significantly reduce the output data signal D on the multipoint bus 240. oThe associated current (intended for use by the third IC 230) is drawn into the second IC 220, causing the problem outlined above relative to the second IC 120, which lacks a BPP. The second IC 220 has a BPP because the ESD protection diodes D1 and D2 no longer draw current from the multipoint bus 240. To provide ESD protection, the second IC 220 includes a fast retraction device 226 coupled between I / O port 224 and Vssx.

[0034] The fast retraction device 226 is a relatively large gate-grounded n-channel FET that breaks down and conducts when the voltage on the multipoint bus 240 is very high, such as in an ESD event. Since the ESD protection diode D1 is no longer present, there is essentially no output data signal D on the multipoint bus 240. o The resulting current flows into the second, higher voltage rail Vddpx2 and causes the problems discussed earlier. However, the fast retraction device 226 has some issues, including a relatively large footprint, significant current leakage, and it cannot be well controlled / defined by the IC foundry because it is not typically a standard cell and may not be available at certain technology nodes.

[0035] Figure 3 A block diagram / schematic representation of an example input / output (I / O) circuit 300 according to another aspect of this disclosure is illustrated. The I / O circuit 300 may be an example of circuitry configured to provide data or clock signals on a multipoint bus for data or clock communication with one or more devices coupled to the multipoint bus. An integrated circuit (IC) may include multiple or a group of such I / O circuits 300. In this example, the I / O circuit 300 provides reverse power protection (BPP) and electrostatic discharge (ESD) protection. However, the I / O circuit 300 provides such protection at the cost that the multipoint bus is not fully functional.

[0036] I / O circuitry 300 includes a transmit (Tx) driver 310 (e.g., FET MP and FET MN, the body region of MP connected to a custom well contact), which is coupled between a high voltage rail Vddpx (off in this example) and a low voltage rail Vssx (e.g., ground), with gates coupled together to form the input of Tx driver 310 and drains coupled together to form the output of Tx driver 310, as similarly discussed in detail with reference to Tx driver 122. The output of Tx driver 310 is coupled to I / O port 320, which in turn is coupled to a multipoint bus (…). Figure 3 (Not shown in the image).

[0037] I / O circuitry 300 includes a first ESD protection diode D1, which includes an anode coupled to I / O port 320 and a cathode coupled to a floating bus Vdd_ESD. The floating bus is not a bus driven to a known voltage. A second ESD protection diode D2 includes a cathode coupled to I / O port 320 and an anode coupled to a lower voltage rail Vssx. I / O port 320 also includes a resistor-capacitor (RC) clamp 330 coupled between the floating bus Vdd_ESD and the lower voltage rail Vssx. Additionally, I / O port 320 includes a fourth diode D4, which includes an anode coupled to a higher voltage rail Vddpx and a cathode coupled to the floating bus Vdd_ESD to provide a supply voltage to RC clamp 330 when Vddpx is on.

[0038] In this example, the ESD protection diode D1 is not coupled to the higher voltage rail Vddpx; therefore, I / O circuit 300 has reverse power protection (BPP) because any current from the multipoint bus will not flow to the higher voltage rail Vddpx. However, when there is a data or clock signal transition on the multipoint bus, the rising transition of the transition signal causes the voltage on the floating bus Vdd_ESD to similarly exhibit a rising edge; thus, the RC clamp 330 turns on and shunts the voltage / current to Vssx. In other words, the RC clamp 330 may not be able to distinguish between normal data / clock bus signals and ESD events. Therefore, I / O circuit 300 provides BPP, but it is not fully functional for the multipoint bus because it cannot be used for data / clock communication.

[0039] Figure 4 A block diagram of another example input / output (I / O) circuit 400 according to another aspect of this disclosure is illustrated. As discussed in further detail herein, I / O circuit 400 provides reverse power protection (BPP) without requiring fast-return devices or power (e.g., supply voltage) from the higher voltage rail Vddpx, while also providing the full functionality of the multipoint bus coupled to I / O circuit 400 (e.g., data / clock signals on it). I / O circuit 400 utilizes the voltage Vddpx on the multipoint bus. bus The clamping circuit is disabled when consistent with data / clock communication signaling, and the voltage V on the multi-point bus is... bus When consistent with ESD events (e.g., voltage V on a multi-point bus) bus (When the voltage exceeds the overvoltage threshold) the clamping circuit is activated to achieve the aforementioned characteristics.

[0040] Specifically, the I / O circuit 400 includes a transmit (Tx) driver 420, which includes an input coupled to a data or clock source 410 and an output coupled to an I / O port 430, which can be coupled to a multipoint bus, wherein the data (or clock) signal D... o The switching can be initiated based on the transmission of data (or clock) signals. The Tx driver 420 can be coupled to and receives power from the higher voltage rail Vddpx and the lower voltage rail Vssx (e.g., ground). The I / O circuit 400 also includes a first electrostatic discharge (ESD) protection diode D1, which includes an anode coupled to the I / O port 430 and a cathode coupled to the floating bus Vdd_ESD. Additionally, the I / O circuit 400 includes a second ESD protection diode D2, which includes a cathode coupled to the I / O port 430 and an anode coupled to the lower voltage rail Vssx. The I / O circuit 400 may optionally include another diode D4, which includes an anode coupled to the higher voltage rail Vddpx and a cathode coupled to the floating bus Vdd_ESD.

[0041] The I / O circuit 400 also includes a dummy power supply 440 coupled between the I / O port 430 and the lower voltage rail Vssx, and optionally coupled to the higher voltage rail Vddpx. The dummy power supply may be a power source that generates the supply voltage by rectifying data, clock, or other types of signals. Furthermore, the I / O circuit 400 includes an overvoltage detector 450 coupled between the I / O port 430 and the lower voltage rail Vssx. The overvoltage detector may be a detector that generates or asserts a signal when the monitored voltage exceeds a threshold voltage.

[0042] Furthermore, I / O circuit 400 includes control circuitry 460 coupled between the higher voltage rail Vddpx and the lower voltage rail Vssx. Control circuitry 460 includes a first input coupled to the output of dummy power supply 440 to receive the supply voltage Vdd_INT, and the second input coupled to the output of overvoltage detector 450 to receive an overvoltage indication signal CLP_CTL. Additionally, I / O circuitry 400 includes clamping circuitry 470 (e.g., a resistor-capacitor (RC) clamping circuit) coupled between the floating bus Vdd_ESD and the lower voltage rail Vssx, and clamping circuitry 470 includes an input coupled to the output of control circuitry 460 to receive a control signal RC_DISABLE.

[0043] During operation, the overvoltage indication signal CLP_CTL generated by the overvoltage detector 450 indicates the voltage V at the I / O port 430. busWhether it is consistent with data / clock communication signaling (e.g., if CLP_CTL < TH) or whether it is consistent with an overvoltage (e.g., ESD) event (e.g., in the case of CLP_CTL > TH). Based on the voltage V at I / O port 430 by pseudo-power supply 440. bus The control circuit 460, powered by the supply voltage Vdd_INT generated by (e.g., data / clock communication signaling), generates the control signal RC_DISABLE based on the overvoltage indication signal CLP_CTL.

[0044] For example, if the overvoltage indication signal CLP_CTL indicates the voltage V at I / O port 430 bus Consistent with the data / clock communication signaling, control circuit 460 generates a control signal RC_DISABLE in an assertion state (e.g., setting it to logic 1 (1)) to disable clamp circuit 470. Therefore, clamp circuit 470 will not be triggered based on the data / clock communication signaling at I / O port 430 (e.g., shunting current from I / O port 430 to Vssx). If the overvoltage indication signal CLP_CTL indicates the voltage V at I / O port 430... bus If the voltage exceeds an overvoltage threshold (e.g., consistent with an ESD event or other overvoltage event), control circuit 460 generates a control signal RC_DISABLE in a deassertion state (e.g., sets it to logic zero (0)) to enable clamp circuit 470. Therefore, clamp circuit 470 is able to be triggered in response to an overvoltage event at I / O port 430 (e.g., shunting current from I / O port 430 to Vssx).

[0045] Since the I / O circuit 400 may be de-energized and there is no supply voltage at the higher voltage rail Vddpx, the dummy power supply 440 supplies power to the voltage V at the I / O port 430. bus The power supply voltage Vdd_INT is generated through rectification. Therefore, the clamping circuit 470 is disabled when normal data / clock communication signaling is present on the multipoint bus (e.g., the multipoint bus can be fully functional), and is enabled when an overvoltage (e.g., ESD) event occurs on the multipoint bus to provide overvoltage protection for the I / O circuit 400.

[0046] Figure 5A schematic diagram illustrating an example overvoltage detector 500 according to another aspect of this disclosure is shown. The overvoltage detector 500 may be an example implementation of an overvoltage detector 450 of I / O circuitry 400. The overvoltage detector 500 includes a set of one or more forward-biased diodes D11 to D1M, which are coupled in series with a resistive device R1 (e.g., a resistor, transistor, lossy inductor, etc.) between I / O port 510 and a lower voltage rail Vssx. The overvoltage detector 500 is configured to generate an overvoltage indication signal CLP_CTL as the voltage at the node between the set of one or more diodes D11 to D1M and the resistive device R1.

[0047] During operation, if the voltage V at I / O port 510... bus Below the cumulative threshold voltage Vd of one or more diodes D11 to D1M in this group (e.g., M 0.6 or 0.7 volts (V) (for example, as in voltage V) bus In the case of data / clock communication signaling coupled to the multipoint bus of I / O port 510, one or more diodes D11 to D1M in this group essentially do not conduct current. In such cases, the overvoltage indication signal CLP_CTL is essentially zero (0) V. If the voltage V at I / O port 510 is... bus The cumulative threshold voltage Vd of one or more diodes D11 to D1M in this group is higher than (e.g., at voltage V). bus In the event of an overvoltage (e.g., ESD) event at I / O port 510, one or more diodes D11 to D1M in this group conduct current. The current flows through the resistive device R1 to generate an overvoltage indication signal CLP_CTL as a positive voltage (e.g., 200 mV to 300 mV). As further discussed herein, the control circuitry generates an assertion or deassertion control signal RC_DISABLE in response to the overvoltage indication signal CLP_CTL being substantially 0V or a positive voltage (e.g., 200 mV to 300 mV) above the overvoltage threshold.

[0048] Figure 5 The voltage V at I / O port 510 associated with the operation of the overvoltage detector 500 discussed is also depicted. bus The voltage-time graph. Therefore, if the voltage V at I / O port 510... bus If the voltage is below the overvoltage threshold (TH), as indicated by the horizontal double-dotted line in the figure, then the voltage at I / O port 510 is consistent with the multipoint bus signaling. If the voltage V at I / O port 510... bus If the voltage exceeds the overvoltage threshold (TH), the voltage at I / O port 510 is consistent with an overvoltage (e.g., ESD) event.

[0049] Figure 6 A schematic diagram of an example control circuit 600 according to another aspect of this disclosure is illustrated. The control circuit 600 may be an example implementation of the control circuit 460 of the I / O circuit 400. The control circuit 600 includes an AC coupling capacitor C1, a latch 610, a pair of transistors (e.g., field-effect transistors (FETs), such as an n-channel FET) M1 and M2, and a buffer 620.

[0050] AC coupling capacitor C1 is coupled between the floating bus Vdd_ESD and the first node n1. Latch 610 is coupled between the first node n1 and the second node n2. Latch 610 further includes cross-coupled inverters 612 and 614, each having a corresponding input and output coupled to node n1, and a corresponding output and input coupled to node n2. Cross-coupled inverters 612 and 614 are each coupled between a dummy power supply 440 (or 700, further discussed herein) and a lower voltage rail Vssx, and are configured to receive power (e.g., supply voltage Vdd_INT) from the dummy power supply and the lower voltage rail. Transistors M1 and M2 (e.g., their drain and source) are coupled between nodes n1 and n2 and the lower voltage rail Vssx, respectively. Transistor M1 (generally referred to as the circuit) includes a control input (e.g., the gate) coupled to an overvoltage detector 450 or 500 to receive an overvoltage indication signal CLP_CTL. Transistor M2 (also referred to as the circuit) includes a control input (e.g., the gate) coupled to the higher voltage rail Vddpx.

[0051] Buffer 620 includes an input coupled to node n1 and an output that can be used as the output of control circuit 600, where a control signal RC_DISABLE is generated. Buffer 620 includes a set of cascaded inverters, where this example is shown as two cascaded inverters 622 and 624 coupled between node n1 and the output. Cascaded inverters 622 and 624 are each coupled between a pseudo-power supply 440 (or 700 discussed further herein) and a lower voltage rail Vssx, and are configured to receive power (e.g., supply voltage Vdd_int) from the pseudo-power supply and the lower voltage rail.

[0052] During operation, the bus voltage V is consistent with the data / clock communication signaling on the multi-point bus AC. busThe circuit is coupled to node n1 via I / O port 430, ESD protection diode D1, Vdd_ESD bus, and AC coupling capacitor C1. Data / clock communication signaling initializes latch 610 such that there is a logic one (1) at node n1 and a logic zero (0) at node n2. In this example, it is assumed that there is no ESD event at I / O port 430 (e.g., CLP_CTL≈0V) and the higher voltage rail Vddpx is off (e.g., Vddpx≈0V). Therefore, transistors M1 and M2 are off. Therefore, buffer 620 outputs a logic one (1) state at node n1 to generate an assertion (e.g., logic one (1)) control signal RC_DISABLE to disable clamp circuit 470 (or 800, as discussed further herein). Therefore, the voltage V on the multipoint bus consistent with the data / clock communication signaling is... bus The disabled clamping circuits 470 or 800 will not be triggered.

[0053] If an overvoltage event occurs at I / O port 430 or 510, overvoltage detector 450 or 500 generates an overvoltage indication signal CLP_CTL at a positive voltage (e.g., 200mV to 300mV) substantially equal to or higher than the threshold voltage of transistor M1. This causes transistor M1 to turn on and pull down node n1 to toggle the state of latch 610, where node n1 is now in a logic zero (0) state and node n2 is in a logic one (1) state. Therefore, buffer 620 outputs a logic zero (0) at node n1 to generate a control signal RC_DISABLE to de-assert (e.g., logic zero (0)) to enable clamp circuit 470 or 800. Therefore, the voltage V on the multipoint bus... bus In conjunction with an overvoltage (e.g., ESD) event, the enabled clamping circuit 470 or 800 can shunt current from I / O port 430 to Vssx via ESD protection diode D1 and floating bus Vdd_ESD to provide overvoltage (e.g., ESD) protection.

[0054] If a supply voltage is present on the higher voltage rail Vddpx (e.g., the corresponding IC is turned on), the corresponding supply voltage Vddpx turns on transistor M2 to configure latch 610 to output a logic-1 (1) state at node n1 and a logic-0 (0) state at node n2. Buffer 620 outputs a logic-1 (1) at node n1 to generate an assertion (e.g., logic-1 (1)) control signal RC_DISABLE to disable clamp circuit 470 or 800. When the supply voltage Vddpx is present, reverse power protection (BPP) is not required; therefore, clamp circuit 470 or 800 can be disabled to avoid power consumption.

[0055] Figure 7A schematic diagram illustrating an example dummy power supply 700 according to another aspect of this disclosure is shown. The dummy power supply 700 may be an example implementation of a dummy power supply 440 of I / O circuitry 400. The dummy power supply generates a supply voltage by rectifying a signal such as a data signal or a clock signal.

[0056] The dummy power supply 700 includes a forward-biased diode D5 coupled in series with a capacitor C2 between I / O port 710 and a lower voltage rail Vssx (e.g., ground). The dummy power supply 700 may optionally include a forward-biased diode D6 coupled in series with a reverse-biased diode D7 between a high voltage rail Vddpx and a lower voltage rail Vssx. The dummy power supply 700 is configured to generate a supply voltage Vdd_INT at the output node between diode D5 and capacitor C2 (and between diodes D6 and D7).

[0057] During operation, when there is no supply voltage at the higher voltage rail Vddpx (e.g., when the corresponding IC is off), the forward bias diode D5 responds to the voltage V at I / O port 710. bus (For example, due to data / clock signaling and / or ESD events) conduction current to charge capacitor C2, thereby generating the supply voltage Vdd_INT. When a supply voltage is present at the higher voltage rail Vddpx, the supply voltage Vdd_INT is one diode drop lower than the supply voltage Vddpx. Therefore, latch 610 of control circuit 600 remains energized to generate an assertion control signal RC_DISABLE to disable clamp circuit 470 or 800, because reverse power protection (BPP) may not be required when a supply voltage Vddpx is present at the higher voltage rail Vddpx.

[0058] Figure 8 A schematic diagram illustrating an example resistor-capacitor (RC) clamp 800 according to another aspect of this disclosure is shown. The RC clamp 800 may be an example implementation of the clamping circuit 470 of the I / O circuit 400. It should be understood that the clamping circuit 470 may be other types of clamping circuits and is not necessarily an RC clamping circuit. The RC clamp 800 includes a resistive device R2 (e.g., a resistor, transistor, lossy inductor, etc.) coupled in series with a capacitor C3 between the floating bus Vdd_ESD and the lower voltage rail Vssx (e.g., ground).

[0059] Additionally, the RC clamp 800 includes a set of transistors M3, M4, and M5 (e.g., FETs or two (2) p-channel FETs and one (1) n-channel FET), which are coupled in series between the floating bus Vdd_ESD and the lower voltage rail Vssx. The control input (e.g., gate) of transistor M3 is coupled to control circuitry 460 or 600 to receive the control signal RC_DISABLE. Transistors M4 and M5 operate as inverters, with their control inputs (e.g., gates) coupled to node n3 between resistor R2 and capacitor C3. The RC clamp 800 also includes another transistor M6 (e.g., an FET or an n-channel FET), which is coupled between the outputs of inverter transistors M4 and M5 (e.g., at their common drain) and the lower voltage rail Vssx. The control input (e.g., gate) of transistor M6 is coupled to control circuitry 460 or 600 to receive the control signal RC_DISABLE. Additionally, the RC clamp 800 includes another transistor M7 (e.g., FET or n-channel FET) coupled between the floating bus Vdd_ESD and the lower voltage rail Vssx, wherein the control input (e.g., gate) is coupled to the output (e.g., drain) of the inverter transistors M4 and M5.

[0060] During operation, when the control signal RC_DISABLE is asserted (e.g., indicating no overvoltage (e.g., ESD) event on the multipoint bus or at an I / O port), transistor M3 is turned off and transistor M6 is turned on. Transistor M3 being turned off disables the inverter operation of transistors M4 and M5, and transistor M6 being turned on turns off transistor M7. This disables RC clamp 800; for example, RC clamp 800 cannot respond to voltage Vdd_ESD on the floating bus. bus The relevant oscillation is used to shunt current from the floating bus Vdd_ESD to Vssx.

[0061] When the control signal RC_DISABLE is deasserted (e.g., indicating an overvoltage (e.g., ESD) event on the multipoint bus or at an I / O port), transistor M3 turns on and transistor M6 turns off. Transistor M3 turns on to enable inverter operation of transistors M4 and M5, and transistor M6 turns off to allow the gate of transistor M7 to be driven by inverters M4 / M5. Since the voltage at node n3 has not yet been charged, inverters M4 / M5 output a logic high voltage to turn on transistor M7 and shunt the current associated with the overvoltage event from the floating bus Vdd_ESD to Vssx. When capacitor C3 is charged to a logic high voltage via resistor R2 due to an overvoltage on the floating bus Vdd_ESD, inverters M4 / M5 output a logic low voltage to turn off transistor M7. Therefore, in the time constant R2 C3 provides overvoltage protection within the specified time window, where R2 also represents the resistance of the resistor R2, and C3 also represents the capacitance of the capacitor C3.

[0062] Figure 9 A block diagram of an example integrated circuit (IC) 900 according to another aspect of this disclosure is illustrated. IC 900 includes a set of N input / output (I / O) circuits 910-1 to 910-N coupled to a common floating bus Vdd_ESD. IC 900 also includes a common clamping circuit 920 (e.g., an RC clamp) coupled between the common floating bus Vdd_ESD and a lower voltage rail Vssx (e.g., ground). Except for the floating bus Vdd_ESD and the clamping circuit 470 being shared for the set of I / O circuits 910-1 to 910-N, each of the set of I / O circuits 910-1 to 910-N can be implemented according to I / O circuit 400. The set of I / O circuits 910-1 to 910-N is configured to generate a set of N control signals RC_DISABLE1 to RC_DISABLE, respectively. N .

[0063] IC 900 also includes logic circuitry 930, which includes inputs coupled to the outputs of the group of I / O circuits 910-1 to 910-N, to receive the group of control signals RC_DISABLE1 to RC_DISABLE from the group of I / O circuits, respectively. N Logic circuit 930 is configured to control the group of control signals RC_DISABLE1 to RC_DISABLE. N An OR operation is performed to generate a shared control signal RC_DISABLE. RC clamp 920 includes an input coupled to the output of logic circuit 930 to receive the shared control signal RC_DISABLE. Therefore, if any of the I / O circuits 910-1 to 910-N detects an overvoltage (e.g., ESD) event, the shared control signal RC_DISABLE becomes deasserted; and in response, clamp circuit 920 is enabled to shunt the current associated with the overvoltage event from the shared floating bus Vdd_ESD to the lower voltage rail Vssx. Otherwise, if none of the I / O circuits 910-1 to 910-N detects an overvoltage event, the shared control signal RC_DISABLE remains asserted; and in response, clamp circuit 920 remains disabled so as not to respond to voltage on the shared floating bus Vdd_ESD.

[0064] Figure 10A block diagram of another example input / output (I / O) circuit 1000 according to another aspect of this disclosure is illustrated. The I / O circuit 1000 includes an overvoltage detector 1020, which includes an input coupled to an input / output (I / O) port 1010. The I / O circuit 1000 also includes a control circuit 1040, which includes an input coupled to an output of the overvoltage detector 1020. The I / O circuit 1000 also includes a dummy power supply 1030, which includes an input coupled to the I / O port 1010 and an output coupled to the control circuit 1040. Additionally, the I / O circuit 1000 includes a clamping circuit 1050 coupled between the I / O port 1010 and a voltage rail Vssx via an ESD protection diode D1, wherein the clamping circuit 1050 includes an input coupled to an output of the control circuit 1040.

[0065] Figure 11 A block diagram illustrating another example of an input / output (I / O) circuit 1100 according to another aspect of this disclosure is shown. The I / O circuit 1100 includes an overvoltage detector 1120 configured to generate an overvoltage indication signal CLP_CTL indicating the voltage V at the input / output (I / O) port 1110. bus Whether the voltage exceeds an overvoltage threshold. The I / O circuit 1100 also includes a control circuit 1130 configured to generate a control signal RC_DISABLE based on an overvoltage indication signal CLP_CTL. Furthermore, the I / O circuit 1100 includes a dummy power supply 1150 coupled to the I / O port 1110 and configured to provide a supply voltage Vdd_INT to the control circuit 1130. Additionally, the I / O circuit 1100 includes a clamping circuit 1140 configured to generate a shunt current from the I / O port via an ESD protection diode D1, wherein the shunt current is enabled or disabled based on the control signal RC_DISABLE.

[0066] Figure 12 A flowchart illustrating an example method 1200 for providing overvoltage protection for input / output (I / O) circuitry according to another aspect of this disclosure is provided. Method 1200 includes generating an overvoltage indication signal that indicates whether the voltage at the input / output (I / O) port is higher than an overvoltage threshold (block 1210). Examples of components used to generate the overvoltage indication signal include any of the overvoltage detectors described herein that indicate whether the voltage at the input / output (I / O) port is higher than an overvoltage threshold.

[0067] Method 1200 further includes generating a control signal based on an overvoltage indication signal (block 1220). Examples of components for generating the control signal based on the overvoltage indication signal include any RC clamp control circuit described herein. Additionally, method 1200 includes enabling or disabling the shunting of current generated from a voltage from an I / O port to a voltage rail based on the control signal (block 1230). Examples of components for enabling or disabling the shunting of current generated from a voltage from an I / O port to a voltage rail based on the control signal include any clamping circuit described herein.

[0068] Method 1200 may further include generating a supply voltage based on the voltage at the I / O port, which is used to generate a control signal. Examples of components for generating the supply voltage include any dummy power supply described herein. Furthermore, according to method 1200, generating the control signal may include: initializing the control signal to a first state based on the voltage at the I / O port; and setting the control signal to a second state in response to the overvoltage indication signal. Examples of components for initializing the control signal to the first state based on the voltage at the I / O port include any latch described herein. Examples of components for setting the control signal to the second state in response to the overvoltage indication signal include circuitry or transistor M1.

[0069] The following provides an overview of the various aspects of this disclosure: Aspect 1: An apparatus comprising: an overvoltage detector including an input terminal coupled to an input / output (I / O) port; a control circuit including an input terminal coupled to an output terminal of the overvoltage detector; a dummy power supply including an input terminal and an output terminal, the input terminal coupled to the I / O port and the output terminal coupled to the control circuit; and a clamping circuit coupled between the I / O port and a voltage rail via a diode, wherein the clamping circuit includes an input terminal coupled to the output terminal of the control circuit.

[0070] Aspect 2: The apparatus according to aspect 1 further includes a floating bus coupled between the diode and the clamping circuit.

[0071] Aspect 3: The apparatus according to aspect 1 or 2, wherein the overvoltage detector includes a set of one or more diodes, the set of one or more diodes being coupled in series with a resistor device between the I / O port and the voltage rail, wherein the node between the set of one or more diodes and the resistor device is coupled to or serves as the output of the overvoltage detector.

[0072] Aspect 4: The apparatus according to any one of Aspects 1 to 3, wherein the dummy power supply includes a first diode coupled in series with a capacitor between the I / O port and the voltage rail, wherein the node between the first diode and the capacitor is coupled to the output of the dummy power supply or serves as the output of the dummy power supply.

[0073] Aspect 5: The apparatus according to aspect 4, wherein the dummy power source further comprises a second diode and a third diode, the second diode being coupled between another voltage rail and the node, and the third diode being coupled between the node and the voltage rail.

[0074] Aspect 6: The apparatus according to any one of Aspects 1 to 5, wherein the control circuit comprises: a capacitor coupled between the diode and a first node; a latch coupled between the first node and a second node; and a first transistor coupled between the first node and the voltage rail, wherein the first transistor includes a control input coupled to or serving as the input of the control circuit.

[0075] Aspect 7: The apparatus according to aspect 6, wherein the latch includes a cross-coupled inverter coupled between the first node and the second node.

[0076] Aspect 8: The apparatus according to aspect 6 or 7, wherein the latch is coupled to the output of the dummy power supply.

[0077] Aspect 9: The apparatus according to any one of Aspects 6 to 8, wherein the control circuit further includes a buffer, the buffer including an input terminal and an output terminal, the input terminal being coupled to the first node, and the output terminal being coupled to or serving as the output terminal of the control circuit.

[0078] Aspect 10: The apparatus according to aspect 9, wherein the buffer includes a set of cascaded inverters coupled between the first node and the output of the buffer.

[0079] Aspect 11: The apparatus according to aspect 9 or 10, wherein the buffer is coupled to the output of the dummy power supply.

[0080] Aspect 12: The apparatus according to any one of Aspects 6 to 11, wherein the control circuit includes a second transistor coupled between the second node and the voltage rail, wherein the second transistor includes a control input coupled to another voltage rail.

[0081] Aspect 13: The apparatus according to any one of Aspects 1 to 12, wherein the clamping circuit comprises: a resistive device coupled in series with a capacitor between the diode and the voltage rail; a first transistor, a second transistor, and a third transistor coupled in series between the diode and the voltage rail, wherein the first transistor includes a control input coupled to or serving as an input of the clamping circuit, wherein the second and third transistors include control inputs coupled to a first node between the resistive device and the capacitor; a fourth transistor coupled between a second node between the second and third transistors and the voltage rail, wherein the fourth transistor includes a control input coupled to or serving as an input of the clamping circuit; and a fifth transistor coupled between the diode and the voltage rail, wherein the fifth transistor includes a control input coupled to or serving as an input of the clamping circuit; and a fifth transistor coupled between the diode and the voltage rail, wherein the fifth transistor includes a control input coupled to the second node.

[0082] Aspect 14: The apparatus according to any one of Aspects 1 to 13, further comprising: a data or clock source; a transmit driver including an input and an output, the input coupled to the data or clock source and the output coupled to the I / O port, wherein the transmit driver is coupled between another voltage rail and the voltage rail; another diode coupled between the I / O port and the voltage rail; and a diode coupled between the other voltage rail and the clamping circuit.

[0083] Aspect 15: An apparatus comprising: an overvoltage detector configured to generate an overvoltage indication signal indicating whether a first voltage at an input / output (I / O) port is higher than an overvoltage threshold; a control circuit configured to generate a control signal based on the overvoltage indication signal; a dummy power supply coupled to the I / O port and configured to provide a supply voltage to the control circuit; and a clamping circuit configured to generate a shunt current from the I / O port via a diode, wherein the shunt current is enabled or disabled based on the control signal.

[0084] Aspect 16: The apparatus according to aspect 15, wherein the dummy power supply is configured to generate the supply voltage from communication signaling at the I / O port.

[0085] Aspect 17: The apparatus according to aspect 15 or 16, wherein the overvoltage detector comprises a set of one or more diodes, the set of one or more diodes being coupled in series with a resistive device between the I / O port and the voltage rail, wherein the overvoltage indication signal is or is based on a second voltage at a node between the set of one or more diodes and the resistive device.

[0086] Aspect 18: The apparatus according to any one of Aspects 15 to 17, wherein the dummy power supply comprises a diode coupled in series with a capacitor between the I / O port and the voltage rail, wherein the supply voltage is or is based on a second voltage at the node between the diode and the capacitor.

[0087] Aspect 19: The apparatus according to any one of Aspects 15 to 18, wherein the control circuitry comprises: a latch configured to initialize the control signal to a first state based on the first voltage at the I / O port; and a circuit configured to toggle the latch to set the control signal to a second state in response to the overvoltage indication signal.

[0088] Aspect 20: The apparatus according to aspect 19, wherein the clamping circuit is configured to be disabled based on the first state of the control signal; or to be enabled based on the second state of the control signal.

[0089] Aspect 21: The apparatus according to aspect 20, wherein the clamping circuit is configured to: not respond to the first voltage at the I / O port when disabled; or shunt current from the I / O port to a voltage rail when enabled in response to the first voltage.

[0090] Aspect 22: A method comprising: generating an overvoltage indication signal indicating whether a voltage at an input / output (I / O) port is higher than an overvoltage threshold; generating a control signal based on the overvoltage indication signal; and enabling or disabling, based on the control signal, the shunting of current generated by the voltage from the I / O port to a voltage rail.

[0091] Aspect 23: According to the method of aspect 22, generating the overvoltage indication signal includes applying the voltage across a set of one or more diodes, the set of one or more diodes being coupled in series with a resistor device between the I / O port and the voltage rail.

[0092] Aspect 24: The method according to aspect 22 or 23 further includes: generating a supply voltage based on the voltage at the I / O port, the supply voltage being used to generate the control signal.

[0093] Aspect 25: The method according to aspect 24, wherein generating the supply voltage includes applying the voltage across a diode at the I / O port, the diode being coupled in series with a capacitor between the I / O port and the voltage rail.

[0094] Aspect 26: The method according to any one of Aspects 22 to 25, wherein generating the control signal comprises: initializing the control signal to a first state based on the voltage at the I / O port; and setting the control signal to a second state in response to the overvoltage indication signal.

[0095] Aspect 27: According to the method of aspect 26, enabling or disabling the shunting of the current comprises: disabling the shunting of the current based on a first state of the control signal; or enabling the shunting of the current based on a second state of the control signal.

[0096] Aspect 28: An apparatus comprising: means for generating an overvoltage indication signal, the overvoltage indication signal indicating whether a voltage at an input / output (I / O) port is higher than an overvoltage threshold; means for generating a control signal based on the overvoltage indication signal; and means for enabling or disabling, based on the control signal, the shunting of current generated from the voltage at the I / O port to a voltage rail.

[0097] Aspect 29: The apparatus according to aspect 28 further includes a component for generating a supply voltage based on the voltage at the I / O port, wherein the component for generating the control signal is coupled to the component for generating the supply voltage.

[0098] Aspect 30: The apparatus according to aspect 28 or 29, wherein the component for generating the control signal includes: a component for initializing the control signal to a first state based on the voltage at the I / O port; and a component for setting the control signal to a second state in response to the overvoltage indication signal.

[0099] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, the apparatus comprising: An overvoltage detector, the overvoltage detector including an input terminal coupled to an input / output (I / O) port; A control circuit, the control circuit including an input terminal, the input terminal of the control circuit being coupled to the output terminal of the overvoltage detector; A pseudo power supply, comprising an input terminal and an output terminal, wherein the input terminal of the pseudo power supply is coupled to the I / O port and the output terminal of the pseudo power supply is coupled to the control circuit; and A clamping circuit, wherein the clamping circuit is coupled between the I / O port and the voltage rail via a diode, wherein the clamping circuit includes an input terminal, the input terminal of which is coupled to the output terminal of the control circuit.

2. The apparatus of claim 1, further comprising a floating bus coupled between the diode and the clamping circuit.

3. The apparatus of claim 1, wherein the overvoltage detector comprises a group of one or more diodes, the group of one or more diodes being coupled in series with a resistor device between the I / O port and the voltage rail, wherein the node between the group of one or more diodes and the resistor device is coupled to or serves as the output of the overvoltage detector.

4. The apparatus of claim 1, wherein the dummy power supply comprises a first diode coupled in series with a capacitor between the I / O port and the voltage rail, wherein the node between the first diode and the capacitor is coupled to the output terminal of the dummy power supply or serves as the output terminal of the dummy power supply.

5. The apparatus of claim 4, wherein the dummy power source further comprises a second diode and a third diode, the second diode being coupled between another voltage rail and the node, and the third diode being coupled between the node and the voltage rail.

6. The apparatus of claim 1, wherein the control circuit comprises: A capacitor, said capacitor being coupled between the diode and the first node; A latch, wherein the latch is coupled between the first node and the second node; and A first transistor is coupled between the first node and the voltage rail, wherein the first transistor includes a control input terminal coupled to or serving as the input terminal of the control circuit.

7. The apparatus of claim 6, wherein the latch includes a cross-coupled inverter coupled between the first node and the second node.

8. The apparatus of claim 6, wherein the latch is coupled to the output of the dummy power supply.

9. The apparatus of claim 6, wherein the control circuit further comprises a buffer, the buffer having an input terminal and an output terminal, the input terminal of the buffer being coupled to the first node, and the output terminal of the buffer being coupled to or serving as the output terminal of the control circuit.

10. The apparatus of claim 9, wherein the buffer comprises a set of cascaded inverters coupled between the first node and the output of the buffer.

11. The apparatus of claim 9, wherein the buffer is coupled to the output of the dummy power supply.

12. The apparatus of claim 6, wherein the control circuitry includes a second transistor coupled between the second node and the voltage rail, wherein the second transistor includes a control input coupled to another voltage rail.

13. The apparatus of claim 1, wherein the clamping circuit comprises: A resistive device, wherein the resistive device is coupled in series with a capacitor between the diode and the voltage rail; A first transistor, a second transistor, and a third transistor are connected in series between the diode and the voltage rail. The first transistor includes a control input terminal coupled to or serving as the input terminal of the clamping circuit. The second and third transistors also include control input terminals coupled to a first node between the resistive device and the capacitor. A fourth transistor, coupled between a second node between the second transistor and the third transistor and the voltage rail, wherein the fourth transistor includes a control input terminal coupled to or serving as the input terminal of the clamping circuit; and A fifth transistor, coupled between the diode and the voltage rail, wherein the fifth transistor includes a control input terminal coupled to the second node.

14. The apparatus according to claim 1, further comprising: Data or clock source; A transmit driver, the transmit driver including an input terminal and an output terminal, the input terminal of the transmit driver being coupled to the data or clock source, the output terminal of the transmit driver being coupled to the I / O port, wherein the transmit driver is coupled between another voltage rail and the voltage rail; Another diode, which is coupled between the I / O port and the voltage rail; and A diode, which is coupled between another voltage rail and the clamping circuit.

15. An apparatus comprising: An overvoltage detector configured to generate an overvoltage indication signal indicating whether a first voltage at an input / output (I / O) port is higher than an overvoltage threshold. A control circuit configured to generate a control signal based on the overvoltage indication signal; A dummy power supply, coupled to the I / O port and configured to provide a power supply voltage to the control circuitry; and A clamping circuit configured to generate a shunt current from the I / O port via an electrostatic discharge (ESD) protection diode, wherein the shunt current is enabled or disabled based on the control signal.

16. The apparatus of claim 15, wherein the dummy power supply is configured to generate the supply voltage from communication signaling at the I / O port.

17. The apparatus of claim 15, wherein the overvoltage detector comprises a set of one or more diodes coupled in series with a resistive device between the I / O port and the voltage rail, wherein the overvoltage indication signal is or is based on a second voltage at a node between the set of one or more diodes and the resistive device.

18. The apparatus of claim 15, wherein the dummy power supply comprises a diode coupled in series with a capacitor between the I / O port and the voltage rail, wherein the power supply voltage is or is based on a second voltage at the node between the diode and the capacitor.

19. The apparatus of claim 15, wherein the control circuit comprises: A latch, the latch being configured to initialize the control signal to a first state based on the first voltage at the I / O port; and A circuit configured to toggle the latch in response to the overvoltage indication signal to set the control signal to a second state.

20. The apparatus of claim 19, wherein the clamping circuit is configured to: It is disabled based on the first state of the control signal; or It is enabled based on the second state of the control signal.

21. The apparatus of claim 20, wherein the clamping circuit is configured to: When disabled, it does not respond to the first voltage at the I / O port; or When enabled, current is shunted from the I / O port to the voltage rail in response to the first voltage.

22. A method, the method comprising: Generate an overvoltage indication signal, which indicates whether the voltage at the input / output (I / O) port is higher than an overvoltage threshold; A control signal is generated based on the overvoltage indication signal; as well as The control signal is used to enable or disable the shunt of current generated by the voltage from the I / O port to the voltage rail.

23. The method of claim 22, wherein generating the overvoltage indication signal comprises applying the voltage across a set of one or more diodes, the set of one or more diodes being coupled in series with a resistive device between the I / O port and the voltage rail.

24. The method according to claim 22, further comprising: A supply voltage is generated based on the voltage at the I / O port, and the supply voltage is used to generate the control signal.

25. The method of claim 24, wherein generating the supply voltage comprises applying the voltage across a diode at the I / O port, the diode being coupled in series with a capacitor between the I / O port and the voltage rail.

26. The method of claim 22, wherein generating the control signal comprises: The control signal is initialized to a first state based on the voltage at the I / O port. as well as The control signal is set to a second state in response to the overvoltage indication signal.

27. The method of claim 26, wherein enabling or disabling the shunt of the current comprises: The current shunt is disabled based on the first state of the control signal; or The current shunting is enabled based on the second state of the control signal.

28. An apparatus comprising: A component for generating an overvoltage indication signal, the overvoltage indication signal indicating whether the voltage at the input / output (I / O) port is higher than an overvoltage threshold; A component for generating a control signal based on the overvoltage indication signal; and A component for enabling or disabling the shunt of current generated by the voltage from the I / O port to the voltage rail based on the control signal.

29. The apparatus of claim 28, further comprising a component for generating a supply voltage based on the voltage at the I / O port, wherein the component for generating the control signal is coupled to the component for generating the supply voltage.

30. The apparatus of claim 28, wherein the component for generating the control signal comprises: A component for initializing the control signal to a first state based on the voltage at the I / O port; and A component for setting the control signal to a second state in response to the overvoltage indication signal.

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