Photoelectric conversion device
By setting multiple embedded regions in the photoelectric conversion layer and adjusting the impurity concentration and potential distribution, the problem of slow signal charge transfer speed was solved, and the signal charge speed was increased and the detection speed was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NAT UNIV CORP SHIZUOKA UNIV
- Filing Date
- 2024-11-07
- Publication Date
- 2026-06-02
AI Technical Summary
In existing photoelectric conversion elements, the transfer speed of signal charge from the photoelectric conversion unit to the signal charge accumulation unit is relatively slow, making it difficult to achieve high-speed signal charge detection.
Multiple buried regions are set in the photoelectric conversion layer. By adjusting the impurity concentration and potential distribution, the carriers can be transferred at high speed between photodiodes with different wavelength components. Specifically, the buried regions of the first conductivity type and the second conductivity type are set alternately, and the impurity concentration gradually increases to ensure that the potential changes monotonically and avoid potential dip.
It achieves high-speed transfer and detection of signal charge, reduces noise in the readout signal, and improves the detection speed of the color image sensor.
Smart Images
Figure CN122139463A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to photoelectric conversion devices. Background Technology
[0002] In recent years, color image sensors that utilize the property that the light absorption coefficients of semiconductors such as silicon differ along the depth direction are becoming increasingly popular. In the photoelectric conversion element described in Patent Document 1 below, three photoelectric conversion sections are formed at positions with different depths in the semiconductor layer, and three signal charge accumulation sections are formed on the surface of the semiconductor layer to accumulate the signal charges generated by each photoelectric conversion section.
[0003] Existing technical documents
[0004] Patent documents
[0005] Patent Document 1: Japanese Patent Application Publication No. 2003-298038
[0006] Patent Document 2: Japanese Patent Publication No. 2007-531254 Summary of the Invention
[0007] The problem that the invention aims to solve
[0008] In the conventional photoelectric conversion element described above, the high-speed transfer of signal charge from the photoelectric conversion unit to the signal charge storage unit creates a limitation. As a result, there is a tendency to make it difficult to achieve high-speed detection of signal charge.
[0009] This disclosure was made in view of the above-mentioned problems, and the object is to provide a high-speed photoelectric conversion device capable of detecting signal charge.
[0010] Technical means to solve the problem
[0011] To address the aforementioned issues, one embodiment of the photoelectric conversion device of the present invention comprises: a semiconductor substrate; and a photoelectric conversion layer formed on the semiconductor substrate, having a first main surface adjacent to the semiconductor substrate and a second main surface along the first main surface; the photoelectric conversion layer comprises: a first buried region of a first conductivity type, buried in the second main surface, converting light of a first wavelength component incident on the second main surface into charge carriers and accumulating the converted charge carriers; and a second buried region of the first conductivity type, buried from the second main surface to a depth greater than the first buried region, converting light of a second wavelength component incident on the second main surface into charge carriers; A third buried region of a first conductivity type is buried in the same layer as the first buried region on the second main surface, accumulating charge carriers converted from the second buried region; and a fourth buried region of the first conductivity type is connected to the second and third buried regions, and is arranged between the second and third buried regions in a manner sandwiched by two regions of the second conductivity type, transferring the charge carriers converted from the second buried region to the third buried region; the impurity concentration of the third buried region is set to be higher than the impurity concentration of the fourth buried region, and the impurity concentration of the fourth buried region is set to be higher than the impurity concentration of the second buried region.
[0012] According to the photoelectric conversion device described above, the first wavelength component of the light incident from the second main surface of the photoelectric conversion layer is converted into charge carriers in the first embedded region of the first conductivity type, and the converted charge carriers are stored. In addition, the second wavelength component of the light incident from the second main surface of the photoelectric conversion layer is converted into charge carriers in the second embedded region of the first conductivity type, and the converted charge carriers are stored in the third embedded region of the first conductivity type via a fourth embedded region of the first conductivity type connected to the second and third embedded regions. Here, the fourth embedded region is sandwiched between two regions of the second conductivity type, and the impurity concentration is set to increase sequentially from the second embedded region to the fourth embedded region and then to the third embedded region. Therefore, a potential dip is less likely to occur in the potential distribution along the charge carrier transfer path from the second embedded region to the third embedded region. Since the potential is formed in a monotonically changing manner, charge carriers can be transferred from the second embedded region to the third embedded region at high speed. As a result, it is possible to achieve high-speed detection of charge carriers accumulated based on light with two wavelength components.
[0013] Invention Effects
[0014] According to this disclosure, it is possible to achieve high-speed detection of signal charge. Attached Figure Description
[0015] Figure 1 This is a top view of the photoelectric conversion device 1 according to the embodiment.
[0016] Figure 2 It is along the connection Figure 1 A cross-sectional view of the lines connecting points G', G, B, F, and F' of the photoelectric conversion device 1 shown.
[0017] Figure 3 It is along the connection Figure 1 A cross-sectional view of the lines connecting points E and E' of the photoelectric conversion device 1 shown.
[0018] Figure 4 It means Figure 2 The graph shows the potential distribution along the depth direction in pixel structure 2.
[0019] Figure 5 It means Figure 2 The graph shows the potential distribution along the depth direction in pixel structure 2.
[0020] Figure 6 This is a cross-sectional view of the pixel structure 2A of the variant example.
[0021] Figure 7 This is a top view of the modified photoelectric conversion device 1A.
[0022] Figure 8 It is along the connection Figure 7 A cross-sectional view of the lines connecting points G', G, B, F, and F' of the photoelectric conversion device 1A shown.
[0023] Figure 9 It is a cross-sectional view along the lines connecting points G', G, B, F, F' of the photoelectric conversion device in the modified example. Detailed Implementation
[0024] Hereinafter, preferred embodiments of the photoelectric conversion device of this disclosure will be described in detail with reference to the accompanying drawings. Furthermore, in the description of the drawings, the same or equivalent parts are given the same reference numerals, and repeated descriptions are omitted.
[0025] First, use Figures 1-3 The structure of the photoelectric conversion device 1 according to the embodiments of the present disclosure will be described. Figure 1 This is a top view of photoelectric conversion device 1. Figure 2 It is along the connection Figure 1 A cross-sectional view of the lines connecting points G', G, B, F, and F' of the photoelectric conversion device 1 shown. Figure 3 It is along the connection Figure 1 The image shows a cross-sectional view of points E and E' of the photoelectric conversion device 1. The photoelectric conversion device 1 is a solid-state imaging device that detects light of three wavelength components incident from the outside and generates a color image signal.
[0026] like Figure 1Schematably, the photoelectric conversion device 1 has a structure formed by arranging a plurality of pixel structures 2 in two dimensions on a semiconductor substrate. The pixel structure 2, in the incident surface 2a where light is incident on the target object, includes: a buried region (first buried region) n1B that generates and stores electrons (signal charges) corresponding to the intensity of the blue light component (first wavelength component) of the incident light; a floating diffusion layer n5B; a transfer gate TX1 disposed between the buried region n1B and the floating diffusion layer n5B; a buried region (third buried region) n1G that stores electrons corresponding to the intensity of the green light component (second wavelength component) of the incident light; a floating diffusion layer n5G; a transfer gate TX2 disposed between the buried region n1G and the floating diffusion layer n5G; a buried region (sixth buried region) n1R that stores electrons corresponding to the intensity of the red light component (third wavelength component) of the incident light; a floating diffusion layer n5R; and a transfer gate TX3 disposed between the buried region n1R and the floating diffusion layer n5R.
[0027] The following is for reference Figure 2 and Figure 3 The detailed layered structure of pixel structure 2 is explained.
[0028] Pixel structure 2 includes: a P-type (second conductivity type) semiconductor substrate 3 such as a silicon substrate; a P-type epitaxial layer, i.e., a photoelectric conversion layer 4, formed on the semiconductor substrate 3; and a metal layer 5 that blocks light from the outside. The photoelectric conversion layer 4 includes: a main surface (first main surface) 4a close to the semiconductor substrate 3; and a main surface (second main surface) 4b constituting an incident surface 2a covered by the metal layer 5 along the main surface 4a. An opening 5a is formed in the center of the metal layer 5 covering a pixel structure 2, and light from the detected object passes through the inside of the opening 5a and is incident on the center of the main surface 4b of the photoelectric conversion layer 4.
[0029] In the region of the photoelectric conversion layer 4 corresponding to the inner side of the opening 5a, from the main surface 4b to the main surface 4a, the following layers are sequentially embedded and stacked: a P-type semiconductor layer p1, an N-type (first conductivity type) embedded region (first embedded region) n1B (opposite polarity to P-type), a P-type semiconductor layer p2, an N-type embedded region (second embedded region) n3G, a P-type semiconductor layer p3, and an N-type embedded region (fifth embedded region) n4R. Embedded region n3G is formed at a deeper location than embedded region n1B. Embedded region n4R is formed at a deeper location than both embedded regions n1B and n3G. A portion of embedded region n4R extends into the same layer as the P-type semiconductor layer p3.
[0030] These P-type semiconductor layers p1 and the buried region n1B constitute a first photodiode disposed near the main surface 4b. Therefore, the buried region n1B converts the blue light component of the light incident from the opening 5a onto the main surface 4b into electrons and stores the converted electrons.
[0031] The P-type semiconductor layer p2 and the buried region n3G constitute a second photodiode buried deeper than the first photodiode from the main surface 4b. Therefore, the buried region n3G converts the green light component, which has a longer wavelength than the blue light component, in the light incident from the opening 5a onto the main surface 4b into electrons.
[0032] The P-type semiconductor layer p3 and the buried region n4R constitute a third photodiode buried deeper than the first and second photodiodes from the main surface 4b. Therefore, the buried region n4R converts the red light component with a longer wavelength than the green light component in the light incident from the opening 5a onto the main surface 4b into electrons.
[0033] Additionally, in the region outside the first to third photodiodes covered by the metal layer 5 in the photoelectric conversion layer 4 (in... Figure 1 In the regions (denoted by n1G and n1R in the attached diagram), an N-type buried region (third buried region) n1G and a P-type semiconductor layer p2 are stacked below the P-type semiconductor layer p1, and an N-type buried region (sixth buried region) n1R and a P-type semiconductor layer p2 are also stacked. These buried regions n1G and n1R are formed in the same layer as buried region n1B, sandwiched between two P-type semiconductor layers. Buried region n1G is provided for accumulating electrons converted from buried region n3G, and buried region n1R is provided for accumulating electrons converted from buried region n4R.
[0034] In addition, in order to reliably separate the electrons caused by the blue light component and the electrons caused by the green light component that are respectively stored in the buried region n1B and the buried region n1G, a P-type buried region p5 connected to the buried region n1B and the buried region n1G can be formed so that a potential barrier is formed between the buried region n1B and the buried region n1G.
[0035] In addition, in the photoelectric conversion layer 4, within the region sandwiched between the buried region n1G and the buried region n3G in the same layer as the P-type semiconductor layer p2, an N-type buried region (fourth buried region) n2G is formed in a manner that connects to a portion of the buried region n1G and a portion of the buried region n3G. Furthermore, a P-type semiconductor layer p4 is formed at the ends of the buried regions n2G, n3G, the P-type semiconductor layer p3, and the buried region n4R. This P-type semiconductor layer p4 is used to form a potential barrier between adjacent pixel structures 2 by connecting across these layers. With this structure, the buried region n2G is positioned between the buried regions n1G and n3G, sandwiched between two P-type semiconductor layers p2 and p4 along the direction of the main surface 4b. The buried region n2G serves to transfer electrons converted by the buried region n3G to the buried region n1G.
[0036] Here, the impurity concentration in buried region n1G is higher than that in buried region n2G. The impurity concentration in buried region n2G is higher than that in buried region n3G. This characteristic allows the potential to change monotonically across buried regions n3G, n2G, and n1G. Furthermore, buried region n2G is formed such that the length L between the interface surface of buried region n1G (perpendicular to the main surface 4b) and the interface surface of buried region n3G is... G The width W is the area sandwiched between two P-type semiconductor layers p2 and p4. G More than 1 / 2. That is, the buried region n2G satisfies the following mathematical formula (1): L G ≥ (1 / 2) W G …(1).
[0037] Therefore, in the buried region n2G, it is not easy for the potential to sink, and a potential that monotonically changes between the interface with the buried region n1G and the interface with the buried region n3G is generated.
[0038] Furthermore, in the photoelectric conversion layer 4, in the region sandwiched between buried regions n1R and n4R in the same layer as the P-type semiconductor layer p2 and the buried region n3G, two N-type buried regions (seventh buried regions) n2R and n3R are formed in such a way that they are connected to a portion of buried region n1R and a portion of buried region n4R. The buried region (first sub-region) n3R is positioned close to the buried region n4R, and the buried region (second sub-region) n2R is positioned close to the buried region n1R. In addition, a P-type semiconductor layer p4 is formed at the ends of the buried regions n2R, n3R, and n4R, and this P-type semiconductor layer p4 is used to form a potential barrier between adjacent pixel structures 2 in such a way that it is connected across these layers. Furthermore, P-type semiconductor layers PW and p4 are formed between buried regions n1R, n2R, and n3R and between buried regions n1B and n3G to form a potential barrier. In this case, the P-type semiconductor layer p4 is formed to the same depth as or shallower than the lower surface of the P-type semiconductor layer p3. With this structure, buried regions n2R and n3R are arranged between buried regions n1R and n4R, sandwiched between the P-type semiconductor layers p4 and PW along the direction of the main surface 4b. Alternatively, omitting the P-type semiconductor layer p4 that overlaps with the P-type semiconductor layer PW, forming the P-type semiconductor layer PW to the depth overlapping with the P-type semiconductor layer p3, and forming the P-type semiconductor layer p4 deeper than the lower surface of the buried region n4R, can also achieve the same configuration effect.
[0039] Here, the impurity concentration in buried region n1R is higher than that in buried regions n2R and n3R. The impurity concentration in buried region n2R is higher than that in buried region n3R. The impurity concentration in buried region n3R is higher than that in buried region n4R. This characteristic allows the potential to change monotonically in the region spanning buried regions n4R, n3R, n2R, and n1R. Furthermore, buried regions n2R and n3R are formed such that the length L of the region sandwiched between two P-type semiconductor layers p4 in buried regions n2R, n3R, and n4R in the direction perpendicular to the main surface 4b is... R The width W is the area sandwiched between two P-type semiconductor layers p4 and pW. R More than three times. That is, the buried regions n2R and n3R are formed to satisfy the following mathematical formula (2): L R ≥3×W R …(2).
[0040] Therefore, in the buried regions n2R and n3R, it is not easy for the potential to sink, and a potential that changes monotonically between the interface with the buried region n1R and the interface with the buried region n4R is generated.
[0041] like Figure 2 and Figure 3 As shown, the photoelectric conversion device 1 further includes: a signal generation unit 6G that generates a signal corresponding to the amount of charge of electrons transferred from the buried region n1G to the floating diffusion layer n5G; a signal generation unit 6R that generates a signal corresponding to the amount of charge of electrons transferred from the buried region n1R to the floating diffusion layer n5R; and a signal generation unit 6B that generates a signal corresponding to the amount of charge of electrons transferred from the buried region n1B to the floating diffusion layer n5B.
[0042] The signal generation unit 6G includes a reset transistor 8, a transistor 9, a select transistor 10, and a bias transistor 11. The reset transistor 8, transistor 9, select transistor 10, and bias transistor 11 are MOS transistors, and a portion of them can be formed on the same semiconductor substrate 3 as the plurality of pixel structures 2. A select signal SL is supplied externally to the gate of the select transistor 10. A reset signal RT is supplied externally to the gate of the reset transistor 8. A transfer signal is supplied externally to the transfer gate TX2. The floating diffusion layer n5G can be externally reset via the reset transistor 8 using a reset potential V. DRT The transistor 9 is connected to the gate of transistor 9. One current terminal (e.g., the source) of transistor 9 is connected to column line 7 via select transistor 10. A potential VDSF is applied from the outside to another current terminal (e.g., the drain) of transistor 9. Transistor 9, acting as a source follower, provides a potential to column line 7 via select transistor 10 corresponding to the charge amount of the floating diffusion layer n5G. A bias voltage Vbias is applied from the outside to the gate of bias transistor 11, and the drain of bias transistor 11 is connected to column line 7. Bias transistor 11 is a common current source for column line 7 that supplies drain current to transistors 9 of each pixel selected by select transistor 10.
[0043] The signal generation unit 6G of the above structure generates a first signal representing a reset level and a second signal representing a signal level overlapping with the reset level as follows: First, a reset signal RT is supplied to the reset transistor 8, and the floating diffusion layer n5G is reset. The reset potential is read out in an external readout circuit via transistor 9. Next, a transfer signal is supplied to the transfer gate TX2, and electrons are transferred from the buried region n1G to the floating diffusion layer n5G. Then, a signal level corresponding to the charge of the electrons transferred in the external readout circuit via transistor 9 is read out. In this way, the signal generation unit 6G can generate a first signal representing the reset level and a second signal representing a signal level overlapping with the reset level.
[0044] Similarly, signal generation units 6R and 6B each include a reset transistor 8, a transistor 9, a selection transistor 10, and a bias transistor 11. The structure and operation of signal generation units 6R and 6B are the same as those of signal generation unit 6G. Signal generation unit 6R generates a first signal representing a reset level; and a second signal representing a signal level that overlaps with the reset level and corresponds to the amount of charge of electrons transferred to the floating diffusion layer n5R. Signal generation unit 6B generates a first signal representing a reset level; and a second signal representing a signal level that overlaps with the reset level and corresponds to the amount of charge of electrons transferred to the floating diffusion layer n5B.
[0045] Reference Figure 4 and Figure 5 The potential distribution along the depth direction in pixel structure 2 is explained. Figure 4 The diagram shows the potential distribution P0 along the direction perpendicular to the main surfaces 4b of the first to third photodiodes in the photoelectric conversion layer 4 of pixel structure 2, and the potential distribution P along the direction perpendicular to the main surfaces 4b of the buried regions n1R, n2R, n3R, and n4R in the photoelectric conversion layer 4. R .exist Figure 5 The diagram shows the potential distribution P0 along the direction perpendicular to the main surfaces 4b of the first to third photodiodes in the photoelectric conversion layer 4 of pixel structure 2, and the potential distribution P along the direction perpendicular to the main surfaces 4b of the buried regions n1G, n2G, and n3G in the photoelectric conversion layer 4. G Here, the equivalent depth of burial in regions n1G and n1R is determined by position d. n1 This means that the depth of the burial area n2G, n2R is determined by the position d. n2 This means that the depth of the burial area n3G and n3R is determined by the position d. n3 This indicates that the depth of the layer above the P-type semiconductor layer p3 and the buried region n4R is determined by position d. p3 This indicates that the depth of the lower layer buried in region n4R is determined by position d. n4 express.
[0046] like Figure 4 As shown, the potential distribution P along the electron transport path across the buried regions n1R, n2R, n3R, and n4R is... R In, a formation is formed from position d n4 To position d n1 A monotonically increasing potential. In particular, since the impurity concentration is set from position d... n4 To position d n1 The potential distribution P increases in stages, and the buried regions n2R and n3R are formed to satisfy the above mathematical formula (2). RIn this way, a partial rise will not form a dip, resulting in a monotonous tilt. In addition, the electron transfer path across the buried regions n1R, n2R, n3R, and n4R is depleted, which in turn reduces the noise of the signal read from the amount of charge transferred to n1R.
[0047] In addition, such as Figure 5 As shown, the potential distribution P along the electron transport path traversing the buried regions n1G, n2G, and n3G is... G In, a formation is formed from position d n3 To position d n1 A monotonically increasing potential. In particular, since the impurity concentration is set from position d... n3 To position d n1 The potential distribution P increases in stages, and the buried region n2G is formed to satisfy the above mathematical formula (1), therefore the potential distribution P G In this way, a dip with partial rise will not form, resulting in a monotonous tilt. In addition, the depletion of the electron transfer path across the buried regions n1G, n2G, and n3G is also achieved, which in turn reduces the noise of the signal read from the amount of charge transferred to n1G.
[0048] The effects of the photoelectric conversion device 1 described above will be explained.
[0049] According to the photoelectric conversion device 1, the blue light component of the light incident from the main surface 4b of the photoelectric conversion layer 4 is converted into electrons in the N-type buried region n1B, and the converted electrons are stored. In addition, the green light component of the light incident from the main surface 4b of the photoelectric conversion layer 4 is converted into electrons in the N-type buried region n3G, and the converted electrons are stored in the N-type buried region n1G via the N-type buried region n2G which is connected to the buried regions n3G and n1G. Here, the buried region n2G is sandwiched between two P-type semiconductor layers p2 and p4, and the impurity concentration is set to increase in the order of buried region n3G, buried region n2G, and buried region n1G. Therefore, the potential distribution P along the electron transport path from buried region n3G to buried region n1G is... G In this system, dips are less likely to occur because the potential is formed in a monotonically changing manner, allowing electrons to be transferred at high speed from the buried region n3G to the buried region n1G. As a result, high-speed detection of electrons accumulated based on two wavelength components of light can be achieved. In addition, the electron transfer path across the buried regions n1G, n2G, and n3G is depleted, which also reduces the noise of the signal read out based on the amount of charge transferred to n1G.
[0050] Furthermore, the photoelectric conversion layer 4 of this embodiment includes: an N-type buried region n4R that converts the red light component incident on the main surface 4b into electrons; an N-type buried region n1R that stores the electrons converted by the buried region n4R; and N-type buried regions n2R and n3R that are connected to the buried regions n4R and n1R and sandwiched between the buried regions n4R and n1R, respectively, to transfer the electrons converted by the buried region n4R to the buried region n1R. In this structure, the red light component of the light incident from the main surface 4b of the photoelectric conversion layer 4 is converted into electrons in the buried region n4R, and the converted electrons are stored in the buried region n1R via the buried regions n2R and n3R that are connected to the buried regions n4R and n1R. Here, buried regions n2R and n3R are sandwiched between two P-type semiconductor layers, and the impurity concentration is set to increase in the order of buried regions n4R, n3R, n2R, and n1R. Consequently, the potential distribution P along the electron transport path from buried region n4R to buried region n1R... R In this configuration, dips are less likely to occur, and the potential is formed through a monotonic change, thus enabling high-speed transfer of electrons from the buried region n4R to the buried region n1R. As a result, high-speed detection of electrons accumulated based on light of three wavelength components is achieved. Furthermore, the depletion of the electron transfer path across the buried regions n1R, n2R, n3R, and n4R is achieved, which also reduces noise in the signal read from the amount of charge transferred to the buried region n1R.
[0051] Furthermore, the buried region n2G is formed to satisfy the above mathematical formula (1). In this case, it is possible to prevent the potential distribution P in the electron transfer path from the buried region n3G to the buried region n1G. G A potential dip is generated in the buried region. As a result, electrons can be transferred at high speed from the buried region n3G to the buried region n1G. Generally, if the N-type region sandwiched by the P-type region is wide, the impurity concentration needs to be reduced to form a monotonic potential tilt. On the other hand, according to the buried region n2G formed in a manner that satisfies the above equation (1), a monotonic potential tilt from the buried region n3G to the buried region n1G can be formed while maintaining a high impurity concentration. As a result, electron movement in the buried regions n3G, n2G, and n1G can be promoted, and the transfer speed of signal charge can be improved.
[0052] Furthermore, the buried regions n2R and n3R are formed to satisfy the above mathematical formula (2). In this case, it is possible to prevent the potential distribution P in the electron transfer path from buried region n4R to buried region n1R. RA potential dip is generated in the buried region. As a result, electrons can be transferred at high speed from the buried region n4R to the buried region n1R. According to the buried regions n2R and n3R formed in a manner that satisfies the above mathematical formula (2), a monotonically tilted potential is formed from the buried region n4R to the buried region n1R while maintaining a relatively high impurity concentration. As a result, electron movement in the buried regions n4R, n3R, n2R, and n1R can be promoted, and the transfer speed of signal charge can be improved.
[0053] This invention is not limited to the embodiments described above. Various modifications to the structure of the embodiments described above are possible.
[0054] Furthermore, in the above embodiment, the P-type photoelectric conversion layer 4 is formed on the P-type semiconductor substrate 3. As a variation, the photoelectric conversion layer 4 may also be stacked on an N-type semiconductor substrate with an epitaxial layer having a higher concentration than the photoelectric conversion layer 4. Figure 6 This is a cross-sectional view of a modified pixel structure 2A. In pixel structure 2A, an N-type semiconductor substrate 3a is provided, which is connected to the main surface 4a via a P-type epitaxial layer 3b with a higher impurity concentration than the photoelectric conversion layer 4. Thus, by using an N-type semiconductor substrate, low crosstalk and low dark current can be achieved.
[0055] In the above embodiment, the region for accumulating electrons converted from light of three wavelength components (e.g., the region of a three-layer structure consisting of a P-type semiconductor layer p1, a buried region n1G, and a P-type semiconductor layer p2) uses a three-layer structure of a P-type semiconductor layer-N-type semiconductor layer-P-type semiconductor layer. As a variation, the region for accumulating electrons may also employ an accumulation gate structure composed of a metal layer-insulator layer-semiconductor layer. Figure 7 This is a top view of the modified photoelectric conversion device 1A. Figure 8 This is a cross-sectional view of the photoelectric conversion device 1A. In the photoelectric conversion device 1A, accumulation gates SG2 and SG3 are formed on the outermost surface of the photoelectric conversion layer 4, separated by a gate insulating film. That is, in the photoelectric conversion layer 4, buried regions n1G and n1R are formed on the outermost surface. An accumulation gate SG2, which serves as a metal layer, is formed on the surface region that includes the buried region n1G in two dimensions, separated by a gate insulating film. An accumulation gate SG3, which serves as a metal layer, is formed on the surface region that includes the buried region n1R in two dimensions, separated by a gate insulating film. As a result, the number of electrons that can be accumulated in the buried regions n1G and n1R can be increased. When accumulating photoelectrons, a positive charge can be applied to the accumulation gates SG2 and SG3 to deepen the potential trap and increase the number of accumulated electrons. When using transfer gates TX2 and TX3 to transfer electrons from the buried region n1G to the floating diffusion layer n5G or from the buried region n1R to the floating diffusion layer n5R, negative charges can be applied to the accumulation gates SG2 and SG3 to promote electron transfer.
[0056] Furthermore, in the absence of a structure with an accumulation gate, a P-type semiconductor layer p1, serving as a pinning layer, is also formed on the surfaces of the buried regions n1G and n1R. Figure 2 However, in the case of a structure with a storage gate, the P-type semiconductor layer p1 is formed in a self-aligned manner in the region outside the storage gate after the storage gate is formed. Figure 8 ).
[0057] Figure 9 This is a cross-sectional view of a modified photoelectric conversion device. In this modified example, compared to... Figure 2 The structure shown differs in the dimensions of the buried regions n2R and n3R, and the positions of the P-type semiconductor layers p4 and PW. In this variation, the positions of the P-type semiconductor layers p4 and PW are changed from point G to closer to point B, and the width of the buried regions n2R and n3R is enlarged on the point B side. Specifically, the width W in the direction parallel to the main surface 4b of the region sandwiched between the two P-type semiconductor layers p4 in the buried regions n2R and n3R is... R2 The width W is set to be greater than the width of the main surface 4b of the region within the buried region n4R that is sandwiched between the regions of the two P-type semiconductor layers p3 and p4. R Specifically, the width W R2 Width W R More than 1.5 times the width W R For values less than twice the value, the following mathematical expression must be satisfied: 1.5W R ≤W R2 ≤2W R .
[0058] According to this variation, a potential dip in the potential distribution along the carrier transfer path from buried region n4R to buried region n1R can be prevented. As a result, carriers can be transferred at high speed from buried region n4R to buried region n1R.
[0059] In this embodiment, the photoelectric conversion layer may also include: a fifth buried region of the first conductivity type, buried deeper than the first and second buried regions from the second main surface, which converts light of the third wavelength component incident on the second main surface into charge carriers; a sixth buried region of the first conductivity type, buried in the same layer as the first buried region in the second main surface, which stores the charge carriers converted by the fifth buried region; and a seventh buried region of the first conductivity type, which is connected to the fifth and sixth buried regions and is arranged between the fifth and sixth buried regions in a manner sandwiched by two regions of the second conductivity type, which transfers the charge carriers converted by the fifth buried region to the sixth buried region; wherein the impurity concentration of the sixth buried region is set to be higher than that of the seventh buried region, and the impurity concentration of the seventh buried region is set to be higher than that of the fifth buried region. In this structure, the third wavelength component of the light incident from the second main surface of the photoelectric conversion layer is converted into charge carriers in the fifth embedded region of the first conductivity type. The converted charge carriers are then stored in the sixth embedded region of the first conductivity type via the seventh embedded region, which is connected to the fifth and sixth embedded regions. Here, the seventh embedded region is sandwiched between two regions of the second conductivity type, and the impurity concentration is set to increase sequentially from the fifth to the sixth embedded region. Consequently, a potential dip is less likely to occur in the potential distribution along the charge carrier transfer path from the fifth to the sixth embedded region, and the potential changes monotonically, allowing for high-speed transfer of charge carriers from the fifth to the sixth embedded region. As a result, high-speed detection of charge carriers stored based on the three wavelength components of the light can be achieved.
[0060] Alternatively, the seventh embedded region may also include a first sub-region close to the fifth embedded region and a second sub-region close to the sixth embedded region, with the impurity concentration in the second sub-region set to be higher than that in the first sub-region. In this case, a monotonically changing potential is easily formed in the potential distribution of the carrier transfer path in the seventh embedded region, enabling carriers to be transferred from the fifth embedded region to the sixth embedded region at a faster speed.
[0061] Furthermore, the length of the fourth embedded region in the direction perpendicular to the second main surface can also be set to be more than half the width between the two regions of the second conductivity type. In this case, it is possible to prevent a potential dip in the potential distribution of the charge carrier transfer path from the second embedded region to the third embedded region. As a result, charge carriers can be transferred from the second embedded region to the third embedded region at high speed.
[0062] Furthermore, the length of the region perpendicular to the second main surface of the region that combines the seventh and fifth buried regions and is sandwiched between two regions of the second conductivity type can be set to more than three times the width between the two regions of the second conductivity type. In this case, a potential dip can be prevented in the potential distribution of the carrier transfer path from the fifth buried region to the sixth buried region. As a result, carriers can be transferred from the fifth buried region to the sixth buried region at high speed.
[0063] Alternatively, the semiconductor substrate may also include a first conductivity type semiconductor substrate, which is connected to the first main surface via an epitaxial layer of a second conductivity type with a higher impurity concentration than the photoelectric conversion layer.
[0064] Alternatively, the sixth buried region can also form the outermost surface of the photoelectric conversion layer, with the accumulation gate formed in the surface region containing the sixth buried region via a gate insulating film. Alternatively, the third buried region can also form the outermost surface of the photoelectric conversion layer, with the accumulation gate formed in the surface region containing the third buried region via a gate insulating film.
[0065] Furthermore, the width of the region in the seventh buried region that is sandwiched between two regions of the second conductivity type, in the direction parallel to the second main surface, can also be set to be greater than the width of the region in the fifth buried region that is sandwiched between two regions of the second conductivity type, in the direction parallel to the second main surface. In this case, a potential dip can be prevented in the potential distribution of the carrier transfer path from the fifth buried region to the sixth buried region. As a result, carriers can be transferred from the fifth buried region to the sixth buried region at high speed.
[0066] Furthermore, the width of the region in the seventh embedded region that is sandwiched between two regions of the second conductivity type, in the direction parallel to the second main surface, can also be set to be at least 1.5 times and less than 2 times the width of the region in the fifth embedded region that is sandwiched between two regions of the second conductivity type, in the direction parallel to the second main surface. In this case, it is also possible to prevent a potential dip in the potential distribution of the carrier transfer path from the fifth embedded region to the sixth embedded region. As a result, it is possible to transfer carriers at high speed from the fifth embedded region to the sixth embedded region.
[0067] The photoelectric conversion device of the embodiment is as described in [1]: "A photoelectric conversion device, wherein:" Semiconductor substrates; and A photoelectric conversion layer is formed on the semiconductor substrate, having a first main surface close to the semiconductor substrate and a second main surface along the first main surface; The photoelectric conversion layer has: The first embedded region of the first conductivity type is embedded in the second main surface, converting the light of the first wavelength component incident on the second main surface into charge carriers and accumulating the converted charge carriers; The second buried region of the first conductivity type is buried at a position deeper than the first buried region from the second main surface, and converts the light of the second wavelength component incident on the second main surface into charge carriers; A third embedded region of the first conductivity type is embedded in the same layer as the first embedded region on the second main surface, accumulating charge carriers converted from the second embedded region; and The fourth embedded region of the first conductivity type is connected to the second embedded region and the third embedded region, and is arranged between the second embedded region and the third embedded region in such a way that it is sandwiched between two regions of the second conductivity type, so as to transfer the charge carriers converted by the second embedded region to the third embedded region. The impurity concentration in the third buried region is set to be higher than that in the fourth buried region, and the impurity concentration in the fourth buried region is set to be higher than that in the second buried region. The photoelectric conversion device of the embodiment can also be as described in [2]: "According to the photoelectric conversion device described in [1] above, wherein, The photoelectric conversion layer has: The fifth embedded region of the first conductivity type is embedded at a position deeper than the first and second embedded regions from the second main surface, and converts the light of the third wavelength component incident on the second main surface into charge carriers. The sixth embedded region of the first conductivity type is embedded in the same layer as the first embedded region on the second main surface, accumulating the charge carriers converted by the fifth embedded region; and The seventh embedded region of the first conductivity type is connected to the fifth embedded region and the sixth embedded region, and is arranged between the fifth embedded region and the sixth embedded region in a manner sandwiched by two regions of the second conductivity type, so as to transfer the charge carriers converted by the fifth embedded region to the sixth embedded region. The impurity concentration in the sixth buried region is set to be higher than that in the seventh buried region, and the impurity concentration in the seventh buried region is set to be higher than that in the fifth buried region. The photoelectric conversion device of the embodiment can also be as described in [3]: "According to the photoelectric conversion device described above [2], wherein, The seventh buried region includes a first sub-region adjacent to the fifth buried region and a second sub-region adjacent to the sixth buried region. The impurity concentration in the second sub-region is set to be higher than that in the first sub-region. The photoelectric conversion device of the embodiment can also be as described in [4]: "In the photoelectric conversion device according to any one of [1] to [3] above, the length of the fourth embedded region in the direction perpendicular to the second main surface is set to be more than 1 / 2 of the width between the two second conductivity type regions." The photoelectric conversion device of the embodiment can also be as described in [5]: "According to the photoelectric conversion device described in [2] or [3] above, wherein, The length of the region formed by combining the seventh embedded region and the region sandwiched between two second conductive type regions in the fifth embedded region, in the direction perpendicular to the second main surface, is set to be at least three times the width between the two second conductive type regions. The photoelectric conversion device of the embodiment can also be as described in [6]: "The photoelectric conversion device according to any one of [1] to [5] above, wherein, The semiconductor substrate includes a first conductivity type semiconductor substrate, which is connected to the first main surface via an epitaxial layer of a second conductivity type with a higher impurity concentration than the photoelectric conversion layer. The photoelectric conversion device of the embodiment can also be as described in [7]: "According to the photoelectric conversion device described in [2], [3] or [5] above, wherein, The sixth buried region is set as the outermost surface of the photoelectric conversion layer, and an accumulation gate is formed on the surface region containing the sixth buried region through a gate insulating film. The photoelectric conversion device of the embodiment can also be as described in [8]: "In the photoelectric conversion device according to any one of [1] to [7] above, the third buried region is set as the outermost surface of the photoelectric conversion layer, and an accumulation gate is formed in the surface region containing the third buried region through the gate insulating film." The photoelectric conversion device of the embodiment can also be as described in [9]: "According to the photoelectric conversion device described in [2] or [3] above, wherein, The width of the area in the seventh embedded region that is sandwiched between two areas of the second conductive type, in the direction parallel to the second main surface, is set to be greater than the width of the area in the fifth embedded region that is sandwiched between two areas of the second conductive type, in the direction parallel to the second main surface. The photoelectric conversion device of the embodiment can also be as described in
[10] : "According to the photoelectric conversion device described above [9], wherein, The width of the area in the seventh embedded region that is sandwiched between two areas of the second conductive type, in the direction parallel to the second main surface, is set to be at least 1.5 times and less than 2 times the width of the area in the fifth embedded region that is sandwiched between two areas of the second conductive type, in the direction parallel to the second main surface. Explanation of reference numerals in the attached figures 1, 1A: Photoelectric conversion device; 3, 3a: Semiconductor substrate; 4: Photoelectric conversion layer; 4a: Main surface (first main surface); 4b: Main surface (second main surface); n1B: Buried area (first buried area); n1G: Buried area (third buried area); n1R: Buried area (sixth buried area); n2G: Buried area (fourth buried area); n2R, n3R: Buried area (seventh buried area); n2R: Buried area (second sub-region); n3G: Buried area (second buried area); n3R: Buried area (first sub-region); n4R: Buried area (fifth buried area); SG2, SG3: Accumulation gate; W G W R W R2 Width; L G L R :length.
Claims
1. A photoelectric conversion device, wherein, have: Semiconductor substrate; as well as A photoelectric conversion layer is formed on the semiconductor substrate, having a first main surface close to the semiconductor substrate and a second main surface along the first main surface; The photoelectric conversion layer has: A first embedded region of a first conductivity type is embedded in the second main surface, converting light of the first wavelength component incident on the second main surface into charge carriers and accumulating the converted charge carriers; The second buried region of the first conductivity type is buried at a position deeper than the first buried region from the second main surface, and converts the light of the second wavelength component incident on the second main surface into charge carriers; The third embedded region of the first conductivity type is embedded in the same layer as the first embedded region on the second main surface, and accumulates the charge carriers converted by the second embedded region; as well as The fourth embedded region of the first conductivity type is connected to the second embedded region and the third embedded region, and is arranged between the second embedded region and the third embedded region in such a way that it is sandwiched between two regions of the second conductivity type, so as to transfer the charge carriers converted by the second embedded region to the third embedded region. The impurity concentration in the third buried region is set to be higher than that in the fourth buried region, and the impurity concentration in the fourth buried region is set to be higher than that in the second buried region.
2. The photoelectric conversion device according to claim 1, wherein, The photoelectric conversion layer has: The fifth embedded region of the first conductivity type is embedded at a position deeper than the first and second embedded regions from the second main surface, and converts the light of the third wavelength component incident on the second main surface into charge carriers. The sixth embedded region of the first conductivity type is embedded in the same layer as the first embedded region on the second main surface, where charge carriers converted from the fifth embedded region are stored. as well as The seventh embedded region of the first conductivity type is connected to the fifth embedded region and the sixth embedded region, and is arranged between the fifth embedded region and the sixth embedded region in a manner sandwiched by two regions of the second conductivity type, so as to transfer the charge carriers converted by the fifth embedded region to the sixth embedded region. The impurity concentration in the sixth buried region is set to be higher than that in the seventh buried region, and the impurity concentration in the seventh buried region is set to be higher than that in the fifth buried region.
3. The photoelectric conversion device according to claim 2, wherein, The seventh embedment area includes a first sub-area adjacent to the fifth embedment area and a second sub-area adjacent to the sixth embedment area. The impurity concentration in the second sub-region is set to be higher than that in the first sub-region.
4. The photoelectric conversion device according to any one of claims 1 to 3, wherein, The length of the fourth embedded region in the direction perpendicular to the second main surface is set to be more than 1 / 2 of the width between the two second conductive regions.
5. The photoelectric conversion device according to claim 2 or 3, wherein, The length of the region formed by combining the seventh embedded region and the region sandwiched between two second conductive regions in the fifth embedded region, in the direction perpendicular to the second main surface, is set to be more than three times the width between the two second conductive regions.
6. The photoelectric conversion device according to any one of claims 1 to 5, wherein, The semiconductor substrate includes a first conductivity type semiconductor substrate, which is connected to the first main surface via an epitaxial layer of a second conductivity type with a higher impurity concentration than the photoelectric conversion layer.
7. The photoelectric conversion device according to claim 2, 3 or 5, wherein, The sixth buried region is set as the outermost surface of the photoelectric conversion layer, and an accumulation gate is formed in the surface region containing the sixth buried region through the gate insulating film.
8. The photoelectric conversion device according to any one of claims 1 to 7, wherein, The third buried region is set as the outermost surface of the photoelectric conversion layer, and an accumulation gate is formed in the surface region containing the third buried region through the gate insulating film.
9. The photoelectric conversion device according to claim 2 or 3, wherein, The width of the area in the seventh embedded region that is sandwiched between two areas of the second conductive type in the direction parallel to the second main surface is set to be greater than the width of the area in the fifth embedded region that is sandwiched between two areas of the second conductive type in the direction parallel to the second main surface.
10. The photoelectric conversion device according to claim 9, wherein, The width of the area in the seventh embedded region that is sandwiched between two areas of the second conductive type in the direction parallel to the second main surface is set to be more than 1.5 times and less than 2 times the width of the area in the fifth embedded region that is sandwiched between two areas of the second conductive type in the direction parallel to the second main surface.