A pressure sensor and method of forming the same

Abstract

The application discloses a pressure sensor and a forming method thereof, and belongs to the technical field of MEMS sensors. The pressure sensor comprises a first substrate having a first surface; and a second substrate stacked along a first direction with the first substrate, the second substrate having opposite second and third surfaces, the second surface being fixedly bonded with the first surface, and a cavity being formed between the second surface and the first surface; the second substrate comprises a first region and a second region, the stress borne by the first region being greater than the stress borne by the second region; a first piezoresistor is located on the third surface of the first region, the first piezoresistor and the cavity being stacked along the first direction, and the first piezoresistor is used for outputting a first voltage signal; and a second piezoresistor is located on the third surface of the second region, the second piezoresistor and the cavity being stacked along the first direction, and the second piezoresistor is used for outputting a second voltage signal. Through the above scheme, two ranges of pressures are measured by using one sensor chip, and the volume of the pressure sensor is effectively reduced.

Description

Technical Field

[0001] This application relates to the field of MEMS sensor technology, and in particular to a pressure sensor and a method for forming the same. Background Technology

[0002] Pressure sensors are used for pressure measurement and monitoring. A piezoresistive resistor is the core component of a pressure sensor. The resistance of a piezoresistive resistor changes with the applied pressure; this characteristic (piezoresistive effect) allows it to convert mechanical pressure signals into electrical signals. Specifically, when a piezoresistive resistor is subjected to external force (pressure), the crystal lattice structure inside the material deforms, causing a change in the mobility of charge carriers (electrons or holes), thus resulting in a change in the resistance value. Consequently, the voltage signal of the piezoresistive resistor changes. This voltage signal is then output to a control module, which converts the voltage signal into a pressure value, thereby enabling pressure measurement and monitoring.

[0003] Among related technologies, MEMS (micro-electro-mechanical systems) piezoresistive pressure sensors are widely used in consumer electronics, medical devices, and wearable devices due to their high sensitivity and good linearity. In wearable devices (such as smartwatches), these pressure sensors can be used to monitor parameters such as blood pressure and altitude. These pressure sensors typically employ a multi-chip design (such as a dual-chamber absolute pressure chip or a combination of two chips with different pressure ranges), but this increases size, making it difficult to meet the compact size requirements of wearable devices. Summary of the Invention

[0004] This application provides a pressure sensor and a method for forming the same, to at least partially solve the above-mentioned technical problems.

[0005] To achieve the above objectives, according to a first aspect of this application, a pressure sensor is provided, comprising: A first substrate has a first surface; A second substrate is stacked with the first substrate along a first direction. The second substrate has a second surface and a third surface opposite to each other. The second surface is bonded and fixed to the first surface, and a cavity is formed between the second surface and the first surface. The second substrate includes a first region and a second region, and the stress on the first region is greater than the stress on the second region. A first varistor is located on the third surface of the first region. The first varistor and the cavity are stacked along the first direction. The first varistor is used to output a first voltage signal. The second varistor is located on the third surface of the second region. The second varistor and the cavity are stacked along the first direction. The second varistor is used to output a second voltage signal.

[0006] In some embodiments, the first substrate has a first groove recessed relative to the first surface, and the second substrate has a second groove recessed relative to the second surface, wherein the first groove and the second groove constitute the cavity; The second groove is located in the second region; The first groove has a first projection on the second surface, and the second groove has a second projection on the second surface, with the second projection falling within the range of the first projection. The first varistor has a fifth projection on the second surface, the fifth projection being within the range of the first projection, and the fifth projection not overlapping with the second projection; The second varistor has a sixth projection on the second surface, and the sixth projection is within the range of the second projection; The first region surrounds the second region; The first voltage signal is greater than the second voltage signal.

[0007] In some embodiments, the first substrate has a first groove recessed relative to the first surface, the first groove constituting the cavity; the pressure sensor further includes: Multiple first support columns are located in the first groove, with one end of the first support column coupled to the bottom of the first groove and the other end coupled to the second surface; The first groove has a geometric center, and a plurality of the first support columns are centrally symmetrical about the geometric center, with the first support columns located between the first area and the second area; The first substrate has a first groove recessed relative to the first surface, the first groove forming the cavity; The first groove has a first projection on the second surface, the first varistor has a seventh projection on the second surface, the seventh projection is within the range of the first projection, the first area is within the range of the first projection, and the second area is within the range of the first projection; The first voltage signal is greater than the second voltage signal.

[0008] In some embodiments, the first substrate has a first groove recessed relative to the first surface, the first groove forming the cavity; the pressure sensor further includes: a plurality of second support posts, the plurality of second support posts being located in the first groove, one end of the second support post being coupled to the second surface, and the other end being spaced from the bottom of the first groove; The second surface has a geometric center, and a plurality of second support columns are centrally symmetrical about the geometric center, with the second support columns located between the first region and the second region; The first substrate has a first groove recessed relative to the first surface, the first groove forming the cavity; The first groove has a first projection on the second surface, the first piezoresistor has an eighth projection on the second surface, the eighth projection is within the range of the first projection, the first area is within the range of the first projection, and the second area is within the range of the first projection. The first voltage signal is greater than the second voltage signal.

[0009] In some embodiments, the pressure sensor further includes: a first dielectric layer located on the third surface; the first dielectric layer includes a fourth surface and a fifth surface, the fourth surface being connected to the third surface; The first conductive structure includes a first via structure penetrating the first dielectric layer, the first via structure being coupled to the first varistor; The second conductive structure includes a second via structure that penetrates the first dielectric layer, and the second via structure is coupled to the second varistor.

[0010] In some embodiments, the first conductive structure further includes: a first wire and a first pad located on the fifth surface of the first dielectric layer and coupled to each other, wherein the first wire is coupled to the first via structure; The second conductive structure further includes: a second conductor and a second pad located on the fifth surface of the first dielectric layer and coupled to each other, wherein the second conductor is coupled to the second via structure.

[0011] In some embodiments, the pressure sensor further includes: a second medium layer located on a fifth surface of the first medium layer; the second medium layer includes a sixth surface and a seventh surface, the sixth surface being connected to the fifth surface of the first medium layer; The third conductive structure includes a third via structure that penetrates the second dielectric layer, the third via structure being coupled to the first pad; The fourth conductive structure includes a fourth via structure penetrating the second dielectric layer, the fourth via structure being coupled to the second pad.

[0012] In some embodiments, the third conductive structure further includes: a third conductor and a third pad located on the seventh surface of the second dielectric layer and coupled to each other, wherein the third conductor is coupled to the third via structure; The fourth conductive structure further includes a fourth conductor and a fourth pad located on the seventh surface of the second dielectric layer and coupled to each other, wherein the fourth conductor is coupled to the fourth via structure.

[0013] In some embodiments, the second projection is a square shape.

[0014] In some embodiments, the first support column has a third projection on the second surface, the third projection being fan-shaped; the first projection being circular.

[0015] In some embodiments, the second support column has the fourth projection on the second surface, the fourth projection being fan-shaped; the first projection being circular.

[0016] According to a second aspect of this application, a method for forming a pressure sensor as described in any embodiment is provided, comprising: Forming a first substrate and a second substrate; The second surface of the second substrate is bonded and fixed to the first surface of the first substrate; A first varistor is formed on the third surface of the first region; A second varistor is formed on the third surface of the second region.

[0017] The beneficial effects of this application are as follows: Based on the pressure sensor provided in the embodiments of this application, since the stress on the first region is greater than that on the second region, when the second substrate is subjected to external pressure, the first piezoresistor located in the first region outputs a larger first pressure signal, which is suitable for small-range pressure measurement; the second piezoresistor located in the second region outputs a smaller second pressure signal, which is suitable for large-range pressure measurement. Therefore, the target pressure value can be determined based on the first pressure signal when sensing small pressure, and based on the second pressure signal when sensing large pressure, thereby achieving pressure measurement of different ranges using the same sensor chip. This helps to reduce the size of the pressure sensor and meets the miniaturization requirements of multi-scenario pressure measurement and wearable devices.

[0018] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0020] Figure 1 This is a partial structural cross-sectional view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 2 This is a top view of the first substrate provided in an exemplary embodiment of this disclosure; Figure 3 yes Figure 2 Cross-sectional view at point AA'; Figure 4 This is a bottom view of the second substrate provided in an exemplary embodiment of this disclosure; Figure 5 This is a schematic diagram of the overall structure of the second substrate provided in an exemplary embodiment of this disclosure; Figure 6 yes Figure 4 Cross-sectional view at BB' in the middle; Figure 7 This is a partial structural cross-sectional view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 8 This is a partial top view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 9 This is a partial structural cross-sectional view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 10 This is a partial top view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 11 This is a partial structural cross-sectional view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 12 This is a partial structural cross-sectional view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 13 This is a top view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 14 This is a top view of the first substrate provided in an exemplary embodiment of this disclosure; Figure 15 This is a partial structural cross-sectional view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 16 This is a partial structural cross-sectional view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 17 This is a partial structural cross-sectional view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 18This is a partial top view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 19 This is a partial structural cross-sectional view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 20 This is a partial top view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 21 This is a partial structural cross-sectional view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 22 This is a top view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 23 This is a cross-sectional view of the first substrate provided in an exemplary embodiment of this disclosure; Figure 24 This is a cross-sectional view of the second substrate and the second support pillar provided in an exemplary embodiment of this disclosure; Figure 25 This is a bottom view of the second substrate and the second support column provided in an exemplary embodiment of this disclosure; Figure 26 This is a schematic diagram of the overall structure of the second substrate and the second support column provided in an exemplary embodiment of this disclosure; Figure 27 This is a partial structural cross-sectional view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 28 This is a partial structural cross-sectional view of the pressure sensor provided in an exemplary embodiment of this disclosure; Figure 29 This is a top view of a partial structure of a pressure sensor provided in an exemplary embodiment of this disclosure; Figure 30 This is a schematic flowchart illustrating a method for forming a pressure sensor provided in an exemplary embodiment of this disclosure.

[0021] Explanation of reference numerals in the attached figures: 1-First substrate; 11-First surface; 12-First groove; 2-Second substrate; 21-Second surface; 22-Third surface; 23-First region; 24-Second region; 25-Second groove; 3-Cavity; 41-First varistor; 42-Second varistor; 51-First support post; 52-Second support post; 61-First dielectric layer; 62-Second dielectric layer; 71-First via structure; 72-Second via structure; 73-First conductor; 74-First pad; 75-Second conductor; 76-Second pad; 81-Third via structure; 82-Fourth via structure; 83-Third conductor; 84-Third pad; 85-Fourth conductor; 86-Fourth pad; 91-First heavily doped conductive region; 92-Second heavily doped conductive region; DD' - Central axis; O - Geometric center; Z - First direction. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0023] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0024] In related technologies, MEMS (micro-electro-mechanical systems) piezoresistive pressure sensors can be applied to wearable devices (such as smartwatches). These pressure sensors typically employ multi-chip designs (such as dual-cavity absolute pressure chips or combinations of dual chips with different pressure ranges), but this increases size, making it difficult to meet the compact size requirements of wearable devices. Therefore, there is a need to develop a miniaturized single-chip solution capable of simultaneously measuring both small-range pressure (such as air pressure and altitude monitoring) and large-range pressure (such as water pressure detection) to adapt to diverse application scenarios.

[0025] This application provides a pressure sensor, see the following embodiment. Figure 1 As shown, the pressure sensor includes: The first substrate 1 has a first surface 11; A second substrate 2 is stacked with the first substrate 1 along the first direction Z. The second substrate 2 has a second surface 21 and a third surface 22 opposite to each other. The second surface 21 is bonded and fixed to the first surface 11, and a cavity 3 is provided between the second surface 21 and the first surface 11. The second substrate 2 includes a first region 23 and a second region 24. Under the same pressure, the deformation of the first region 23 in the first direction Z is greater than the deformation of the second region 24 in the first direction Z. The first varistor 41 is located on the third surface 22 of the first region 23. The first varistor 41 and the cavity 3 are stacked along the first direction Z. The first varistor 41 is used to output the first voltage signal. The second varistor 42 is located on the third surface 22 of the second region 24. The second varistor 42 and the cavity 3 are stacked along the first direction Z. The second varistor 42 is used to output the second voltage signal.

[0026] In some embodiments, the pressure sensor and the control module (IC chip) are coupled together. A first voltage signal and a second voltage signal are output to the control module. The control module calculates and analyzes the first voltage signal or the second voltage signal to obtain the target pressure value, which is used as the final measurement result of the pressure sensor.

[0027] Because the stress on the first zone 23 is greater than that on the second zone 24, when subjected to external pressure (stress), the first pressure-sensitive resistor 41 located in the first zone 23 is in a high-stress state. The first pressure signal output by the first pressure-sensitive resistor 41 is relatively large, suitable for small-range pressure measurement. That is, when sensing a small pressure, the first pressure signal is converted into a target pressure value, which is used as the final measurement result of the pressure sensor. The second pressure-sensitive resistor 42 is in a low-stress state, and the second pressure signal output by the second pressure-sensitive resistor 42 is relatively small, suitable for large-range pressure measurement. That is, when sensing a large pressure, the second pressure signal is converted into a target pressure value, which is used as the final measurement result of the pressure sensor. It should be noted that when subjected to external pressure (stress), the first pressure-sensitive resistor 41 outputs a first voltage signal to the control module, and simultaneously, the second pressure-sensitive resistor 42 outputs a second voltage signal to the control module. The control module then determines which voltage signal's calculation result to use as the target pressure value.

[0028] Specifically, the control module receives and analyzes a first voltage signal, calculates a first pressure value, and if the first pressure value meets a preset small-range pressure interval, it is used as the target pressure value acquired by the pressure sensor. If the first pressure value does not meet the preset small-range pressure interval, the control module receives and analyzes a second voltage signal, calculates a second pressure value, and uses the second pressure value as the target pressure value acquired by the pressure sensor. In other embodiments, the control module may also preferentially calculate the second pressure value using the second voltage signal, detect whether the second pressure value meets a preset large-range pressure interval, and if the second pressure value meets the preset large-range pressure interval, it is used as the target pressure value acquired by the pressure sensor. If the second pressure value does not meet the preset large-range pressure interval, the first pressure value is calculated using the first voltage signal and used as the target pressure value acquired by the pressure sensor.

[0029] In some embodiments, the small-range pressure range is 50 kPa to 500 kPa; the large-range pressure range is 500 kPa to 2 MPa.

[0030] Through the above embodiments, it is possible to measure pressure values ​​of both large and small ranges using a single sensor chip, effectively reducing the size of the pressure sensor, meeting the pressure measurement needs of multiple scenarios, and simultaneously meeting the compact size requirements of wearable devices.

[0031] The pressure sensor and its manufacturing method will be explained in detail below with reference to the accompanying drawings.

[0032] Example 1 In some embodiments, see Figure 2 and Figure 3 As shown, Figure 3 yes Figure 2 In the cross-sectional view at AA', the first substrate 1 has a first groove 12 recessed relative to the first surface 11, and the projection of the first groove 12 along the first direction Z is rectangular. The material of the first substrate 1 includes silicon.

[0033] In some embodiments, see Figure 4 , Figure 5 and Figure 6 As shown, Figure 6 yes Figure 4 In the cross-sectional view at BB', the second substrate 2 has a second groove 25 recessed relative to the second surface 21. The second groove 25 has a second projection on the second surface 21, and the second projection is in the shape of a square. The material of the second substrate 2 includes silicon.

[0034] In some embodiments, see Figure 7As shown, the second surface 21 is bonded and fixed to the first surface 11, and then thinned to a suitable thickness by chemical mechanical polishing. The first groove 12 and the second groove 25 constitute the cavity 3. The portion of the second substrate 2 that overlaps with the second groove 25 along the first direction Z constitutes the second region 24. The portion of the second substrate 2 that does not overlap with the second groove 25 along the first direction Z and overlaps with the first groove 12 along the first direction Z constitutes the first region 23. It should be noted that the first region 23 does not include the central region of the second substrate 2 (i.e., the region surrounded by the second groove 25).

[0035] Under the same pressure, the deformation of the first region (23) in the first direction (Z) is greater than that of the second region (24) in the first direction (Z).

[0036] In some embodiments, see Figure 1 and Figure 8 As shown, Figure 1 yes Figure 8 In the cross-sectional view at CC', a first varistor 41 and a second varistor 42 are formed on the third surface 22 by diffusion or ion implantation. Furthermore, a first heavily doped conductive region 91 (not shown) coupled to the first varistor 41 and a second heavily doped conductive region 92 (not shown) coupled to the second varistor 42 can be formed simultaneously.

[0037] The first varistor 41 and the first heavily doped conductive region 91 are integrally formed and disposed in the same layer. The doping concentrations of the first varistor 41 and the first heavily doped conductive region 91 are different, therefore their resistance values ​​are different. The second varistor 42 and the second heavily doped conductive region 92 are integrally formed and disposed in the same layer. The doping concentrations of the second varistor 42 and the second heavily doped conductive region 92 are different, therefore their resistance values ​​are different. The first heavily doped conductive region 91 is used to increase the contact area of ​​the first varistor 41, and the second heavily doped conductive region 92 is used to increase the contact area of ​​the second varistor 42, in order to facilitate the extraction of voltage signals.

[0038] In some embodiments, see Figure 1 As shown, the thickness of the second substrate 2 at the location of the first varistor 41 is greater than the thickness of the second substrate 2 at the location of the second varistor 42, where the thickness refers to the dimension of the second substrate 2 in the first direction Z.

[0039] In some embodiments, see Figure 1 and Figure 8As shown, the second groove 25 is located in the second region 24; the first groove 12 has a first projection on the second surface 21, and the second groove 25 has a second projection on the second surface 21, with the second projection within the range of the first projection; the first varistor 41 has a fifth projection on the second surface 21, which does not overlap with the second projection, and the fifth projection is within the range of the first projection; the second varistor 42 has a sixth projection on the second surface 21, with the sixth projection within the range of the second projection; the first region 23 surrounds the second region 24; the first voltage signal is greater than the second voltage signal.

[0040] In the above embodiment, a U-shaped second groove 25 is formed on the second surface 21, thereby dividing the second substrate 2 into regions of different thicknesses: the portion directly opposite the second groove 25 is thinner and is designated as the second region 24; the portion outside the second groove 25 but within the first groove 12 is thicker and is designated as the first region 23. A first piezoresistive resistor 41 is disposed on the third surface 22 of the first region 23, and a second piezoresistive resistor 42 is disposed on the third surface 22 of the second region 24. The second substrate 2 serves as the "sensitive membrane structure" in the pressure sensor. Due to the fixed support constraint at the edge of the second substrate 2, a significant stress concentration effect occurs at the edge under pressure, causing the first piezoresistive resistor 41 to always be in a high stress state, resulting in a larger first voltage signal output by the first piezoresistive resistor 41. Simultaneously, the second piezoresistive resistor 42 is in a lower stress state because the stress is dispersed by the second groove 25, resulting in a smaller second voltage signal output by the second piezoresistive resistor 42. The thickness of the second substrate 2 is determined by the pressure range.

[0041] In some embodiments, see Figure 9 and Figure 10 As shown, it should be noted that in Figure 10 For ease of illustration, the first dielectric layer 61 is omitted. A first dielectric layer 61 is grown on the third surface 22 of the second substrate 2. The material of the first dielectric layer 61 includes silicon oxide, silicon nitride, and a silicon oxide-silicon nitride composite. Through-holes are etched on the first dielectric layer 61, penetrating the first dielectric layer 61 along a first direction Z. The through-holes and a first heavily doped conductive region 91 are stacked along the first direction Z, and the through-holes and a second heavily doped conductive region 92 are stacked along the first direction Z. A first via structure 71 is formed in the through-hole corresponding to the first heavily doped conductive region 91. A first varistor 41 is coupled to the first heavily doped conductive region 91, and the first heavily doped conductive region 91 is coupled to the first via structure 71. A second via structure 72 is formed in the through-hole corresponding to the second heavily doped conductive region 92. A second varistor 42 is coupled to the second heavily doped conductive region 92, and the second heavily doped conductive region 92 is coupled to the second via structure 72. The first via structure 71 constitutes a first conductive structure. The second via structure 72 constitutes a second conductive structure.

[0042] In some embodiments, see Figure 9 and Figure 10 As shown, the first dielectric layer 61 includes a fourth surface and a fifth surface, the fourth surface being connected to the third surface 22. A first conductive structure and a second conductive structure are further formed on the surface of the first dielectric layer 61. The first conductive structure further includes a first conductor 73 and a first pad 74 located on the fifth surface of the first dielectric layer 61 and coupled to each other, the first conductor 73 being coupled to a first via structure 71. The second conductive structure further includes a second conductor 75 and a second pad 76 located on the fifth surface of the first dielectric layer 61 and coupled to each other, the second conductor 75 being coupled to a second via structure 72. Multiple first varistors 41 are interconnected through the first conductor 73, forming a Wheatstone bridge. Multiple second varistors 42 are interconnected through the second conductor 75, forming a Wheatstone bridge. The first conductor 73 and the first pad 74 are made of aluminum. The second conductor 75 and the second pad 76 are made of aluminum.

[0043] In some embodiments, see Figure 11 As shown, a second dielectric layer 62 is formed on the surface of the first dielectric layer 61, a first conductive structure is located between the first dielectric layer 61 and the second dielectric layer 62, and a second conductive structure is located between the first dielectric layer 61 and the second dielectric layer 62.

[0044] In some embodiments, see Figure 12 and Figure 13 As shown, vias are etched on the second dielectric layer 62, penetrating the second dielectric layer 62 along the first direction Z. The vias and the first pad 74 are stacked along the first direction Z, and the vias and the second pad 76 are also stacked along the first direction Z. A third via structure 81 is formed in the via corresponding to the first pad 74, and the third via structure 81 is coupled to the first pad 74. A fourth via structure 82 is formed in the via corresponding to the second pad 76, and the fourth via structure 82 is coupled to the second pad 76. The third via structure 81 constitutes a third conductive structure. The fourth via structure 82 constitutes a fourth conductive structure. The material of the second dielectric layer 62 includes silicon oxide, silicon nitride, and a silicon nitride-silicon oxide composite. After forming the second dielectric layer 62, the surface of the second dielectric layer 62 can be chemically and mechanically polished to smooth the surface and avoid surface undulations caused by the presence of the first and second conductive structures.

[0045] In some embodiments, see Figure 12 and Figure 13As shown, the second dielectric layer 62 includes a sixth surface and a seventh surface, with the sixth surface connected to the fifth surface of the first dielectric layer 61. A third conductive structure and a fourth conductive structure are further formed on the surface of the second dielectric layer 62. The third conductive structure further includes a third conductor 83 and a third pad 84 located on the seventh surface of the second dielectric layer 62 and coupled to each other; the third conductor 83 is coupled to a third via structure 81. The fourth conductive structure further includes a fourth conductor 85 and a fourth pad 86 located on the seventh surface of the second dielectric layer 62 and coupled to each other; the fourth conductor 85 is coupled to a fourth via structure 82. The material of the third conductor 83 and the third pad 84 includes aluminum. The material of the fourth conductor 85 and the fourth pad 86 includes aluminum. The third pad 84 is coupled to a control module. The fourth pad 86 is coupled to a control module.

[0046] In some embodiments, a first voltage signal is transmitted to the control module through a first heavily doped conductive region 91, a first via structure 71, a first conductor 73, a first pad 74, a third via structure 81, and a third pad 84. A second voltage signal is transmitted to the control module through a second heavily doped conductive region 92, a second via structure 72, a second conductor 75, a second pad 76, a fourth via structure 82, and a fourth pad 86.

[0047] Through the above embodiments, the use of a two-layer wiring structure (the first conductor 73 and the second conductor 75 are the first layer of wiring, and the third conductor 83 and the fourth conductor 85 are the second layer of wiring) avoids the problem of cross-short circuit between the first voltage signal and the second voltage signal.

[0048] In some embodiments, see Figure 13 As shown, the first projection has a central axis DD', which is also the central axis of the third surface 22; the third pad 84 and the fourth pad 86 are located on opposite sides of the central axis DD'. This embodiment makes it easier for the control module to distinguish voltage signals from two different transmission paths.

[0049] Example 2 In some embodiments, see Figure 14 and Figure 15 As shown, Figure 15 yes Figure 14In the cross-sectional view at EE', the first substrate 1 has a first groove 12 recessed relative to the first surface 11, and a plurality of first support pillars 51 (four first support pillars 51 are provided in this embodiment) are provided in the first groove 12. The first support pillars 51 are located in the first groove 12, one end of the first support pillar 51 is coupled to the bottom of the first groove 12, and the other end is coupled to the second surface 21. The first groove 12 has a geometric center O, which is the center of the projection of the first groove 12 along the first direction Z. The plurality of first support pillars 51 are centrally symmetrical about the geometric center O. The first surface 11 has a central axis EE', and the plurality of first support pillars 51 are axially symmetrical about the central axis EE'.

[0050] In some embodiments, the first substrate 1 has a first groove 12 recessed relative to the first surface 11, and the first surface 11 and the second surface 21 are bonded and fixed together. Figure 16 In the structure shown, the first groove 12 forms the cavity 3. The top end of the first support column 51 is coupled to the second substrate 2.

[0051] In some embodiments, see Figure 17 and Figure 18 As shown, on the third surface 22, a first varistor 41 and a second varistor 42 are formed by diffusion or ion implantation. Furthermore, a first heavily doped conductive region 91 (not shown) coupled to the first varistor 41 and a second heavily doped conductive region 92 (not shown) coupled to the second varistor 42 can be formed simultaneously. The first varistor 41 and the first heavily doped conductive region 91 are integrally formed and disposed in the same layer. The doping concentrations of the first varistor 41 and the first heavily doped conductive region 91 are different, therefore their resistance values ​​are different. The second varistor 42 and the second heavily doped conductive region 92 are integrally formed and disposed in the same layer. The doping concentrations of the second varistor 42 and the second heavily doped conductive region 92 are different, therefore their resistance values ​​are different. The first heavily doped conductive region 91 is used to increase the contact area of ​​the first varistor 41, and the second heavily doped conductive region 92 is used to increase the contact area of ​​the second varistor 42, in order to facilitate the extraction of voltage signals.

[0052] In some embodiments, see Figure 17 and Figure 18 As shown, Figure 17 yes Figure 18In the cross-sectional view corresponding to FF', the first support column 51 is located between the first region 23 and the second region 24, with one end of the first support column 51 coupled to the bottom of the first groove 12 and the other end coupled to the second surface 21. Thus, the first support column 51 provides local support for the second substrate. When the second substrate is deformed under pressure, the inner region enclosed by the multiple first support columns 51 experiences significant stress concentration, and the first varistor 41 located in this region is under high stress, resulting in a larger output signal. Conversely, the region outside the first support columns 51 has greater overall stiffness, smaller deformation, and relatively lower stress, leading to a smaller output signal from the second varistor 42 located in this region. Therefore, in this embodiment, the inner region enclosed by the multiple first support columns 51 is the first region 23, and the region outside the first support columns 51 is the second region 24. The first groove 12 has a first projection on the second surface 21, the first varistor 41 has a seventh projection on the second surface 21, the seventh projection is within the range of the first projection, the second varistor 42 has a projection on the second surface 21 within the range of the first projection, the first region 23 is within the range of the first projection, the second region 24 is within the range of the first projection; the first voltage signal is greater than the second voltage signal.

[0053] In some embodiments, see Figure 18 As shown, the first support column 51 has a third projection on the second surface 21, which is a fan-shaped projection; the first projection is a circle.

[0054] In the above embodiment, four first support pillars 51 are provided in the cavity 3, and the first support pillars 51 are bonded to the second surface 21 of the second substrate 2 to form a fixed support. At this time, the second substrate 2 is fixed in the following ways: edge fixed support and partial fixed support of the second surface 21. A first varistor 41 is provided in the first region 23, and a second varistor 42 is provided in the second region 24. When the second substrate 2 is deformed by pressure, due to the stress concentration effect of the local fixed support structure, the first region 23 surrounded by the arc-shaped first support pillars 51 produces a large curvature change, and the first varistor 41 is in a high stress state and outputs a large first voltage signal; while the second region 24 located outside the first support pillars 51 has a larger overall stiffness and smaller deformation, and the second varistor 42 is in a low stress state and outputs a smaller second voltage signal.

[0055] In some embodiments, see Figure 19 and Figure 20 As shown, it should be noted that in Figure 20For ease of illustration, the first dielectric layer 61 is omitted. A first dielectric layer 61 is grown on the third surface 22 of the second substrate 2. The material of the first dielectric layer 61 includes silicon oxide, silicon nitride, and a silicon oxide-silicon nitride composite. Through-holes are etched on the first dielectric layer 61, penetrating the first dielectric layer 61 along a first direction Z. The through-holes and a first heavily doped conductive region 91 are stacked along the first direction Z, and the through-holes and a second heavily doped conductive region 92 are stacked along the first direction Z. A first via structure 71 is formed in the through-hole corresponding to the first heavily doped conductive region 91. A first varistor 41 is coupled to the first heavily doped conductive region 91, and the first heavily doped conductive region 91 is coupled to the first via structure 71. A second via structure 72 is formed in the through-hole corresponding to the second heavily doped conductive region 92. A second varistor 42 is coupled to the second heavily doped conductive region 92, and the second heavily doped conductive region 92 is coupled to the second via structure 72. The first via structure 71 constitutes a first conductive structure. The second via structure 72 constitutes a second conductive structure.

[0056] In some embodiments, see Figure 21 and Figure 22 As shown, a second dielectric layer 62 is formed on the surface of the first dielectric layer 61. A first conductive structure is located between the first dielectric layer 61 and the second dielectric layer 62, and a second conductive structure is located between the first dielectric layer 61 and the second dielectric layer 62. Through-holes are etched on the second dielectric layer 62, penetrating the second dielectric layer 62 along a first direction Z. The through-holes and a first pad 74 are stacked along the first direction Z, and the through-holes and a second pad 76 are stacked along the first direction Z. A third via structure 81 is formed in the through-hole corresponding to the first pad 74, and the third via structure 81 is coupled to the first pad 74. A fourth via structure 82 is formed in the through-hole corresponding to the second pad 76, and the fourth via structure 82 is coupled to the second pad 76. The third via structure 81 constitutes the third conductive structure. The fourth via structure 82 constitutes the fourth conductive structure.

[0057] In some embodiments, see Figure 21 and Figure 22 As shown, a third conductive structure and a fourth conductive structure are further formed on the surface of the second dielectric layer 62. The third conductive structure further includes a third conductor 83 and a third pad 84 located on the surface of the second dielectric layer 62 and coupled to each other. The third conductor 83 is coupled to the third via structure 81. The fourth conductive structure further includes a fourth conductor 85 and a fourth pad 86 located on the surface of the second dielectric layer 62 and coupled to each other. The fourth conductor 85 is coupled to the fourth via structure 82. The material of the third conductor 83 and the third pad 84 includes aluminum. The material of the fourth conductor 85 and the fourth pad 86 includes aluminum. The third pad 84 is coupled to the control module. The fourth pad 86 is coupled to the control module.

[0058] In some embodiments, see Figure 22 As shown, the third pad 84 and the fourth pad 86 are located on opposite sides of the central axis DD'.

[0059] Example 3 In some embodiments, see Figure 23 As shown, the first substrate 1 has a first groove 12 recessed relative to the first surface 11, and the projection of the first groove 12 along the first direction Z is circular.

[0060] In some embodiments, see Figure 24 , Figure 25 and Figure 26 As shown, the second substrate 2 has a second surface 21 and a third surface 22 facing each other, and a plurality of second support pillars 52 (four second support pillars 52 are provided in this embodiment) are on the second surface 21. One end of the second support pillar 52 is coupled to the second surface 21. The projection of the second substrate 2 along the first direction Z is circular.

[0061] In some embodiments, see Figure 25 As shown, the second surface 21 has a geometric center O, and the plurality of second support columns 52 are centrally symmetrical about the geometric center O. The geometric center O is the center of the circle of the second surface 21.

[0062] In some embodiments, the second surface 21 is bonded and fixed to the first surface 11, and thinned to a suitable thickness by chemical mechanical polishing, with the first groove 12 forming the cavity 3, resulting in the following... Figure 27 The structure shown is as follows. The second support column 52 is located in the cavity 3. One end of the second support column 52 is coupled to the second surface 21, and the other end is spaced apart from the bottom of the first groove 12.

[0063] In some embodiments, see Figure 27 As shown, the second support column 52 is located between the first region 23 and the second region 24, dividing the second substrate 2 into the first region 23 and the second region 24. Since the region located outside the second support column 52 is closer to the edge support, the outer region is more prone to forming larger bending stress when the second substrate is deformed under pressure. In contrast, the stress distribution of the inner region enclosed by the second support column 52 changes due to the influence of the local protrusion structure, resulting in a smaller local strain than the outer region. Therefore, in this embodiment, the inner region enclosed by the second support column 52 is the second region 24, and the region located outside the second support column 52 and within the range of the first groove 12 is the first region 23.

[0064] In some embodiments, see Figure 28 and Figure 29 As shown, Figure 28 yes Figure 29A cross-sectional view at point GG' shows that on the third surface 22, a first varistor 41 and a second varistor 42 are formed by diffusion or ion implantation. A first groove 12 has a first projection on the second surface 21. The projections of the first varistor 41 and the second varistor 42 on the second surface 21 are within the range of the first projection. A first region 23 and a second region 24 are also within the range of the first projection. The first voltage signal is greater than the second voltage signal.

[0065] In some embodiments, see Figure 26 , Figure 29 As shown, the second support column 52 has a fourth projection on the second surface 21, which is a fan-shaped projection; the first projection is a circle.

[0066] Through the above embodiments, when the second substrate 2 is deformed under pressure, the outer first region 23 forms a stress concentration area due to edge constraints, and the first varistor 41 outputs a larger first voltage signal; the inner second region 24 is affected by the mass load of the second support column 52 and stress shunting, the strain of the second region 24 is smaller, and the second varistor 42 outputs a smaller second voltage signal.

[0067] In some embodiments, the first voltage signal is transmitted to the control module through the first heavily doped conductive region 91, the first via structure 71, the first conductor 73, the first pad 74, the third via structure 81, and the third pad 84. The second voltage signal is transmitted to the control module through the second heavily doped conductive region 92, the second via structure 72, the second conductor 75, the second pad 76, the fourth via structure 82, and the fourth pad 86. Specific implementation methods can be found in Embodiments 1 and 2, and will not be elaborated upon here.

[0068] This application provides a method for forming a pressure sensor as described in any of the above embodiments. (See attached document.) Figure 30 As shown, it includes: S101: Form the first substrate 1 and the second substrate 2; S102: Bond and fix the second surface 21 of the second substrate 2 to the first surface 11 of the first substrate 1; S103: A first varistor 41 is formed on the third surface 22 of the first region 23; S104: A second varistor 42 is formed on the third surface 22 of the second region 24.

[0069] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0070] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0071] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0072] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A pressure sensor, characterized in that, include: The first substrate (1) has a first surface (11); A second substrate (2) is stacked with the first substrate (1) along a first direction (Z). The second substrate (2) has a second surface (21) and a third surface (22) opposite to each other. The second surface (21) is bonded to the first surface (11). A cavity (3) is provided between the second surface (21) and the first surface (11). The second substrate (2) includes a first region (23) and a second region (24). The stress on the first region (23) is greater than the stress on the second region (24). The first varistor (41) is located on the third surface (22) of the first region (23). The first varistor (41) and the cavity (3) are stacked along the first direction (Z). The first varistor (41) is used to output a first voltage signal. The second varistor (42) is located on the third surface (22) of the second region (24). The second varistor (42) and the cavity (3) are stacked along the first direction (Z). The second varistor (42) is used to output a second voltage signal.

2. The pressure sensor according to claim 1, characterized in that, The first substrate (1) has a first groove (12) recessed relative to the first surface (11), and the second substrate (2) has a second groove (25) recessed relative to the second surface (21). The first groove (12) and the second groove (25) constitute the cavity (3). The second groove (25) is located in the second region (24); The first groove (12) has a first projection on the second surface (21), and the second groove (25) has a second projection on the second surface (21), the second projection being within the range of the first projection; The first varistor (41) has a fifth projection on the second surface (21), the fifth projection being within the range of the first projection, and the fifth projection not overlapping with the second projection; The second varistor (42) has a sixth projection on the second surface (21), the sixth projection being within the range of the second projection; The first region (23) surrounds the second region (24); The first voltage signal is greater than the second voltage signal.

3. The pressure sensor according to claim 1, characterized in that, The first substrate (1) has a first groove (12) recessed relative to the first surface (11), the first groove (12) forming the cavity (3); the pressure sensor further includes: Multiple first support columns (51) are located in the first groove. One end of the first support column is coupled to the bottom of the first groove, and the other end is coupled to the second surface (21). The first groove (12) has a geometric center (O), and a plurality of the first support columns (51) are centrally symmetrical about the geometric center (O). The first support columns (51) are located between the first region (23) and the second region (24). The first groove (12) has a first projection on the second surface (21), the first piezoresistor (41) has a seventh projection on the second surface (21), the seventh projection is within the range of the first projection, the first area (23) is within the range of the first projection, and the second area (24) is within the range of the first projection. The first voltage signal is greater than the second voltage signal.

4. The pressure sensor according to claim 1, characterized in that, The first substrate (1) has a first groove (12) recessed relative to the first surface (11), the first groove (12) forming the cavity (3); the pressure sensor further includes: A plurality of second support columns (52) are located in the first groove (12), one end of the second support column (52) is coupled to the second surface (21), and the other end is spaced from the bottom of the first groove; The second surface (21) has a geometric center (O), and a plurality of second support columns (52) are centrally symmetrical about the geometric center (O), with the second support columns (52) located between the first region (23) and the second region (24); The first groove (12) has a first projection on the second surface (21), the first piezoresistor (41) has an eighth projection on the second surface (21), the eighth projection is within the range of the first projection, the first area (23) is within the range of the first projection, and the second area (24) is within the range of the first projection. The first voltage signal is greater than the second voltage signal.

5. The pressure sensor according to any one of claims 1 to 4, characterized in that, Also includes: A first dielectric layer (61) located on the third surface (22) includes a fourth surface and a fifth surface, the fourth surface being connected to the third surface (22); The first conductive structure includes a first via structure (71) penetrating the first dielectric layer (61), and the first via structure (71) is coupled to the first varistor (41). The second conductive structure includes a second via structure (72) penetrating the first dielectric layer (61), and the second via structure (72) is coupled to the second varistor (42).

6. The pressure sensor according to claim 5, characterized in that, The first conductive structure further includes: a first conductor (73) and a first pad (74) located on the fifth surface of the first dielectric layer (61) and coupled to each other, wherein the first conductor (73) is coupled to the first via structure (71); The second conductive structure further includes a second conductor (75) and a second pad (76) located on the fifth surface of the first dielectric layer (61) and coupled to each other, wherein the second conductor (75) is coupled to the second via structure (72).

7. The pressure sensor according to claim 6, characterized in that, Also includes: A second dielectric layer (62) located on the fifth surface of the first dielectric layer (61), the second dielectric layer (62) including a sixth surface and a seventh surface, the sixth surface being connected to the fifth surface of the first dielectric layer (61); The third conductive structure includes a third via structure (81) penetrating the second dielectric layer (62), the third via structure (81) being coupled to the first pad (74); The fourth conductive structure includes a fourth via structure (82) penetrating the second dielectric layer (62) and coupled to the second pad (76).

8. The pressure sensor according to claim 7, characterized in that, The third conductive structure further includes a third conductor (83) and a third pad (84) located on the seventh surface of the second dielectric layer (62) and coupled to each other, wherein the third conductor (83) is coupled to the third via structure (81); The fourth conductive structure further includes a fourth conductor (85) and a fourth pad (86) located on the seventh surface of the second dielectric layer (62) and coupled to each other, wherein the fourth conductor (85) is coupled to the fourth via structure (82).

9. The pressure sensor according to claim 2, characterized in that, The second projection is a square shape.

10. The pressure sensor according to claim 3, characterized in that, The first support column (51) has a third projection on the second surface (21), the third projection being fan-shaped; the first projection being circular.

11. The pressure sensor according to claim 4, characterized in that, The second support column (52) has a fourth projection on the second surface (21), the fourth projection being fan-shaped; the first projection being circular.

12. A method for forming a pressure sensor as described in any one of claims 1 to 11, characterized in that, include: Forming a first substrate (1) and a second substrate (2); The second surface (21) of the second substrate (2) is bonded and fixed to the first surface (11) of the first substrate (1); A first varistor (41) is formed on the third surface (22) of the first region (23); A second varistor (42) is formed on the third surface (22) of the second region (24).

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