An integrated control module, IO interface circuit and controller

Abstract

The application discloses an integrated control module, an IO interface circuit and a controller, wherein the integrated control module is configured to build a closed-loop control system in an analog domain, convert an electrical signal input by an IO interface into an analog input waveform by using a waveform encoder, synthesize the analog input waveform into a periodic time-division multiplexing analog input signal wave by using an input waveform multiplexer driven by a time sequence controller, generate an isomorphic analog setting signal wave by setting a waveform generator, directly analog subtract two waveforms by using a differential amplifier to obtain an analog differential signal wave, separate the analog differential signal wave into independent pulse error signals of each channel by using a synchronous demodulation and distribution unit in combination with a sample and hold circuit, and finally generate a driving signal by an analog PID controller. The application solves the problems of the synchronism and the integration of multi-loop control by using a unique analog domain time-division multiplexing and demodulation architecture, and provides a new hardware solution for high-performance real-time control.

Description

Technical Field

[0001] This invention relates to the field of industrial automation control technology, and more specifically, to an integrated control module, an I / O interface circuit, and a controller. Background Technology

[0002] In existing industrial control systems, such as programmable logic controllers (PLCs) and distributed control systems (DCSs), a discrete control architecture is commonly used. That is, each controlled physical quantity, such as temperature, humidity, pressure, or actuators such as compressors and fans, usually corresponds to an independent input / output I / O channel and an independent control algorithm. The central processing unit processes the signals of each channel sequentially in a polling or interrupt manner.

[0003] This traditional architecture has the following inherent drawbacks: poor synchronization, as it uses sequential polling, the sampling and control output times of different channels differ, making true synchronization difficult. For strongly coupled multivariable systems, this asynchrony can affect control quality and system stability; complex architecture, with numerous independent I / O channels and corresponding control loops leading to complex system wiring, high hardware costs, and limited scalability; and difficulty in collaborative optimization, as each control loop is relatively independent, making it difficult to achieve coordinated action and energy efficiency optimization of multiple actuators at the system level.

[0004] Therefore, there is an urgent need in this field for a new controller architecture that can achieve high synchronization, high integration, and easy collaborative control. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide an integrated control module, IO interface circuit and controller. By waveformizing multiple signals and performing integrated differential processing, the control architecture is simplified, sampling and control are highly synchronized, and multi-variable collaborative optimization is achieved.

[0006] To achieve the above objectives, the present invention provides the following technical solution: In one aspect, the present invention provides an integrated control module. In this technical solution, the integrated control module includes an analog differential calculation unit, a synchronous demodulation and distribution unit, N signal holding and control units, and N output terminals. In this technical solution, the analog differential calculation unit includes a timing controller, an input waveform multiplexer, a set waveform generator, a set waveform multiplexer, and a differential amplifier. The timing controller generates a system master clock with a period of T and selection signals for N time slots. The multiplexer's input terminals are connected to multiple analog input waveforms from the IO interface circuit, and its selection control terminal is connected to the timing controller. Under the control of the selection signals, it synthesizes the multiple analog input waveforms from the IO interface circuit into the analog input signal wave. The control terminal of the set waveform generator is connected to a user-defined value, and its output terminal generates an analog set waveform with the same waveform encoding format as the IO interface circuit. The waveform multiplexer is configured to receive an analog input signal wave with period T from at least one I / O interface circuit, and simultaneously receive an internally generated analog setting signal wave with the same period T and waveform encoding format. The analog input signal wave and the analog setting signal wave are directly subtracted by the differential amplifier to obtain and output an analog differential signal wave with the same period T.

[0007] In the technical solution of this invention, the synchronous demodulation and distribution unit is connected to the analog differential calculation unit. The synchronous demodulation and distribution unit includes an analog multiplexer. A single input terminal of the analog multiplexer is connected to the output of the differential amplifier. The N output terminals of the analog multiplexer correspond to N independent output channels. The selection control terminal of the analog multiplexer is connected to the timing controller. The synchronous demodulation and distribution unit is configured to: based on the gating signal generated by the timing controller, treat the analog differential signal wave as a waveform composed of N time-slot signals in chronological order. The composite signal wave is demodulated from the composite wave in each time slot by the analog multiplexer and routed to the output channel uniquely corresponding to that time slot, thereby completing the demodulation and distribution of the analog differential signal wave. That is, the synchronous demodulation and distribution unit receives the analog differential signal wave and, based on the condition of being synchronized with the timing signal with period T used to generate the analog differential signal wave, demodulates the analog differential signal wave into N independent pulse error signals, and distributes the N pulse error signals to N independent output channels in time sequence. In the technical solution of this invention, the signal holding and control unit includes a sample-and-hold circuit and an analog PID controller. The input terminal of the sample-and-hold circuit is connected to one output terminal of the analog multiplexer, and the control terminal of the sample-and-hold circuit is connected to a gating signal generated by the timing controller for sampling and holding the pulse error signal within a time slot. The input terminal of the analog PID controller is connected to the output terminal of the sample-and-hold circuit, and the output terminal of the analog PID controller is used to output a continuous control voltage or current. Each signal holding and control unit is connected to one output channel of the synchronous demodulation and distribution unit and is configured to convert the distributed pulse error signal into a continuous signal and generate a control signal for driving the actuator based on the continuous signal. Another aspect of this invention provides an I / O interface circuit for implementing the integrated control module described above. The I / O interface circuit includes N I / O interface channels, each I / O interface channel including a physical interface and a corresponding waveform encoder. The waveform encoder is connected to its corresponding physical interface for converting the electrical signal input through the physical interface into an analog input waveform. The waveform encoder is a voltage-controlled oscillator or a precision voltage source, and its output waveform is a sine wave, square wave, or DC voltage.

[0008] The present invention also provides a controller, which includes an IO interface circuit as described above, an integrated control module, and N actuator drive circuits, wherein the N actuator drive circuits are respectively connected to the N output terminals of the integrated control module for amplifying control signals to drive actuators.

[0009] Beneficial Effects: In summary, this invention provides an integrated control module, I / O interface circuit, and controller. By constructing a novel control architecture based on direct differential and synchronous demodulation of analog waveforms, this invention effectively avoids the inherent delays caused by sampling, quantization, and program execution in traditional digital control, thereby improving the system's response speed and control accuracy. Simultaneously, a high-precision timing synchronization mechanism ensures strict synchronization of sampling and updates across all control loops. Furthermore, the highly integrated waveform signal stream processing method of this invention combines multiple signal transmissions and processing into one, greatly simplifying system wiring and reducing hardware complexity and cost. In conclusion, this invention provides a novel solution for the field of high-performance integrated control.

[0010] Other features and advantages of the present invention will be set forth in the following description. Attached Figure Description

[0011] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of an integrated control module according to an embodiment of the present invention; Figure 2 This is a schematic diagram of an I / O interface circuit according to an embodiment of the present invention;

[0013] Figure 3 This is a schematic diagram of a time-division multiplexed analog input waveform according to an embodiment of the present invention. Detailed Implementation

[0014] The present invention will now be described with reference to specific embodiments. It should be noted that the embodiments described below are examples of the present invention and are only used to illustrate the invention, not to limit it. Other combinations and various modifications within the scope of the present invention can be made without departing from its spirit or scope. This embodiment provides, in one aspect, an integrated control module. Figure 1 This is a schematic diagram of an integrated control module according to an embodiment of the present invention, such as... Figure 1 As shown, in this embodiment, the integrated control module includes an analog differential calculation unit, a synchronous demodulation and distribution unit, N signal holding and control units, and N output terminals.

[0015] Specifically, in this embodiment, the analog differential calculation unit includes a timing controller, an input waveform multiplexer, a setting waveform generator, a setting waveform multiplexer, and a differential amplifier. The timing controller generates a system master clock with a period of T and gating signals for N time slots. The multiplexer's input terminals are connected to multiple analog input waveforms from the I / O interface circuit, and its selection control terminal is connected to the timing controller to synthesize the multiple analog input waveforms from the I / O interface circuit into an analog input signal wave under the control of the gating signals. The setting waveform generator's control terminal is connected to a user-defined value, and its output terminal generates an analog setting waveform with the same waveform encoding format as the I / O interface circuit. The input terminal of the waveform multiplexer is connected to the output of the waveform generator, and the selection control terminal of the waveform multiplexer is connected to the timing controller to generate an analog setting signal wave. The non-inverting input terminal of the differential amplifier is connected to the output of the waveform multiplexer, and the inverting input terminal of the differential amplifier is connected to the output of the input waveform multiplexer. That is, the analog differential calculation unit is configured to receive an analog input signal wave with a period of T from at least one IO interface circuit, and simultaneously receive an internally generated analog setting signal wave with the same period T and the same waveform encoding format. The analog input signal wave and the analog setting signal wave are directly subtracted by the differential amplifier to obtain and output an analog differential signal wave with the same period T.

[0016] The task of the analog differential calculation unit is to generate a time-division multiplexed analog differential signal wave containing control error information from all channels. Its working principle is as follows: it is uniformly commanded by a high-precision timing controller. Figure 3 This is a schematic diagram of a time-division multiplexed analog input waveform according to an embodiment of the present invention, as shown below. Figure 3 As shown, the timing controller generates a master clock signal with a period of T, and divides each period T into N consecutive and non-overlapping time slots. For an example, please refer to [link / reference]. Figure 3 The circuit is divided into four time slots, A, B, C, and D, representing four I / O interface channels. The electrical signals input from each I / O interface channel have been converted into characteristic analog input waveforms (e.g., sine waves of different frequencies) by a waveform encoder (e.g., a voltage-controlled oscillator) in the I / O interface circuit. These waveforms are then fed into an input waveform multiplexer. Simultaneously, a waveform generator produces a corresponding analog set waveform based on the user's settings. At this point, under the command of the timing controller, the input waveform multiplexer selects the waveform of the first I / O interface channel (e.g., temperature data) in time slot A. Figure 3 The waveform shown is a sine wave with frequency f1. The waveform of the second IO interface channel (e.g., humidity data) selected in time slot B is, for example... Figure 3The waveform shown is a sine wave with a frequency of f2. Similarly, the waveform for the third IO interface channel is selected in time slot C, and the waveform for the fourth IO interface channel is selected in time slot D, respectively corresponding to... Figure 3 The sinusoidal waveforms shown have frequencies f3 and f4, which output a time-division multiplexed analog input signal wave with a period of T, for example... Figure 3 The waveform L1 shown also goes through the same multiplexing process to form a time-division multiplexed analog setting signal wave. Then, the analog input signal wave and the analog setting signal wave are directly fed into a high-precision, wide-bandwidth differential amplifier for analog subtraction. The output of the amplifier is the time-division multiplexed analog differential signal wave, which represents the control error of the corresponding channel in each time slot. Specifically, in this embodiment, the synchronous demodulation and distribution unit is connected to the analog differential calculation unit. The synchronous demodulation and distribution unit includes an analog multiplexer. A single input terminal of the analog multiplexer is connected to the output of the differential amplifier. The N output terminals of the analog multiplexer correspond to N independent output channels. The selection control terminal of the analog multiplexer is connected to the timing controller. The synchronous demodulation and distribution unit is configured to: based on the gating signal generated by the timing controller, regard the analog differential signal wave as a signal wave composed of N time-slot signals in time sequence, and demodulate the signal of the current time slot from the composite wave in each time slot through the analog multiplexer, and route it to the output channel uniquely corresponding to that time slot, thereby completing the demodulation and distribution of the analog differential signal wave. That is, the synchronous demodulation and distribution unit receives the analog differential signal wave, and based on the condition of maintaining synchronization with the timing signal with period T used to generate the analog differential signal wave, demodulates the analog differential signal wave into N independent pulse error signals, and distributes the N pulse error signals to the N independent output channels in time sequence.

[0017] The analog differential calculation unit outputs a multiplexed signal, which must be demodulated and isolated for independent control. The synchronous demodulation and distribution unit is designed to solve this problem. Essentially, the synchronous demodulation and distribution unit is an analog multiplexer whose control terminal is strictly synchronized with the aforementioned timing controller. When the timing controller indicates that it is currently in time slot A, the analog multiplexer connects the output of the differential amplifier (which carries the error information of the first IO interface channel) to the output terminal dedicated to the first IO interface channel. When the timing enters time slot B, it immediately switches to the output terminal of the second IO interface channel, and so on. In this way, the analog differential signal wave output by the analog differential calculation unit is completely demodulated and distributed to N independent output lines. Specifically, in this embodiment, the signal holding and control unit includes a sample-and-hold circuit and an analog PID controller. The input of the sample-and-hold circuit is connected to an output of an analog multiplexer, and the control of the sample-and-hold circuit is connected to a gating signal generated by a timing controller for sampling and holding the pulse error signal within a time slot. The input of the analog PID controller is connected to the output of the sample-and-hold circuit, and the output of the analog PID controller is used to output a continuous control voltage or current. Each signal holding and control unit is connected to an output channel of a synchronous demodulation and distribution unit and is configured to convert the distributed pulse error signal into a continuous signal and generate a control signal for driving the actuator based on the continuous signal.

[0018] In this embodiment, since the N independent output channels corresponding to the N output terminals of the analog multiplexer only have signals within their corresponding time slots, and are empty for the rest of the time (i.e., pulsed error signals), which are insufficient to drive the subsequent actuators, each output channel is equipped with a sample-and-hold circuit. This circuit rapidly samples the signal within its own time slot and holds the signal for the entire period T, thus providing a stable and continuous signal for the actuator circuit. This continuous signal is ultimately fed into an analog PID controller (composed of operational amplifiers, resistors, and capacitors), which generates a continuous control output to directly drive the actuator. This embodiment also provides an I / O interface circuit for implementing the integrated control module described above. Figure 2 This is a schematic diagram of an I / O interface circuit according to an embodiment of the present invention, such as... Figure 2 As shown, the IO interface circuit includes N IO interface channels. Each IO interface channel includes a physical interface and a corresponding waveform encoder. The waveform encoder is connected to its corresponding physical interface and is used to convert the electrical signal input through the physical interface into an analog input waveform. The waveform encoder is a voltage-controlled oscillator or a precision voltage source, and its output waveform is a sine wave, a square wave, or a DC voltage.

[0019] This embodiment also improves a controller, which includes the IO interface circuit, integrated control module, and N actuator drive circuits as described above. Please refer to [link / reference needed]. Figure 1 N actuator drive circuits are connected to the N output terminals of the integrated control module to amplify the control signals to drive the actuators.

[0020] Specifically, this embodiment also provides a specific example of a four-channel temperature and humidity controller: This controller is used to control a constant temperature and humidity chamber, and needs to control two heaters (IO interface channel 1 and IO interface channel 2) and two humidifiers (IO interface channel 3 and IO interface channel 4).

[0021] IO interface circuit: Includes four identical waveform encoders, each consisting of a voltage-controlled oscillator (VCO). Its input is connected to the analog voltage output of a high-precision temperature / humidity sensor chip (exemplarily, the SHT35 temperature / humidity sensor chip). The VCO converts the sensor voltage into a sine wave, for example, 2.5kHz for 25℃ and 3.0kHz for 30℃.

[0022] In the integrated control module, the analog differential calculation unit adopts: a timing controller: a combination of a crystal oscillator and a CD4520 binary counter to generate a square wave with a period of T=10ms, and then uses a CD4017 decimal counter / distributor to divide the 10ms period into four 2.5ms time slots, namely time slots A, B, C, and D; an input waveform multiplexer: an ADG1404 four-channel analog multiplexer is selected, with its four input terminals connected to the sine waves from the voltage-controlled oscillator for the IO interface channels respectively, and its address lines controlled by the four output terminals of the CD4017, that is, selecting different IO interface channels in sequence according to time slots A, B, C, and D;

[0023] Waveform generator setting: Four precision programmable waveform generator chips are used, each corresponding to a set value of one of the four channels. The user sets the target temperature (e.g., 26℃) via potentiometer, which will output a corresponding 2.6kHz continuous sine wave.

[0024] Setting waveform multiplexer: Also use ADG1404, its input terminal is connected to four setting waveforms, and the address control is completely synchronized with the above input waveform multiplexer;

[0025] Differential Amplifier: The AD8276 high-performance differential amplifier is used, with the gain set to 1. Its non-inverting input is connected to the output of the set waveform multiplexer, and its inverting input is connected to the output of the input waveform multiplexer.

[0026] The synchronous demodulation and distribution unit adopts:

[0027] Analog multiplexer: Select CD4052 analog multiplexer / distributor, configure it to a 1-input, 4-output distribution mode, connect its input to the output of AD8276 differential amplifier, and synchronize its address control lines with the aforementioned CD4017;

[0028] Working process: In time slot A, CD4052 connects the path to the first output terminal. At this time, the error signal output by the differential amplifier is sent to the subsequent circuit of IO interface channel 1. In time slot B, it switches to the second output terminal, and so on.

[0029] The signal holding and control unit employs: a sample-and-hold circuit: each channel uses an LF398 sample-and-hold chip, whose sampling control terminal is connected to a pulse signal generated by a timing controller and aligned with the time slot of that channel. It samples the error signal within a 2.5ms time slot and holds the error signal for the following 7.5ms; an analog PID controller: each channel uses a PID circuit composed of an OPA2171 operational amplifier. The PID parameters are determined by adjusting precision resistors and capacitors. The hold error signal output by the LF398 serves as the input to the analog PID controller, and the output of the analog PID controller is directly sent to the subsequent power amplifier circuit, i.e., the actuator drive circuit; Specific implementation: the IO interface circuit outputs changing electrical signals through four high-precision temperature / humidity sensor chips, and four voltage-controlled oscillators... The device converts the electrical signals output by the four high-precision temperature / humidity sensor chips into sine waves and sends them to the integrated control module. In the integrated control module, the timing controller cyclically selects four time slots A, B, C, and D with a period of 10ms. In time slot A, the analog input signal wave and the analog setting signal wave of IO interface channel 1 are selected and the analog setting waveform of the corresponding set value is selected. They are subtracted by a differential amplifier, and the resulting error signal is sent to the sample-and-hold circuit LF398 of IO interface channel 1 through a multiplexer. LF398 samples and holds this error signal. The analog PID controller of IO interface channel 1 calculates the control quantity based on this error signal and drives heater 1 to work. When the timing enters time slot B, it automatically switches to processing IO interface channel 2, and so on.

[0030] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. An integrated control module, characterized in that, include: An analog differential calculation unit is configured to receive an analog input signal wave with a period of T from at least one I / O interface circuit, and synchronously receive an internally generated analog setting signal wave with the same period T and waveform encoding format. The analog input signal wave and the analog setting signal wave are directly subtracted using a differential amplifier to obtain and output an analog differential signal wave with the same period T. A synchronous demodulation and distribution unit, connected to the analog differential calculation unit, is configured to receive the analog differential signal wave and, based on synchronization with the timing signal with a period of T used to generate the analog differential signal wave, demodulate the analog differential signal wave into N independent pulse error signals, and distribute the N pulse error signals to N independent output channels in chronological order. N signal holding and control units, each connected to one output channel of the synchronous demodulation and distribution unit, are configured to convert the distributed pulse error signals into continuous signals and generate control signals for driving the actuator based on these continuous signals.

2. The integrated control module according to claim 1, characterized in that, The analog differential calculation unit includes: a timing controller for generating a system master clock with a period of T and gating signals for N time slots; an input waveform multiplexer, whose multiple input terminals are connected to multiple analog input waveforms from the IO interface circuit, and whose selection control terminal is connected to the timing controller, for synthesizing the multiple analog input waveforms from the IO interface circuit into the analog input signal wave under the control of the gating signals; a setting waveform generator, whose control terminal is connected to a user-defined value, and whose output terminal generates an analog setting waveform with the same waveform encoding format as the IO interface circuit; a setting waveform multiplexer, whose input terminal is connected to the output of the setting waveform generator, and whose selection control terminal is connected to the timing controller, for generating the analog setting signal wave; and a differential amplifier, whose non-inverting input terminal is connected to the output of the setting waveform multiplexer, and whose inverting input terminal is connected to the output of the input waveform multiplexer.

3. The integrated control module according to claim 2, characterized in that, The synchronous demodulation and distribution unit includes: an analog multiplexer, whose single input terminal is connected to the output of the differential amplifier, whose N output terminals correspond to N independent output channels respectively, and whose selection control terminal is connected to the timing controller; wherein, the synchronous demodulation and distribution unit is configured to: based on the gating signal generated by the timing controller, regard the analog differential signal wave as a signal wave composed of N time-slot signals in time sequence, and through the analog multiplexer, demodulate the signal of the current time slot from the composite wave in each time slot, and route it to the output channel uniquely corresponding to that time slot, thereby completing the demodulation and distribution of the analog differential signal wave.

4. The integrated control module according to claim 3, characterized in that, The signal holding and control unit includes: a sample-and-hold circuit, whose input is connected to one output of the analog multiplexer and whose control is connected to a gating signal generated by the timing controller, for sampling and holding the pulse error signal within a time slot; and an analog PID controller, whose input is connected to the output of the sample-and-hold circuit and whose output is used to output a continuous control voltage or current.

5. An I / O interface circuit for implementing the integrated control module as described in any one of claims 1-4, characterized in that, include: N IO interface channels, each IO interface channel includes a physical interface and a corresponding waveform encoder; The waveform encoder is connected to its corresponding physical interface and is used to convert the electrical signal input through the physical interface into an analog input waveform.

6. The I / O interface circuit according to claim 5, characterized in that, The waveform encoder is a voltage-controlled oscillator or a precision voltage source, and its output waveform is a sine wave, a square wave, or a DC voltage.

7. A controller, characterized in that, include: The I / O interface circuit as described in claim 5 or 6; the integrated control module as described in any one of claims 1-4; N actuator drive circuits are connected to the N output terminals of the integrated control module, respectively, to amplify the control signals to drive the actuators.

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