A soft and hard bidirectional semantic addressing jump method

Abstract

The application discloses a soft and hard bidirectional semantic addressing jump method, belongs to the technical field of artificial intelligence data addressing and end-side storage, and is applied to the scene of artificial intelligence end-side equipment and edge computing equipment. According to the application, the semantic unit division is completed according to the minimum semantic granularity for the data to be processed, the unique mapping binding relationship between the software end logical address and the hardware end physical address is established based on the semantic unit, the one-way or bidirectional corresponding switching of the two types of addresses is realized through jump or table lookup operation, and the address one-to-one mapping alignment is kept through the semantic unit in the whole switching process and after the switching is completed. The application can cover the bidirectional addressing scene, solves the problems of asynchronous addressing, data disorder, power-off loss of mapping and high power consumption in the prior art, and improves the addressing stability of equipment.

Description

[0001] Terminology Definition In this application, all core terms are defined uniformly as follows, and those skilled in the art can clearly understand the technical boundaries of this invention based on these definitions: 1. Minimum semantic granularity: refers to the smallest data unit of the artificial intelligence data to be processed that can be divided and has complete and independent semantic information. Once divided, it cannot be further divided, otherwise the core semantic information will be lost. 2. Semantic unit partitioning: refers to the operation of dividing continuous data to be processed into multiple data semantic units with independent semantic information according to the smallest semantic granularity; 3. Software and hardware co-operation end: refers to the execution entity that works together with the software end to complete the semantic unit division operation. The splitting rules are configured by the software end, and the splitting action is executed by the hardware end. 4. Third-party processing end: refers to a coprocessing unit that is independent of the software main control system and the hardware functional chip, and is specifically used to perform semantic unit partitioning operations, including microcontrollers, coprocessors, etc. 5. Atomic jump operation: refers to an address switching operation that is indivisible, uninterruptible, and unreversible. It has only two results: jump completion or jump failure. There is no intermediate execution state. 6. One-to-one mapping alignment: This means that a software logical address uniquely corresponds to a hardware physical address, and the two form an anchoring relationship through data semantic units, without many-to-one or one-to-many mapping deviations. Technical Field

[0002] This invention relates to the fields of artificial intelligence data addressing and edge storage technology, and in particular to a software and hardware bidirectional semantic addressing jump method, which can be applied to inference data processing and data storage scenarios of artificial intelligence edge devices, edge computing devices, and smart hardware devices. Background Technology

[0003] With the rapid deployment of artificial intelligence (AI) technology, AI edge computing devices and edge devices are placing increasingly higher demands on the stability, low power consumption, and real-time performance of data addressing. Current AI data addressing solutions suffer from the following inherent technical shortcomings: 1. Incomplete coverage of addressing scenarios: Most solutions only support one-way addressing, which involves splitting data semantics on the software side and matching the physical address on the hardware side. A few solutions only support one-way mapping after semantic parsing on the hardware side. They cannot cover both software and hardware two-way semantic addressing scenarios at the same time, resulting in extremely poor compatibility and inability to adapt to the diverse inference and storage needs of AI edge devices. 2. Insufficient addressing synchronization: Existing solutions are prone to address mapping offset and mismatch between logical and physical addresses during the switching between software and hardware addresses, which can lead to disordered AI inference data, calculation errors, and even data loss. 3. Mapping relationships are easily lost after power failure: The address mapping relationships in existing solutions are mostly temporary caches. After the device loses power or the system restarts, the mapping relationships are easily lost, resulting in data that cannot be read or written normally, which seriously affects the commercial stability of artificial intelligence devices; 4. Excessive power consumption: Existing solutions require frequent address remapping and full address verification operations, resulting in high power consumption, which cannot be adapted to the large-scale commercial deployment of battery-powered AI edge devices.

[0004] To address the aforementioned shortcomings, the closest publicly disclosed technology to existing technology is the patent application "Artificial Intelligence Chip, Method for Virtual Address Translation" published by Biren Technology in February 2026. This solution only optimizes the execution efficiency of one-way translation from software virtual address to hardware physical address. It does not involve address mapping design with data semantic unit as anchor point, nor does it support reverse addressing scenarios where hardware splits semantic matching software address. It cannot solve the addressing synchronization and data out-of-order problems in bidirectional scenarios, nor can it achieve rapid recovery of mapping relationship after power failure. It still has the above four core shortcomings.

[0005] In addition, the existing addressing schemes have a narrow scope of protection and are easily circumvented by competitors by splitting the steps, changing the execution entity, or adjusting the switching method, thus failing to form comprehensive and stable patent protection. Summary of the Invention

[0006] Purpose of the invention To address the aforementioned technical deficiencies in existing technologies, the present invention aims to provide a software-hardware bidirectional semantic addressing and jumping method. This method can simultaneously cover bidirectional addressing scenarios where software-side semantic matching of hardware addresses and hardware-side semantic matching of software addresses are performed. It ensures the alignment of software and hardware addresses throughout the process, solving the core problems of asynchronous addressing, out-of-order data, loss of mapping relationship after power failure, and high device power consumption in existing technologies. Furthermore, the solution has comprehensive scenario coverage, strong anti-circumvention capabilities, and can form a complete patent protection scope. Technical solution

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A software-hardware bidirectional semantic addressing jump method, applied to inference data processing or data storage scenarios of AI edge computing devices, includes the following steps: Step S1: For the artificial intelligence reasoning data or stored data to be processed, the semantic units are divided according to the smallest semantic granularity of the data to obtain data semantic units that correspond one-to-one with the data to be processed; the execution subject of the semantic unit division can be any one of software, hardware, software-hardware co-processing or third-party processing. Step S2: Perform address mapping binding based on the data semantic unit, where each data semantic unit corresponds to a unique mapping relationship between the software-side logical address and the hardware-side physical address; Step S3: Based on the address mapping binding relationship, the one-way or two-way correspondence switching between the software-side logical address and the hardware-side physical address is realized through the address mapping jump operation or table lookup switching operation, and the switching direction is consistent with the matching direction of the address mapping binding. In step S4, during the entire address switching process and after the switching is completed, the software-side logical address and the hardware-side physical address always maintain a one-to-one mapping and alignment through the data semantic unit, and the address mapping relationship does not shift during the switching process.

[0008] Furthermore, the jump operation in step S3 is an indivisible atomic jump operation, and the jump process cannot be interrupted or rolled back.

[0009] Furthermore, in step S1, the smallest semantic granularity is the smallest data unit that can be divided from the artificial intelligence data to be processed and has complete semantic information, including any one of artificial intelligence tensor semantic units, text semantic units, and file data block semantic units.

[0010] Furthermore, the software-side logical address and the hardware-side physical address are switched through one or more virtual mapping intermediate layers. Throughout the switching process and after completion, the one-to-one mapping alignment is maintained through data semantic units.

[0011] Furthermore, the triggering conditions for the address switching operation in step S3 include any one or more combinations of data reading, data writing, address mapping update, data semantic re-splitting, artificial intelligence inference task scheduling, and address recovery after device power failure and restart.

[0012] Furthermore, after the address switching operation is completed, an end-to-end consistency check is performed on the software-side addressing result and the hardware-side addressing result. If the check fails, the address mapping binding and switching operation is re-executed.

[0013] Furthermore, the address mapping binding relationship is solidified through a unique universal identifier. After the device is powered off, the system is restarted, or cross-device transmission occurs, the mapping binding relationship can be restored, cannot be tampered with, and maintains a one-to-one correspondence with the data semantic unit. Beneficial effects

[0014] Compared with the prior art, the present invention has the following outstanding substantive features and significant progress: 1. Comprehensive coverage of two-way scenarios, filling the gaps in existing technologies: This invention covers two core addressing scenarios: "software-side semantic matching of hardware addresses" and "hardware-side semantic matching of software addresses". It is also compatible with the execution methods of third-party processing terminals and software-hardware co-processing terminals, completely filling the gaps in existing technologies and covering all scenarios of semantic addressing operations of artificial intelligence edge devices. 2. End-to-end anchoring and mapping alignment to solve addressing synchronization defects: This invention uses data semantic units as the only anchor point to ensure that the logical address on the software side and the physical address on the hardware side always maintain a one-to-one mapping alignment throughout the entire address switching process and after completion. This completely solves the core defects of existing technologies such as addressing offset, data disorder, and calculation errors, and greatly improves the stability of artificial intelligence inference and storage. 3. Fixed and recoverable mapping relationship, adaptable to commercial deployment needs: This invention uses a unique universal identification code to fix the address mapping binding relationship. After the device is powered off, restarted, or transmitted across devices, the mapping relationship can be quickly restored and cannot be tampered with, solving the industry pain point of data loss after power failure. At the same time, it does not require frequent full address remapping, which greatly reduces device power consumption and perfectly adapts to the large-scale commercial needs of artificial intelligence edge devices. 4. This invention is the first to propose a core technical solution of "establishing a unique binding between soft and hard addresses by using semantic units as anchors to achieve full alignment of bidirectional addressing". It is not a simple combination of existing unidirectional technologies, but can produce a synergistic technical effect of 1+1>2. 5. Strong anti-circumvention capabilities and complete and stable protection scope: This invention comprehensively covers all execution subjects, switching methods, triggering scenarios, and transmission paths through a high-level overview. Competitors cannot circumvent it by changing names, splitting steps, adjusting timing, or adding intermediate layers. As long as the core functions and technical effects of this invention are achieved, they fall within the protection scope of this invention. Detailed Implementation

[0015] The technical solution of the present invention will be further described in detail below with reference to specific embodiments. These embodiments are only for illustrating the present invention and are not intended to limit the scope of protection of the present invention. Those skilled in the art can directly replicate the technical solution of the present invention without creative effort based on the following embodiments.

[0016] Example 1: A one-way addressing scenario where the software side decomposes semantics and matches them to find the physical address on the hardware side. This embodiment applies to the scenario of writing inference data to storage using an AI edge camera. The specific execution steps are as follows: S101, for the face inference tensor data (AI inference data to be processed) collected by the AI ​​camera, the software side of the device (embedded operating system of the advanced simplified instruction set main control chip) performs semantic unit division; according to the minimum semantic granularity rule, the tensor data is split into complete tensor units of individual face features (if any data segment is lost after splitting, the complete semantics of the face features will be lost), and data semantic units corresponding one-to-one with each face feature are obtained; S102, the software side performs address mapping binding based on the divided data semantic units, binding a unique software side logical address (the virtual memory address of the operating system) to the hardware side physical address (the physical block address of the flash memory chip) for each facial feature semantic unit; S103, based on the above address mapping and binding relationship, through an indivisible atomic jump operation, a one-way correspondence switching from the software-side logical address to the hardware-side physical address is realized. The switching direction is consistent with the address matching direction, and the jump process cannot be interrupted. S104, throughout the entire process of the atomic jump operation and after the switch is completed, the software-side logical address and the hardware-side physical address are always aligned one-to-one through the semantic units of facial features, and the address mapping relationship does not shift during the jump process; S105 After the jump is completed, an end-to-end consistency check is performed on the software addressing result and the hardware addressing result. If the check passes, the inference data writing operation is executed. If the check fails, the mapping binding and jump operation is re-executed.

[0017] In this embodiment, the address mapping binding relationship is solidified by a unique universal identifier, and the solidified mapping relationship is stored in a fixed partition of the storage chip. After the device is powered off and restarted, the mapping relationship can be quickly read and restored by the unique universal identifier without re-performing semantic division and address binding, which greatly improves the device startup speed and data stability.

[0018] Example 2: A one-way addressing scenario where semantics are decomposed on the hardware side and matched to find the logical address on the software side. This embodiment is applied to a scenario where data is stored, read, and inferred from an AI edge computing box. The specific execution steps are as follows: S201, for the industrial part defect detection image data (artificial intelligence storage data to be processed) stored in the edge computing box hardware storage chip, the hardware (the built-in main control processing unit of the storage chip) performs semantic unit division; according to the minimum semantic granularity rule, the image data is split into complete image block units of a single defect feature (if any data segment is lost after splitting, the complete semantics of the defect feature will be lost), and data semantic units corresponding to each defect image block are obtained. S202, on the hardware side, based on the partitioned data semantic units, performs address mapping binding, binding a unique mapping relationship between the hardware physical address (physical page address of the storage chip) and the software logical address (virtual memory address of the inference system) for the semantic unit of each defective image block; S203, based on the above address mapping and binding relationship, through the pre-configured static mapping table lookup and switching operation, the one-way correspondence switching from the physical address on the hardware side to the logical address on the software side is realized, and the switching direction is consistent with the address matching direction; S204, throughout the entire process of the table lookup and switching operation and after the switching is completed, the physical address on the hardware side and the logical address on the software side are always aligned one-to-one through the semantic units of the defective image block, and the address mapping relationship does not shift during the switching process; S205 After the switch is completed, the corresponding image data is loaded into the inference memory of the software and the artificial intelligence defect detection inference task is executed. At the same time, the addressing result is checked for consistency. If the check fails, the mapping binding and switching operation is re-executed.

[0019] Example 3: Semantic decomposition of hardware and software co-working terminals, bidirectional address switching scenario with virtual middleware layer This embodiment is applied to a large-model inference scenario on the edge of an AI smartphone. The software and hardware work together to complete semantic segmentation, and bidirectional address switching is accomplished through a virtual mapping intermediate layer. The specific execution steps are as follows: S301, for the dialogue text data and inference tensor data of the large model on the edge, the semantic unit division is performed by the software and hardware co-processing end: the splitting rules are configured by the software end (mobile operating system), and the splitting action is executed by the hardware end (neural network processor chip); according to the minimum semantic granularity rule, the text data is split into the smallest word segmentation unit, and the tensor data is split into the smallest inference unit, so as to obtain the data semantic units that correspond one-to-one with the data to be processed. S302, based on the partitioned data semantic units, establishes a unique mapping and binding relationship between the software-side logical address (memory virtual address) and the hardware-side physical address (on-chip storage address of the neural network processor) corresponding to each semantic unit, and the two are transferred through a virtual mapping intermediate layer; S303, based on the mapping and binding relationship, realizes bidirectional switching between the logical address of the software side and the physical address of the hardware side through atomic jump operations according to the scheduling requirements of the inference task: during inference calculation, it switches from the software side to the hardware side; when the inference result is returned, it switches from the hardware side to the software side. S304: Throughout the bidirectional switching process and after each switching, the software-side logical address and the hardware-side physical address are always aligned one-to-one through the data semantic unit. The relay of the virtual intermediate layer does not change the address mapping relationship, and there is no address offset during the switching process. S305 performs a consistency check after each switch, and the mapping and binding relationship is solidified by a unique universal identifier. After the phone is locked, powered off, or restarted, the mapping relationship can be quickly restored through the unique universal identifier without re-initializing the large model inference environment, which greatly improves inference speed and user experience.

Claims

1. A software-hardware bidirectional semantic addressing jump method, applied to inference data processing or data storage scenarios of artificial intelligence edge computing devices, characterized in that, Includes the following steps: Step S1: For the artificial intelligence reasoning data or stored data to be processed, the semantic units are divided according to the smallest semantic granularity of the data to obtain data semantic units that correspond one-to-one with the data to be processed; the execution subject of the semantic unit division can be any one of software, hardware, software-hardware co-processing or third-party processing. Step S2: Perform address mapping binding based on the data semantic unit, where each data semantic unit corresponds to a unique mapping relationship between the software-side logical address and the hardware-side physical address; Step S3: Based on the address mapping binding relationship, the one-way or two-way correspondence switching between the software-side logical address and the hardware-side physical address is realized through the address mapping jump operation or table lookup switching operation, and the switching direction is consistent with the matching direction of the address mapping binding. In step S4, during the entire address switching process and after the switching is completed, the software-side logical address and the hardware-side physical address always maintain a one-to-one mapping and alignment through the data semantic unit, and the address mapping relationship does not shift during the switching process.

2. The software and hardware bidirectional semantic addressing jump method according to claim 1, characterized in that, The jump operation in step S3 is an indivisible atomic jump operation, and the jump process cannot be interrupted or rolled back.

3. The software and hardware bidirectional semantic addressing jump method according to claim 1, characterized in that, In step S1, the smallest semantic granularity is the smallest data unit that can be divided from the artificial intelligence data to be processed and has complete semantic information, including any one of artificial intelligence tensor semantic units, text semantic units, and file data block semantic units.

4. The software and hardware bidirectional semantic addressing jump method according to claim 1, characterized in that, The software-side logical address and the hardware-side physical address are switched through one or more virtual mapping intermediate layers. Throughout the switching process and after completion, the one-to-one mapping alignment is maintained through data semantic units.

5. The software and hardware bidirectional semantic addressing jump method according to claim 1, characterized in that, The triggering conditions for the address switching operation in step S3 include any one or more combinations of data reading, data writing, address mapping update, data semantic re-splitting, artificial intelligence inference task scheduling, and address recovery after device power failure and restart.

6. The software and hardware bidirectional semantic addressing jump method according to claim 1, characterized in that, After the address switching operation is completed, an end-to-end consistency check is performed on the software-side addressing result and the hardware-side addressing result. If the check fails, the address mapping binding and switching operation is re-executed.

7. The software and hardware bidirectional semantic addressing jump method according to claim 1, characterized in that, The address mapping binding relationship is solidified by a unique universal identifier. After the device is powered off, the system is restarted, or the data is transmitted across devices, the mapping binding relationship can be restored, cannot be tampered with, and maintains a one-to-one correspondence with the data semantic unit.