A cross-domain circuit and method supporting dynamic voltage or frequency scaling

Abstract

The application relates to the technical field of master-slave data interaction, in particular to a cross-domain circuit and method supporting dynamic voltage or frequency adjustment, which comprises a host cross-domain circuit and a slave cross-domain circuit connected in sequence, the host cross-domain circuit is connected with an upstream host device, and the slave cross-domain circuit is connected with a downstream slave device; the host cross-domain circuit comprises a distribution control circuit, a first state controller, a first transaction blocking circuit and a sending module; the slave cross-domain circuit comprises a second state controller, a second transaction blocking circuit and a receiving module; the host cross-domain circuit and the slave cross-domain circuit are completely separated from different clock domains, reset domains and power domains, the circuit is more easily realized on a large-scale high-speed chip, and the system is convenient to control; the distribution control circuit, the first state controller and the first transaction blocking circuit work cooperatively to support an error response function and a blocking function of a protocol data transmission channel, and better safety of the system can be provided.

Description

Technical Field

[0001] This invention relates to the field of master-slave data interaction technology, and in particular to a cross-domain circuit and method that supports dynamic voltage or frequency adjustment. Background Technology

[0002] With the rapid development of large-scale digital integrated circuits, multiple clock domains, multiple reset domains, and multiple power domains in chips are becoming increasingly common. As the circuit size increases, the number of signal lines for data interaction between different domains also increases, making chip interconnection and implementation increasingly complex and difficult.

[0003] In existing technologies, cross-asynchronous transmission of multi-bit signals is typically achieved through asynchronous first-in-first-out (FIFO) buffering. However, this method does not effectively separate the clock, reset, and power domains. Therefore, as circuit size increases, the difficulties in controlling and implementing cross-domain transmission remain unresolved. This is particularly true for high-speed buses like AXI (Advanced eXtensible Interface), where cross-domain transmission is often necessary to balance overall system performance and power consumption. To facilitate control and cross-domain circuit implementation, providing flexible adjustment of voltage and frequency across both domains while ensuring the performance of the AXI high-speed bus, complete domain separation and dynamic voltage or frequency adjustment are crucial.

[0004] Existing technologies are complex and difficult to implement on chips in high-speed AXI protocol cross-domain transmission circuits in large-scale circuits. They also cannot completely separate different clock domains, reset domains, and power domains, and cannot achieve flexible adjustment of voltage or frequency between the two domains.

[0005] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0006] The technical problem to be solved by the present invention is how to solve the problem that the existing technology cannot completely separate different clock domains, reset domains and power domains in large-scale circuit high-speed protocol cross-domain transmission circuits, and at the same time cannot achieve flexible adjustment of voltage or frequency between the two domains.

[0007] The present invention adopts the following technical solution: In a first aspect, a cross-domain circuit supporting dynamic voltage or frequency adjustment is provided, comprising a master cross-domain circuit and a slave cross-domain circuit connected in sequence. The master cross-domain circuit is used to connect to an upstream master device, and the slave cross-domain circuit is used to connect to a downstream slave device. The master cross-domain circuit includes a distribution control circuit, a first state controller, a first transaction blocking circuit, and a transmission module. The slave cross-domain circuit includes a second state controller, a second transaction blocking circuit, and a receiving module. The first transaction blocking circuit is used to receive protocol data from the upstream master device, and transmit the protocol data to the downstream slave device in sequence through the sending module, the receiving module and the second transaction blocking circuit; The sending module and the receiving module are used to temporarily store the protocol data and synchronize the clock difference between the two sides through a handshake control signal; The distribution control circuit is used to receive low-power instructions. The first state controller and the second state controller are used to respond to the low-power instructions respectively. When one side needs to be reset, the first state controller and the second state controller are used to control the first transaction blocking circuit and the second transaction blocking circuit to block incomplete transactions, so as to trigger the internal self-reset logic and isolate the other side domain for separate reset.

[0008] Preferably, it also includes a low-power module, which is connected in series between the host cross-domain circuit and the slave cross-domain circuit; When one side needs to be powered off, the first state controller responds to the low-power command and puts the low-power module into a power-down state to power off one side.

[0009] Preferably, the host cross-domain circuit further includes a selection circuit and an error responder. The control terminal of the selection circuit is connected to the distribution control circuit. The common terminal of the selection circuit is used to connect to the upstream master device. The first branch terminal of the selection circuit is connected to the first transaction blocking circuit. The second branch terminal of the selection circuit is connected to the error responder. The selection circuit is used to receive protocol data from the upstream master device and send the protocol data to the first transaction blocking circuit or the error responder according to the selection control signal from the distribution control circuit. When the selection circuit transmits the protocol data to the first transaction blocking circuit, the first transaction blocking circuit is used to transmit the protocol data to the sending module, and the sending module transmits the protocol data to the slave cross-domain circuit. When the selection circuit transmits the protocol data to the error responder, the error responder generates a corresponding error response and returns it to the upstream master device.

[0010] Preferably, the transmitting module includes multiple transmitters, each transmitter corresponding to a protocol data transmission channel, and each transmitter includes a transmitting control circuit and a buffer circuit; the receiving module includes multiple receivers, and each receiver includes a receiving control circuit. The sending control circuit is connected to the first transaction blocking circuit, the buffer circuit and the receiving control circuit respectively, and the receiving control circuit is also connected to the second transaction blocking circuit and the buffer circuit respectively. The transmitting control circuit is used to store protocol data into the buffer circuit according to the source handshake signal, and send a write instruction asynchronous signal to the receiving control module. The receiving control circuit is used to generate a read indication synchronization signal according to the write indication asynchronous signal to read the corresponding protocol data from the cache circuit, and interact with the second transaction blocking circuit through the destination handshake signal to transmit the protocol data to the second transaction blocking circuit.

[0011] Preferably, the host cross-domain circuit further includes a first protocol monitor and a first debug monitor; The first protocol monitor and the first debug monitor are respectively connected to the first status controller; the first protocol monitor is also connected to the first transaction blocking circuit and the first debug monitor; the first debug monitor is also used to connect to the upstream master device; The first protocol monitor is used to monitor the transaction completion status of each transmission channel of the protocol data and initiate blocking of each transmission channel; The first debug monitor is used to monitor the internal signals of the cross-domain circuit to obtain whether there are any abnormalities in the transmission of protocol data.

[0012] Preferably, the first state controller includes a request receiving circuit, a request sending circuit, a state machine circuit, a blocking sending circuit, and a self-reset circuit. The request receiving circuit is connected to the distribution control circuit and the state machine circuit respectively. The state machine circuit is also connected to the request sending circuit, the blocking sending circuit and the self-reset circuit respectively. The request sending circuit is also connected to the second state controller. The blocking sending circuit is also connected to the first protocol monitor. The self-reset circuit is also connected to the first transaction blocking circuit. The request receiving circuit is used to receive low-power instructions from the distribution control circuit; The state machine circuit is used to control the request sending circuit to send an LPI request to the slave cross-domain circuit according to the low-power instruction, and to perform state transitions according to the slave cross-domain circuit response, the current state, and the state transition conditions. The state machine circuit is also used to control the blocking sending circuit to output a blocking request signal to the first protocol monitor. The state machine circuit is also used to control the self-reset circuit to output a self-reset signal to the first transaction blocking circuit, and to control the blocking sending circuit to initiate a final blocking signal to the first protocol monitor. The first protocol monitor is used to initiate blocking of each transmission channel of protocol data according to the final blocking signal; the first transaction blocking circuit is used to perform self-reset according to the self-reset signal.

[0013] Preferably, the first protocol monitor includes a channel counting circuit and a channel blocking control circuit; The channel counting circuit is connected to the transmission channels of the protocol data and the channel blocking control circuit respectively. The channel blocking control circuit is also connected to the first transaction blocking circuit. The channel counting circuit is used to obtain the transaction completion status of different transmission channels of the protocol data; The channel blocking control circuit is used to initiate blocking of each transmission channel by the first transaction blocking circuit according to the transaction completion status of different transmission channels of the protocol data.

[0014] Preferably, the first debug monitor includes a transaction count collection circuit, an exception reset monitoring circuit, a cache empty / full status monitoring circuit, and a control status collection circuit; The transaction count collection circuit is connected to the channel count circuit, the abnormal reset monitoring circuit and the buffer empty / full status monitoring circuit are respectively connected to each transmission channel of the protocol data, and the control status collection circuit is connected to the first status controller; the transaction count collection circuit, the abnormal reset monitoring circuit, the buffer empty / full status monitoring circuit and the control status collection circuit are also respectively connected to the upstream master device; The transaction counting collection circuit is used to obtain the transaction completion status of each transmission channel of the protocol data according to the channel counting circuit; The abnormal reset monitoring circuit is used to monitor the read / write indication asynchronous signal of each transmission channel of the protocol data, and to determine the abnormal reset situation based on the abnormal jump of the read / write indication asynchronous signal in the power-on state. The buffer full / empty status monitoring circuit is used to monitor the read / write indication asynchronous signal of each transmission channel of the protocol data, and to determine the corresponding transmission channel has a buffer abnormality based on the buffer full / empty status. The control state collection circuit is used to acquire the internal state machine state signal in the first state controller in order to determine the abnormal situation of the cross-domain circuit. The first debug monitor is used to report transaction completion status, abnormal reset status, cache abnormal status, and cross-domain circuit abnormal status to the upstream master device.

[0015] In a second aspect, a method for supporting dynamic voltage or frequency regulation is provided, implemented in a cross-domain circuit supporting dynamic voltage or frequency regulation as described in the first aspect, comprising: The first transaction blocking circuit receives protocol data from the upstream master device and transmits the protocol data to the downstream slave device in sequence through the sending module, the receiving module, and the second transaction blocking circuit. The sending module and the receiving module temporarily store the protocol data and synchronize the clock difference between the two sides through a handshake control signal to ensure the correctness and maximum throughput of the protocol data in asynchronous transmission. The distribution control circuit receives a low-power instruction. The first state controller and the second state controller respond to the low-power instruction respectively. When one side needs to be reset, the first state controller and the second state controller respectively control the first transaction blocking circuit and the second transaction blocking circuit to block incomplete transactions, so as to trigger the internal self-reset logic and isolate the other side domain to be reset separately. When one side needs to be powered off, the first state controller responds to the low-power command and puts the low-power module into a power-down state to power off one side.

[0016] Preferably, the host cross-domain circuit further includes a selection circuit and an error responder, and the method further includes: The selection circuit receives protocol data from the upstream master device and sends the protocol data to the first transaction blocking circuit or the error responder according to the selection control signal from the distribution control circuit. When the selection circuit transmits the protocol data to the first transaction blocking circuit, the first transaction blocking circuit transmits the protocol data to the sending module, and the sending module transmits the protocol data to the slave cross-domain circuit. When the selection circuit transmits the protocol data to the error responder, the error responder generates a corresponding error response and returns it to the upstream master device.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention improves the performance of protocol data transmission across clock domains by using handshake control signals between the transmitting and receiving modules. It prevents data transmission errors when both sides are at arbitrarily different clock frequencies and ensures maximum data throughput. Regarding different reset domains, if a reset of only one side is required, it is only necessary to control the first state controller to enter a power-down state and then block and self-reset the transaction through the first transaction blocking circuit. This allows for a safe individual reset of one reset domain without affecting the other side.

[0018] In summary, this embodiment completely separates the clock domain, reset domain, and power domain through the host cross-domain circuit and the slave cross-domain circuit, making it easier to implement on large-scale high-speed chips and facilitating system control. By working together with the distribution control circuit, the first state controller, and the first transaction blocking circuit, it supports error response functions and the blocking function of the protocol data transmission channel, thus providing better system security. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a cross-domain circuit that supports dynamic voltage or frequency adjustment, provided in an embodiment of the present invention. Figure 2 This is another structural schematic diagram of a cross-domain circuit that supports dynamic voltage or frequency adjustment, provided by an embodiment of the present invention; Figure 3 This is a schematic diagram of a specific structure of a cross-domain circuit that supports dynamic voltage or frequency adjustment, provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the structure of a transmitter and receiver provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a first state controller provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a first protocol monitor provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of a first debugging monitor provided in an embodiment of the present invention; Figure 8 This is a flowchart illustrating a method for maintaining dynamic voltage or frequency adjustment provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0022] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0023] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0024] In describing some embodiments, the terms "coupled," "coupled," and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "connected" or "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other, such as "optical coupling," "wireless connection," etc. The embodiments disclosed herein are not necessarily limited to the scope of this invention.

[0025] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0026] To address the problem in existing technologies where different clock, reset, and power domains cannot be completely separated in high-speed cross-domain transmission circuits of large-scale circuits, and where flexible adjustment of voltage or frequency between the two domains is not possible, in one embodiment, such as... Figure 1 As shown, this embodiment proposes a cross-domain circuit that supports dynamic voltage or frequency adjustment, including a host cross-domain circuit and a slave cross-domain circuit connected in sequence. The host cross-domain circuit is used to connect to an upstream master device, and the slave cross-domain circuit is used to connect to a downstream slave device. The host cross-domain circuit includes a distribution control circuit, a first state controller, a first transaction blocking circuit, and a sending module. The slave cross-domain circuit includes a second state controller, a second transaction blocking circuit, and a receiving module.

[0027] The distribution control circuit is connected to the first state controller, which is connected to both the first transaction blocking circuit and the second state controller. The second state controller is also connected to the second transaction blocking circuit. The input terminal of the first transaction blocking circuit is connected to the upstream master device, and the output terminal of the first transaction blocking circuit is connected to the sending module. The sending module is connected to the receiving module, and the receiving module is connected to the second transaction blocking circuit. The second transaction blocking circuit is also connected to the downstream slave device.

[0028] The first transaction blocking circuit is used to receive protocol data (i.e., AXI) from the upstream master device, and transmit the protocol data to the downstream slave device in sequence through the sending module, the receiving module, and the second transaction blocking circuit. The sending module and the receiving module are used to temporarily store the protocol data and synchronize the clock difference between the two sides through a handshake control signal to ensure the correctness and maximum throughput of the protocol data in asynchronous transmission. The distribution control circuit is used to receive low-power instructions (i.e., LPI). The first state controller and the second state controller are used to respond to the low-power instructions respectively. When one side needs to be reset, the first state controller and the second state controller are used to control the first transaction blocking circuit and the second transaction blocking circuit to block unfinished transactions to trigger internal self-reset logic to isolate the other side domain from being reset separately. In one embodiment, refer to Figure 1 The cross-domain circuit supporting dynamic voltage or frequency adjustment also includes a low-power module, which is connected in series between the host cross-domain circuit and the slave cross-domain circuit. When one side needs to be powered off, the first state controller responds to the low-power command and puts the low-power module into a power-down state to power off one side.

[0029] In one embodiment, the distribution control circuit is used to receive low-power instructions, which typically originate from the system's control center (or upstream master device).

[0030] In this process, the upstream master device sends protocol data to the first transaction blocking circuit, which then transmits the protocol data to the sending module. The sending module temporarily stores the data, synchronizes its clock with the receiving module via a handshake control signal, and sends the protocol data to the receiving module. After receiving the protocol data, the receiving module transmits it to the second transaction blocking circuit, which ultimately transmits the protocol data to the downstream slave device.

[0031] When one side needs to be reset, the distribution control circuit receives a low-power command and passes it to the first state controller. The first state controller and the second state controller respectively control the first transaction blocking circuit and the second transaction blocking circuit to block incomplete transactions, triggering the internal self-reset logic to achieve a separate reset of one side while isolating the other side from being affected.

[0032] When one side needs to be powered off, the distribution control circuit receives a low-power command, and the first state controller responds to the low-power command by putting the low-power module into a power-down state, thereby enabling the separate power-off of one side.

[0033] The low-power instructions used for reset and power-off are the same. Whether the system performs a power-off or reset operation on either side of the power domain or the reset domain is independent of the low-power instruction sending. In one embodiment, for safety reasons, the system needs to send a low-power instruction first. After the internal self-reset of the circuits on both sides is completed, it can then decide whether to perform a reset operation or a power-off operation.

[0034] In one embodiment, the low-power module includes multiple low-power units, each of which is disposed in the asynchronous signal transmission channel of the protocol data.

[0035] The structure of the cross-domain circuit that supports dynamic voltage or frequency regulation will be described in detail below.

[0036] In one embodiment, such as Figure 2 As shown, the host cross-domain circuit also includes a selection circuit and an error responder. The control terminal of the selection circuit is connected to the distribution control circuit. The common terminal of the selection circuit is used to connect to the upstream master device. The first branch terminal of the selection circuit is connected to the first transaction blocking circuit. The second branch terminal of the selection circuit is connected to the error responder. The selection circuit is used to receive protocol data from the upstream master device and send the protocol data to the first transaction blocking circuit or the error responder according to the selection control signal from the distribution control circuit; when the selection circuit sends the protocol data to the first transaction blocking circuit, the first transaction blocking circuit is used to send the protocol data to the sending module, and the sending module sends the protocol data to the slave cross-domain circuit; when the selection circuit sends the protocol data to the error responder, the error responder is used to generate a corresponding error response and return it to the upstream master device.

[0037] The distribution control circuit determines whether the system is in normal operating mode based on its operating status and received relevant information, and sends a corresponding selection control signal (i.e., the SEL signal) to the selection circuit. Upon receiving the selection control signal, the selection circuit sends the protocol data received from the upstream master device at the common terminal to the first transaction blocking circuit through the first branch terminal. The first transaction blocking circuit receives the protocol data and passes it to the sending module. The sending module temporarily stores the protocol data and synchronizes its clock with the receiving module in the slave cross-domain circuit using a handshake control signal to ensure the correctness and maximum throughput of the data in asynchronous transmission. Finally, it sends the protocol data to the slave cross-domain circuit.

[0038] When the system detects certain anomalies, it sends a corresponding selection control signal to the selection circuit via the distribution control circuit, instructing it to redirect the protocol data to the error handling path. Based on the received selection control signal, the selection circuit sends the protocol data received at the common terminal to the error responder via the second branch terminal. Upon receiving the protocol data, the error responder generates corresponding error response information based on the specific error type. The error responder returns the generated error response information to the upstream master device, enabling the upstream master device to take appropriate actions, such as retransmitting data or adjusting system configuration.

[0039] In one embodiment, the workflow comprises two main categories: AXI protocol data flow and LPI control flow. Specifically, the protocol data in this embodiment is AXI protocol data, and the low-power commands are LPI.

[0040] The AXI protocol data includes: an AXI protocol data stream from the upstream master device connected to the host cross-domain circuit, and then sent to the downstream slave device by the slave cross-domain circuit. The upstream input protocol data is transmitted to either the first transaction blocking circuit or the error responder, depending on the distribution control circuit. If sent to the first transaction blocking circuit, the protocol data is indirectly controlled by the first state controller (via the sel signal), which determines whether it is allowed to be sent to the downstream slave device. If allowed, the protocol data can be transmitted across clock domains to the receiving module of the slave cross-domain circuit via the sending module. If the distribution control circuit decides to send the protocol data to the error responder, it will reply with a corresponding number of error responses in the host cross-domain circuit, and will not send it to the downstream slave device.

[0041] The LPI control flow (Low Power Instruction) includes: Low power instructions from external sources are only connected to the host cross-domain circuitry and, after logical processing by the distribution control circuitry, are input to the error responder and the first state controller. The first state controller responds to the low power instructions and controls the transmission of protocol data, as well as issuing LPI requests to the state controller of the slave-side cross-domain circuitry. Simultaneously, the low power instructions input to the host cross-domain circuitry are processed by the distribution control circuitry to control the LPI state (power-on or power-off state) of the error responder, placing the error responder in the opposite LPI state to other circuits.

[0042] In one embodiment, if protocol data still enters the host cross-domain circuit after the cross-domain circuit enters the power-down state, the error responder will reply with the corresponding error response to inform the upstream master device that the downstream slave device is in an inaccessible state. This ensures the security of some devices in the system after power-down.

[0043] In one embodiment, such as Figure 3 and Figure 4 As shown, the sending module includes multiple transmitters, each corresponding to a protocol data transmission channel. Each transmitter includes a sending control circuit and a buffer circuit. The receiving module includes multiple receivers, each including a receiving control circuit. The sending control circuit is connected to the first transaction blocking circuit, the buffer circuit, and the receiving control circuit, respectively. The receiving control circuit is also connected to the second transaction blocking circuit and the buffer circuit, respectively. The sending control circuit is used to store the protocol data (i.e., the source data signal) into the buffer circuit according to the source handshake signal and to send a write indication asynchronous signal to the receiving control module. The receiving control circuit is used to generate a read indication synchronization signal according to the write indication asynchronous signal to read the corresponding protocol data from the buffer circuit, and to interact with the second transaction blocking circuit through the destination handshake signal to transmit the protocol data (i.e., the destination data signal) to the second transaction blocking circuit.

[0044] In one embodiment, refer to Figure 3 The host cross-domain circuit further includes multiple receivers, and the slave cross-domain circuit further includes multiple transmitters for transmitting and receiving data on the R and B transmission channels. In one embodiment, the synchronizer is used for clock synchronization of protocol data on both sides.

[0045] The buffer circuit includes multiple data registers for temporarily storing protocol data from upstream. The source handshake signal includes a source handshake request signal and a source handshake completion signal, and the destination handshake signal includes a destination handshake request signal and a destination handshake completion signal.

[0046] In one embodiment, a source handshake request signal and protocol data are sent to the transmitter's transmission control circuit. The transmission control circuit generates a write indication synchronization signal to indicate the location in the buffer circuit where the protocol data is stored. Upon receiving the protocol data, it immediately replies with a source handshake completion signal to the first transaction blocking circuit.

[0047] On the other hand, when the transmitting control circuit receives the protocol data, it sends a write instruction asynchronous signal to the receiving control circuit to inform the receiver that it can start receiving the protocol data. Then, it receives a read instruction asynchronous signal (indicating the position of a data in the buffer circuit that has been received) in response to the receiving control circuit, and receives a read instruction synchronization signal (indicating the position of the next data to be received in the buffer circuit).

[0048] When the receiver receives the protocol data and continues transmission downstream, it sends a destination handshake request signal and the read protocol data to the downstream device (i.e., the second transaction blocking circuit). When the downstream device replies with a destination handshake completion signal, it indicates that the currently transmitted protocol data has been received. The correctness and stability of cross-domain data transmission are ensured by using asynchronous write and read indicators for handshaking, and by synchronizing at least two registers after the asynchronous signal crosses domains.

[0049] Furthermore, the transmitter's transmit control circuit determines whether the buffer circuit is full based on the write indication asynchronous signal and the read indication asynchronous signal. Otherwise, it will continuously receive protocol data to the buffer circuit; that is, for each source handshake request signal, a source handshake completion signal will be sent until the data register in the buffer circuit is full. In one embodiment, to ensure the transmission performance of protocol data, the buffer depth must be at least the number of registers traversed by the write indication asynchronous signal after crossing the domain plus 2 (e.g., ...). Figure 4 The required buffer depth shown in the example should be 6, which ensures the performance of protocol data transmission across clock domains.

[0050] In one embodiment, such as Figure 3 As shown, the host cross-domain circuit further includes a first protocol monitor and a first debug monitor; the first protocol monitor and the first debug monitor are respectively connected to the first status controller; the first protocol monitor is also connected to the first transaction blocking circuit and the first debug monitor; the first debug monitor is also used to connect to the upstream master device; the first protocol monitor is used to monitor the transaction completion status of each transmission channel of the protocol data and initiate blocking of each transmission channel; the first debug monitor is used to monitor the internal signals of the cross-domain circuit to obtain whether there is an abnormality in the transmission of protocol data.

[0051] The slave cross-domain circuit further includes a second protocol monitor and a second debugging monitor; the first protocol monitor and the second protocol monitor have the same structure; the first debugging monitor and the second debugging monitor have the same structure. The principles of the second protocol monitor and the second debugging monitor can be derived from the above. This embodiment uses the first protocol monitor and the first debugging monitor as examples for specific explanation.

[0052] In one embodiment, the first protocol monitor performs real-time monitoring of the transaction completion status of each transmission channel of the protocol data. It checks whether the data transmission on each transmission channel is completed according to the predetermined protocol and process, such as whether there is data loss or transmission timeout. When a problem is detected in a transaction of a certain transmission channel, the first protocol monitor initiates a blocking operation for that channel, that is, sends relevant instructions to the first transaction blocking circuit to suspend data transmission on that channel, preventing the problem from spreading further and ensuring the normal operation of other channels.

[0053] The first debugging monitor comprehensively monitors the internal signals of the cross-domain circuit, which include the operating status of each part of the circuit and the data transmission status. By analyzing the internal signals, the first debugging monitor can determine whether there are any abnormalities in the transmission of protocol data. Once an abnormality is detected, the first debugging monitor will feed back the relevant information to the upstream master device, and can also interact with the first status controller to take further action. The internal signals will be described in detail below.

[0054] In one embodiment, such as Figure 5As shown, the first state controller includes a request receiving circuit, a request sending circuit, a state machine circuit, a blocking sending circuit, and a self-reset circuit; the request receiving circuit is connected to the distribution control circuit and the state machine circuit respectively, and the state machine circuit is also connected to the request sending circuit, the blocking sending circuit, and the self-reset circuit respectively; the request sending circuit is also connected to the second state controller, the blocking sending circuit is also connected to the first protocol monitor, and the self-reset circuit is also connected to the first transaction blocking circuit.

[0055] The request receiving circuit is used to receive a low-power instruction (i.e., LPI) from the distribution control circuit; the state machine circuit is used to control the request sending circuit to send an LPI request to the slave cross-domain circuit according to the low-power instruction, and to perform state transitions according to the slave cross-domain circuit response, current state, and state transition conditions; the state machine circuit is also used to control the blocking sending circuit to output a blocking request signal to the first protocol monitor, and the state machine circuit is also used to control the self-reset circuit to output a self-reset signal to the first transaction blocking circuit, and to control the blocking sending circuit to initiate a final blocking signal to the first protocol monitor; the first protocol monitor is used to initiate blocking of each transmission channel of protocol data according to the final blocking signal; the first transaction blocking circuit is used to perform a self-reset according to the self-reset signal.

[0056] In one embodiment, the request receiving circuit receives a low-power instruction from the distribution control circuit. Based on the received low-power instruction, the state machine circuit controls the request sending circuit to send an LPI request to the slave cross-domain circuit. Sending the LPI request is to coordinate with the slave cross-domain circuit, ensuring it is also ready to enter a low-power state. Simultaneously, the state machine circuit performs state transitions based on the slave cross-domain circuit's response, its current state, and pre-set state transition conditions to adapt to different operating modes. The state machine circuit controls the blocking sending circuit to output a blocking request signal to the first protocol monitor. The blocking request signal informs the first protocol monitor that a blocking operation may be needed on the protocol data transmission channel, preparing for subsequent low-power processing or reset operations. Simultaneously, the state machine circuit controls the self-reset circuit to output a self-reset signal to the first transaction blocking circuit. Upon receiving the self-reset signal, the first transaction blocking circuit performs a self-reset operation, clearing the current transaction state and preparing for a new operating state.

[0057] The state machine circuit controls the blocking transmission circuit to initiate a final blocking signal to the first protocol monitor. Based on the final blocking signal, the first protocol monitor initiates blocking of each transmission channel of the protocol data, ensuring that no new data transmission occurs during low-power or reset operations, avoiding data corruption. This achieves the blocking of protocol data transmission after power-down and resets all circuits except the first state controller. The structure and working principle of the second state controller will not be described in detail in this embodiment.

[0058] In one embodiment, such as Figure 6 As shown, the first protocol monitor includes a channel counting circuit and a channel blocking control circuit; the channel counting circuit is connected to different transmission channels of the protocol data and the channel blocking control circuit respectively, and the channel blocking control circuit is also connected to the first transaction blocking circuit; the channel counting circuit is used to obtain the transaction completion status of different transmission channels of the protocol data; the channel blocking control circuit is used to initiate blocking of each transmission channel to the first transaction blocking circuit according to the transaction completion status of different transmission channels of the protocol data.

[0059] In one embodiment, the transmission channels for the protocol data include: a read address channel ar (hereinafter referred to as the ar channel), a read data channel r (hereinafter referred to as the r channel), a write address channel aw (hereinafter referred to as the aw channel), a write data channel w (hereinafter referred to as the w channel), and a write response channel b (hereinafter referred to as the b channel).

[0060] The channel counting circuit includes aw and b channel counting circuits, aw and w channel counting circuits, and ar and r channel counting circuits. The channel blocking circuit includes b channel blocking circuit, aw channel blocking circuit, w channel blocking circuit, and a channel blocking circuit. The first protocol monitor also includes a w and aw channel receive order monitoring circuit and an incomplete read / write status collection circuit. For specific connection methods, refer to... Figure 6 I will not go into too much detail here.

[0061] The internal three channel counting circuits record the completion status of transactions between aw and b, aw and w, and ar and r, respectively. The channel blocking control circuit initiates blocking based on the completion status of the corresponding channel transactions. If a blocking request signal from the first state controller arrives, and the aw / b / w / ar / r channel blocking control circuit knows that the corresponding transmission channel transaction has been completed, it will send blocking signals for the corresponding channels (b channel blocking signal, aw channel blocking signal, w channel blocking signal, and a channel blocking signal) to the first transaction blocking circuit. The first transaction blocking circuit then blocks the corresponding transmission channel according to the corresponding channel blocking signal. In one embodiment, the blocking of aw and w channels also needs to be based on the output of the w and aw channel reception order monitoring circuit. If aw arrives at the first protocol monitor before w, the aw channel is blocked with higher priority; if aw arrives at the first protocol monitor before w, the w channel is blocked with higher priority. The specific structure and working principle of the second protocol monitor are not described in detail in this embodiment.

[0062] In one embodiment, such as Figure 7 As shown, the first debug monitor includes a transaction count collection circuit, an abnormal reset monitoring circuit, a buffer full / empty status monitoring circuit, and a control status collection circuit; the transaction count collection circuit is connected to the channel count circuit, the abnormal reset monitoring circuit and the buffer full / empty status monitoring circuit are respectively connected to each transmission channel of the protocol data, and the control status collection circuit is connected to the first status controller; the transaction count collection circuit, the abnormal reset monitoring circuit, the buffer full / empty status monitoring circuit, and the control status collection circuit are also respectively connected to the upstream master device.

[0063] The transaction counting collection circuit is used to obtain the transaction completion status of each transmission channel of the protocol data according to the channel counting circuit; the abnormal reset monitoring circuit is used to monitor the read / write indication asynchronous signal of each transmission channel of the protocol data, and to determine the occurrence of an abnormal reset situation based on the abnormal jump of the read / write indication asynchronous signal in the power-on state; the buffer empty / full status monitoring circuit is used to monitor the read / write indication asynchronous signal of each transmission channel of the protocol data, and to determine the occurrence of a buffer abnormality in the corresponding transmission channel based on the buffer empty / full status; the control status collection circuit is used to obtain the internal state machine status signal in the first state controller to determine the cross-domain circuit abnormality; the first debugging monitor is used to report the transaction completion status, abnormal reset status, buffer abnormality, and cross-domain circuit abnormality to the upstream master device.

[0064] The first debug monitor mainly uses four circuits (i.e., transaction count collection circuit, abnormal reset monitoring circuit, buffer empty / full status monitoring circuit, and control status collection circuit) to collect, merge, and register four types of signals for output.

[0065] In one embodiment, the transaction completion status includes: the transaction counting collection circuit collects three sets of read and write count values ​​from the first protocol monitor (obtaining the corresponding count values ​​through the above-mentioned aw and b channel counting circuit, aw and w channel counting circuit, and ar and r channel counting circuit respectively), and obtains whether there are still uncompleted transactions for each transmission channel of the protocol data based on the corresponding count values.

[0066] Abnormal reset situations include: The abnormal reset monitoring circuit monitors the read / write indication asynchronous signals of each transmission channel of the protocol data. If these read / write indication asynchronous signals show abnormal transitions during power-on, it is determined that an abnormal reset situation has occurred.

[0067] Cache anomalies include: the cache empty / full status monitoring circuit also monitors the asynchronous read / write indication signals of each transmission channel of the protocol data, and the output can observe whether the cache is always full. If it is always full, then the transaction transmission on this channel has encountered an anomaly.

[0068] Cross-domain circuit anomalies include: the control state collection circuit acquires state signals from the internal state machine circuit of the first state controller, thereby eliminating cross-domain circuit anomalies when an anomaly occurs.

[0069] Transaction completion status, abnormal reset status, cache exception status, and cross-domain circuit exception status are reported together as monitoring results to the upstream master device. The specific structure and working principle of the second debugging monitor will not be described in detail in this embodiment.

[0070] This invention improves the performance of cross-clock domain data transmission by using handshake control signals between the transmitting and receiving modules. It prevents data transmission errors when both sides are at arbitrarily different clock frequencies and ensures maximum data throughput. Regarding different reset domains, if a reset of one side is required, it is only necessary to control the first state controller to enter a power-down state and block and self-reset the transaction through the first transaction blocking circuit to safely reset one side's reset domain without affecting the other side. When in different power domains, one side can be safely powered off by controlling the low-power module.

[0071] In summary, this embodiment completely separates the clock domain, reset domain, and power domain through the host cross-domain circuit and the slave cross-domain circuit, which is easier to implement on large-scale high-speed chips and facilitates system control. By working together with the distribution control circuit, the first state controller, and the first transaction blocking circuit, it supports error response functions and blocking functions for protocol data transmission channels, thus providing better system security.

[0072] To further illustrate the cross-domain circuit supporting dynamic voltage or frequency adjustment described in the foregoing embodiments, in one embodiment, such as Figure 8 As shown, this embodiment proposes a method to support dynamic voltage or frequency regulation, specifically including: Step 101: The first transaction blocking circuit receives protocol data from the upstream master device and transmits the protocol data to the downstream slave device in sequence through the sending module, the receiving module, and the second transaction blocking circuit.

[0073] Step 102: The sending module and the receiving module temporarily store the protocol data and synchronize the clock difference between the two sides through a handshake control signal to ensure the correctness and maximum throughput of the protocol data in asynchronous transmission.

[0074] In this process, the upstream master device sends protocol data to the first transaction blocking circuit, which then transmits the protocol data to the sending module. The sending module temporarily stores the data and synchronizes its clock with the receiving module via a handshake control signal before sending the protocol data to the receiving module. After receiving the protocol data, the receiving module transmits it to the second transaction blocking circuit, which ultimately transmits the protocol data to the downstream slave device.

[0075] Step 103: The distribution control circuit receives a low-power instruction. The first state controller and the second state controller respond to the low-power instruction respectively. When one side needs to be reset, the first state controller and the second state controller respectively control the first transaction blocking circuit and the second transaction blocking circuit to block incomplete transactions, so as to trigger the internal self-reset logic and isolate the other side domain for separate reset.

[0076] When one side needs to be reset, the distribution control circuit receives a low-power command and passes it to the first state controller. The first state controller and the second state controller respectively control the first transaction blocking circuit and the second transaction blocking circuit to block incomplete transactions, triggering the internal self-reset logic to achieve a separate reset of one side while isolating the other side from being affected.

[0077] Step 104: When one side needs to be powered off, the first state controller responds to the low power command and puts the low power module into the power-down state to power off one side.

[0078] When one side needs to be powered off, the distribution control circuit receives a low-power command, and the first state controller responds to the low-power command by putting the low-power module into a power-down state, thereby turning off the power to one side.

[0079] In one embodiment, the method for supporting dynamic voltage or frequency regulation further includes: The selection circuit receives protocol data from the upstream master device and sends the protocol data to the first transaction blocking circuit or the error responder according to the selection control signal from the distribution control circuit. When the selection circuit sends the protocol data to the first transaction blocking circuit, the first transaction blocking circuit sends the protocol data to the sending module, and the sending module sends the protocol data to the slave cross-domain circuit. When the selection circuit sends the protocol data to the error responder, the error responder generates a corresponding error response and returns it to the upstream master device.

[0080] The distribution control circuit determines whether the system is in normal operating mode based on its operating status and received relevant information, and sends a corresponding selection control signal (i.e., the SEL signal) to the selection circuit. Upon receiving the selection control signal, the selection circuit sends the protocol data received from the upstream master device at the common terminal to the first transaction blocking circuit through the first branch terminal. The first transaction blocking circuit receives the protocol data and passes it to the sending module. The sending module temporarily stores the protocol data and synchronizes its clock with the receiving module in the slave cross-domain circuit using a handshake control signal to ensure the correctness and maximum throughput of the data in asynchronous transmission. Finally, it sends the protocol data to the slave cross-domain circuit.

[0081] When the system detects certain anomalies, it sends a specific selection control signal to the selection circuit via the distribution control circuit, instructing it to redirect protocol data to the error handling path. Based on the received selection control signal, the selection circuit sends the protocol data received at the common terminal to the error responder via the second branch terminal. Upon receiving the protocol data, the error responder generates corresponding error response information based on the specific error type. The error responder returns the generated error response information to the upstream master device, enabling the master device to take appropriate actions, such as retransmitting data or adjusting system configuration.

[0082] In one embodiment, the method for supporting dynamic voltage or frequency adjustment further includes: the first protocol monitor monitoring the transaction completion status of each transmission channel of the protocol data and initiating blocking of each transmission channel; the first debug monitor monitoring the internal signals of the cross-domain circuit to obtain whether there are any abnormalities in the transmission of the protocol data.

[0083] The slave cross-domain circuit further includes a second protocol monitor and a second debugging monitor; the first protocol monitor and the second protocol monitor have the same structure; the first debugging monitor and the second debugging monitor have the same structure. The principles of the second protocol monitor and the second debugging monitor can be deduced from the above embodiments. This embodiment uses the first protocol monitor and the first debugging monitor as examples for specific explanation.

[0084] The first protocol monitor performs real-time monitoring of the transaction completion status of each transmission channel of the protocol data. It checks whether the data transmission on each channel is completed according to the predetermined protocol and process, such as whether there is data loss or transmission timeout. When a problem is detected in a transaction of a certain transmission channel, the first protocol monitor will initiate a blocking operation for that channel, that is, send a command to the first transaction blocking circuit to suspend data transmission on that channel, prevent the problem from spreading further, and ensure the normal operation of other channels.

[0085] The first debugging monitor comprehensively monitors the internal signals of the cross-domain circuit, which include the operating status of each part of the circuit and the data transmission status. By analyzing the internal signals, the first debugging monitor can determine whether there are any abnormalities in the transmission of protocol data. Once an abnormality is detected, the first debugging monitor will feed back the relevant information to the upstream master device, and can also interact with the first status controller to take further action.

[0086] In summary, this embodiment completely separates the clock domain, reset domain, and power domain through the host cross-domain circuit and the slave cross-domain circuit, which is easier to implement on large-scale high-speed chips and facilitates system control. By working together with the distribution control circuit, the first state controller, and the first transaction blocking circuit, it supports error response functions and blocking functions for protocol data transmission channels, thus providing better system security.

[0087] The specific structure of the cross-domain circuit supporting dynamic voltage or frequency adjustment is described in the foregoing embodiments and will not be repeated in this embodiment.

[0088] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A transdomain circuit supporting dynamic voltage or frequency regulation, characterized in that, It includes a host cross-domain circuit and a slave cross-domain circuit connected in sequence. The host cross-domain circuit is used to connect to an upstream master device, and the slave cross-domain circuit is used to connect to a downstream slave device. The host cross-domain circuit includes a distribution control circuit, a first state controller, a first transaction blocking circuit, and a sending module. The slave cross-domain circuit includes a second state controller, a second transaction blocking circuit, and a receiving module. The first transaction blocking circuit is used to receive protocol data from the upstream master device, and transmit the protocol data to the downstream slave device in sequence through the sending module, the receiving module and the second transaction blocking circuit; The sending module and the receiving module are used to temporarily store the protocol data and synchronize the clock difference between the two sides through a handshake control signal; The distribution control circuit is used to receive low-power instructions. The first state controller and the second state controller are used to respond to the low-power instructions respectively. When one side needs to be reset, the first state controller and the second state controller are used to control the first transaction blocking circuit and the second transaction blocking circuit to block incomplete transactions, so as to trigger the internal self-reset logic and isolate the other side domain for separate reset.

2. The cross-domain circuit supporting dynamic voltage or frequency adjustment according to claim 1, characterized in that, It also includes a low-power module, which is connected in series between the host cross-domain circuit and the slave cross-domain circuit; When one side needs to be powered off, the first state controller responds to the low-power command and puts the low-power module into a power-down state to power off one side.

3. The cross-domain circuit supporting dynamic voltage or frequency adjustment according to claim 1, characterized in that, The host cross-domain circuit also includes a selection circuit and an error responder. The control terminal of the selection circuit is connected to the distribution control circuit. The common terminal of the selection circuit is used to connect to the upstream master device. The first branch terminal of the selection circuit is connected to the first transaction blocking circuit. The second branch terminal of the selection circuit is connected to the error responder. The selection circuit is used to receive protocol data from the upstream master device and send the protocol data to the first transaction blocking circuit or the error responder according to the selection control signal from the distribution control circuit. When the selection circuit transmits the protocol data to the first transaction blocking circuit, the first transaction blocking circuit is used to transmit the protocol data to the sending module, and the sending module transmits the protocol data to the slave cross-domain circuit. When the selection circuit transmits the protocol data to the error responder, the error responder generates a corresponding error response and returns it to the upstream master device.

4. The cross-domain circuit supporting dynamic voltage or frequency adjustment according to claim 1, characterized in that, The transmitting module includes multiple transmitters, each transmitter corresponding to a protocol data transmission channel. Each transmitter includes a transmitting control circuit and a buffering circuit. The receiving module includes multiple receivers, each receiver including a receiving control circuit. The sending control circuit is connected to the first transaction blocking circuit, the buffer circuit and the receiving control circuit respectively, and the receiving control circuit is also connected to the second transaction blocking circuit and the buffer circuit respectively. The transmitting control circuit is used to store protocol data into the buffer circuit according to the source handshake signal, and send a write instruction asynchronous signal to the receiving control module. The receiving control circuit is used to generate a read indication synchronization signal according to the write indication asynchronous signal to read the corresponding protocol data from the cache circuit, and interact with the second transaction blocking circuit through the destination handshake signal to transmit the protocol data to the second transaction blocking circuit.

5. The cross-domain circuit supporting dynamic voltage or frequency adjustment according to claim 1, characterized in that, The host cross-domain circuit also includes a first protocol monitor and a first debug monitor; The first protocol monitor and the first debug monitor are respectively connected to the first status controller; the first protocol monitor is also connected to the first transaction blocking circuit and the first debug monitor; the first debug monitor is also used to connect to the upstream master device; The first protocol monitor is used to monitor the transaction completion status of each transmission channel of the protocol data and initiate blocking of each transmission channel; The first debug monitor is used to monitor the internal signals of the cross-domain circuit to obtain whether there are any abnormalities in the transmission of protocol data.

6. The cross-domain circuit supporting dynamic voltage or frequency adjustment according to claim 5, characterized in that, The first state controller includes a request receiving circuit, a request sending circuit, a state machine circuit, a blocking sending circuit, and a self-reset circuit; The request receiving circuit is connected to the distribution control circuit and the state machine circuit respectively. The state machine circuit is also connected to the request sending circuit, the blocking sending circuit and the self-reset circuit respectively. The request sending circuit is also connected to the second state controller. The blocking sending circuit is also connected to the first protocol monitor. The self-reset circuit is also connected to the first transaction blocking circuit. The request receiving circuit is used to receive low-power instructions from the distribution control circuit; The state machine circuit is used to control the request sending circuit to send an LPI request to the slave cross-domain circuit according to the low-power instruction, and to perform state transitions according to the slave cross-domain circuit response, the current state, and the state transition conditions. The state machine circuit is also used to control the blocking sending circuit to output a blocking request signal to the first protocol monitor. The state machine circuit is also used to control the self-reset circuit to output a self-reset signal to the first transaction blocking circuit, and to control the blocking sending circuit to initiate a final blocking signal to the first protocol monitor. The first protocol monitor is used to initiate blocking of each transmission channel of protocol data according to the final blocking signal; the first transaction blocking circuit is used to perform self-reset according to the self-reset signal.

7. The cross-domain circuit supporting dynamic voltage or frequency adjustment according to claim 5, characterized in that, The first protocol monitor includes a channel counting circuit and a channel blocking control circuit; The channel counting circuit is connected to the transmission channels of the protocol data and the channel blocking control circuit respectively. The channel blocking control circuit is also connected to the first transaction blocking circuit. The channel counting circuit is used to obtain the transaction completion status of different transmission channels of the protocol data; The channel blocking control circuit is used to initiate blocking of each transmission channel by the first transaction blocking circuit according to the transaction completion status of different transmission channels of the protocol data.

8. The cross-domain circuit supporting dynamic voltage or frequency adjustment according to claim 7, characterized in that, The first debug monitor includes a transaction count collection circuit, an exception reset monitoring circuit, a cache empty / full status monitoring circuit, and a control status collection circuit; The transaction count collection circuit is connected to the channel count circuit, the abnormal reset monitoring circuit and the buffer empty / full status monitoring circuit are respectively connected to each transmission channel of the protocol data, and the control status collection circuit is connected to the first status controller; the transaction count collection circuit, the abnormal reset monitoring circuit, the buffer empty / full status monitoring circuit and the control status collection circuit are also respectively connected to the upstream master device; The transaction counting collection circuit is used to obtain the transaction completion status of each transmission channel of the protocol data according to the channel counting circuit; The abnormal reset monitoring circuit is used to monitor the read / write indication asynchronous signal of each transmission channel of the protocol data, and to determine the abnormal reset situation based on the abnormal jump of the read / write indication asynchronous signal in the power-on state. The buffer full / empty status monitoring circuit is used to monitor the read / write indication asynchronous signal of each transmission channel of the protocol data, and to determine the corresponding transmission channel has a buffer abnormality based on the buffer full / empty status. The control state collection circuit is used to acquire the internal state machine state signal in the first state controller in order to determine the abnormal situation of the cross-domain circuit. The first debug monitor is used to report transaction completion status, abnormal reset status, cache abnormal status, and cross-domain circuit abnormal status to the upstream master device.

9. A method for supporting dynamic voltage or frequency regulation, characterized in that, The cross-domain circuit supporting dynamic voltage or frequency regulation as described in any one of claims 1 to 8 includes: The first transaction blocking circuit receives protocol data from the upstream master device and transmits the protocol data to the downstream slave device in sequence through the sending module, the receiving module, and the second transaction blocking circuit. The sending module and the receiving module temporarily store the protocol data and synchronize the clock difference between the two sides through a handshake control signal to ensure the correctness and maximum throughput of the protocol data in asynchronous transmission. The distribution control circuit receives a low-power instruction. The first state controller and the second state controller respond to the low-power instruction respectively. When one side needs to be reset, the first state controller and the second state controller respectively control the first transaction blocking circuit and the second transaction blocking circuit to block incomplete transactions, so as to trigger the internal self-reset logic and isolate the other side domain to be reset separately. When one side needs to be powered off, the first state controller responds to the low-power command and puts the low-power module into a power-down state to power off one side.

10. The method for supporting dynamic voltage or frequency regulation according to claim 9, characterized in that, The host cross-domain circuit also includes a selection circuit and an error responder, and the method further includes: The selection circuit receives protocol data from the upstream master device and sends the protocol data to the first transaction blocking circuit or the error responder according to the selection control signal from the distribution control circuit. When the selection circuit transmits the protocol data to the first transaction blocking circuit, the first transaction blocking circuit transmits the protocol data to the sending module, and the sending module transmits the protocol data to the slave cross-domain circuit. When the selection circuit transmits the protocol data to the error responder, the error responder generates a corresponding error response and returns it to the upstream master device.

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