Design method of GPU delay-type hardware Trojan triggered by NVLink interconnection
By designing a hardware Trojan that monitors NVLink port traffic characteristics and applies random delay control, the security issues of NVLink interconnect communication in multi-GPU systems are solved, enabling covert interference and efficiency reduction in the multi-GPU collaborative computing process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- EAST CHINA NORMAL UNIV
- Filing Date
- 2026-03-23
- Publication Date
- 2026-06-05
AI Technical Summary
In the current technology, research on the security of interconnect communication between GPUs in multi-GPU systems is still lacking, especially under the NVLink high-speed interconnect architecture, where no research on hardware Trojans has been reported, affecting the overall performance and efficiency of multi-GPU collaborative computing.
Design a GPU latency-based hardware Trojan for NVLink interconnects. By monitoring NVLink port traffic characteristics and calculating correlation metrics between ports, when trigger conditions are met, apply random delay control to control transactions, atomic transactions, and latency-sensitive transactions to create covert interference and avoid directly modifying communication content.
Without altering the communication content, latency control is used to create covert interference in the multi-GPU collaborative computing process, improving the concealment of the hardware Trojan and significantly increasing the communication latency of the multi-GPU system, thus reducing the overall execution efficiency.
Smart Images
Figure CN122153976A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit hardware security, specifically relating to a method for designing a hardware Trojan with delayed communication paths between multiple GPUs for NVLink high-speed interconnect architecture. Background Technology
[0002] Hardware Trojans are maliciously implanted abnormal circuit structures or control logic during the design, manufacturing, packaging, or integration stages of integrated circuits. They are typically activated by specific triggering conditions and then carry out malicious behaviors, such as information leakage, functional alteration, and denial-of-service attacks. Due to their strong concealment and difficulty in detection, hardware Trojans have become an important research problem in the field of integrated circuit security.
[0003] With the rapid development of artificial intelligence computing and high-performance computing, graphics processing units (GPUs), with their strong parallel computing capabilities, have been widely used in deep learning training, scientific computing, and other high-load parallel tasks. Especially in multi-GPU collaborative computing scenarios, GPUs need to frequently exchange data and coordinate states, and the operational security of these interactions has a significant impact on the stability and execution efficiency of the entire computing system.
[0004] In the operation of a multi-GPU system, in addition to the internal computation of each individual GPU, the interconnection and communication between GPUs is also a crucial factor affecting the overall system performance. When multiple GPUs perform operations such as parameter synchronization, gradient exchange, and task collaboration, they typically exhibit communication behaviors with certain synchronicity, correlation, and timing characteristics. Disruptions to these communication behaviors can easily impact the overall execution efficiency of multi-GPU collaborative tasks.
[0005] Current research on hardware Trojans mainly focuses on central processing units and other general-purpose digital circuits. Research on hardware Trojans targeting GPUs is currently nonexistent.
[0006] In multi-GPU systems, GPUs typically communicate with each other via high-speed interconnect structures. NVLink is one of the important interconnect methods for high-speed data exchange between GPUs, commonly used for parameter synchronization, gradient exchange, task coordination, and other communication tasks during multi-GPU collaborative computing. Because this type of interconnect communication is closely linked to the parallel task execution process, any delay in its transmission can significantly impact the overall task completion time.
[0007] In view of this, the present invention proposes a delayed hardware Trojan design method for NVLink high-speed interconnect architecture. It can combine the traffic characteristics of NVLink interconnect port to determine the trigger and implement selective delay control on the target communication process when the conditions are met, thereby forming a covert interference to the multi-GPU collaborative computing process without directly modifying the communication content. Summary of the Invention
[0008] To date, research on GPU-targeted hardware Trojans remains lacking. This invention proposes a method for designing a GPU-delayed hardware Trojan triggered by NVLink interconnects. This method monitors the traffic characteristics of multiple NVLink interconnect ports on the host GPU within a preset time window and determines the triggering conditions for the hardware Trojan based on pre-defined correlation rules. When the triggering conditions are met, malicious delay control is applied to latency-sensitive transactions on selected interconnect ports, thereby creating covert interference in the multi-GPU collaborative computing process without directly tampering with the communication content.
[0009] Technical solution: The technical solution proposed in this invention is as follows:
[0010] A method for designing a GPU latency-based hardware Trojan triggered by NVLink interconnect includes the following steps:
[0011] (1) Traffic feature monitoring: The hardware Trojan implanted in the NVLink control circuit of the host GPU collects and counts the traffic features of multiple NVLink ports of the host GPU within a preset time window. The traffic features are the preset NVLink port activation frequency.
[0012] (2) Trigger determination: Based on the traffic feature sequence of each NVLink port within the preset time window, calculate the correlation measurement value between each pair of ports; when the correlation measurement value between any group or multiple groups of ports exceeds the preset threshold, the hardware Trojan trigger condition is determined to be met.
[0013] Furthermore, the correlation metric can be obtained by a cross-correlation function or other statistical functions that can characterize the consistency of traffic changes between ports, so as to determine the correlation behavior of multi-port communication.
[0014] (3) Malicious delay application: When the triggering condition is met, the hardware Trojan applies delay control to the target port communication transaction corresponding to the triggering condition. The delay control is preferentially applied to control transactions, atomic transactions and other transactions that are sensitive to time delay, so as to enhance the performance interference effect on the multi-GPU collaborative computing process.
[0015] Furthermore, the delay control does not parse the semantic content of the interconnected transmission data, nor does it directly modify the communication payload. Instead, it disturbs the transmission timing of the target transaction to ensure the stealth of the hardware Trojan's behavior.
[0016] (4) Delay control rules: The delay control uses a random bit sequence mapping method to generate the delay intensity. The corresponding delay size is determined according to the position of the first bit that is "1" in the random bit sequence, so that the applied delay has a non-uniform distribution characteristic, thereby applying a continuous disturbance to the information synchronization process of the multi-GPU system without significantly changing the overall communication bandwidth statistical characteristics.
[0017] Furthermore, let the randomly generated binary sequence be b1, b2, ..., b n When the first bit in the sequence that has a value of 1 is the k-th bit, the delay strength is k - 1; the actual additional delay can be expressed as... , where D is the preset base delay period.
[0018] To further explain, the hardware Trojan can dynamically determine whether to trigger and the target of delayed action after triggering based on the NVLink port traffic characteristics under different parallel computing tasks.
[0019] Beneficial effects: Compared with the prior art, the present invention has the following advantages:
[0020] (1) This invention proposes a GPU latency-based hardware Trojan design method for multi-GPU interconnect communication scenarios, which triggers the hardware Trojan based on the interconnect communication behavior during multi-GPU collaborative computing, filling the gap in existing research on GPU hardware Trojans.
[0021] (2) This invention does not require parsing the interconnection communication content or directly modifying the communication payload. Instead, it monitors the NVLink port traffic characteristics and applies delay control to the target transaction transmission timing to achieve covert interference to the multi-GPU collaborative computing process, thus having good covertness.
[0022] (3) This invention prioritizes applying delays to control transactions, atomic transactions and other time-sensitive transactions, and uses a random bit sequence mapping method to determine the delay intensity, so that the malicious delay has a certain degree of randomness and non-uniformity, which is conducive to creating continuous disturbances to the information synchronization process of multi-GPU systems and improving the concealment of hardware Trojan behavior. Attached Figure Description
[0023] Figure 1 This is a flowchart of the technical solution of the present invention. Detailed Implementation
[0024] The invention will now be further explained with reference to the accompanying drawings.
[0025] The hardware Trojan implanted in the NVLink control circuit of the host GPU according to the present invention has the following basic functions: judging the traffic characteristics of multiple NVLink ports of the host GPU within a preset time window, and when the preset triggering conditions are met, prioritizing the action on control transactions, atomic transactions and other latency-sensitive transactions in the target port, thereby increasing the waiting time in the multi-GPU collaborative execution process and reducing the overall execution efficiency.
[0026] The specific implementation of the present invention can be divided into the following steps:
[0027] Step 1: Implant a hardware Trojan into the NVLink control circuit of the host GPU, enabling it to sense the traffic characteristics of multiple NVLink ports in a continuous clock cycle, so as to form a traffic characteristic representation of the corresponding port for subsequent trigger condition determination.
[0028] Furthermore, the traffic characteristics described in step 1 are obtained through the NVLink port enable frequency.
[0029] Furthermore, the sensing process described in step 1 includes: recording whether any transactions arrive at each NVLink port in each clock cycle; classifying and identifying the transaction types; sampling the port's busy / idle status; and forming a statistical vector for the corresponding port within a preset time window. The statistical vector may include indicators such as the number of transactions, average arrival interval, transaction type percentage, and port busy duration.
[0030] Step 2: For the traffic characteristics of multiple ports obtained within a preset time window, the hardware Trojan calculates the correlation metric between each pair of ports. When the correlation metric between any pair of ports exceeds a preset threshold, the trigger condition is met, and delay control is performed on the target transaction of the corresponding port.
[0031] Furthermore, the correlation metric value described in step 2 is obtained through a cross-correlation function.
[0032] To further explain, when multiple ports exhibit a highly consistent trend in port activation frequency within the same time window, it typically reflects the presence of synchronous switching, centralized protocol implementation, or other cooperative communication behaviors in the current multi-GPU system. Therefore, triggering latency control under this condition is more likely to impact overall execution efficiency.
[0033] Step 3: After the Trojan triggering condition is met, the delay control logic applies an additional delay to the target transaction in the port corresponding to the triggering condition; the delay is preferentially applied to control transactions, atomic transactions and other transactions that are more sensitive to latency, so as to enhance the impact on the multi-GPU collaborative execution process.
[0034] To further explain, control transactions and atomic transactions typically involve processes such as synchronization control, access arbitration, status confirmation, or shared resource coordination. Increased latency in these transactions can more easily lead to an increase in the overall runtime of the computational task. Therefore, this invention applies a delay to these types of transactions to have a more significant impact on the overall task execution time with a smaller intervention scope.
[0035] Step 4: The delay control logic generates a set of random bit sequences and determines the corresponding delay intensity based on the position of the first bit with a value of "1" in the random bit sequence. The actual additional delay is then determined by the delay level and the preset base delay period. This method makes the applied delay non-uniformly random, thereby reducing the regularity of the delay behavior.
[0036] Step 5: Once the latency intensity is determined, the hardware Trojan adds a corresponding waiting period to the selected transaction during the transmission process on the NVLink port that meets the triggering conditions, so as to increase the completion latency of this type of transaction.
[0037] Furthermore, the waiting period described in step 5 has a practical physical timing meaning, corresponding to several consecutive clock cycles during the operation of the integrated circuit. During these consecutive clock cycles, the target transaction does not proceed to the subsequent process, thus delaying the actual completion time of the transaction.
[0038] To further explain, since this invention does not impose a uniform delay on all transactions, but only adds a waiting period to some latency-sensitive transactions according to a random delay level after the preset triggering conditions are met, the impact on the overall link utilization and average throughput is relatively small, while the synchronous waiting in the multi-GPU collaborative computing process is more likely to cause interference.
[0039] The present invention will be further described in detail below through specific embodiments. It should be understood that the embodiments provided below are only for the purpose of fully and completely disclosing the present invention and fully conveying the technical concept of the present invention to those skilled in the art. The present invention can also be implemented in many different forms and is not limited to the embodiments described herein.
[0040] In this embodiment, a multi-GPU platform comprising eight GPUs is constructed, with one GPU serving as the host GPU and implanting the hardware Trojan described in this invention. The GPUs are connected to adjacent nodes via four high-speed interconnect links, forming an interconnect topology. The time window length for determining the hardware Trojan trigger is set to 300 clock cycles, the correlation threshold is set to 0.995, and the base latency period is set to 200 clock cycles.
[0041] To further explain, in this embodiment, the correlation determination is performed by sliding within a fixed time window, that is, the correlation calculation of the port pair is performed once every 10 clock cycles; the length of the random bit sequence is set to 8 bits; when multiple port pairs meet the triggering condition at the same time, the port with the highest correlation metric value is selected as the object of delay action.
[0042] During multi-GPU collaborative computing tasks, multiple NVLink ports of the host GPU simultaneously participate in inter-GPU communication. A hardware trojan implanted in the host GPU continuously monitors the traffic characteristics of relevant ports within a time window and calculates the correlation metric between each pair of ports. When the correlation metric exceeds a preset threshold, a trigger condition is deemed met, and delay control is preferentially applied to control transactions, atomic transactions, and other latency-sensitive transactions in the corresponding port. After the corresponding delay control is completed, the hardware trojan returns to the monitoring state and continues to collect and analyze port traffic characteristics in subsequent time windows, waiting for the next trigger condition to be met.
[0043] In this embodiment, the latency control generates latency intensity through random bit sequence mapping, resulting in differences in the additional latency corresponding to different triggering events. This method can increase communication latency during multi-GPU collaborative computing while keeping the overall average link occupancy relatively small, thereby reducing the overall system execution efficiency.
[0044] To verify the technical effect of the present invention, under the same task load conditions, the task running time, number of hardware Trojan triggers and cumulative latency intensity were tested in the cases of no hardware Trojan and with hardware Trojan implanted, respectively. The results are shown in Table 1.
[0045] The results shown in Table 1 indicate that the task execution time was 7560 seconds without the hardware Trojan implanted; after implantation, the task execution time increased to 9676 seconds, an increase of 2116 seconds compared to the control, representing an increase of approximately 27.99%. Simultaneously, the hardware Trojan was triggered 20 times, with a cumulative latency intensity of 23. These results demonstrate that the hardware Trojan described in this invention can increase the total task execution time through a limited number of latency events during multi-GPU task execution, indicating that the triggering mechanism and latency control method can impact system execution efficiency. Table 1 Comparison of multi-GPU task execution time and triggering conditions before and after hardware Trojan implantation
[0046] To further explain, this invention performs sequential statistics on 20 trigger events generated when a hardware Trojan is implanted, recording the random bit sequence, delay strength, and corresponding additional delay for each trigger. Since the base delay period is set to 200 clock cycles in this embodiment, when the delay strength is 1, the corresponding additional delay is 200 clock cycles; when the delay strength is 2, the corresponding additional delay is 400 clock cycles. Table 2 Random sequence, latency intensity, and additional latency of 20 trigger events of the hardware Trojan.
[0047] As shown in Table 2, the 20 hardware Trojan triggers in this embodiment do not uniformly generate delays of the same intensity. Instead, the delay intensities vary based on the position of the first "1" bit in the random bit sequence. Specifically, delay intensity 0 is triggered 11 times, delay intensity 1 is triggered 2 times, delay intensity 2 is triggered 2 times, delay intensity 3 is triggered 4 times, and delay intensity 5 is triggered 1 time, resulting in a cumulative delay intensity of 23 and a cumulative additional delay of 4600 clock cycles. This result demonstrates that the delay control described in this invention exhibits randomness and non-uniformity, which helps reduce the regularity of hardware Trojan behavior and makes it more concealed.
[0048] Further analysis reveals that this invention does not rely on direct modification of communication content. Instead, it utilizes multi-port traffic characteristics for triggering and judgment, and imposes additional waiting periods on latency-sensitive transactions. Therefore, its operation primarily manifests as an increase in latency in the communication path between multiple GPUs, rather than a change in the link data content. This characteristic helps improve the stealth of hardware Trojan behavior.
[0049] In summary, this invention proposes a GPU-delayed hardware Trojan design method triggered by NVLink interconnects. This method continuously monitors the traffic characteristics of multiple interconnect ports on the host GPU and applies a delay to the target transaction when preset trigger conditions are met. This increases communication latency in multi-GPU collaborative computing without directly modifying the communication content and reduces the overall system execution efficiency.
[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the present invention. For those skilled in the art, any equivalent substitutions or improvements made without departing from the technical concept of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for designing a GPU latency-based hardware Trojan triggered by NVLink interconnect, characterized in that, Includes the following steps: Step 1: Implant a hardware Trojan into the NVLink control circuit of the host GPU to collect and statistically analyze the traffic characteristics of multiple NVLink ports of the host GPU within a preset time window; Step 2: Calculate the correlation metric between each pair of ports based on the traffic characteristic sequence corresponding to each NVLink port within the preset time window; Step 3: When the correlation metric between any group of NVLink ports exceeds a preset threshold, it is determined that the hardware Trojan trigger condition is met, and delay control is applied to the target port communication transactions corresponding to the trigger condition.
2. The GPU latency-based hardware Trojan design method for NVLink interconnect triggering according to claim 1, characterized in that, The traffic characteristic is the frequency of NVLink port activation.
3. The GPU latency-based hardware Trojan design method for NVLink interconnect triggering according to claim 1, characterized in that, The correlation metric is obtained through a cross-correlation function.
4. The GPU latency-based hardware Trojan design method for NVLink interconnect triggering according to claim 1, characterized in that, The delay control is preferentially applied to control transactions, atomic transactions, and other delay-sensitive transactions. The delay control does not parse the semantic content of interconnected transmission data, nor does it directly modify the communication payload. Instead, it is achieved by applying a delay to the transmission timing of the target transaction.
5. The GPU latency-based hardware Trojan design method for NVLink interconnect triggering according to claim 1, characterized in that, The delay control uses a random bit sequence mapping method to generate the delay intensity. The corresponding delay size is determined based on the position of the first "1" bit in the random bit sequence, so that the applied delay exhibits a non-uniform distribution characteristic.
6. The GPU latency-based hardware Trojan design method for NVLink interconnect triggering according to claim 5, characterized in that, it is set that... The randomly generated binary sequence is b1, b2, ..., b n When the first bit in the sequence that has a value of 1 is the k-th bit, the delay strength is k - 1; the actual additional delay is expressed as... , where D is the preset base delay period.