System-on-chip based peripheral attribute ordering method

Abstract

The application discloses a system-on-chip-based peripheral attribute sorting method, which comprises the following steps: establishing communication with peripherals mounted on a system bus through a bridge and distinguishing different types of peripherals; configuring the number of different peripheral attributes in each type of peripheral; and sorting the peripheral attributes of each type of peripheral according to the number of the same type of peripheral attribute. By executing the peripheral attribute sorting method, the system bus is mounted with multiple types of peripherals, and the different peripheral attributes in each type of peripheral are allowed to be configured and sorted according to the number of the same type of peripheral attribute, so that the automatic configuration of the different peripheral attributes in each type of peripheral is completed in the same type of peripheral attribute sorting mode of different peripherals, the peripheral system where the bridge is located is more universal, the demand of different chip interface design projects is compatible, and different application scenarios are adapted.

Description

Technical Field

[0001] This application relates to the technical field of system-on-a-chip design, and more particularly to a method for sorting peripheral attributes based on system-on-a-chip. Background Technology

[0002] Modern system-on-chip (SoC) designs are becoming increasingly complex, incorporating multiple processor cores, memory controllers, high-speed interfaces, and low-speed peripherals. Design teams need to manage a large number of modules and interfaces, and traditional manual configuration methods can no longer meet the demands of efficient design. Therefore, it is necessary to use a system bus to connect and manage different peripherals.

[0003] Chinese invention patent application CN202111298659.6 discloses a bus interface-based read controller. Utilizing a dedicated module for system startup and a dedicated module for initializing the SPI interface, the read controller can continuously read data from peripheral data memory under the corresponding operating mode of the SPI interface module, thus improving the speed of data reading from the data memory. While overcoming the drawback of requiring CPU intervention for each address access, the starting address parsed by the system bus interface module cannot initiate high-speed reading of external memory connected to other communication interfaces besides the SPI interface. This makes it difficult to be compatible with the requirements of different peripherals, and the read controller's lack of versatility for peripherals restricts the development efficiency of the system-on-a-chip (SoC) for multiple connected peripherals. Summary of the Invention

[0004] This application proposes a peripheral attribute sorting method based on a system-on-a-chip, and the specific technical solution is as follows: The peripheral attribute sorting method based on the system-on-a-chip includes: establishing communication with peripherals connected to the system bus via a bridge and distinguishing between different types of peripherals; configuring the number of different peripheral attributes in each type of peripheral; and sorting the peripheral attributes of each type of peripheral according to the number of peripheral attributes of the same type. In summary, by executing the peripheral attribute sorting method, not only can multiple types of peripherals be connected to the system bus, but it also allows for the configuration of different peripheral attributes in each type of peripheral and sorting according to the number of peripheral attributes of the same type. This enables automatic configuration of different peripheral attributes in each type of peripheral by sorting different peripherals by the same type of peripheral attribute, making the peripheral system where the bridge is located more universal, compatible with the needs of different chip interface design projects, and adaptable to different application scenarios. Furthermore, the peripheral connection and peripheral attribute configuration performed when executing the peripheral attribute sorting method both support parametric configuration, fully utilizing EDA tools for automated configuration and hardware generation, reducing manual modification of hardware design, and improving design efficiency and quality.

[0005] Furthermore, the method for configuring the number of different peripheral attributes in each type of peripheral includes: configuring at least the number of peripherals in each type of peripheral, the number of interrupts for each peripheral in each type of peripheral, the number of DMA channels for each peripheral in each type of peripheral, the number of input signals for each peripheral in each type of peripheral, the number of output signals for each peripheral in each type of peripheral, and the number of enable signals for each peripheral in each type of peripheral; wherein, a peripheral attribute is a base address, or an interrupt, or a DMA channel, or an input signal, or an output signal, or an enable signal; wherein, the number of peripheral attributes of the same type is the number of base addresses, or the number of interrupts, or the number of DMA channels, or the number of input signals, or the number of output signals, or the number of enable signals. Based on this, according to the number of peripheral attributes of the same type, the peripheral attributes of each type of peripheral are sorted to form peripheral address sequences, peripheral interrupt sequences, DMA channel sequences, input signal sequences, output signal sequences, and enable signal sequences, respectively. Each sequence is instantiated into the bridge in the order of the peripheral attributes of the attached peripherals.

[0006] Further, the method for sorting the peripheral attributes of each type of peripheral according to the number of peripheral attributes of the same type includes: Step A1, setting the order between different types of peripherals connected to the system bus; then executing Step A2; Step A2, determining whether the sorting of peripheral attributes of the same type has been completed in all types of peripherals connected to the system bus, if yes, ending, otherwise executing Step A3; Step A3, determining whether the sorting of peripheral attributes of the same type has been completed in the sorted i-th type of peripheral, if yes, executing Step A5, otherwise executing Step A4; Step A4, in the sorted i-th type of peripheral, starting from the i-th peripheral attribute number, sorting the peripheral attributes of the same type of peripheral of each peripheral according to the number of peripheral attributes of the same type, sequentially obtaining the peripheral attributes of the sorted i-th type of peripheral. The sequence number of the same type of peripheral attribute of each peripheral is determined, and the sorting of the same type of peripheral attribute is completed in the sorted i-th type of peripheral; then step A2 is executed; step A5: calculate the sequence number of the same type of peripheral attribute of the first-ranked peripheral in the sorted i+1 type of peripheral, obtain the i+1 peripheral attribute sequence number, update the i+1 peripheral attribute sequence number to the i-th peripheral attribute sequence number, update the sorted i+1 type of peripheral to the sorted i-th type of peripheral, update the number of peripherals in the sorted i+1 type of peripheral to the number of peripherals in the sorted i-th type of peripheral, and then execute step A4; where i is an integer greater than or equal to 1; where the number of the same type of peripheral attribute configured in each peripheral in the same type of peripheral is equal. In summary, by repeatedly executing steps A2 to A5, the peripheral attributes of the same type of peripheral can be further sorted among the pre-sorted peripherals of various types, thereby achieving the sorting of all types of peripheral attributes of all peripherals mounted on the system bus.

[0007] Further, in step A4, in sorting the i-th type of peripherals, starting from the i-th peripheral attribute index, the peripheral attributes of the same type of each peripheral are sorted according to the number of peripheral attributes of the same type, and the method for obtaining the index of the peripheral attribute of the same type of each peripheral in the sorted i-th type of peripherals includes: in sorting the i-th type of peripherals, configuring the first index of the peripheral attribute of the same type of the j-th peripheral as the index of the i-th peripheral attribute; then, starting from the index of the i-th peripheral attribute, each increment of the value by 1 yields the index of one peripheral attribute of the same type of peripheral, until the number of incremented indexes reaches the sorting level. The difference between the number of the same type of peripheral attributes configured in each peripheral of the i-th type and the value 1 is calculated. Then, the latest obtained sequence number is added to the value 1, and the result of the addition is configured as the first sequence number of the same type of peripheral attribute of the (j+1)-th peripheral. This process continues until the number of sequence numbers of the same type of peripheral attributes configured successively is equal to the difference between the product of the number of peripherals of the i-th type of peripheral and the number of the same type of peripheral attributes configured in each peripheral of the i-th type of peripheral and the value 1. Then, the sorting of the same type of peripheral attributes of each peripheral of the i-th type of peripheral is completed. Here, j is an integer greater than or equal to 1.

[0008] In summary, in the sorting of peripherals of the i-th type, starting from the i-th peripheral attribute index, the index of each peripheral attribute in the same type is obtained by incrementing the value by 1. Then, in the sorting of peripherals of the i-th type, after completing the sorting of all peripheral attributes in the same type of peripheral attributes of the j-th peripheral, the index of the i-th peripheral attribute is updated by incrementing the value by 1. This process is repeated iteratively according to the number of peripheral attributes of the same type in the sorting of peripherals of the i-th type, until the sorting of peripheral attributes of the same type of peripherals in the sorting of peripherals of the i-th type is completed.

[0009] Further, after sorting the peripheral attributes of the same type in the i-th type of peripherals, the latest obtained sequence number is added to the value 1 to obtain the (i+1)-th peripheral attribute sequence number in step A5. The (i+1)-th peripheral attribute sequence number in step A5 is equal to the sum of the product of the number of peripherals of the i-th type of peripherals and the number of peripheral attributes of the same type configured in the i-th type of peripherals, and the i-th peripheral attribute sequence number. Thus, the process switches from sorting the i-th type of peripherals to sorting the (i+1)-th type of peripherals. Steps A4 and A5 are then executed to sort the peripherals of the (i+1)-th type of peripherals, and the difference between the first sequence numbers of the same type of peripheral attributes in adjacent types of peripherals is determined to be equal to the product of the number of peripherals of the i-th type of peripherals and the number of peripheral attributes of the same type configured in the i-th type of peripherals.

[0010] Furthermore, in step A4, if the peripheral attributes of the same type that are sorted are the base addresses of the peripherals, then in the peripherals of the same type, the quantity of the same type of peripheral attributes in each peripheral is configured to be equal to the value 1, and the number of peripherals is configured to be 1. If the peripheral of the same type is the first type of peripheral in the sorting, then the first peripheral attribute number is configured to the value 0. At this time, the base address assigned to the first type of peripheral in the sorting is equal to binary 0. Then, by executing steps A1 to A5, the i-th peripheral attribute number is configured to i-1. Then, the i-th peripheral attribute number is converted into a binary number, and then the converted binary number is assigned to the base address in the order of high bits to low bits, so that the base addresses of the various types of peripherals connected to the system bus are sorted in ascending order according to the size relationship of the binary numbers within the same bit range.

[0011] Furthermore, in step A4, if the peripheral attributes of the same type that are sorted are interrupts of the peripheral, then: in the first type of peripheral that is sorted, the first peripheral attribute number is configured as interrupt number 0; then, by executing steps A1 to A5, the i-th peripheral attribute number is configured as interrupt number i-1; wherein, the number of peripherals of each type of peripheral is equal to the value 1; the number of peripheral attributes of the same type configured for each peripheral in each type of peripheral is the number of interrupts, and the number of interrupts is equal to the bit width of the corresponding interrupt signal; the number of interrupts pre-allocated by the CPU to each type of peripheral is greater than or equal to the value 1, so that each type of peripheral gets at least one interrupt number.

[0012] Furthermore, in step A4, if the peripheral attributes of the same type being sorted are DMA channels of the peripherals, then: in the first type of peripheral being sorted, the first peripheral attribute number is configured as DMA channel number 0; then, by executing steps A1 to A5, the i-th peripheral attribute number is configured as DMA channel number i-1; wherein, the number of peripherals of each type of peripheral is equal to the value 1; the number of peripheral attributes of the same type configured for each type of peripheral is the number of DMA channels; in each type of peripheral, the number of DMA channels of each peripheral is greater than or equal to the value 0, so that one peripheral can interact with another peripheral through its DMA channel or prevent one peripheral from interacting with other peripherals.

[0013] Furthermore, if the peripheral attributes of each type of peripheral are input signals, output signals, or enable signals, and the number of the same type of peripheral attribute configured for each type of peripheral is equal to the number of input signals, output signals, or enable signals, then the following applies: If the input signals of the same peripheral are obtained from a batch of AFIO pins, and the output signals of the same peripheral are output to another batch of AFIO pins, then the number of input signals of the same peripheral is not equal to the number of output signals configured for the same peripheral; wherein, the enable signal of the same peripheral is used to control the output of the same peripheral configured output signal from the other batch of AFIO pins; the number of input signals of the same peripheral is greater than or equal to 0. This ensures normal signal interaction between each type of peripheral and the system bus, avoiding pin multiplexing conflicts between multiple input / output signals of the same peripheral.

[0014] Furthermore, if the input signal of the same peripheral is obtained from a batch of AFIO pins, it is determined that the GPIO pins with input function in the same peripheral are controlled by the CPU, and the batch of AFIO pins is determined to be a batch of spare pins in the same peripheral, wherein the batch of spare pins is multiplexed to transmit the input signal; if the output signal of the same peripheral is output to another batch of AFIO pins, it is determined that the GPIO pins with output function in the same peripheral are controlled by the CPU, and the other batch of AFIO pins is determined to be another batch of spare pins in the same peripheral, wherein the other batch of spare pins is multiplexed to transmit the output signal. Thus, multiple AFIO pins are used to achieve functional remapping of GPIO pins.

[0015] Furthermore, in step A1, when establishing communication with the various peripherals connected to the system bus via the bridge, the peripherals currently required to be started and those currently disabled are identified among the peripherals connected to the system bus. Then, different types of peripherals and their order are distinguished from the identified peripherals currently required to be started. This ensures that when the bridge performs a write operation, it sequentially sends data from other speeds of the system bus to the peripherals of the required type, and when the bridge performs a read operation, it sequentially sends data output from the peripherals of the required type to other speeds of the system bus.

[0016] Furthermore, in step A1, when serial communication interface devices exist among the different types of peripherals connected to the system bus, the order of these peripherals is as follows: SPI0 interface device, SPI1 interface device, QSPI interface device, UART interface device, USART interface device, and I2C interface device. Within the same type of peripheral, the number of interrupts configured for each peripheral is equal to 1, and the number of DMA channels configured for each peripheral is equal to 2. The number of peripherals for each type is equal to 1. In summary, step A1 sorts the different types of serial communication interface devices according to their functional completeness, the number of communication signals, and the complexity of the executed commands.

[0017] Further, in step A1, when different types of peripherals connected to the system bus have timers, the order of the peripherals is: BFTM timer, EBFTM timer, GPTM timer, and MCTM timer; the timer ranked first is configured to be arranged after the I2C interface device. During the repeated execution of steps A2 to A5, the peripheral attributes of each peripheral of the same type are sorted within each peripheral, and then the sorting of the peripheral attributes of each peripheral of the same type is completed sequentially within each type of timer. Based on this, according to the completeness of the counting function, the quantity of communication signals and PWM signals generated, and the complexity of executing timing commands, the sorting configuration of the peripheral attributes of each type of peripheral for SPI0 interface devices, SPI1 interface devices, QSPI interface devices, UART interface devices, USART interface devices, I2C interface devices, BFTM timer, EBFTM timer, GPTM timer, and MCTM timer is completed. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a peripheral system built by various types of peripherals connected by an APB bridge and its host interface, as disclosed in an embodiment of this application.

[0019] Figure 2This is a flowchart illustrating a peripheral attribute sorting method based on a system-on-a-chip, which is another embodiment of this application.

[0020] Figure 3 This is a flowchart illustrating a method for sorting the attributes of peripherals of the same type in a sorting type i, as disclosed in another embodiment of this application. Detailed Implementation

[0021] The present application will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, intended only to illustrate the basic concept of the present application, and therefore only show the method steps relevant to the present application.

[0022] Considering that the same basic chip design can be used for multiple project developments, it needs to adapt to different project requirements and reduce the need to redesign circuit hardware for each project, thus minimizing manual coding errors. Parametric configuration is necessary to support multi-project reuse and to automatically generate hardware description files. Furthermore, automated tools can be used to verify the correctness of parameter configurations, ensuring design quality. Parametric configuration also allows for dynamic adjustment of the number of peripherals connected to each bus without redesigning the hardware. It allows for the allocation of the base address and address range of each peripheral to adapt to different system requirements. It also allows for dynamic adjustment of the bit width of the data bus, address bus, and control signals to accommodate different peripheral requirements. New peripherals can be added or replaced by modifying parameter configuration files without altering the underlying hardware design. Parametric configuration allows for the integration of each peripheral into the system. It also allows for debugging and maintaining system configurations, improving maintainability. Dynamic adjustment of the number of peripherals and address space based on actual needs avoids resource waste. Finally, parametric configuration allows for finer management of clock gating and power management, reducing power consumption.

[0023] Based on this, this application discloses a peripheral attribute sorting method based on a system-on-a-chip (SoC). The executing entity of the peripheral attribute sorting method based on the SoC is a bridge or the peripheral system in which the bridge resides. (See reference...) Figure 1 As can be seen, when the bridge is an APB bridge, the peripheral system where the APB bridge is located can connect each peripheral to the system bus of the AMBA architecture to form a system-on-a-chip, which is also convenient for parameterized configuration. In the system-on-a-chip, the APB bridge can be understood as a slave of the AHB bus, and at the same time, the APB bridge is the master of the APB bus.

[0024] Combination Figure 2 It can be seen that the peripheral attribute sorting method includes: This application establishes communication with peripherals connected to the system bus via a bridge, distinguishes different types of peripherals, and identifies different types of peripherals on the connected system bus, all of which belong to peripherals to be sorted / configured, so as to facilitate parameterized configuration through interaction with external buses with different transmission rates. For mounting / configuring low-speed peripherals, an APB bridge is used, and the system bus for mounting the peripherals uses an APB bus; conversely, for mounting / configuring peripherals supporting high-speed transmission, an AHB bridge is used, and the system bus for mounting the peripherals uses an AHB bus. Preferably, as follows... Figure 1 As shown, the APB bridge uses multiple APB-Ms to connect different peripherals. Each peripheral is connected to the APB bus and its type is distinguished. Different types of peripherals interact with the AHB bus through the APB bridge. The APB-M represents the host interface of the APB bus relative to the peripheral. Figure 1 In the peripheral system, various low-speed and low-power peripheral devices and internal modules are mounted to the peripheral system through the APB bridge, which can realize data communication between the AHB bus, APB bus and peripherals, reduce the requirements and development difficulty for technicians, and shorten the cycle required to build the APB subsystem-level parameter configuration platform.

[0025] Based on the distinction between the types of peripherals connected to the system bus, the number of different peripheral attributes within each type of peripheral is configured. Each type of peripheral is configured with different peripheral attributes, and each type of peripheral attribute is configured with a certain number of attributes. Therefore, the configuration of all types of peripherals for the same peripheral attribute can be encapsulated into a sequence. Both the peripheral type and the type of peripheral attribute can be predefined in the corresponding host interface of the system bus to be connected. It should be noted that in configuring the number of different peripheral attributes for each type of peripheral, the peripheral attributes of multiple peripheral modules of the same type can be configured cyclically by parameterizing the different peripheral attributes within each type of peripheral. For the same type of peripheral, peripheral attributes such as bus data width, address width, peripheral type, quantity, base address, address space, DMA channel, interrupt, and signals output to mapped pins can be configured.

[0026] Indicatively, such as Figure 1As shown, the peripherals connected to the APB bus are SPI0 interface devices, SPI1 interface devices, QSPI interface devices, UART interface devices, USART interface devices, I2C interface devices, BFTM timer, EBFTM timer, GPTM timer, MCTM timer, and DTIMER timer. They are connected to the APB bus through an APB-M in the corresponding order, and then parameterized and interacted with the AHB bus through the APB bridge. Among them, peripherals of each type, including SPI0 interface devices, SPI1 interface devices, QSPI interface devices, UART interface devices, USART interface devices, I2C interface devices, BFTM timer, EBFTM timer, GPTM timer, MCTM timer, and DTIMER timer, are connected to the APB bus in a certain number. Moreover, each peripheral in each type is configured with a certain number of peripheral attributes. For example, there are 3 SPI0 interface devices connected to the APB bus. Each SPI0 interface device is configured with at least 3 DMA channels and 2 interrupt sources, and also supports 4 input signals and 4 output signals. The parameter information of the attributes of each type of peripheral is configurable, and the number of peripherals connected is also configurable.

[0027] Based on the number of peripheral attributes of each type in the same type of peripheral, the peripheral attributes of each type of peripheral are sorted according to the number of peripheral attributes of the same type. At least the storage order of the peripheral attributes of each type of peripheral in the same address space is configured. Then, the peripheral attributes of the same type of peripheral of each peripheral can be automatically defined into a peripheral attribute sequence. Schematic, the peripheral attributes of the same type of peripheral in each type of peripheral are formed into a peripheral attribute sequence in the order of SPI0 interface device, SPI1 interface device, QSPI interface device, UART interface device, USART interface device, I2C interface device, BFTM timer, EBFTM timer, GPTM timer, MCTM timer, and DTIMER timer. Based on this, the automatic sorting of signals included in the peripheral attributes of each type of peripheral can be supported, and the orderly connection of interfaces of different peripherals can also be controlled, so as to facilitate the instantiation of the peripheral system in the EDA (Electronic Design Automation) tool and the read and write scheduling of various types of peripherals connected to the system bus.

[0028] In summary, by executing the peripheral attribute sorting method, not only can multiple types of peripherals be mounted on the system bus, but it also allows for the configuration of different peripheral attributes within each type of peripheral and sorting based on the quantity of peripheral attributes of the same type. This enables automatic configuration of different peripheral attributes within each type of peripheral by sorting them by the same type of peripheral attribute, making the peripheral system where the bridge resides more versatile, compatible with the needs of different chip interface design projects, and adaptable to different application scenarios. Moreover, the peripheral mounting and peripheral attribute configuration performed when executing the peripheral attribute sorting method both support parametric configuration, fully utilizing EDA tools for automated configuration and hardware generation, reducing manual modifications to hardware design, and improving design efficiency and quality.

[0029] Specifically, the method for configuring the number of different peripheral attributes in each type of peripheral includes: configuring at least the number of peripherals in each type of peripheral, the number of interrupts for each peripheral in each type of peripheral, the number of DMA channels for each peripheral in each type of peripheral, the number of input signals for each peripheral in each type of peripheral, the number of output signals for each peripheral in each type of peripheral, and the number of enable signals for each peripheral in each type of peripheral; it is understood that each peripheral in the same type of peripheral that needs to be configured is a peripheral to be sorted / peripheral to be configured, and they are peripherals of the same type to be sorted. Configure / to be configured peripherals; the number of peripherals in each type of peripheral is the total number of peripherals in the same type of peripheral. The number of peripherals in a type of peripheral is 1. A peripheral in a type of peripheral can be configured with multiple interrupts, multiple DMA channels, multiple input signals, multiple output signals, or multiple enable signals. Therefore, the number of DMA channels, the number of input signals, the number of output signals, and the number of enable signals of each peripheral in each type of peripheral are specifically configured.

[0030] Each type of peripheral or each peripheral device mounted on the system bus is pre-configured, corresponding to Figure 1 In this system, the system bus used to mount different types of peripherals to be sorted is the APB bus. Each type of peripheral or each peripheral can be automatically selected by the APB bridge or configured after receiving instructions transmitted by the AHB bus, so as to realize the classification and attribute information allocation of peripherals and meet the requirements of generality and multiplexing.

[0031] The peripheral attributes of each peripheral device are: base address, interrupt, DMA channel, input signal, output signal, or enable signal. The number of peripheral attributes of the same type is the number of base addresses, interrupts, DMA channels, input signals, output signals, or enable signals; all of these are configurable options in the bridge. Based on this, the peripheral attributes of each type of peripheral device are sorted according to the number of peripheral attributes of the same type, forming peripheral address sequences, peripheral interrupt sequences, DMA channel sequences, input signal sequences, output signal sequences, and enable signal sequences, respectively. Each sequence is instantiated into the bridge in the order of the peripheral attributes of the connected peripheral devices.

[0032] As one embodiment, the method of sorting peripheral attributes of each type of peripheral according to the number of attributes of the same type is as follows: Figure 3 As shown, it includes: Step A1: Set the order of different types of peripherals connected to the system bus to distinguish between the i-th type of peripheral and the (i+1)-th type of peripheral; then execute step A2. Based on the completeness of functionality, the number of communication signals, and the complexity of executed commands, the order of different types of peripherals can be set as: serial peripheral interface, synchronous / asynchronous transceiver, bidirectional two-wire synchronous serial bus interface, basic timer, timer for outputting PWM waves, and timers with more complex and comprehensive functions. Two peripherals in an adjacent order can be represented by the i-th type of peripheral and the (i+1)-th type of peripheral.

[0033] Step A2: Determine whether the sorting of the same type of peripheral attributes has been completed in all types of peripherals connected to the system bus. If yes, the process ends; otherwise, proceed to step A3. Therefore, when it is detected that the peripheral attributes of each type of peripheral (which can be uniformly low-speed transmission peripheral devices) connected to the system bus have been sorted according to the number of peripheral attributes of the same type, the execution of the peripheral attribute sorting method ends.

[0034] Step A3: Determine whether the sorting of peripheral attributes of the same type has been completed in the sorted i-th type of peripherals. If yes, proceed to step A5 to traverse the peripheral attributes of the same type of peripherals in the sorted (i+1)-th type of peripherals. Otherwise, proceed to step A4. Thus, if the sorting of peripheral attributes of the same type has not been completed in all types of peripherals connected to the system bus, determine whether the sorting of peripheral attributes of the same type of peripherals in the currently sorted i-th type of peripherals has been completed.

[0035] Step A4: In the sorting of peripherals of type i, starting from the attribute number of peripheral i, sort the peripheral attributes of the same type of peripherals according to the number of peripheral attributes of the same type, and obtain the index of the peripheral attributes of the same type of peripherals of each peripheral in the sorting of peripherals of type i. Specifically, the index of each peripheral attribute of the same type of peripheral, and determine that the sorting of peripheral attributes of the same type of peripheral is completed in the sorting of peripherals of type i. The index of each type of peripheral attribute of each peripheral in the sorting of peripherals of type i represents the sorting position of each type of peripheral attribute in a one-address space; then execute step A2.

[0036] In step A4, among the peripherals of the same type sorted i, the attribute number of the i-th peripheral can be equivalent to the index or base address index of the peripheral sorted first. Starting from the attribute number of the i-th peripheral, the offset of the same type of peripheral attribute for each peripheral is set sequentially by incrementing a counter, which serves as its index. This can be understood as follows: each time a peripheral is added to the system bus, the offset of each peripheral attribute of the same type is incremented by one. The number of times the counter is incremented for each peripheral is equal to the difference between the number of peripheral attributes of the same type and the value 1, until the number of increments equals the difference between the number of peripherals of the i-th type sorted peripheral and the value 1. This completes the sorting of peripheral attributes of the same type among the i-th type of peripherals. Note that the number of the same type of peripheral attributes configured for each peripheral in the same type is equal.

[0037] It should be noted that the number of the same type of peripheral attributes configured in each peripheral of the same type in the i-th sorted peripheral is equal. This can be understood as follows: for the first peripheral of the same type in the first sorted peripheral, the index of its same type of peripheral attribute starts from 0 and increases to the difference between the number of the same type of peripheral attributes configured in the first peripheral and the value 1. For the second peripheral of the same type in the first sorted peripheral, the index of its same type of peripheral attribute starts from the number of the same type of peripheral attributes and increases by the difference between the number of the same type of peripheral attributes configured in the second peripheral and the value 1, and so on, incrementing by one, to complete the sorting of the same type of peripheral attributes of each peripheral in the i-th sorted peripheral. Here, i is an integer greater than or equal to 1.

[0038] Step A5: Calculate the serial number of the peripheral attribute of the first-ranked peripheral in the (i+1)th type of peripheral, and obtain the (i+1)th peripheral attribute serial number. Then configure the serial number or base address serial number of the first-ranked peripheral in the (i+1)th type of peripheral. Next, update the (i+1)th peripheral attribute serial number to the (i)th peripheral attribute serial number, update the (i+1)th type of peripheral to the (i)th type of peripheral, and update the number of peripherals in the (i+1)th type of peripheral to the number of peripherals in the (i)th type of peripheral. Then execute step A4 to sort the peripheral attributes of the same type of peripheral in the (i+1)th type of peripheral.

[0039] In summary, by repeatedly executing steps A2 to A5, the peripheral attributes of the same type of peripheral can be further sorted among the pre-sorted peripherals of various types, thereby achieving the sorting of all types of peripheral attributes of all peripherals mounted on the system bus.

[0040] It should be noted that while the number of the same type of peripheral attributes configured in each peripheral of type i+1 is equal, the number of the same type of peripheral attributes configured in each peripheral of type i is not necessarily equal to the number of the same type of peripheral attributes configured in each peripheral of type i+1. Therefore, the number of the same type of peripheral attributes configured in each peripheral of type i+1 still needs to be updated to the number of the same type of peripheral attributes configured in each peripheral of type i.

[0041] Specifically, in step A4 above, in sorting the i-th type of peripherals, starting from the i-th peripheral attribute number, the peripheral attributes of the same type of each peripheral are sorted according to the number of peripheral attributes of the same type, and the method for obtaining the serial numbers of the peripheral attributes of the same type of each peripheral in the sorted i-th type of peripherals includes: in sorting the i-th type of peripherals, taking the first serial number of the peripheral attribute of the same type of the j-th peripheral (when starting to sort the peripheral attributes of the i-th type of peripherals, it is equivalent to sorting the j-th peripheral attribute of the j-th peripheral) The serial number of the peripheral attribute is configured as the serial number of the i-th peripheral attribute. Then, starting from the serial number of the i-th peripheral attribute, the serial number is incremented by 1 each time, i.e., the count is incremented once. This yields the serial number of one peripheral attribute of the same type. The address offset generated by incrementing the serial number by 1 is the address offset allowed by the address space lock of the peripheral of the same type that belongs to the i-th sorted peripheral. When the serial number is incremented by 1 in the hardware, a counter register is used to count to maintain the automatic execution of the command corresponding to the serial number increment. The serial number 1 can be selected as the binary number 1.

[0042] In the sorted i-th type of peripheral, starting from the i-th peripheral attribute number, the number of peripheral attributes of the same type is incremented by 1 sequentially until the number of incremented numbers reaches the difference between the number of peripheral attributes of the same type configured in each peripheral in the sorted i-th type of peripheral and the value 1, thus completing the sorting of all peripheral attributes of the same type in the j-th peripheral. Then, the newly obtained sequence number is added to the value 1, and the result is configured as the first sequence number of the same type peripheral attribute of the (j+1)th peripheral, so that the absolute value of the difference between the sequence numbers of the same type peripheral attribute of two adjacent peripherals is equal to the number of the same type peripheral attributes configured in each peripheral of the i-th type of peripheral in the sorting. Then, the first sequence number of the same type peripheral attribute of the (j+1)th peripheral can be updated to the sequence number of the i-th peripheral attribute, and the value is incremented by 1 in the same type of peripheral in the i-th sorting according to the number of the same type peripheral attributes, until the number of the increased sequence numbers reaches the number of the same type peripherals configured in each peripheral of the i-th sorting. The difference between the number of peripheral attributes of the same type and the value 1 is used to sort all peripheral attributes of the same type in the (j+1)th peripheral of the i-th type of peripheral; where j is an integer greater than or equal to 1; this process is repeated iteratively until j increases from the value 1 to the number of peripherals of the i-th type of peripheral. The number of the sequence numbers of the same type of peripheral attributes configured successively is equal to the difference between the product of the number of peripherals of the i-th type of peripheral and the number of the same type of peripheral attributes configured in the i-th type of peripheral and the value 1. Then, it is determined that the same type of peripheral attributes of each peripheral in the i-th type of peripheral are sorted. Therefore, in the peripherals of the i-th type of sorting, starting from the i-th peripheral attribute index, the index of each peripheral attribute in the same type of peripheral attribute is obtained by incrementing the value by 1. Then, in the peripherals of the i-th type of sorting, after sorting all peripheral attributes in the same type of peripheral attribute of the j-th peripheral, the index of the i-th peripheral attribute is updated by incrementing the value by 1. In the peripherals of the i-th type of sorting, the value is incremented by 1 according to the number of peripheral attributes of the same type. This process is repeated iteratively to complete the sorting of the peripheral attributes of the same type of peripherals in the peripherals of the i-th type of sorting.

[0043] It should be noted that the number of peripherals of the same type in the i-th sorted peripheral is pre-configured. It can be understood that by iterating through the difference between the number of peripherals and the value 1 times, each peripheral in the i-th sorted peripheral of the same type can be generated, and the same type of peripheral attributes in each peripheral are also generated iteratively. For example, to generate two I2C interface devices, the data signal SDA and clock signal SCL (two external parameter attributes of the same type) required to output the I2C interface device number 1 are numbered 1 and 2 in the system bus (since the I2C interface device is connected, the system bus can be the APB bus). Then, the data signal SDA and clock signal SCL (two external parameter attributes of the same type) required to output the I2C interface device number 2 are numbered 3 and 4 in the system bus. This completes the sorting of the same type of external parameter attributes in the two I2C interface devices of the same type.

[0044] In the above embodiment, after sorting the peripheral attributes of the same type in the peripherals of the i-th type, the latest obtained sequence number is added to the value 1 to obtain the (i+1)-th peripheral attribute sequence number in step A5. The (i+1)-th peripheral attribute sequence number in step A5 is equal to the sum of the product of the number of peripherals of the same type in the i-th type and the number of peripheral attributes of the same type configured in the i-th type of peripherals, and the i-th peripheral attribute sequence number. Thus, the peripherals are switched from the i-th type to the (i+1)-th type. Then, steps A4 and A5 are executed to sort the peripherals of the (i+1)-th type, and the difference between the first sequence number of the same type peripheral attribute in the two types of peripherals in adjacent orders is determined to be equal to the product of the number of peripherals of the same type in the i-th type and the number of peripheral attributes of the same type configured in the i-th type of peripherals.

[0045] Based on the steps provided in the foregoing embodiments, when the peripheral attributes of the same type that are sorted in step A4 are the base addresses of the peripherals, in the peripherals of the same type, the number of peripheral attributes of the same type in each peripheral is configured to be equal to the value 1, and the number of peripherals is configured to be the value 1, that is, there is only 1 peripheral and one base address in each type of peripheral; then the serial number of the peripheral attribute of the same type is the serial number of the base address.

[0046] When a peripheral of the same type is the first type of peripheral in the sorting, the attribute number of the first peripheral is configured to the value 0. At this time, the base address assigned to the first type of peripheral is equal to binary 0. Then, by executing steps A1 to A5, the first type of peripheral is sorted to the i-th type of peripheral. i will increase as the number of peripherals connected to the system bus increases, and the base address of the peripheral will also increase accordingly. In the i-th type of peripheral, the attribute number of the i-th peripheral is configured to i-1 (i may be greater than or equal to decimal 2). The attribute number of the i-th peripheral is then converted into a binary number, and the converted binary number is assigned to the base address in the order of high bits to low bits. For example, the binary number converted from the attribute number of the i-th peripheral is fixedly assigned to the bit range of [15:12] of the base address, and the base address is sorted according to this bit range to obtain the unique base address number of each peripheral of the same type.

[0047] Since in sorting the i-th type of peripherals, starting from the base address of the first peripheral in the sorting, by executing steps A1 to A5, the count is incremented by one in turn to obtain the sequence number of the base address of each peripheral. The difference between the base addresses of two peripherals in adjacent sequences is equal to the value 1. This completes the sorting of each peripheral in sorting the i-th type of peripherals, thereby making the base addresses of each type of peripheral connected to the system bus sorted in ascending order according to the binary value relationship within the same bit range.

[0048] Based on the steps provided in the foregoing embodiments, in step A4, when the peripheral attribute of the same type being sorted is the interrupt of the peripheral, the number of peripheral attributes of the same type in each peripheral of the same type is not necessarily equal to the value 1. The number of peripherals of each type is equal to the value 1, meaning there is only one peripheral in each type. The sequence number of the peripheral attribute of the same type is the interrupt number. Since the interrupt signal of each peripheral connected to the system bus is different, the interrupt numbers configured for different peripherals are not equal.

[0049] In the first type of peripheral, the attribute number of the first peripheral is configured as interrupt number 0. Then, by executing steps A1 to A5, peripherals of the i-th type are sorted from the first type, where i increases with the number of peripherals connected to the system bus, and the interrupt numbers of each interrupt in each type of peripheral also increase accordingly. In the i-th type of peripheral, the attribute number of the i-th peripheral is configured as interrupt number i-1. Each interrupt number can be assigned as a unique identifier for an interrupt source of a peripheral. The interrupt number is bound to the corresponding driver so that the handler in the corresponding peripheral can be called when the CPU triggers an interrupt. In some systems, interrupt numbers are also used to manage interrupt priorities, ensuring that high-priority interrupts are processed first.

[0050] In step A4, when the peripheral attributes of the same type are sorted as interrupts, the number of peripheral attributes of the same type configured for each type of peripheral is the number of interrupts or interrupt numbers. The number of interrupts is equal to the bit width of the corresponding interrupt signal. The number of interrupts pre-allocated by the CPU to each type of peripheral is greater than or equal to the value 1, so that each type of peripheral gets at least one interrupt number. Furthermore, by executing steps A1 to A5, the interrupt numbers obtained by each peripheral in sequence are different from each other, so as to trigger the CPU to execute different interrupt handling instructions in sequence.

[0051] Based on the steps provided in the foregoing embodiments, when the peripheral attributes of the same type sorted in step A4 are DMA channels of the peripheral, the number of peripheral attributes of the same type in each peripheral is configured to be mostly equal to the value 2, and the number of peripherals in each type is equal to the value 1, that is, there is only 1 peripheral in each type of peripheral; the serial number of the peripheral attribute of the same type is the DMA channel number. The DMA channels of each peripheral connected to the system bus are independent of each other, so the DMA channel numbers configured for different peripherals are not equal.

[0052] In the first type of peripheral, the attribute number of the first peripheral is configured as DMA channel number 0. Then, by executing steps A1 to A5, peripherals of type i are sorted from the first type of peripheral. i increases with the number of peripherals connected to the system bus, and the DMA channel numbers of each type of peripheral also increase accordingly. In the i-th type of peripheral, the attribute number of the i-th peripheral is configured as DMA channel number i-1. It should be noted that DMA (Direct Memory Access) provides high-speed data transfer between peripherals and memory, and between memory devices. It allows hardware devices of different speeds to communicate without relying on the CPU. During this time, the CPU cannot use memory for its own purposes.

[0053] In step A4, if the peripheral attributes of the same type that are sorted are the DMA channels of the peripheral, the number of peripheral attributes of the same type configured for each type of peripheral is the number of DMA channels. In each type of peripheral, the number of DMA channels of each peripheral is greater than or equal to the value 0. This allows a single peripheral to be configured with multiple DMA channels or not to be configured with DMA channels, so that one peripheral can interact with another peripheral through its DMA channel or prevent one peripheral from interacting with other peripherals.

[0054] Preferably, twice the number of DMA channels for the same peripheral is equal to the bit width of the signal required for DMA communication by the same peripheral, so that when the peripheral is a serial communication device, the number of DMA channels of the serial communication device is equal to the value 2. Each DMA channel supports software triggering and specific hardware triggering (the hardware trigger source is different for each DMA channel). Memory-to-memory transfers generally use software triggering, while peripheral-to-memory data transfers generally use hardware triggering.

[0055] When the number of the same type of peripheral attributes configured in each type of peripheral is the number of DMA channels, if the sum of the number of response signals and request signals required by the same peripheral for DMA communication changes, then the number of DMA channels configured in the same peripheral changes; preferably, the number of response signals required by the same peripheral for DMA communication is greater than or equal to 0, and the number of request signals required by the same peripheral for interaction through DMA communication is greater than or equal to 0.

[0056] Based on the steps provided in the foregoing embodiments, it is known that when the peripheral attributes of each type of peripheral are input signals, output signals, or enable signals, and the number of the same type of peripheral attributes configured for each type of peripheral is the number of input signals, the number of output signals, or the number of enable signals, the following exists: To illustrate, within the same type of peripheral, there is no limit to the number of peripheral attributes of the same type in each peripheral, and by default there is only 1 peripheral in each type of peripheral.

[0057] In step A4, when the peripheral attributes of the same type are input signals, the serial number of the peripheral attribute of the same type is the serial number of the input signal. The input signals of each peripheral connected to the system bus are independent, so the serial numbers of the input signals configured for different peripherals are not equal. In the first type of peripheral being sorted, the serial number of the first peripheral attribute is configured as input signal 0. Then, by executing steps A1 to A5, the first type of peripheral is sorted from the first type of peripheral, and the i-th type of peripheral is sorted. i increases with the number of peripherals connected to the system bus, and the serial numbers of each input signal in each type of peripheral also increase accordingly. In the i-th type of peripheral being sorted, the serial number of the i-th peripheral attribute is configured as input signal i-1.

[0058] Similarly, when the peripheral attributes of the same type being sorted in step A4 are output signals, the serial number of the peripheral attribute of the same type is the serial number of the output signal. The output signals of each peripheral connected to the system bus are independent of each other, and the number of output signals of each peripheral may not be related to the number of input signals, so the serial numbers of the output signals configured for different peripherals are not equal; in sorting the first type of peripheral, the serial number of the first peripheral attribute is configured as output signal 0; then, by executing steps A1 to A5, sorting starts from the first type of peripheral to the i-th type of peripheral, where i increases with the number of peripherals connected to the system bus, and the serial numbers of each output signal in each type of peripheral also increase accordingly; in sorting the i-th type of peripheral, the serial number of the i-th peripheral attribute is configured as output signal i-1.

[0059] Similarly, when the peripheral attributes of the same type being sorted in step A4 are the enable signals of the peripherals, the sequence number of the peripheral attribute of the same type is the sequence number of the enable signal. The enable signals of each peripheral connected to the system bus are independent of each other, and each peripheral's enable signal can be associated with an output signal. The sequence numbers of the enable signals configured for different peripherals are not equal. In sorting the first type of peripheral, the sequence number of the first peripheral attribute is configured as enable signal 0. Then, by executing steps A1 to A5, the first type of peripheral is sorted from the first type of peripheral. The sequence number of the first type of peripheral increases with the number of peripherals connected to the system bus, and the sequence number of each enable signal in each type of peripheral also increases accordingly. In sorting the first type of peripheral, the sequence number of the first peripheral attribute is configured as enable signal i-1.

[0060] If the input signals of the same peripheral are obtained from a batch of AFIO pins, and the output signals of the same peripheral are output to another batch of AFIO pins, then the number of input signals of the same peripheral is not equal to the number of output signals configured for the same peripheral. A batch of AFIO pins can be mapped to the input pins of the same peripheral (the original input pins may be occupied by other peripherals or the CPU) to transmit input signals from outside the peripheral to the inside of the same peripheral; the other batch of AFIO pins can be mapped to the output pins of the same peripheral (the original output pins may be occupied by other peripherals or the CPU) to transmit the output signals of the peripheral to the outside, for example... Figure 1 The logic circuit shown uses an enable signal for the same peripheral to control another batch of AFIO pins to output the same peripheral's configured output signal. This maintains normal signal interaction between various types of peripherals and the system bus, preventing pin multiplexing conflicts caused by multiple input / output signals of the same peripheral.

[0061] It is worth noting that the number of input signals of the same peripheral is greater than or equal to 0, the number of output signals of the same peripheral is greater than or equal to 0, and the number of enable signals of the same peripheral is greater than or equal to 0; the number of input signals of different peripherals is not necessarily equal, the number of output signals of different peripherals is not necessarily equal, and the number of enable signals of different peripherals is not necessarily equal.

[0062] In some embodiments, if the input signal of the same peripheral is obtained from a batch of AFIO pins, it is determined that the GPIO pins with input function in the same peripheral have been controlled by the CPU, and it is determined that the batch of AFIO pins is a batch of spare pins in the same peripheral, wherein the batch of spare pins is multiplexed to transmit the input signal; if the output signal of the same peripheral is output to another batch of AFIO pins, it is determined that the GPIO pins with output function in the same peripheral have been controlled by the CPU, and it is determined that the other batch of AFIO pins is another batch of spare pins in the same peripheral, wherein the other batch of spare pins is multiplexed to transmit the output signal.

[0063] It's important to note that AFIO (Alternate Function Input / Output) pins are primarily used to resolve pin conflicts. When multiple modules need to use the same pin, AFIO can map these modules to other pins, thus avoiding conflicts. When the same GPIO pin is controlled by the CPU (general-purpose function) and a peripheral device, a conflict arises. The GPIO doesn't know which control is responsible for the output level, leading to remapping. Remapping involves referencing the multiplexed function to other pins. For example, if pin 1 is controlled by the CPU and other modules, causing a conflict, the multiplexed function of the other module is assigned to pin 2, which then acts as an AFIO pin to output the high and low levels controlled by the other module. Many general-purpose peripherals, such as I2C and SPI interface devices, require communication pins to multiplex external GPIO pins through AFIO pins.

[0064] GPIO (General Purpose Input Output) is a general-purpose input / output interface primarily used to connect various external devices, such as sensors and LEDs. GPIO pins can be configured for input, output, or other special functions, offering advantages such as low power consumption, small package size, and low cost. GPIO registers can be used to select the function of a pin; for example, reading a register can determine the pin's high or low potential, or writing to a register can cause the pin to output a high or low potential.

[0065] As one embodiment, in step A1 above, when establishing communication with each peripheral connected to the system bus via the bridge, the peripherals currently required to be started and those currently disabled are identified among the peripherals connected to the system bus. Then, different types of peripherals and their order are distinguished from the identified peripherals currently required to be started. This allows the bridge to sequentially send data from other speeds of the system bus to the peripherals of the required type during write operations, and sequentially send data output from the peripherals of the required type during read operations to other speeds of the system bus. Therefore, to be compatible with the connected low-speed peripherals, the system bus uses the AHB bus. Thus, during write operations, the bridge sequentially sends data from the AHB bus to the peripherals of the required type during write operations, and during read operations, the bridge sequentially sends data output from the peripherals of the required type during read operations to the AHB bus. To ensure compatibility with the high-speed peripherals, the system bus uses the AHB bus. When performing a write operation, the bridge sends the data from the AHB bus to the various types of peripherals that need to be started in sequence. When performing a read operation, the bridge sends the data output by the various types of peripherals that need to be started to the AHB bus in sequence.

[0066] When identifying the peripherals currently required to be started and those currently disabled among the peripherals connected to the system bus, the peripheral required to be started can be replaced with a peripheral with different functional characteristics, such as replacing the UART interface with a USART interface that has more functions, thereby enhancing the versatility of the subsystem. Peripherals currently disabled by the bridge can also be re-connected to the address communication range of the system bus in the future via a start signal.

[0067] It should be noted that AHB (Advanced High Performance Bus) is an advanced high-performance bus primarily used for connections between high-performance modules (such as CPUs, DMA, and DSPs), supporting high-speed data transmission; APB (Advanced Peripheral Bus) is one of the bus structures in AMBA (Advanced Microcontroller Bus Architecture), primarily used for connections between low-bandwidth peripherals. The APB bus protocol is a standard on-chip bus structure suitable for low-power and low-bandwidth peripheral interfaces, such as UART and IIC.

[0068] Based on the foregoing embodiments, in step A1, when there are serial communication interface devices among the different types of peripherals connected to the system bus, the order of the peripherals is: SPI0 interface device, SPI1 interface device, QSPI interface device, UART interface device, USART interface device, and I2C interface device. All of these interface devices support communication with... Figure 1 The logic circuits shown interact with each other. Since they are all connected to low-speed peripherals, the system bus can use the APB bus. In the subsequent repeated execution of steps A2 to A5, the peripheral attributes of each peripheral of the same type will be sorted in the peripheral attributes of each peripheral of the same type. Then, the peripheral attributes of each peripheral of the same type will be sorted in the serial communication interface devices of each type in sequence. Based on this, the configuration of the peripheral attributes of each type of SPI0 interface device, SPI1 interface device, QSPI interface device, UART interface device, USART interface device and I2C interface device will be completed in an orderly manner.

[0069] When all types of peripherals are serial communication interface devices, the number of interrupts configured for each peripheral is equal to the value 1, which can be regarded as equal to the bit width of the interrupt signal generated by the same peripheral; the number of DMA channels configured for each peripheral is equal to the value 2; and the number of peripherals for each type of peripheral is equal to the value 1.

[0070] One system bus corresponds to one serial communication interface bus driver, and multiple serial communication interface devices can be connected to one system bus.

[0071] It's important to note that SPI (Serial Peripheral Interface) is a high-speed data transmission interface used for rapid communication between a host and peripheral devices. The SPI0 interface is the most basic and commonly used SPI interface, typically employing two data lines on the bus: the master-slave input signal (mosi) and the master-slave output signal (miso). The data transmission speed is fixed. Compared to SPI0, the SPI1 interface allows for a variable time interval between the rising and falling edges of the clock signal SCK, meaning its data transmission speed is also variable. The QSPI (Quad-SPI) interface is a four-channel SPI specifically designed for communication with flash memory chips that support this interface. Compared to SPI0 and SPI1, it achieves approximately four times the throughput; it is also faster than traditional SPI because the four-channel SPI uses four data lines.

[0072] UART stands for Universal Asynchronous Receiver and Transmitter; USART stands for Universal Synchronous Asynchronous Receiver and Transmitter.

[0073] An I2C (Inter-Integrated Circuit) interface device is a bidirectional two-wire synchronous serial bus interface device, mainly used to connect microcontrollers and various peripheral devices, such as sensors, memory, and displays. I2C interface devices use two lines: SDA (serial data line) and SCL (serial clock line), through which bidirectional data transmission and synchronization are achieved.

[0074] In summary, step A1 sorts different types of serial communication interface devices according to the completeness of their functions, the number of communication signals, and the complexity of the executed commands.

[0075] Based on the aforementioned embodiments, in step A1, when different types of peripherals connected to the system bus have timers, the order of the peripherals is: BFTM timer, EBFTM timer, GPTM timer, and MCTM timer. The timer ranked first is configured to be placed after the I2C interface device; that is, the first peripheral of the BFTM timer type is placed after the last peripheral of the I2C interface device. During the repeated execution of steps A2 to A5, the peripheral attributes of each peripheral of the same type are sorted within each peripheral, and then the sorting of the peripheral attributes of each peripheral of the same type is completed sequentially within each type of timer. Based on this, according to the completeness of the counting function, the quantity of communication signals and PWM signals generated, and the complexity of executing timing commands, the sorting configuration of the peripheral attributes of each type of peripheral for SPI0 interface devices, SPI1 interface devices, QSPI interface devices, UART interface devices, USART interface devices, I2C interface devices, BFTM timer, EBFTM timer, GPTM timer, and MCTM timer is completed.

[0076] It should be noted that the BFTM timer is a basic function timer, a simple 32-bit up-counter, used to measure time intervals and generate a single or repeating interrupt. The EBFTM timer is a PWM generation timer, adding the function of outputting a PWM wave to the BFTM timer. The GPTM timer is a PWM generation and capture timer, belonging to the most complex and comprehensive counter category, and is also a counter with counting functions. The MCTM timer is a motor control timer, including a 16-bit up / down counter, four 16-bit CCRs (capture / compare registers), a 16-bit counter reload register (CRR), an 8-bit repeating counter, and several control / status registers. It can be used to measure the pulse width of input signals or generate output waveforms. The MCTM timer supports encoder interfaces with incremental decoders with two input ports, providing full-featured support for motor control, Hall sensor interfaces, and brake inputs.

[0077] The DTIMER timer is a timer register in a 32-bit microcontroller used to control SDIO (Safety Digital Input / Output) operations. The DTIMER timer is used to set the timer value for data transmission to ensure accuracy and stability. When different types of peripherals connected to the system bus have their own timers, the DTIMER timer can be configured to run after the MCTM timer.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A peripheral attribute sorting method based on a system-on-a-chip, characterized in that, The peripheral attribute sorting method includes: The bridge establishes communication with peripherals connected to the system bus and distinguishes between different types of peripherals. Configure the number of different peripheral attributes in each type of peripheral; The peripheral attributes of each type of peripheral are sorted according to the number of attributes of the same type.

2. The peripheral attribute sorting method according to claim 1, characterized in that, The method for configuring the number of different peripheral attributes in each type of peripheral includes: Configure at least the number of peripherals in each type of peripheral, the number of interrupts for each peripheral in each type of peripheral, the number of DMA channels for each peripheral in each type of peripheral, the number of input signals for each peripheral in each type of peripheral, the number of output signals for each peripheral in each type of peripheral, and the number of enable signals for each peripheral in each type of peripheral. Among them, the peripheral attributes are base address, interrupt, DMA channel, input signal, output signal, or enable signal; Among them, the number of peripheral attributes of the same type is the number of base addresses, or the number of interrupts, or the number of DMA channels, or the number of input signals, or the number of output signals, or the number of enable signals.

3. The peripheral attribute sorting method according to claim 2, characterized in that, The method for sorting peripheral attributes of each type of peripheral according to the number of attributes of the same type includes: Step A1: Set the order of different types of peripherals connected to the system bus; then proceed to step A2. Step A2: Determine whether the attributes of the same type of peripheral have been sorted in all types of peripherals connected to the system bus. If yes, end the process; otherwise, proceed to step A3. Step A3: Determine whether the sorting of the attributes of the same type of peripheral has been completed in the sorting of the i-th type of peripheral. If yes, proceed to step A5; otherwise, proceed to step A4. Step A4: In the sorting of peripherals of type i, starting from the attribute number of peripheral i, sort the peripherals of the same type according to the number of peripherals of the same type, and obtain the index of the peripherals of the same type in the sorting of peripherals of type i, and determine that the sorting of peripherals of the same type is completed in the sorting of peripherals of type i; then execute step A2. Step A5: Calculate the index of the same type of peripheral attribute of the first-ranked peripheral in the (i+1)th type of peripheral, obtain the (i+1)th peripheral attribute index, update the (i+1)th peripheral attribute index to the i-th peripheral attribute index, update the (i+1)th type of peripheral to the i-th type of peripheral, update the number of peripherals in the (i+1)th type of peripheral to the number of peripherals in the i-th type of peripheral, and then execute step A4; Where i is an integer greater than or equal to 1; Among them, the number of peripheral attributes of the same type configured in each peripheral of the same type is equal.

4. The peripheral attribute sorting method according to claim 3, characterized in that, In step A4, in sorting the i-th type of peripherals, starting from the i-th peripheral attribute number, the peripheral attributes of the same type of each peripheral are sorted according to the number of peripheral attributes of the same type, and the method for obtaining the index of the peripheral attribute of the same type of each peripheral in the sorted i-th type of peripherals includes: In sorting peripherals of type i, the first index of the peripheral attribute of type j of peripheral j is configured as the index of peripheral attribute i. Then, starting from the index of peripheral attribute i, each increment of the value 1 yields the index of one peripheral attribute of type i, until the number of incremented indexes reaches the difference between the number of peripheral attributes of type i configured in all peripherals of type i and the value 1. Then, the latest index is added to the value 1, and the result is configured as the first index of peripheral attribute j+1 of peripheral j, until the number of indexes of peripheral attributes of type i configured successively is equal to the difference between the product of the number of peripherals of type i and the number of peripheral attributes of type i configured in all peripherals of type i and the value 1. Then, it is determined that the peripheral attributes of type i of peripherals are sorted. Where j is an integer greater than or equal to 1.

5. The peripheral attribute sorting method according to claim 4, characterized in that, After sorting the peripheral attributes of the same type in the peripherals of the i-th type, the latest obtained sequence number is added to the value 1 to obtain the (i+1)-th peripheral attribute sequence number in step A5. The (i+1)-th peripheral attribute sequence number in step A5 is equal to the sum of the product of the number of peripherals of the i-th type and the number of peripheral attributes of the same type configured in the i-th type of peripherals, and the i-th peripheral attribute sequence number.

6. The peripheral attribute sorting method according to claim 5, characterized in that, In step A4, if the peripheral attribute of the same type that is sorted is the base address of the peripheral, then in the peripheral of the same type, the quantity of the same type peripheral attribute in each peripheral is configured to be equal to the value 1, and the number of peripherals is configured to be 1. When the peripheral of the same type is the first type of peripheral in the sorting, the attribute number of the first peripheral is configured to the value 0. At this time, the base address assigned to the first type of peripheral in the sorting is equal to binary 0. Then, by executing steps A1 to A5, the attribute number of the i-th peripheral is configured as i-1; the attribute number of the i-th peripheral is converted into a binary number, and the converted binary number is allocated to the base address in the order of high bits to low bits, so that the base addresses of various types of peripherals connected to the system bus are sorted in ascending order according to the size relationship of binary numbers within the same bit range.

7. The peripheral attribute sorting method according to claim 5, characterized in that, In step A4, if the peripherals of the same type are sorted and their attributes are interrupts, then: In the first type of peripheral, the attribute number of the first peripheral is configured as interrupt number 0; then, by executing steps A1 to A5, the attribute number of the i-th peripheral is configured as interrupt number i-1; In this context, the number of peripherals for each type of peripheral is equal to the value 1; the number of peripheral attributes of the same type configured for each peripheral in each type of peripheral is the number of interrupts, and the number of interrupts is equal to the bit width of the corresponding interrupt signal; the number of interrupts pre-allocated by the CPU to each type of peripheral is greater than or equal to the value 1, so that each type of peripheral gets at least one interrupt number.

8. The peripheral attribute sorting method according to claim 5, characterized in that, In step A4, if the peripherals of the same type that are sorted have the same attribute as the peripheral's DMA channel, then: In the first type of peripheral, the first peripheral attribute number is configured as DMA channel number 0; then, by executing steps A1 to A5, the i-th peripheral attribute number is configured as DMA channel number i-1; In this context, the number of peripherals for each type of peripheral is equal to the value 1; the number of the same type of peripheral attributes configured for each type of peripheral is the number of DMA channels; in each type of peripheral, the number of DMA channels for each peripheral is greater than or equal to the value 0, so that one peripheral can interact with another peripheral through its DMA channel or prevent one peripheral from interacting with other peripherals.

9. The peripheral attribute sorting method according to claim 1, characterized in that, When the peripheral attributes of each type of peripheral are input signals, output signals, or enable signals, and the number of the same type of peripheral attribute configured for each type of peripheral is equal to the number of input signals, output signals, or enable signals, then the following applies: If the input signal of the same peripheral is obtained from a batch of AFIO pins, and the output signal of the same peripheral is output to another batch of AFIO pins, then the number of input signals of the same peripheral is not equal to the number of output signals configured for the same peripheral; wherein, the enable signal of the same peripheral is used to control the output of the output signal configured for the same peripheral from the other batch of AFIO pins; the number of input signals of the same peripheral is greater than or equal to the value 0.

10. The peripheral attribute sorting method according to claim 9, characterized in that, If the input signal of the same peripheral is obtained from the output of a batch of AFIO pins, it is determined that the GPIO pins with input function in the same peripheral have been controlled by the CPU, and it is determined that the batch of AFIO pins is a batch of spare pins in the same peripheral, wherein the batch of spare pins is multiplexed to transmit the input signal. If the output signal of the same peripheral is output to another batch of AFIO pins, it is determined that the GPIO pins with output function in the same peripheral have been controlled by the CPU, and it is determined that the other batch of AFIO pins is another batch of spare pins in the same peripheral, wherein the other batch of spare pins is multiplexed to transmit the output signal.

11. The peripheral attribute sorting method according to claim 3, characterized in that, When establishing communication with each peripheral connected to the system B bus through the bridge in step A1, the peripherals that need to be started and those that are currently disabled are identified among the peripherals connected to the system bus. Then, different types of peripherals and their order are distinguished from the identified peripherals that need to be started.

12. The peripheral attribute sorting method according to claim 11, characterized in that, In step A1, if there are serial communication interface devices among the different types of peripherals connected to the system bus, the order of the peripherals is: SPI0 interface device, SPI1 interface device, QSPI interface device, UART interface device, USART interface device, and I2C interface device. Within the same type of peripheral, the number of interrupts configured for each peripheral is equal to the value 1, and the number of DMA channels configured for each peripheral is equal to the value 2; among them, the number of peripherals for each type of peripheral is equal to the value 1.

13. The peripheral attribute sorting method according to claim 12, characterized in that, In step A1, when different types of peripherals connected to the system bus have timers, the order of the peripherals is: BFTM timer, EBFTM timer, GPTM timer, and MCTM timer; among them, the timer that is ranked first is configured to be arranged after the I2C interface device.

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