Memory operation method, memory and storage system

Abstract

The present disclosure provides a memory operation method, a memory and a storage system, and relates to the technical field of memories. The method comprises the following steps: in a process of performing a target operation on a memory, obtaining a current temperature and a historical temperature of the memory, the target operation comprising at least one of an erase operation, a programming operation and a reading operation; determining whether a temperature variation of the memory is greater than a preset temperature threshold according to the current temperature and the historical temperature; in response to determining that the temperature variation of the memory is greater than the preset temperature threshold, determining whether a data transmission channel of the memory is currently idle; and in response to determining that the data transmission channel of the memory is currently idle, performing a first interface impedance calibration operation on the memory according to the current temperature. The method realizes interface impedance calibration when the data transmission channel is idle in the process of performing the target operation on the memory.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and more specifically, to a memory operation method, a memory, and a storage system. Background Technology

[0002] Flash memory is a widely used non-volatile memory that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Memory such as NAND is widely used in electronic devices such as mobile phones, computers, and consoles. As the operating speed of electronic devices increases, the impedance of the memory interface in electronic devices can be calibrated to ensure high-speed data transmission.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a memory operation method, a memory, and a storage system.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a memory operation method is provided, comprising: during a target operation on the memory, acquiring a current temperature and a historical temperature of the memory, the target operation including at least one of an erase operation, a programming operation, and a read operation; determining whether the temperature change of the memory is greater than a preset temperature threshold based on the current temperature and the historical temperature; in response to determining that the temperature change of the memory is greater than the preset temperature threshold, determining whether the data transmission channel of the memory is currently idle; and in response to determining that the data transmission channel of the memory is currently idle, performing a first interface impedance calibration operation on the memory based on the current temperature.

[0007] According to one embodiment of this disclosure, in response to determining that the temperature change of the memory is greater than a preset temperature threshold, determining whether the data transmission channel of the memory is currently idle includes: in response to determining that the temperature change of the memory is greater than the preset temperature threshold, acquiring a data transmission signal value; and determining whether the data transmission channel of the memory is currently idle based on the data transmission signal value.

[0008] According to one embodiment of this disclosure, in response to determining that the temperature change of the memory is greater than a preset temperature threshold, acquiring a data transmission signal value includes: in response to determining that the temperature change of the memory is greater than the preset temperature threshold, sending first interface impedance calibration operation trigger information; and in response to the first interface impedance calibration operation trigger information, acquiring the data transmission signal value.

[0009] According to one embodiment of this disclosure, in response to determining that the data transmission channel of the memory is currently idle, a first reference resistor interface impedance calibration operation is performed on the memory based on the current temperature, including: in response to determining that the data transmission channel of the memory is currently idle, obtaining a calibration value corresponding to the current temperature of the memory; and performing a first interface impedance calibration operation on the memory according to the calibration value.

[0010] According to one embodiment of this disclosure, in response to determining that the data transmission channel of the memory is currently idle, obtaining a calibration value corresponding to the current temperature of the memory includes: in response to determining that the data transmission channel of the memory is currently idle, obtaining the current power supply voltage of the memory; and obtaining a calibration value corresponding to the current temperature and the current power supply voltage of the memory.

[0011] According to one embodiment of this disclosure, obtaining a calibration value corresponding to the current temperature and current power supply voltage of the memory includes: obtaining the corresponding calibration value from a lookup table stored in a configuration storage block according to the current temperature and current power supply voltage of the memory.

[0012] According to one embodiment of this disclosure, during a target operation on the memory, obtaining the current temperature and historical temperature of the memory includes: measuring the temperature of the memory at a predetermined frequency; during the target operation on the memory, obtaining the temperature of the memory measured at the current time point or a first time point before the current time point as the current temperature, and obtaining the temperature of the memory measured at the current time point or a second time point before the first time point as the historical temperature.

[0013] According to one embodiment of this disclosure, the method further includes: in response to determining that the data transmission channel of the memory is currently occupied, determining whether to receive second interface impedance calibration operation trigger information; and in response to determining that the second interface impedance calibration operation trigger information is received, sending first interface impedance calibration operation reset information.

[0014] According to another aspect of this disclosure, a memory is provided, comprising: a memory cell array; and peripheral circuitry coupled to the memory cell array, configured to: during a target operation on the memory, acquire a current temperature and a historical temperature of the memory, the target operation including at least one of an erase operation, a programming operation, and a read operation; determine whether the temperature change of the memory is greater than a preset temperature threshold based on the current temperature and the historical temperature; in response to determining that the temperature change of the memory is greater than the preset temperature threshold, determine whether the data transmission channel of the memory is currently idle; and in response to determining that the data transmission channel of the memory is currently idle, perform a first interface impedance calibration operation on the memory based on the current temperature.

[0015] According to one embodiment of this disclosure, the peripheral circuit includes a control logic unit and an interface impedance calibration unit, wherein: the control logic unit is configured to send a first interface impedance calibration operation trigger information to the interface impedance calibration unit in response to determining that the temperature change of the memory is greater than a preset temperature threshold; the interface impedance calibration unit is configured to acquire a data transmission signal value in response to receiving the first interface impedance calibration operation trigger information.

[0016] According to one embodiment of this disclosure, the interface impedance calibration unit is further configured to determine whether the data transmission channel of the memory is currently idle based on the data transmission signal value.

[0017] According to one embodiment of this disclosure, the interface impedance calibration unit is further configured to, in response to determining that the data transmission channel of the memory is currently idle, acquire a calibration value corresponding to the current temperature of the memory; and perform a first interface impedance calibration operation on the memory according to the calibration value.

[0018] According to one embodiment of this disclosure, the interface impedance calibration unit is further configured to, in response to determining that the data transmission channel of the memory is currently idle, acquire the current power supply voltage of the memory; and acquire a calibration value corresponding to the current temperature and current power supply voltage of the memory.

[0019] According to one embodiment of this disclosure, the storage cell array includes a configuration storage block storing a lookup table; the interface impedance calibration unit is further configured to retrieve a corresponding calibration value from the lookup table according to the current temperature and current power supply voltage of the memory.

[0020] According to one embodiment of this disclosure, the peripheral circuit further includes a temperature sensor configured to measure the temperature of the memory at a predetermined frequency; the control logic unit is further configured to, during the process of performing the target operation on the memory, acquire the temperature of the memory measured at the current time point or a first time point before the current time point as the current temperature, and acquire the temperature of the memory measured at the current time point or a second time point before the first time point as the historical temperature.

[0021] According to one embodiment of this disclosure, the control logic unit is further configured to, in response to determining that the data transmission channel of the memory is currently occupied, determine whether to receive second interface impedance calibration operation trigger information; and in response to determining that the second interface impedance calibration operation trigger information is received, send first interface impedance calibration operation reset information to the interface impedance calibration unit.

[0022] According to another aspect of this disclosure, a storage system is provided, comprising: a memory as described above and a controller coupled to said memory.

[0023] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0024] The above and other objects, features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0025] Figure 1 A block diagram of an exemplary system with a memory is shown in an embodiment of this disclosure.

[0026] Figure 2A A block diagram of a memory system is shown as an example.

[0027] Figure 2B A block diagram of another memory system is shown as an example.

[0028] Figure 3 A schematic circuit diagram of a memory 300 including peripheral circuitry provided for an embodiment of this disclosure.

[0029] Figure 4 This is a schematic diagram of a peripheral circuit provided in an embodiment of the present disclosure.

[0030] Figure 5 This is a flowchart illustrating a memory operation method according to an exemplary embodiment.

[0031] Figure 6 It shows Figure 5 The step S502 shown is a schematic diagram of the processing procedure in one embodiment.

[0032] Figure 7 It shows Figure 5 The step S506 shown is a schematic diagram of the processing procedure in one embodiment.

[0033] Figure 8 It shows Figure 3 The step S702 shown is a schematic diagram of the processing procedure in one embodiment.

[0034] Figure 9 This is a flowchart illustrating another memory operation method according to an exemplary embodiment.

[0035] Figure 10 It shows Figure 5 The step S508 shown is a schematic diagram of the processing procedure in one embodiment.

[0036] Figure 11 It shows Figure 5 The step S1002 shown is a schematic diagram of the processing procedure in one embodiment.

[0037] Figure 12 It is based on Figures 5 to 11 The diagram shows a schematic of an interface impedance calibration operation for a memory. Detailed Implementation

[0038] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0039] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0040] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. The symbol " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0041] In this disclosure, unless otherwise expressly specified and limited, the term "connection" and similar terms should be interpreted broadly, for example, it can refer to an electrical connection or the ability to communicate with each other; it can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0042] Figure 1 A block diagram of an exemplary system with memory is shown according to an embodiment of this disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, or any other suitable electronic device having memory therein.

[0043] like Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor) of an electronic device. The host 108 may be configured to send data to or receive data from the memory 104.

[0044] Memory 104 can be any memory disclosed herein, such as non-volatile memory. Non-volatile memory can be NAND flash memory (e.g., three-dimensional (3D) NAND flash memory).

[0045] In some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108.

[0046] In some embodiments, the memory controller 106 is configured to send commands to the memory 104 to cause the memory 104 to perform the memory operation methods provided in the embodiments of this disclosure.

[0047] In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0048] In some embodiments, the memory controller 106 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which can be used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 106 can be configured to send commands to the memory 104 to cause the memory 104 to perform operations, such as read, erase, and program operations.

[0049] The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0050] In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0051] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0052] Figure 2A A block diagram of a memory system is shown as an example. Figure 2AAs shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (also known as a PCMCIA card, Personal Computer Memory Card International Association card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., MMC card, RS-MMC card, MMCmicro card, etc.), an SD card (e.g., SD card, miniSD card, microSD card, SDHC card, etc.), a UFS card, etc. The memory card 202 may also include a connector for connecting the memory card 202 to a host computer (e.g., ...). Figure 1 The memory card connector 204 is coupled to the host 108.

[0053] Figure 2B A block diagram of another memory system is shown as an example. Figure 2B As shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., ...). Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0054] Figure 3 A schematic circuit diagram of a memory 300 including peripheral circuitry provided for embodiments of this disclosure. The memory 300 may be... Figure 1 An example of memory 104 is shown. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of memory strings 308 of NAND flash memory, each memory string 308 extending vertically above a substrate (not shown).

[0055] In some embodiments, the peripheral circuit 302 is configured to perform the operation methods provided in the embodiments of this disclosure. It is understood that the peripheral circuit 302 may be configured to perform the operation methods provided in the embodiments of this disclosure according to instructions received from the memory controller 106.

[0056] In some embodiments, each memory string 308 includes a plurality of memory cells 306 that are series-coupled and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell that includes a floating-gate transistor, or a charge-trapping type memory cell that includes a charge-trapping transistor.

[0057] In some embodiments, each storage unit 306 may store 1 bit of data, 2 bits of data, or more bits of data, i.e., it may be a single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), or a higher-level type.

[0058] like Figure 3 As shown, each memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. SSG 310 and DSG 312 may be configured to activate the selected memory string 308 during read and program operations.

[0059] In some embodiments, the sources of memory strings 308 within the same block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). For example, all memory strings 308 within the same block 304 have an array common source (ACS). Figure 3 As shown, the storage string 308 can be organized into multiple blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is a basic data unit for an erase operation, that is, all storage cells 306 on the same block 304 are erased simultaneously.

[0060] In some embodiments, the transistor of the DSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). Each memory string 308 can be configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0061] like Figure 3As shown, the memory cells 306 of the memory string 308 can be coupled via word lines (WL) 318, which selects which row of memory cells 306 is affected by read and program operations. Peripheral circuitry 302 can be coupled to the memory cell array 301 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each memory cell 306 targeted for operation via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313, and by sensing voltage and / or current signals from each memory cell 306 targeted for operation. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0062] Figure 4 This is a schematic diagram of a peripheral circuit provided in an embodiment of this disclosure. (See diagram below.) Figure 4 As shown, the peripheral circuitry 302 may include a page buffer circuit / sensor amplifier 404, a column decoder / BL driver 406, a row decoder / WL driver 408, a voltage generator 410, a control logic unit 412, a register 414, input / output (I / O) circuitry 416, and a data bus 418. It should be understood that in some examples, it may also include... Figure 4 Additional peripheral circuitry not shown.

[0063] In some embodiments, the page buffer circuit / sensor amplifier 404 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic unit 412. For example, the page buffer circuit / sensor amplifier 404 can store a page of programming data (write data) to be programmed into the memory cell array 301. As another example, the page buffer circuit / sensor amplifier 404 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. The column decoder / BL driver 406 can be configured to be controlled by the control logic unit 412 and to select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 410.

[0064] The row decoder / WL driver 408 can be configured to be controlled by the control logic unit 412 and to select / deselect block 304 of the memory cell array 301 and select / deselect word line 318 of block 304. The row decoder / WL driver 408 can also be configured to drive word line 318 using word line voltages generated from the voltage generator 410. In some embodiments, the row decoder / WL driver 408 can also select / deselect and drive SSG line 314 and DSG line 313. The voltage generator 410 can be configured to be controlled by the control logic unit 412 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages, etc., to be supplied to the memory cell array 301.

[0065] Control logic unit 412 can be coupled to each part of peripheral circuitry 302 and is configured to control the operation of each part. Register 414 can be coupled to control logic unit 412 and may include a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Input / output circuitry 416 can be coupled to control logic unit 412 and acts as a control buffer to buffer inputs from the host (…). Figure 4 The input / output circuit 416 receives control commands (not shown) and relays them to the control logic unit 412, and buffers status information received from the control logic unit 412 and relays it to the host. The input / output circuit 416 can also be coupled to the column decoder / bit line driver 406 via the data bus 418, and acts as a data I / O interface and data buffer to buffer data and relay it to or from the memory cell array 301.

[0066] As the operating speed of electronic devices containing memory increases, the oscillation width of signals transmitted between memories decreases to minimize transmission delays. With this reduced oscillation width, signal transmission becomes more susceptible to external noise, and signal reflection at the interface increases due to impedance mismatch. This impedance mismatch can be caused by variations in the memory manufacturing process, supply voltage, and operating temperature. This mismatch can distort the signal output from the memory, leading to set / hold failures or misjudgments of signal levels in another memory, thus hindering high-speed data transmission. In some embodiments, calibration methods, such as the ZQ calibration method, can be introduced to calibrate the interface impedance. Figure 4As shown, the peripheral circuit 302 may further include an interface impedance calibration unit 420 connected to the input / output circuit 416 and / or the data bus 418. The interface impedance calibration unit 420 may be a calibration circuit including a control unit, pull-up resistors, pull-down resistors, etc. Figure 4 (Not shown in the diagram), the control unit adjusts the pull-up and pull-down resistors associated with the input / output circuit 416 and / or the data bus 418, simultaneously affecting the voltage at the ZQ pin (also known as the Vccq / 2 pin, where Vccq is the power supply voltage). The interface impedance calibration unit 420 can be coupled to the control logic unit 412, receiving signals from the control logic unit 412 to adjust the pull-up and pull-down resistors.

[0067] In some embodiments, the peripheral circuit 302 may further include a temperature sensor 401, which may be connected to the control logic unit 412 and the memory cell array 402 respectively, and may be configured to measure the temperature of the memory at a predetermined frequency. The control logic unit 412 may acquire the temperature measured by the temperature sensor 401 and obtain a related temperature compensation adjustment signal accordingly, and then send the temperature compensation adjustment signal to the voltage generator 410, etc., to realize the corresponding temperature compensation in operations such as programming, reading, and erasing. The control logic unit 412 may also obtain a corresponding trigger signal based on the temperature measured by the temperature sensor 401, and then send the trigger signal to the interface impedance calibration unit 420 to trigger the interface impedance calibration operation.

[0068] Figure 5 This is a flowchart illustrating a memory operation method according to an exemplary embodiment. Figure 5 The method shown can be applied, for example, to... Figure 3 The memory 300 shown.

[0069] refer to Figure 5 The method 50 provided in this embodiment may include the following steps.

[0070] In step S502, during the target operation on the memory, the current temperature and historical temperature of the memory are obtained. The target operation includes at least one of the following: erase operation, program operation, and read operation.

[0071] In some embodiments, during a target operation on the memory, the memory temperature measured at the current time point or a first time point prior to the current time point can be obtained as the current temperature, and the memory temperature measured at a second time point prior to the current time point or the first time point can be obtained as the historical temperature. For example, the memory temperature can be measured by a temperature sensor at a predetermined frequency, and a register module (e.g., a first register) can store the memory temperatures measured by the temperature sensor, updating the stored temperature value with each measurement result from the temperature sensor. The control logic unit can also be configured with one or more registers (e.g., a second register) to receive signals corresponding to the measured memory temperature from the first register and perform related calculations using a logic operation unit. During the execution of target operations such as erase, program, and read operations on the memory, the control logic unit can, during the instruction execution intervals while the memory is executing the command corresponding to the target operation, retrieve the current stored value (measured by the temperature sensor at the current time point or a first time point before the current time point) from the first register as the current temperature of the memory, and store it in the second register. The temperature value stored in the second register before the current temperature of the memory is stored is the temperature value previously retrieved from the first register (measured by the temperature sensor at a second time point before the current time point or the first time point), which can be used as the historical temperature of the memory. The implementation method can be referred to [reference needed]. Figure 6 .

[0072] In step S504, it is determined whether the temperature change of the memory is greater than a preset temperature threshold based on the current temperature and historical temperatures.

[0073] In some embodiments, the current temperature can be subtracted from the historical temperature, and the absolute value of the difference can be taken as the temperature change of the memory. Then, the temperature change of the memory can be compared with a preset temperature threshold. The preset temperature threshold can be set according to the actual situation of the memory and environmental conditions, such as 10℃, 15℃, 20℃, 25℃, etc.

[0074] In some embodiments, a storage unit for caching signals corresponding to the current temperature and historical temperature and a logic operation unit for performing related operations can be provided in the control logic unit. By performing logic operations on the signals corresponding to the current temperature and historical temperature through the logic operation unit, the result corresponds to the absolute value of the difference between the current temperature and the historical temperature, and is compared with the signal value corresponding to a preset temperature threshold.

[0075] In step S506, in response to determining that the temperature change of the memory is greater than a preset temperature threshold, it is determined whether the data transmission channel of the memory is currently idle.

[0076] In some embodiments, during the execution of commands such as programming, reading, and erasing, and when executing instructions involving data reading and writing, the memory's data transmission channel may be occupied. During the intervals between instruction executions corresponding to the memory's data transmission channel occupancy, the memory's data transmission channel is in an idle state. The occupancy status of the memory's data transmission channel can be determined to perform a first interface impedance calibration operation when the memory's data transmission channel is idle.

[0077] In some embodiments, if the temperature change of the memory is determined to be greater than a preset temperature threshold, a data transmission signal value characterizing whether the data transmission channel is currently idle can be obtained, and the idleness of the memory's data transmission channel can be determined based on this data transmission signal value. Implementation methods can refer to [reference needed]. Figure 7 and Figure 8 .

[0078] In some embodiments, if it is determined that the temperature change of the memory is not greater than a preset temperature threshold, no operation may be performed, and the process may return to step S502 to continue acquiring temperature sensor measurements of the memory at a predetermined frequency during the target operation on the memory.

[0079] In step S508, in response to determining that the data transmission channel of the memory is currently idle, a first interface impedance calibration operation is performed on the memory based on the current temperature.

[0080] In some embodiments, when the interface impedance calibration unit determines that the data transmission channel of the memory is currently idle, it can obtain the calibration value corresponding to the current temperature of the memory through a lookup table based on the current temperature of the memory, and perform a first interface impedance calibration operation on the memory according to the calibration value. The implementation method can be referred to... Figure 10 and Figure 11 .

[0081] In other embodiments, if the control logic unit determines whether the data transmission channel of the memory is currently idle, the control logic unit can obtain the calibration value corresponding to the current temperature of the memory by looking up a table based on the current temperature of the memory, and then send the corresponding calibration value to the interface impedance calibration unit so that the interface impedance calibration unit can perform a first interface impedance calibration operation on the memory according to the calibration value.

[0082] In some embodiments, if it is determined that the data transmission channel of the memory is currently occupied (i.e., not idle), upon determining that the second interface impedance calibration operation trigger information has been received, the first interface impedance calibration operation can be stopped and the second interface impedance calibration operation can be performed instead. Furthermore, a first interface impedance calibration operation reset message can be sent to the interface impedance calibration unit to indicate that the current first interface impedance calibration operation will not be performed. The implementation method can be referred to... Figure 9 .

[0083] According to the memory operation method provided in this disclosure, during a target operation on the memory including at least one of erasing, programming, and reading operations, the current temperature and historical temperature of the memory are obtained. If the temperature change of the memory is greater than a preset temperature threshold based on the current temperature and historical temperature, it is determined whether the data transmission channel of the memory is currently idle. If it is determined that the data transmission channel of the memory is currently idle, a first interface impedance calibration operation is performed on the memory based on the current temperature. This achieves the interface impedance calibration operation corresponding to the current temperature when the data transmission channel is idle during the target operation of the memory. Without introducing additional time overhead, the frequency of executing interface impedance calibration commands can be reduced, thereby improving the performance of the memory system.

[0084] Figure 6 It shows Figure 5 The step S502 shown is a schematic diagram of the processing procedure in one embodiment. (See attached diagram.) Figure 6 As shown in the present embodiment, step S502 may further include the following steps.

[0085] Step S602: Measure the temperature of the memory at a predetermined frequency.

[0086] In some embodiments, a temperature sensor coupled to the memory cell array can measure the temperature of the memory at a predetermined frequency under the control of a control logic unit. The predetermined frequency can be set according to actual needs, such as 10 milliseconds, 50 milliseconds, 1 second, 10 seconds, 30 seconds, or 1 minute, etc. A first register can be configured to store the temperature of the memory measured by the temperature sensor. After each measurement, the temperature sensor re-stores the result to the first register to update its stored temperature value. The control logic unit can control the output signal of the temperature sensor to the first register to be proportional to the measured temperature value, so that the value stored in the first register corresponds to the temperature value.

[0087] Step S604: During the target operation on the memory, the temperature of the memory measured at the current time point or at a first time point before the current time point is obtained as the current temperature, and the temperature of the memory measured at the current time point or at a second time point before the first time point is obtained as the historical temperature.

[0088] In some embodiments, during operations such as erasing, programming, and reading from the memory, the control logic unit can retrieve the temperature value stored in the first register and store it in the second register within a pre-set clock cycle during the execution of the corresponding command. The temperature change of the memory is obtained by subtracting the changes in the values ​​stored in the second register, and the corresponding trigger signal is determined based on this temperature change. The second register updates its stored values ​​according to the frequency of temperature sensor measurements. When the first register retrieves a stored value from the second register at the current time point, it may retrieve the stored temperature value measured by the temperature sensor at the current time point, or it may retrieve the stored temperature value measured by the temperature sensor at the most recent measurement time point before the current time point (i.e., the first time point). The two cases are explained below.

[0089] In the case where the first register retrieves the stored temperature value measured by the temperature sensor at the current time point from the second register, after the temperature sensor measures the memory temperature at time point t2 (e.g., corresponding to the aforementioned second time point), it transmits the corresponding signal temp_2 to the first register for storage. During the erase operation after time point t2, the second register retrieves temp_2 from the first register and stores it. Then, after the temperature sensor measures the memory temperature at time point t1 (e.g., corresponding to the aforementioned current time point), it transmits the corresponding signal temp_1 to the first register for storage, overwriting temp_2. At this time, during the interval of memory programming operations, the second register retrieves temp_1 from the first register. Therefore, the temperature value corresponding to temp_1 is the current temperature of the memory, and the temperature value corresponding to temp_2 is the historical temperature of the memory. When the control logic unit updates the stored value of the second register from temp_1 in the first register, it can also calculate the difference between temp_1 and temp_2 through the logic operation unit to obtain the temperature change between the current temperature and the historical temperature.

[0090] In the case where the first register retrieves the stored temperature value from the second register at the current time point, as measured by the temperature sensor at a previous time point, after the temperature sensor measures the memory temperature at time point t2' (e.g., corresponding to the aforementioned second time point), it transmits the corresponding signal temp_2' to the first register for storage. During the first target operation (e.g., erase) after time point t2', the second register retrieves temp_2' from the first register and stores it. Then, after the temperature sensor measures the memory temperature at time point t1' (e.g., corresponding to the aforementioned first time point), it transmits the corresponding signal temp_1' to the first register for storage, overwriting temp_2'. At this time, the value stored in the second memory is still temp_2'. Then, at time point t0 (e.g., corresponding to the aforementioned current time point), during the interval of the second target operation (e.g., programming) of the memory, the second register retrieves temp_1' from the first register (the temperature sensor does not perform any further measurements between time points t1' and t0). The temperature value corresponding to temp_1' is the current temperature of the memory, and the temperature value corresponding to temp_2' is the historical temperature of the memory. When the control logic unit updates the stored value of the second register from temp_1' in the first register, it can also calculate the difference between temp_1' and temp_2' through the logic operation unit to obtain the temperature change between the current temperature and the historical temperature.

[0091] According to the method provided in the embodiments of this disclosure, by obtaining the temperature of the memory measured at a first time point before the current time point or the current time point during the process of erasing, programming, reading and other operations on the memory, the temperature of the memory measured at a second time point before the current time point or the first time point is obtained as the historical temperature. The temperature change of the memory can be obtained conveniently and accurately, so that corresponding compensation and adjustment can be made in the memory operation according to the temperature change of the memory, thereby improving the reliability of the memory.

[0092] Figure 7 It shows Figure 5 The step S506 shown is a schematic diagram of the processing procedure in one embodiment. (See attached diagram.) Figure 7 As shown in the present embodiment, step S506 may further include the following steps.

[0093] Step S702: In response to determining that the temperature change of the memory is greater than a preset temperature threshold, the data transmission signal value is acquired.

[0094] In some embodiments, the value stored in a memory cell associated with the data transmission channel or the potential of a node can be set as a data transmission signal value to characterize whether the data transmission channel is occupied or idle. For example, the value stored in the corresponding memory cell is "0" or "1" to indicate that it is idle or occupied. Another example is that the potential of the corresponding node is high potential (e.g., greater than the threshold voltage of the transistor connected to its gate) or low potential (e.g., not greater than the threshold voltage of the transistor connected to its gate) to indicate that it is idle or occupied.

[0095] In some embodiments, the control logic unit may send first interface impedance calibration operation trigger information to the interface impedance calibration unit when it determines that the temperature change of the memory is greater than a preset temperature threshold, so as to trigger the interface impedance calibration unit to obtain the data transmission signal value from the corresponding cell or node, etc. Implementation methods may refer to... Figure 8 .

[0096] In other embodiments, the control logic unit may also obtain data transmission signal values ​​from the corresponding unit or node when it determines that the temperature change of the memory is greater than a preset temperature threshold.

[0097] Step S704: Determine whether the data transmission channel of the memory is currently idle based on the data transmission signal value.

[0098] In some embodiments, after being triggered by the first interface impedance calibration operation trigger information, the interface impedance calibration unit can determine whether the data transmission channel of the memory is currently idle based on the acquired data transmission signal value.

[0099] In other embodiments, the control logic unit may determine whether the data transmission channel of the memory is currently idle based on the data transmission signal value obtained from the corresponding unit or node.

[0100] According to the method provided in the embodiments of this disclosure, when it is determined that the temperature change of the memory is greater than a preset temperature threshold, the data transmission signal value is obtained and the data transmission channel of the memory is determined to be idle. This allows for convenient and accurate determination of whether the data transmission channel of the memory is currently idle, so as to realize the first interface impedance calibration operation when the data transmission channel of the memory is currently idle.

[0101] Figure 8 It shows Figure 3 The step S702 shown is a schematic diagram of the processing procedure in one embodiment. (See attached diagram.) Figure 8 As shown in the embodiments of this disclosure, step S702 may further include the following steps.

[0102] In step S802, in response to determining that the temperature change of the memory is greater than a preset temperature threshold, a first interface impedance calibration operation trigger message is sent.

[0103] In some embodiments, the control logic unit may send a first interface impedance calibration operation trigger information to the interface impedance calibration unit when it determines that the temperature change of the memory is greater than a preset temperature threshold. The first interface impedance calibration operation trigger information may be, for example, a pulse signal or a high potential (e.g., a voltage greater than the threshold voltage of the transistor connected to its gate), etc., and this disclosure does not limit it.

[0104] Step S804: In response to the trigger information of the first interface impedance calibration operation, acquire the data transmission signal value.

[0105] In some embodiments, the interface impedance calibration unit can be triggered by a first interface impedance calibration operation trigger information to obtain a data transmission signal value from a corresponding unit or node. For example, the interface impedance calibration unit may have a switch unit between itself and the corresponding unit or node, and the first interface impedance calibration operation trigger information may be configured to enable the switch unit to open.

[0106] According to the method provided in this disclosure, when the temperature change of the memory is greater than a preset temperature threshold, a first interface impedance calibration operation trigger information is sent to trigger the corresponding unit to obtain the data transmission signal value and determine whether the data transmission channel of the memory is currently idle. Appropriate units can be flexibly set according to the actual situation of the memory to obtain the data transmission signal value used to determine whether the data transmission channel of the memory is currently idle, thereby improving the adaptability of the memory system.

[0107] Figure 9 This is a flowchart illustrating another memory operation method according to an exemplary embodiment. For example... Figure 9 The method shown can be applied, for example, to... Figure 3 The memory 300 shown is executed after step S506.

[0108] refer to Figure 9 The method 90 provided in this embodiment may include the following steps.

[0109] In step S902, in response to determining that the data transmission channel of the memory is currently occupied, it is determined whether to receive the second interface impedance calibration operation trigger information.

[0110] In some embodiments, if it is determined that the data transmission channel of the memory is not currently idle, it can be determined whether a second interface impedance calibration operation trigger message has been received. The second interface impedance calibration operation trigger message can be information used to trigger a second interface impedance calibration operation. The second interface impedance calibration operation can be an operation executing a ZQ calibration command, such as ZQCL (ZQ CALIBRATION LONG) or ZQCS (ZQ CALIBRATION SHORT), etc. If it is determined that the second interface impedance calibration operation trigger message has been received, the second interface impedance calibration operation can be performed after the target operation of the memory is completed.

[0111] In step S904, in response to determining that the second interface impedance calibration operation trigger information has been received, the first interface impedance calibration operation reset information is sent.

[0112] In some embodiments, if the control logic unit determines in step S506 that the temperature change of the memory is greater than a preset temperature threshold, and if the control logic unit determines that the data transmission channel of the memory is currently occupied, then if it determines that the second interface impedance calibration operation trigger information has been received, it can stop performing the first interface impedance calibration operation and perform the second interface impedance calibration operation instead, and can send the first interface impedance calibration operation reset information to the interface impedance calibration unit to indicate that the first interface impedance calibration operation will not be performed again, that is, it will no longer determine whether the data transmission channel of the memory is currently idle.

[0113] According to the method provided in the embodiments of this disclosure, when it is determined that the data transmission channel of the memory is currently occupied, it is determined whether to receive the second interface impedance calibration operation trigger information. If it is determined that the second interface impedance calibration operation trigger information is received, the first interface impedance calibration operation reset information is sent, so that it is no longer necessary to determine whether the data transmission channel of the memory is currently idle. This converts the interface impedance calibration operation to be performed in response to determining that the temperature change of the memory is greater than a preset temperature threshold from the first interface impedance calibration operation to the second interface impedance calibration operation, providing a more flexible interface impedance calibration mode for the memory.

[0114] Figure 10 It shows Figure 5 The step S508 shown is a schematic diagram of the processing procedure in one embodiment. (See attached diagram.) Figure 10 As shown in the embodiments of this disclosure, step S508 may further include the following steps.

[0115] In step S1002, in response to determining that the data transmission channel of the memory is currently idle, a calibration value corresponding to the current temperature of the memory is obtained.

[0116] In some embodiments, the memory cell array may include a configuration memory block that stores a lookup table containing a correspondence between the memory's temperature and calibration values. The interface impedance calibration unit can retrieve the calibration value corresponding to the memory's current temperature from the lookup table if it determines that the memory's data transmission channel is currently idle.

[0117] In other embodiments, the lookup table stored in the configuration memory block may include the correspondence between the memory temperature, the memory power supply voltage, and calibration values. The interface impedance calibration unit can retrieve the calibration values ​​corresponding to the current temperature and current power supply voltage of the memory from the lookup table when it is determined that the data transmission channel of the memory is currently idle. Implementation methods can refer to [the relevant documentation]. Figure 11 .

[0118] Step S1004: Perform the first interface impedance calibration operation on the memory according to the calibration value.

[0119] In some embodiments, the calibration value can be represented as a binary code, and the first interface impedance calibration operation can be to control the conduction or shutdown of the MOS transistor contained in the pull-up resistor or pull-down resistor in the interface impedance calibration unit by the binary code corresponding to the calibration value, so as to calibrate the resistance value of the pull-up resistor or pull-down resistor.

[0120] According to the method provided in the embodiments of this disclosure, when it is determined that the data transmission channel of the memory is currently idle, a calibration value corresponding to the current temperature of the memory is obtained, and a first interface impedance calibration operation is performed on the memory according to the calibration value, so as to realize the corresponding interface impedance calibration operation in response to the temperature change of the memory.

[0121] Figure 11 It shows Figure 5 The step S1002 shown is a schematic diagram of the processing procedure in one embodiment. (See attached diagram.) Figure 11 As shown in the present embodiment, step S1002 may further include the following steps.

[0122] In step S1102, in response to determining that the data transmission channel of the memory is currently idle, the current power supply voltage of the memory is obtained.

[0123] In some embodiments, the interface impedance calibration unit can obtain the current power supply voltage Vccq of the memory through the voltage measurement unit when it is determined that the data transmission channel of the memory is currently idle.

[0124] Step S1104: Obtain the calibration value corresponding to the current temperature and current power supply voltage of the memory.

[0125] In some embodiments, in a predetermined test mode of the memory system, the memory controller can adjust the temperature and power supply voltage of the memory, and then control the memory to perform interface impedance calibration operations, such as executing ZQCL and / or ZQCS commands, obtaining the calibration value corresponding to the command execution result, and generating a lookup table that records the correspondence between the calibration value and the memory temperature and power supply voltage. The lookup table can be stored in the configuration storage block.

[0126] In other embodiments, a lookup table corresponding to the temperature and power supply voltage of the memory and the calibration value can also be generated by simulation calculation, and the lookup table can be stored in the configuration storage block.

[0127] For example, calibration values ​​may include pull-up resistor ZQ calibration values, pull-down resistor ZQ calibration values, etc. Table 1 below provides an example lookup table for pull-up resistor ZQ calibration values ​​of memories produced under two different process conditions.

[0128] Table 1

[0129]

[0130]

[0131] In Table 1, the first row below the "Memory Temperature" column represents the memory temperature values ​​(8 examples in total), ranging from -40 to 100℃; the first column to the right of the "Power Supply Voltage" column represents the power supply voltage values ​​(7 examples in total); the values ​​in the diagonal rows and columns of the "Pull-up Resistor ZQ Calibration Value" column represent the pull-up resistor ZQ calibration values ​​under the power supply voltage of the corresponding row and the memory temperature of the corresponding column. As shown in Table 1, for example, for a memory produced under the first process condition, the pull-up resistor ZQ calibration value corresponding to a memory temperature of -40℃ and a power supply voltage of 1.16V is 41, and the pull-up resistor ZQ calibration value corresponding to a memory temperature of 20℃ and a power supply voltage of 1.24V is 40. As another example, for a memory produced under the second process condition, the pull-up resistor ZQ calibration value corresponding to a memory temperature of -40℃ and a power supply voltage of 1.16V is 51, and the pull-up resistor ZQ calibration value corresponding to a memory temperature of 20℃ and a power supply voltage of 1.24V is 48.

[0132] For example, step S11042 can be executed to obtain the corresponding calibration value from the lookup table stored in the configuration storage block according to the current temperature and current power supply voltage of the memory. Referring to Table 1, taking the memory produced under the second process conditions as an example, if the current temperature of the memory is 60°C and the current power supply voltage is 1.2V, the corresponding pull-up resistor ZQ calibration value of 50 can be obtained from the lookup table.

[0133] In some embodiments, if the current temperature and / or current power supply voltage of the memory do not have an exact corresponding value in the lookup table, the closest value can be selected for lookup. Taking a memory manufactured under the second process conditions as an example, for instance, if the current temperature of the memory is 35°C and the current power supply voltage is 1.28V, the pull-up resistor calibration value 46 corresponding to a memory temperature of 40°C and a power supply voltage of 1.28V can be obtained from the lookup table as the corresponding pull-up resistor calibration value ZQ. As another example, if the current temperature of the memory is 15°C and the current power supply voltage is 1.25V, the pull-up resistor calibration value 48 corresponding to a memory temperature of 20°C and a power supply voltage of 1.24V can be obtained from the lookup table as the corresponding pull-up resistor calibration value ZQ.

[0134] According to the method provided in the embodiments of this disclosure, when it is determined that the data transmission channel of the memory is currently idle, the current power supply voltage of the memory is obtained, and then the corresponding calibration value is obtained from the lookup table stored in the configuration memory block according to the current temperature and current power supply voltage of the memory, so as to perform a first interface impedance calibration operation on the memory according to the calibration value, which can realize the interface impedance calibration operation quickly and accurately in response to the temperature change of the memory.

[0135] Figure 12 It is based on Figures 5 to 11 The diagram illustrates a procedure for interface impedance calibration of a memory. Figure 12 The interface impedance calibration operation procedure shown may include the following steps S1202 to S1212.

[0136] Steps S1202 to S1204 involve measuring the temperature of the memory and updating its current temperature during the target operation. In some embodiments, steps S602 to S604 may be referred to.

[0137] Step S1206: Determine whether the temperature change of the memory exceeds a preset temperature threshold and whether to trigger calibration settings. The method for determining whether the temperature change of the memory exceeds the preset temperature threshold can be found in step S504. Triggering calibration settings can mean setting an interface impedance calibration operation to be performed, including a first interface impedance calibration operation, a second interface impedance calibration operation, etc.

[0138] In step S1207, if the temperature change of the memory is not greater than the preset temperature threshold and / or the calibration setting is not triggered, the process ends, i.e., the interface impedance calibration operation is not performed.

[0139] In step S1208, if the temperature change of the memory exceeds a preset temperature threshold and triggers calibration settings, the interface impedance calibration unit is triggered to enter the first interface impedance calibration process. After entering the first interface impedance calibration process, if no first interface impedance calibration operation reset information is received, the interface impedance calibration unit may execute step S1210 at a certain frequency until the first interface impedance calibration operation reset information is received and the process ends.

[0140] In step S1210, after the interface impedance calibration unit enters the first interface impedance calibration process, it determines whether the data transmission channel of the memory is currently idle. The implementation method can refer to step S506.

[0141] In step S12112, if the interface impedance calibration unit determines that the data transmission channel of the memory is not currently idle, it can send a signal to the control logic unit, which will then determine whether to receive the second interface impedance calibration operation trigger information. The implementation method can refer to step S902.

[0142] If it is determined that the second interface impedance calibration operation trigger information has not been received, the process can return to step S1210 and wait for the data transmission channel to become idle.

[0143] In step S12114, if the control logic unit determines that it has received the second interface impedance calibration operation trigger information, it can send the first interface impedance calibration operation reset information to the sending interface impedance calibration unit and end the current first interface impedance calibration process. The implementation method can refer to step S904.

[0144] In step S1212, if the interface impedance calibration unit determines that the data transmission channel of the memory is currently idle, then the memory is subjected to a first interface impedance calibration operation based on the current temperature. The implementation method can be referred to in step S508.

[0145] According to the memory operation method provided in this disclosure, by obtaining the temperature change of the memory during the erasure, programming, and reading operations, and when the temperature change exceeds a preset temperature threshold, a first interface impedance calibration operation is performed on the memory based on the current temperature when the data transmission channel of the memory is idle. This achieves the goal of reducing the frequency of executing the interface impedance calibration command by adding only a small amount of signal, and avoids conflicts in data transmission channel occupancy.

[0146] Exemplary embodiments of this disclosure have been specifically shown and described above. It should be understood that this disclosure is not limited to the detailed structures, arrangements, or implementations described herein; rather, this disclosure is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A memory operation method, characterized in that, include: During the target operation on the memory, the current temperature and historical temperature of the memory are obtained, and the target operation includes at least one of the erase operation, programming operation, and read operation; Based on the current temperature and the historical temperature, determine whether the temperature change of the memory is greater than a preset temperature threshold. In response to determining that the temperature change of the memory is greater than a preset temperature threshold, it is determined whether the data transmission channel of the memory is currently idle; In response to determining that the data transmission channel of the memory is currently idle, a first interface impedance calibration operation is performed on the memory based on the current temperature.

2. The method according to claim 1, characterized in that, In response to determining that the temperature change of the memory is greater than a preset temperature threshold, determining whether the data transmission channel of the memory is currently idle includes: In response to determining that the temperature change of the memory is greater than a preset temperature threshold, a data transmission signal value is acquired; The data transmission signal value is used to determine whether the data transmission channel of the memory is currently idle.

3. The method according to claim 2, characterized in that, In response to determining that the temperature change of the memory is greater than a preset temperature threshold, a data transmission signal value is acquired, including: In response to determining that the temperature change of the memory is greater than a preset temperature threshold, a first interface impedance calibration operation trigger message is sent. In response to the first interface impedance calibration operation trigger information, the data transmission signal value is acquired.

4. The method according to any one of claims 1 to 3, characterized in that, In response to determining that the data transmission channel of the memory is currently idle, a first reference resistor interface impedance calibration operation is performed on the memory based on the current temperature, including: In response to determining that the data transmission channel of the memory is currently idle, a calibration value corresponding to the current temperature of the memory is obtained; Perform a first interface impedance calibration operation on the memory according to the calibration value.

5. The method according to claim 4, characterized in that, In response to determining that the data transmission channel of the memory is currently idle, a calibration value corresponding to the current temperature of the memory is obtained, including: In response to determining that the data transmission channel of the memory is currently idle, the current power supply voltage of the memory is obtained; Obtain the calibration values ​​corresponding to the current temperature and current power supply voltage of the memory.

6. The method according to claim 5, characterized in that, Obtaining calibration values ​​corresponding to the current temperature and current power supply voltage of the memory, including: The corresponding calibration value is obtained from the lookup table stored in the configuration storage block according to the current temperature and current power supply voltage of the memory.

7. The method according to any one of claims 1 to 6, characterized in that, During the target operation on the memory, the current temperature and historical temperature of the memory are obtained, including: The temperature of the memory is measured at a predetermined frequency; During the target operation on the memory, the temperature of the memory measured at the current time point or at a first time point before the current time point is obtained as the current temperature, and the temperature of the memory measured at a second time point before the current time point or at a second time point before the first time point is obtained as the historical temperature.

8. The method according to claim 3, characterized in that, Also includes: In response to determining that the data transmission channel of the memory is currently occupied, it is determined whether to receive the second interface impedance calibration operation trigger information; In response to determining that the second interface impedance calibration operation trigger information has been received, the first interface impedance calibration operation reset information is sent.

9. A memory, characterized in that, include: Storage cell array; Peripheral circuitry, coupled to the memory cell array, is configured as follows: During the target operation on the memory, the current temperature and historical temperature of the memory are obtained, and the target operation includes at least one of the erase operation, programming operation, and read operation; Based on the current temperature and the historical temperature, determine whether the temperature change of the memory is greater than a preset temperature threshold. In response to determining that the temperature change of the memory is greater than a preset temperature threshold, it is determined whether the data transmission channel of the memory is currently idle; In response to determining that the data transmission channel of the memory is currently idle, a first interface impedance calibration operation is performed on the memory based on the current temperature.

10. The memory according to claim 9, characterized in that, The peripheral circuitry includes a control logic unit and an interface impedance calibration unit, wherein: The control logic unit is configured to send a first interface impedance calibration operation trigger information to the interface impedance calibration unit in response to determining that the temperature change of the memory is greater than a preset temperature threshold. The interface impedance calibration unit is configured to acquire a data transmission signal value in response to receiving the first interface impedance calibration operation trigger information.

11. The memory according to claim 10, characterized in that, The interface impedance calibration unit is also configured to determine whether the data transmission channel of the memory is currently idle based on the data transmission signal value.

12. The memory according to claim 10 or 11, characterized in that, The interface impedance calibration unit is further configured to, in response to determining that the data transmission channel of the memory is currently idle, acquire a calibration value corresponding to the current temperature of the memory; and perform a first interface impedance calibration operation on the memory according to the calibration value.

13. The memory according to claim 12, characterized in that, The interface impedance calibration unit is also configured to, in response to determining that the data transmission channel of the memory is currently idle, acquire the current power supply voltage of the memory; and acquire a calibration value corresponding to the current temperature and current power supply voltage of the memory.

14. The memory according to claim 13, characterized in that, The storage unit array includes a configuration storage block, in which a lookup table is stored; The interface impedance calibration unit is also configured to retrieve the corresponding calibration value from the lookup table according to the current temperature and current power supply voltage of the memory.

15. The memory according to any one of claims 10 to 14, characterized in that, The peripheral circuitry also includes a temperature sensor configured to measure the temperature of the memory at a predetermined frequency. The control logic unit is further configured to, during the process of performing the target operation on the memory, obtain the temperature of the memory measured at the current time point or a first time point before the current time point as the current temperature, and obtain the temperature of the memory measured at the current time point or a second time point before the first time point as the historical temperature.

16. The memory according to any one of claims 10 to 14, characterized in that, The control logic unit is further configured to, in response to determining that the data transmission channel of the memory is currently occupied, determine whether to receive the second interface impedance calibration operation trigger information; and in response to determining that the second interface impedance calibration operation trigger information is received, send the first interface impedance calibration operation reset information to the interface impedance calibration unit.

17. A storage system, characterized in that, It includes the memory as described in any one of claims 9-16 and the controller coupled to the memory.

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