An operating method of a phase change memory, a control circuit and a phase change memory

Abstract

The application discloses an operating method of a phase change memory, a control circuit and the phase change memory, and relates to the technical field of memories. The method comprises the following steps: decoding an operation command to obtain a target operation address; determining a storage area where a phase change memory unit to be operated is located according to the target operation address; acquiring a timing adjustment parameter corresponding to the storage area where the phase change memory to be operated is located; adjusting a key stage timing of the phase change memory unit to be operated according to the timing adjustment parameter to obtain a target time length; and providing required energy for executing a target operation of the phase change memory unit to be operated by making the key stage timing last for the target time length. In this way, the required energy can be provided for the phase change memory unit to be operated located in different storage areas according to the timing adjustment parameter, so that the power consumption of the phase change memory for executing the target operation is reduced, and the cycle performance of the phase change memory is significantly improved.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to an operation method, control circuit, and phase-change memory. Background Technology

[0002] Phase-change memory (PCM) utilizes the difference in conductivity or impedance between crystalline and amorphous states of a specific phase-change material to store data, making it a non-volatile memory. A PCM block is a large-scale memory cell structure composed of numerous word lines (WL), bit lines (BL), and phase-change memory cells (PCM cells). The parasitic resistance inherent in the WL / BL is related to its length. Because the PCM cell's distance from the WL / BL driver varies, and the overall resistance of PCM cells at different locations differs, the energy required for write operations also varies. Therefore, a design is urgently needed to provide the necessary energy to PCM cells located in different memory regions within a PCM. Summary of the Invention

[0003] A method for operating a phase change memory, a control circuit, and a phase change memory are provided, which aim to provide the required energy for PCM cells located in different storage areas in a PCM.

[0004] In a first aspect, a method for operating a phase-change memory is provided. The phase-change memory includes multiple memory regions and a driving region, and each memory region includes multiple phase-change memory cells. The method includes: Decode the operation command to obtain the target operation address; The memory area where the phase-change memory cell to be operated is located is determined based on the target operation address; Obtain the timing adjustment parameters corresponding to the memory area where the phase-change memory to be operated is located; The timing of the critical stages of the phase-change memory cell to be operated is adjusted according to the timing adjustment parameters to obtain the target duration. The timing of the key stages is extended to the target duration to provide the energy required for the phase-change memory unit to perform the target operation.

[0005] In some embodiments, the operation method of the phase change memory further includes: configuring multiple sets of timing adjustment parameters for the phase change memory cells to be operated located in multiple memory areas; wherein each timing adjustment parameter corresponds to a memory area; and storing the multiple sets of timing adjustment parameters in a timing adjustment parameter table.

[0006] In some embodiments, the operation method of the phase-change memory further includes: dividing multiple storage areas according to the type and structure of the phase-change memory to obtain a first storage area and a second storage area; wherein the distance from the first storage area to the driving area is less than the distance from the second storage area to the driving area.

[0007] In some implementations, obtaining timing adjustment parameters corresponding to the memory region where the phase-change memory to be operated is located includes: obtaining a first timing adjustment parameter corresponding to a first memory region from a timing adjustment parameter table; and / or obtaining a second timing adjustment parameter corresponding to a second memory region from a timing adjustment parameter table.

[0008] In some implementations, the target duration includes: a first duration and a second duration; adjusting the timing of key stages of the phase-change memory cell to be operated according to timing adjustment parameters to obtain the target duration includes: adjusting the timing of key stages of the phase-change memory cell to be operated according to the first timing adjustment parameters to obtain the first duration; and / or adjusting the timing of key stages of the phase-change memory cell to be operated according to the second timing adjustment parameters to obtain the second duration; wherein the duration of the first duration is shorter than the duration of the second duration.

[0009] In some implementations, the critical stage timing is sustained for a target duration to provide the energy required for the phase-change memory cell to perform the target operation, including: sustaining the critical stage timing for a first duration to provide the energy required for the phase-change memory cell to perform the target operation located in a first memory area; and / or sustaining the critical stage timing for a second duration to provide the energy required for the phase-change memory cell to perform the target operation located in a second memory area.

[0010] In some embodiments, the operation method of the phase change memory further includes: dividing multiple storage areas according to the type and structure of the phase change memory to obtain a dynamic storage area; wherein the dynamic storage area is the storage area other than the first storage area and the second storage area.

[0011] In some implementations, dividing multiple storage areas according to the type and structure of the phase-change memory further includes: dividing the dynamic storage area into a first storage area according to the type and structure of the phase-change memory; or dividing the dynamic storage area into a second storage area according to the type and structure of the phase-change memory.

[0012] In a second aspect, a control circuit for a phase-change memory is also provided, for performing the steps of the phase-change memory operation method of the first aspect, including: The decoder is used to decode the operation command to obtain the target operation address; The region calculation module is used to determine the memory region where the phase-change memory cell to be operated is located based on the target operation address. The timing configuration module is used to obtain timing adjustment parameters corresponding to the memory area where the phase-change memory to be operated is located; The adjustment module adjusts the timing of key stages of the phase-change memory unit to be operated according to the timing adjustment parameters to obtain the target duration; The control module is used to maintain the timing of critical stages for the target duration, providing the necessary energy for the phase-change memory unit to perform the target operation.

[0013] Thirdly, a phase-change memory is also provided, comprising: At least one memory array, each memory array comprising multiple phase-change memory cells; The controller includes the control circuitry for the phase-change memory as provided in the second aspect.

[0014] According to the technical solution of this application, by obtaining the corresponding timing adjustment parameters through the storage area where the phase-change memory to be operated is located, the required energy can be provided to the phase-change memory cells located in different storage areas according to the timing adjustment parameters, thereby reducing the power consumption of the phase-change memory when performing the target operation, and thus significantly improving the cycle performance of the phase-change memory. At the same time, key performance parameters such as write interference, read window margin, and power consumption in the global region of the PCM array are optimized. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the resistance value distribution of the cross-structure phase memory provided in some embodiments of this application; Figure 2 This is a flowchart illustrating the operation method of a phase-change memory provided in some embodiments of this application; Figure 3 These are schematic diagrams of crystallization waveforms in different storage regions provided in some embodiments of this application; Figure 4 This is a schematic diagram of the control circuit of the phase change memory provided in some embodiments of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] In the description of the embodiments of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0019] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0020] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0021] In related technologies, phase change memory (PCM) utilizes the difference in conductivity or impedance between crystalline and amorphous states of specific phase change materials to store data, making it a type of non-volatile memory. A PCM block is a large-scale memory cell structure composed of numerous write lines / blanks (WL / BL) and PCM cells. The parasitic resistance inherent in the WL / BL is related to its length. Because the PCM cells are located at different distances from the WL / BL driver, and the overall resistance of PCM cells at different locations varies, the energy required for write operations also differs. Figure 1This is a schematic diagram of the resistance value distribution of the cross-structure phase memory provided in some embodiments of this application, such as... Figure 1 As shown, a block exhibits a regular distribution of resistance values ​​based on its positional range.

[0022] Phase-change memory (PCM) applications in servers must meet certain power consumption requirements. PCM stores data through the transition between crystalline and amorphous states; this transition takes a considerable amount of time, and reducing this time can effectively lower power consumption. Due to differences in manufacturing processes and cell locations, PCM cells in different positions exhibit varying crystallinity.

[0023] To at least partially address one or more of the aforementioned problems and other potential issues, this disclosure proposes an operation scheme for a phase-change memory (PCM). The scheme includes: decoding an operation command to obtain a target operation address; determining the memory region where the PCM cell to be operated is located based on the target operation address; obtaining timing adjustment parameters corresponding to the memory region where the PCM cell to be operated is located; adjusting the timing of critical stages of the PCM cell to be operated based on the timing adjustment parameters to obtain a target duration; and maintaining the critical stage timing for the target duration to provide the necessary energy for the PCM cell to perform the target operation. Thus, by obtaining the corresponding timing adjustment parameters based on the memory region where the PCM cell to be operated is located, the necessary energy can be provided to PCM cells located in different memory regions, thereby reducing the power consumption of the PCM when performing the target operation and significantly improving the cyclic performance of the PCM.

[0024] Figure 2 This is a flowchart illustrating the operation method of a phase-change memory provided in some embodiments of this application, such as... Figure 2 As shown, the method includes at least the following steps: S201: Decode the operation command to obtain the target operation address; S202: Determine the memory area where the phase-change memory cell to be operated is located based on the target operation address; S203: Obtain the timing adjustment parameters corresponding to the memory area where the phase-change memory to be operated is located; S204: Adjust the timing of the critical stages of the phase-change memory cell to be operated according to the timing adjustment parameters to obtain the target duration; S205: The timing of the critical stage is maintained for the target duration to provide the energy required for the phase-change memory cell to perform the target operation.

[0025] The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0026] S201: Decode the operation command to obtain the target operation address.

[0027] In some embodiments, the operation instruction may be a command sent from the external controller or processor of the phase-change memory to the phase-change memory. For example, when the phase-change memory needs to perform a target operation, the external controller generates an operation command containing the target operation address.

[0028] In some embodiments, decoding an operation command to obtain a target operation address includes: a decoder receiving an operation command; and decoding the operation command using preset decoding logic to obtain the target operation address.

[0029] In some embodiments, the target operation address is used to locate the position of the phase-change memory cell to be operated and to determine the storage area where the phase-change memory cell to be operated is located based on the position of the phase-change memory cell to be operated.

[0030] In some embodiments, the phase-change memory (PCM) includes multiple memory regions and a driving region, each memory region including multiple PCM cells. The multiple memory regions are divided according to the electrical distance between the PCM cells and the word line driver and the bit line driver. The PCM cells in different memory regions have different electrical distances to the drivers due to differences in the parasitic resistance of the word lines and bit lines. PCM cells with greater electrical distances require more power from the drivers when performing write operations. The memory region includes a first memory region and a second memory region; wherein the first memory region has a smaller electrical distance, and the second memory region has a larger electrical distance. However, depending on the type and structure of the PCM, the memory region may also include a dynamic memory region; wherein the dynamic memory region can be an intermediate region between the first memory region and the second memory region. Figure 3 These are schematic diagrams of crystallization waveforms in different memory regions provided in some embodiments of this application, such as... Figure 3 As shown, the region closest to the word line driver or bit line driver is defined as region 1 (i.e., the first memory region). During operation, the large overshoot current in region 1 results in poor cycling performance. To meet a certain number of cycles, the crystallization waveform in region 1 requires T1ns (nanoseconds). The region farther from the word line driver or bit line driver is defined as region 2 (i.e., the second memory region), where the crystallization waveform requires T2ns, and the duration of T1 is shorter than that of T2. Region 3, located between region 1 and region 2, requires a crystallization waveform with a T3ns duration between T1 and T2. By dividing the memory region into different areas and assigning different crystallization durations, the phase-change memory cells in each region can be provided with more precise energy, avoiding energy waste or insufficiency.

[0031] It should be noted that the dynamic storage area refers to the storage areas other than the first and second storage areas. When dividing the storage areas of the phase change memory, the dynamic storage area can be assigned to the first storage area or assigned to the second storage area according to the type and structure of the phase change memory.

[0032] In some embodiments, the target operation type includes: a first write operation and a second write operation; wherein, the first write operation is a set operation to transform the phase change material from an amorphous state to a crystalline state, which requires a relatively long crystallization time to form a stable crystalline structure, thereby achieving data storage in a low-resistivity state. The second write operation is a reset operation to transform the phase change material from a crystalline state to an amorphous state, which requires high instantaneous energy to rapidly melt the phase change material and form an amorphous state through rapid cooling, thereby achieving data storage in a high-resistivity state.

[0033] S202: Determine the memory area where the phase-change memory cell to be operated is located based on the target operation address.

[0034] In some embodiments, the memory area includes a first memory area and a second memory area; the distance from the first memory area to the driver area is less than the distance from the second memory area to the driver area. The driver area refers to the region where word line drivers or bit line drivers are deployed; the driver area includes a word line driver area and a bit line driver area. These word line driver areas and bit line driver areas are typically located in the peripheral area of ​​the memory array. For example, the word line driver area can be arranged along the row edge of the memory array to drive the selection and signal application of each word line; the bit line driver area can be arranged along the column edge of the memory array to drive the bit lines and detect signals. The word line driver area refers to the circuit area capable of providing drive signals to word lines, containing multiple word line drivers (WL drivers), each corresponding to one word line, used to select the corresponding word line according to the row address signal and apply the voltage or current signal required for the write operation to the selected word line. The bit line driver area refers to the circuit area capable of providing drive signals to bit lines and detecting signals, containing bit line drivers (BL drivers) used to control the operating state of the bit lines according to the column address signal.

[0035] In some embodiments, determining the storage area where the phase-change memory cell to be operated is located based on the target operation address includes: determining the specific location of the phase-change memory cell to be operated in the storage array based on the row address and column address information in the target operation address; and determining the storage area where the phase-change memory cell to be operated is located based on the specific location of the phase-change memory cell to be operated in the storage array. For example, the storage array is pre-divided into multiple diamond shapes (e.g., based on their distance from word line drivers and bit line drivers). Figure 1The memory is divided into a matrix-like storage area, with each storage area corresponding to a specific address range. The target operation address is obtained, and the target operation address is parsed by the address decoder to obtain the row number and column number corresponding to the target operation address. The row number and column number are compared with the preset address range of each storage area. If the row number and column number fall within the address range of storage area A, it is determined that the phase change memory cell to be operated is located in storage area A.

[0036] For example, a memory array with 1024 rows and 1024 columns can be divided into memory area 1, memory area 2, and memory area 3. Memory area 1 contains phase-change memory cells within the range of row address 512±64 and column address 512±64. Phase-change memory cells in memory area 1 are close to the word line driver area or bit line driver area, and have the lowest parasitic resistance. Memory area 2 contains phase-change memory cells outside the range of row address 512±128 to 512±64 and column address 512±128 to 512±64. Memory area 3 contains phase-change memory cells within the remaining range of row and column addresses. Phase-change memory cells in memory area 3 are far from the word line driver area or bit line driver area, and have the highest parasitic resistance. In this way, the memory area where the phase-change memory cell to be operated is located can be quickly and accurately determined according to the target operation address.

[0037] S203: Obtain the timing adjustment parameters corresponding to the memory area where the phase-change memory to be operated is located.

[0038] In some embodiments, obtaining the timing adjustment parameters corresponding to the storage area where the phase-change memory to be operated is located includes: configuring multiple sets of timing adjustment parameters for the phase-change memory cells to be operated located in multiple storage areas, each set of timing adjustment parameters corresponding to a storage area; and obtaining timing adjustment parameters matching the storage area where the phase-change memory to be operated is located from the multiple sets of timing adjustment parameters according to the storage area where the phase-change memory to be operated is located. The timing adjustment parameters for adjusting the first write operation may include: current pulse width and current amplitude; the timing adjustment parameters for adjusting the second write operation may include: current pulse width, current amplitude, rise time, and fall time. It should be noted that the above is only an illustrative example and is not intended to limit all possible contents of the timing adjustment parameters; it is simply not exhaustive.

[0039] For example, when the phase change memory cell to be operated is located in a storage area close to the driving area, the storage area is the first storage area; if the phase change memory cell to be operated is the first storage cell, when the phase change memory cell to be operated performs the first write operation, the timing adjustment parameters corresponding to the first storage area (e.g., the current pulse width is 50ns and the current amplitude is 1.2mA) are obtained from the timing adjustment parameter table.

[0040] For example, when the phase-change memory cell to be operated is located in a memory region far from the driving region, this memory region is designated as the second memory region. If the phase-change memory cell to be operated is the second memory cell, when the phase-change memory cell to be operated performs the first write operation, the timing adjustment parameters corresponding to the second memory region are obtained from the timing adjustment parameter table (e.g., current pulse width of 10ns, current amplitude of 3.5mA, rise time of 2ns, and fall time of 1ns). In this way, precise timing adjustment parameters can be provided for the parasitic resistance characteristics of different memory regions and the energy requirements of different operation types.

[0041] S204: Adjust the timing of the critical stages of the phase-change memory cell to be operated according to the timing adjustment parameters to obtain the target duration.

[0042] In some embodiments, the critical stage timing refers to the current pulse application stage during which the phase change memory to be operated plays a decisive role in the state transition of the phase change material during the execution of the target operation. For the first write operation, the critical stage timing can be the stage in which the phase change material begins to crystallize from an amorphous state and gradually forms a stable crystalline structure. The current pulse width in this stage directly affects the degree of crystallization and the stability of the crystalline structure. By adjusting the current pulse width and amplitude in this stage, it can be ensured that the phase change material obtains sufficient energy to complete the crystallization transition, while avoiding material loss due to excessive energy. For the second write operation, the critical stage timing can be the stage in which the phase change material is rapidly heated to a molten state and then rapidly cooled to form an amorphous state. The current pulse amplitude, rise time, and fall time in this stage are crucial. A higher current amplitude and a steep rise time can achieve rapid melting of the material, while a rapid fall time can ensure that the molten zone cools rapidly to form an amorphous state. Adjusting these parameters can precisely control the melting and rapid cooling processes to ensure the stable formation of the amorphous state.

[0043] S205: The timing of the critical stage is maintained for the target duration to provide the energy required for the phase-change memory cell to perform the target operation.

[0044] For example, when the phase change memory cell to be operated is located in storage area 1 and performs the first write operation, the current output timing of the key stages in the write operation is adjusted according to its corresponding timing adjustment parameters (such as current pulse width T1ns and current amplitude I1mA). Specifically, during the crystallization stage of the set operation, the current source is controlled to output a current pulse with a width of T1ns and an amplitude of I1mA. This pulse can just meet the energy required for the crystallization of the phase change material in the phase change memory cell to be operated in storage area 1, thus avoiding damage to the cycle performance caused by overshoot current due to excessive current or pulse duration, and ensuring that the phase change material can stably transform into a crystalline state. When the cell to be operated is located in storage area 2 and performs the first write operation, based on its corresponding longer pulse width T2ns (T2>T1) and the appropriate current amplitude I2mA (I2>I1), the energy loss caused by the large parasitic resistance is compensated by extending the duration of the current pulse, ensuring that the phase change memory cell far from the driving area can also obtain sufficient energy to complete the crystallization. In this way, each phase-change memory cell can receive an energy supply that is highly matched to its location characteristics when performing a write operation, thereby minimizing the power consumption of the write operation and extending the service life of the phase-change memory while ensuring the reliability of data storage.

[0045] In some embodiments, the target duration refers to the specific duration of the critical stage timing after the timing adjustment parameters have been adjusted, which directly determines how much energy the phase change memory cell to be operated acquires during the critical stage.

[0046] The solution of this disclosure obtains the corresponding timing adjustment parameters by determining the storage area where the phase-change memory (PCM) to be operated is located. Based on these timing adjustment parameters, the required energy can be provided to the PCM cells located in different storage areas, thereby reducing the power consumption of the PCM when performing the target operation and significantly improving the cyclic performance of the PCM. Simultaneously, key performance parameters such as write interference, read window margin, and power consumption in the global region of the PCM array are optimized.

[0047] In this embodiment of the disclosure, the operation method of the phase-change memory further includes: configuring multiple sets of timing adjustment parameters for each phase-change memory cell to be operated located in multiple memory areas; wherein each set of timing adjustment parameters corresponds to one memory area; Store multiple sets of timing adjustment parameters in a timing adjustment parameter table.

[0048] The energy required for a phase-change memory cell located in a different storage area to perform the target operation varies.

[0049] In some embodiments, the multiple sets of timing adjustment parameters can be stored in a timing adjustment parameter table. After determining the storage area where the phase change memory to be operated is located, the timing adjustment parameters corresponding to the storage area where the phase change memory to be operated is located are retrieved from the timing adjustment parameter table.

[0050] In some embodiments, the varying distances between different memory regions and the drive region result in different lengths of the word lines and bit lines connecting them. Memory regions farther from the drive region have longer word lines and bit lines, leading to greater parasitic resistance. During a write operation, current must flow through these word lines and bit lines to reach the phase-change memory cell to be operated on. The presence of parasitic resistance causes a voltage drop, reducing the effective voltage applied across the phase-change memory cell. To ensure the phase-change material receives sufficient energy to complete the corresponding state transition (whether it's the crystallization energy required for a set operation or the melting and quenching energy required for a reset operation), higher energy is required. For example, for a set operation, the phase-change memory cell located in the second memory region may require a higher current amplitude or a longer current pulse width compared to the phase-change memory cell located in the first memory region to compensate for the energy loss caused by parasitic resistance, ensuring that the phase-change material can fully crystallize and reach a stable low-resistance state. Conversely, for the reset operation, although its instantaneous energy requirement is high, the parasitic resistance will also consume some energy. Therefore, it is necessary to adjust the current pulse parameters (such as amplitude, width, rise time and fall time) of the reset operation according to the storage area location of the phase change memory cell to be operated, so as to ensure that the phase change material can be effectively melted and rapidly cooled into an amorphous state.

[0051] In this way, by configuring multiple sets of timing adjustment parameters for the phase change memory units to be operated in multiple memory areas, it is possible to adapt to the electrical characteristics requirements of different memory areas to the greatest extent possible, thereby ensuring the reliability of the target operation while achieving precise energy delivery and effective power consumption control.

[0052] In this embodiment of the disclosure, the operation method of the phase change memory further includes: dividing multiple storage areas according to the type and structure of the phase change memory to obtain a first storage area and a second storage area; wherein the distance from the first storage area to the driving area is less than the distance from the second storage area to the driving area.

[0053] For example, in a phase-change memory (PCM) employing a cross-shaped array structure, the memory array is composed of numerous word lines extending along the row direction and bit lines extending along the column direction, with the PCM cells located at the intersections of the word lines and bit lines. Specifically, for a rectangular cross-shaped memory array, the area closest to the word line driving region can be designated as the first memory region. PCM cells located in the first memory region have shorter word line lengths and lower parasitic resistance due to their proximity to the driving region. Conversely, the central region of the array or the region far from at least one driving region can be designated as the second memory region. PCM cells located in the second memory region have longer word line or bit line lengths and relatively higher parasitic resistance. For phase-change memory with transistor gating structure, its storage cell is usually connected in series with an access transistor. The drive signal needs to pass through the source, drain and metal interconnect of the transistor to reach the phase-change material. In this case, when dividing the storage area, in addition to considering the distance from the peripheral drive circuit module, it may also be necessary to consider the on-resistance characteristics of the access transistor itself and the resistance difference caused by the layout of the metal interconnect. The area with a smaller total parasitic resistance of the electrical path is divided into the first storage area, and the area with a larger total parasitic resistance is divided into the second storage area.

[0054] It should be noted that the farther the storage area is from the driving area, the greater the energy required for the phase-change memory cell to perform the target operation located in the storage area; the closer the storage area is to the driving area, the less energy required for the phase-change memory cell to perform the target operation located in the storage area.

[0055] In this way, by dividing the storage array into multiple storage areas at different distances from the drive area, the problem of uneven electrical performance caused by differences in physical layout can be effectively compensated, ensuring the operational consistency and reliability of the phase storage cells in the entire storage array.

[0056] In this embodiment of the disclosure, obtaining timing adjustment parameters corresponding to the storage area where the phase-change memory to be operated is located includes: obtaining a first timing adjustment parameter corresponding to the first storage area from a timing adjustment parameter table; and / or obtaining a second timing adjustment parameter corresponding to the second storage area from a timing adjustment parameter table.

[0057] For example, in the first memory region, which is close to the drive region and has lower parasitic resistance, the timing adjustment parameters for a write operation are a current amplitude of 1.0 mA and a pulse width of 40 ns to provide continuous and stable crystallization energy. For the second memory region, which is far from the drive region and has higher parasitic resistance, the timing adjustment parameters for a write operation are adjusted to a current amplitude of 1.2 mA and a pulse width of 45 ns. This allows for precise energy delivery and effective power consumption control.

[0058] In this embodiment of the disclosure, the target duration includes: a first duration and a second duration; adjusting the timing of key stages of the phase-change memory unit to be operated according to timing adjustment parameters to obtain the target duration includes: adjusting the timing of key stages of the phase-change memory unit to be operated according to the first timing adjustment parameters to obtain the first duration; and / or adjusting the timing of key stages of the phase-change memory unit to be operated according to the second timing adjustment parameters to obtain the second duration; wherein, the duration of the first duration is less than the duration of the second duration.

[0059] In this embodiment of the disclosure, the timing of the critical stage is sustained for a target duration to provide the energy required for the phase-change memory cell to perform the target operation, including: sustaining the timing of the critical stage for a first duration to provide the energy required for the phase-change memory cell to perform the target operation in the first storage area; and / or sustaining the timing of the critical stage for a second duration to provide the energy required for the phase-change memory cell to perform the target operation in the second storage area.

[0060] Specifically, because the first memory region is close to the word line driving region or bit line driving region, its word lines and bit lines are shorter, resulting in lower parasitic resistance. During the target operation, the energy loss of current flowing through the word lines and bit lines is relatively low, ensuring more effective energy reaches the phase-change memory cell. To avoid increased power consumption due to excess energy and its impact on cell lifetime, a first timing adjustment parameter is used to adjust the duration of the critical stage timing of the phase-change memory cell to be operated on in the first memory region, resulting in a first duration.

[0061] In some embodiments, the first duration refers to the time required for the phase change memory cell located in the first storage area to undergo a critical phase transition of the phase change material during the execution of the target operation. For example, in a set operation, the critical phase may be the process by which the phase change material crystallizes from an amorphous state and gradually forms a stable crystalline phase structure, and the first duration is the current pulse width required to ensure that the crystallization process is fully completed so that the phase change memory cell reaches a stable low-resistance state; in a reset operation, the critical phase may be the process by which the phase change material is heated above its melting point and kept in a molten state, and then rapidly cooled to form an amorphous state, and the first duration corresponds to the current pulse width required to ensure that the phase change material is fully melted and to provide a sufficient time window for subsequent rapid cooling.

[0062] For example, when the phase change memory cell located in the first storage area performs a first write operation, the first timing adjustment parameter adopts a lower current amplitude or shorter pulse width relative to the first storage area, without considering the small parasitic resistance, to precisely control the energy input. This ensures that the phase change material completes the crystallization process and forms a stable crystalline state while avoiding unnecessary energy consumption. Similarly, when the phase change memory cell located in the first storage area performs a second write operation, the first timing adjustment parameter will correspondingly shorten the duration of the current pulse or reduce the instantaneous energy peak. Utilizing the advantage of smaller parasitic resistance, this optimizes the timing and precisely delivers energy while ensuring that the phase change material melts rapidly and cools quickly to an amorphous state.

[0063] For example, for the second write operation in the first storage area, while ensuring rapid melting of the crystalline phase change material, the rise time of the current pulse can be shortened from the original 1.2ns to 1.0ns, allowing the current to reach its peak and complete the melting process more quickly. At the same time, after the phase change material has been fully melted, the pulse width can be shortened from 11ns to 10ns, and the fall time can be shortened from 0.6ns to 0.5ns to accelerate the current cutoff and achieve rapid solidification. This effectively shortens the overall phase current action time while ensuring the amorphous state transformation effect, reduces the ineffective energy output, and further improves the energy efficiency ratio of the phase change memory when operating in the first storage area.

[0064] In some embodiments, the second duration refers to the time required for the phase change memory cell located in the second storage region to undergo a critical phase transition of the phase change material during the execution of a target operation. Because the distance from the first storage region to the drive region is less than the distance from the second storage region to the drive region, its word lines and bit lines are longer, resulting in greater parasitic resistance. During the execution of the target operation, the energy loss of current flowing through these lines is higher, and the effective energy reaching the phase change memory cell is relatively insufficient. Therefore, to ensure that the phase change material can absorb sufficient energy to reliably transition from one state to another, the second duration determined by the second timing adjustment parameter needs to be longer than the first duration. For example, in a set operation, for a phase change memory cell in the second storage region, due to energy attenuation caused by parasitic resistance, the process of the phase change material crystallizing from an amorphous state to form a stable crystalline phase structure requires a longer current pulse duration. That is, the second duration should be set longer than the first duration of the first storage region to ensure that the crystallization process is fully completed, allowing the cell to reach a stable low-resistance state. In the reset operation, the phase change material is heated above its melting point and kept in a molten state before being rapidly cooled to form an amorphous state. Due to energy loss during transmission, a longer pulse width is required to ensure that the phase change material is fully melted and to provide a sufficient time window for subsequent rapid cooling. Therefore, the second duration will be correspondingly longer than the first duration of the first storage area during the reset operation.

[0065] For example, when the phase-change memory cell located in the second storage region performs a first write operation, the second timing adjustment parameters will employ a higher current amplitude and / or a longer pulse width than those in the first storage region. Assuming the first storage region has a current amplitude of 1.0 mA and a pulse width of 40 ns during the first write operation, the second storage region, due to its higher parasitic resistance, may have its corresponding current amplitude adjusted to 1.2 mA and its pulse width extended to 45 ns to compensate for energy loss. This additional current and time ensures that despite significant energy loss along the circuit, the energy reaching the phase-change memory cell is still sufficient to drive the phase-change material to crystallize from an amorphous state, gradually forming a stable crystalline phase structure, and ultimately reaching a stable low-resistance state. Similarly, the second timing adjustment parameters will be compensated accordingly during the second write operation. In the reset operation, in order to ensure that the phase change material can be heated above the melting point and maintain sufficient melting time, the second timing adjustment parameters may increase the peak value of the current pulse, for example, from 2.5mA in the first storage area to 2.8mA, while extending the pulse width from 10ns in the first storage area to 12ns.

[0066] In this embodiment of the disclosure, the operation method of the phase change memory includes: dividing multiple storage areas according to the type and structure of the phase change memory to obtain a dynamic storage area; wherein, the dynamic storage area is the storage area other than the first storage area and the second storage area.

[0067] In this embodiment of the disclosure, the division of multiple storage areas according to the type and structure of the phase change memory further includes: dividing the dynamic storage area into the first storage area according to the type and structure of the phase change memory; or dividing the dynamic storage area into the second storage area according to the type and structure of the phase change memory.

[0068] For example, the phase-change memory includes six memory regions (denoted as memory region 1, memory region 2, memory region 3, memory region 4, memory region 5, and memory region 6). Regions 1 and 2 are 50 nm away from the driving region, regions 3 and 4 are 90 nm away, and regions 5 and 6 are 150 nm away. Regions 1 and 2 are designated as the first memory region, and regions 5 and 6 are designated as the second memory region. Further, regions 3 and 4 can be designated as dynamic memory regions. Specifically, region 3 can be assigned to the first memory region, and timing adjustment parameters corresponding to the first region can be used to adjust the timing of key stages of the phase-change memory cell to be operated; region 4 can also be assigned to the second memory region, and timing adjustment parameters corresponding to the second region can be used.

[0069] In some embodiments, for phase-change memory cells in the dynamic memory region, when acquiring timing adjustment parameters, a more refined correspondence model between parasitic resistance and timing parameters can be established. By real-time monitoring or pre-measuring the actual parasitic resistance values ​​of each cell in the dynamic memory region, the most suitable dynamic timing adjustment parameters can be matched from the timing adjustment parameter table.

[0070] It should be noted that the allocation of the dynamic storage area to the first storage area or the second storage area can be adjusted based on factors such as the actual application requirements for memory performance, the specific measured values ​​of parasitic resistance in different areas, and the frequency of operations.

[0071] Figure 4 This is a schematic diagram of the control circuit of the phase-change memory provided in some embodiments of this application, such as... Figure 4 As shown, the circuit includes at least: The decoder is used to decode the operation command to obtain the target operation address; The region calculation module is used to determine the memory region where the phase-change memory cell to be operated is located based on the target operation address. The timing configuration module is used to obtain timing adjustment parameters corresponding to the memory area where the phase-change memory to be operated is located; The adjustment module is used to adjust the timing of key stages of the phase-change memory cell to be operated according to the timing adjustment parameters to obtain the target duration; The control module is used to maintain the timing of critical stages for the target duration, providing the necessary energy for the phase-change memory unit to perform the target operation.

[0072] refer to Figure 4The decoder receives the operation command and decodes it to obtain the target operation address. The region calculation module determines the storage area corresponding to the phase storage unit to be operated based on the decoded target operation address. According to the storage area, it obtains timing adjustment parameter 1 from the corresponding signal groups "Write Operation_Stage 1_Region 1_Fine-tuning Signal", "Write Operation_Stage 1_Region 2_Fine-tuning Signal", and "Write Operation_Stage 1_Region 3_Fine-tuning Signal". According to the storage area, it obtains timing adjustment parameter 1 from the corresponding signal groups "Write Operation_Stage 2_Region 1_Fine-tuning Signal", "Write Operation_Stage 2_Region 2_Fine-tuning Signal", and "...". The timing adjustment parameter 2 is obtained from "Write Operation_Phase 2_Region 3_Fine-tuning Signal"; timing adjustment parameter 1 is sent to the Write Operation_Phase 1 counter, which triggers the Phase 1 start signal, and feedback is given upon completion of Phase 1; timing adjustment parameter 2 is sent to the Write Operation_Phase 2 counter, which triggers the Phase 2 start signal, and feedback is given upon completion of Phase 2; the adjustment module adjusts the timing of the key stages of the phase change memory cell to be operated according to the timing adjustment parameters to obtain the target duration; the control module maintains the timing of the key stages for the target duration to provide the energy required for the phase change memory cell to perform the target operation.

[0073] In some embodiments, the timing configuration module includes a stage counter and a multiplexer. The stage counter is used to generate precise time sequence signals required for different operations based on preset reference timing and key stage adjustment parameters, such as the start time, duration, and end time of a control current pulse. The multiplexer is used to select and output corresponding parameters from multiple sets of timing adjustment parameters to the timing counter based on the storage area where the phase-change memory cell to be operated is located and the target operation type, so as to drive the counter to generate timing signals adapted to the current operation scenario. For example, when the area calculation module determines that the phase-change memory cell to be operated is located in the first storage area and the target operation type is the second write operation, the multiplexer will select the timing adjustment parameters corresponding to the second write operation in the first storage area (such as a current amplitude of 5.0mA and a pulse width of 10ns) and input the timing adjustment parameters into the timing counter. The counter then generates a pulse timing control signal containing a rise time of 1ns and a fall time of 0.5ns, which is then applied to the bit line and word line drivers by the control module to achieve precise energy delivery to the phase-change memory cell.

[0074] In this way, the required energy can be provided to the phase change memory cells located in different storage areas according to the timing parameters, thereby reducing the power consumption of the phase change memory write operation and significantly improving the cycle performance of the phase change memory.

[0075] In another embodiment of this disclosure, a phase-change memory is provided, comprising: At least one memory array, each memory array comprising multiple phase-change memory cells; The control circuit of the phase change memory as described in the foregoing embodiments.

[0076] In this way, by adjusting the timing parameters, the required energy is provided to the phase-change memory cells located in different memory areas, thereby reducing the power consumption of the phase-change memory write operation and significantly improving the cycle performance of the phase-change memory.

[0077] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0078] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0079] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for operating a phase-change memory (PCM), wherein the PCM includes multiple storage areas and a driving area, each storage area including multiple PCM cells, characterized in that, The method includes: Decode the operation command to obtain the target operation address; The memory area where the phase-change memory cell to be operated is located is determined based on the target operation address; Obtain the timing adjustment parameters corresponding to the storage area where the phase-change memory to be operated is located; The timing of the key stages of the phase-change memory cell to be operated is adjusted according to the timing adjustment parameters to obtain the target duration; The timing of the key stages is extended to the target duration to provide the energy required for the phase-change memory unit to perform the target operation.

2. The method according to claim 1, characterized in that, The method further includes: Multiple sets of timing adjustment parameters are configured for each phase-change memory cell to be operated, located in multiple storage areas; wherein each set of timing adjustment parameters corresponds to one of the storage areas. Multiple sets of timing adjustment parameters are stored in a timing adjustment parameter table.

3. The method according to claim 2, characterized in that, Also includes: The multiple storage areas are divided according to the type and structure of the phase change memory to obtain a first storage area and a second storage area; wherein the distance from the first storage area to the driving area is less than the distance from the second storage area to the driving area.

4. The method according to claim 3, characterized in that, The step of obtaining timing adjustment parameters corresponding to the memory region where the phase-change memory to be operated is located includes: Obtain the first timing adjustment parameter corresponding to the first storage area from the timing adjustment parameter table; and / or Obtain the second timing adjustment parameter corresponding to the second storage area from the timing adjustment parameter table.

5. The method according to claim 4, characterized in that, The target duration includes: a first duration and a second duration; adjusting the timing of key stages of the phase-change memory cell to be operated according to the timing adjustment parameters to obtain the target duration includes: The timing of key stages of the phase-change memory cell to be operated is adjusted according to the first timing adjustment parameter to obtain the first duration; and / or The timing of the key stages of the phase-change memory cell to be operated is adjusted according to the second timing adjustment parameter to obtain the second duration; The duration of the first duration is shorter than the duration of the second duration.

6. The method according to claim 5, characterized in that, The step of extending the timing of the key stages for the target duration to provide the energy required for the phase-change memory cell to perform the target operation includes: The key stage timing is maintained for the first duration to provide the necessary energy for the phase-change memory cell located in the first storage area to perform the target operation; and / or The key stage timing is extended for the second duration to provide the energy required for the phase-change memory cell to be operated in the second storage area to perform the target operation.

7. The method according to claim 3, characterized in that, Also includes: The multiple storage areas are divided according to the type and structure of the phase change memory to obtain a dynamic storage area; wherein, the dynamic storage area is the other storage areas besides the first storage area and the second storage area.

8. The method according to claim 7, characterized in that, The step of dividing the multiple storage areas according to the type and structure of the phase-change memory further includes: The dynamic storage area is allocated to the first storage area according to the type and structure of the phase-change memory; or The dynamic storage area is divided into the second storage area according to the type and structure of the phase change memory.

9. A control circuit for a phase-change memory, characterized in that, The steps for performing the operation method as described in any one of claims 1 to 8 include: The decoder is used to decode the operation command to obtain the target operation address; The region calculation module is used to determine the storage area where the phase-change memory unit to be operated is located based on the target operation address; The timing configuration module is used to obtain timing adjustment parameters corresponding to the storage area where the phase-change memory to be operated is located; The adjustment module adjusts the timing of key stages of the phase-change memory unit to be operated according to the timing adjustment parameters to obtain the target duration; The control module is used to maintain the timing of the key stages for the target duration, thereby providing the energy required for the phase-change memory unit to perform the target operation.

10. A phase-change memory, characterized in that, include: At least one memory array, each of the memory arrays comprising a plurality of phase-change memory cells; The controller includes the control circuitry for the phase-change memory as described in claim 9.

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