Storage device, storage controller, and universal flash storage system

Abstract

A storage device, a storage controller, and a general flash memory storage system are provided. The storage device includes: a first nonvolatile memory device including a first current management circuit configured to determine an execution timing of a first command based on first peak information, and output first elapsed time information indicating an internal operation time according to the first command; a second nonvolatile memory device including a second current management circuit configured to determine an execution timing of a second command based on the first peak information, and output second elapsed time information indicating an internal operation time according to the second command; and a storage controller including a peak manager circuit configured to deactivate a malfunctioning current management circuit among the first current management circuit and the second current management circuit based on the first elapsed time information and the second elapsed time information.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0178469, filed with the Korean Intellectual Property Office on December 4, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to storage devices, storage controllers, and general-purpose flash memory storage systems. Background Technology

[0003] Recently, with the increasing versatility of information and communication devices, there is a growing demand for larger capacity and higher integration of memory devices. In particular, research is underway on stacking non-volatile memory cells and increasing input / output speeds to address the need for high integration and high performance of non-volatile memory cells. However, memory operations on non-volatile memory devices can generate high peak currents exceeding a certain level, potentially severely compromising the overall performance and stability of memory devices comprising multiple non-volatile memory cells. Summary of the Invention

[0004] One or more embodiments provide a storage device for efficiently managing peak current periods with concentrated power consumption.

[0005] One or more embodiments also provide a storage device that efficiently manages peak current segments in response to abnormal operating current management circuitry.

[0006] According to one aspect of an embodiment, a storage device includes: a first non-volatile memory device including a first current management circuit configured to receive a first command and first peak information in a first mode and determine the execution timing of the first command based on the first peak information, wherein the first non-volatile memory device is configured to output first elapsed time information indicating internal operation time according to the first command; a second non-volatile memory device including a second current management circuit configured to receive a second command and first peak information in a first mode and determine the execution timing of the second command based on the first peak information, wherein the second non-volatile memory device is configured to output second elapsed time information indicating internal operation time according to the second command; and a storage controller including a peak manager circuit configured to: output the first peak information and deactivate a faulty current management circuit in the first current management circuit and the second current management circuit based on the first elapsed time information and the second elapsed time information.

[0007] According to another aspect of the embodiment, the memory controller includes: a processor configured to: output commands to control memory operations on a non-volatile memory device comprising a plurality of memory cells, and output dummy commands to control test operations on a current management circuit within the non-volatile memory device based on a signal representing the internal state of the non-volatile memory device; a peak manager circuit configured to: output pseudo-peak information indicating a peak current segment based on the dummy commands, receive elapsed time information indicating the internal operation time of the non-volatile memory device according to the dummy commands, and determine the performance of the current management circuit based on the elapsed time information; and a queue manager circuit configured to perform queue management operations for the non-volatile memory device based on the performance of the current management circuit.

[0008] According to another aspect of the embodiments, a Universal Flash Storage (UFS) system includes: a UFS host configured to determine a power budget; and a UFS device. The UFS device includes: a plurality of non-volatile memories, wherein one of the plurality of non-volatile memories includes current management circuitry configured to: share peak information of a peak current segment indicating a command based on the power budget and determine the execution timing of the command; and a UFS controller configured to: output a dummy command for testing the performance of the current management circuitry and a pseudo-peak signal including a predefined peak current segment, control the power of the current management circuitry based on the dummy command and the pseudo-peak signal based on the internal operating time of the plurality of non-volatile memories, and perform queue management operations on the plurality of non-volatile memories based on the internal operating time of the plurality of non-volatile memories. Attached Figure Description

[0009] The above and other aspects will become clearer from the following description of embodiments in conjunction with the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a storage device according to some embodiments.

[0011] Figure 2 This is a block diagram of a storage device according to some embodiments.

[0012] Figure 3 This is a diagram illustrating a semiconductor package according to some embodiments.

[0013] Figure 4A This is for illustrating the operation according to some embodiments. Figure 3 A diagram illustrating the method of using a memory die.

[0014] Figure 4B It is used to illustrate some embodiments Figure 3 A diagram illustrating the operation method of a memory die.

[0015] Figure 5 yes Figure 1 Block diagram of the storage controller.

[0016] Figure 6 yes Figure 1 Block diagram of a non-volatile memory device.

[0017] Figure 7 It is used for explanation Figure 6 The circuit diagram of the memory block of the memory cell array.

[0018] Figure 8 This is a diagram illustrating the operation of a non-volatile memory device according to some embodiments.

[0019] Figure 9 This is a timing diagram illustrating the operation method of a non-volatile memory device according to some embodiments.

[0020] Figure 10 This is a timing diagram illustrating the operation method of a non-volatile memory device according to some embodiments.

[0021] Figure 11 This is a timing diagram illustrating the operation method of a non-volatile memory device according to some embodiments.

[0022] Figure 12 This is a block diagram of a queue manager according to some embodiments.

[0023] Figure 13 This is a timing diagram used to illustrate the operation of a queue manager according to some embodiments.

[0024] Figure 14 This is a diagram showing the peak current value based on parameter settings of a non-volatile memory device according to some embodiments.

[0025] Figure 15 This is a flowchart illustrating a method of operating a storage device according to some embodiments.

[0026] Figure 16 This is a block diagram illustrating a solid-state drive (SSD) system for an application storage device according to some embodiments.

[0027] Figure 17 This is a block diagram illustrating a Universal Flash Storage (UFS) system according to some embodiments. Detailed Implementation

[0028] In the following detailed description, embodiments are described with reference to the accompanying drawings. Specific embodiments have been shown and described in the detailed description below. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention.

[0029] The accompanying drawings and description are intended to be illustrative in nature. Throughout the specification, the same reference numerals denote the same elements. For clarity of illustration, parts not directly related to the description may be omitted.

[0030] In the flowchart described with reference to the accompanying drawings, the order of operations can be changed, some operations can be combined, some operations can be split, and certain operations may not be performed.

[0031] Furthermore, unless explicitly stated as “a” or “singular” is used, a statement written in the singular can be interpreted as either singular or plural. Terms including ordinal numbers (such as first, second, etc.) can be used to describe various components, but components are not limited by these terms. These terms can be used to distinguish one component from another.

[0032] Figure 1 This is a block diagram illustrating a storage device according to some embodiments.

[0033] In some embodiments, the storage device 10 may include a storage controller 20 and a non-volatile memory device (NVM) 30. The non-volatile memory device 30 may include a plurality of non-volatile memory devices (NVMa) 31 and (NVMb) 33.

[0034] The storage controller 20 controls the overall operation of the storage device 10 and the overall data exchange between an external device (e.g., a host) and the non-volatile memory device 30. The storage controller 20 can be implemented as an integrated circuit (IC), a system-on-a-chip (SoC), an application processor (AP), a mobile AP, a chipset, or a collection of chips. As an example, the storage controller 20 can be a semiconductor device that controls the non-volatile memory device 30 to write or read data based on requests from the host, and the storage controller 20 can also be a component included in the application processor (AP).

[0035] The storage controller 20 can send a command (CMD) and an address (ADDR) to the non-volatile memory device 30 upon request from the host. When the non-volatile memory device 30 receives a command (CMD) and an address (ADDR) from the storage controller 20 to write data (DATA), the non-volatile memory device 30 can write the corresponding data (DATA) to the memory location corresponding to the address (ADDR). Furthermore, the storage controller 20 can be configured to run firmware for controlling the non-volatile memory device 30. For example, the non-volatile memory device 30 can be implemented in the form of a solid-state drive (SSD), a smart SSD, an embedded multimedia card (eMMC), an embedded universal flash memory (UFS) storage device, a UFS memory card, a compact flash (CF), a secure digital card (SD), a Micro-SD, a Mini-SD, an xD, a memory stick, or a similar form.

[0036] In some embodiments, the non-volatile memory device 30 may generate a ready / busy signal (RNB) indicating a busy state where an internal operation is being performed or a ready state where no internal operation is being performed (i.e., completed), and may send the ready / busy signal (RNB) to the memory controller 20. Specifically, the memory controller 20 may send a command to check the internal state of the non-volatile memory device 30, and the non-volatile memory device 30 may send a ready / busy signal (RNB) to the memory controller 20 in response to the command of the memory controller 20. For example, while the non-volatile memory device 30 reads data (DATA) in response to a read command from the memory controller 20 or writes data (DATA) in response to a write command from the memory controller 20, the non-volatile memory device 30 may send a ready / busy signal (RNB) indicating a busy state (e.g., logic low level) to the memory controller 20. Optionally, when the internal operation of the non-volatile memory device 30 is completed or not performed, the non-volatile memory device 30 may send a ready / busy signal indicating a ready state (e.g., a logic high level) to the memory controller 20. The memory controller 20 can check the internal state of the non-volatile memory device 30 via the ready / busy signal (RNB). In the present disclosure below, programming (or writing), reading, and erasing operations of the non-volatile memory device 30 are referred to as memory operations.

[0037] In some embodiments, the storage controller 20 may receive a power budget allocated to the storage device 10 from the host. The host may send the power budget allocated to the storage device 10 to the storage controller 20, but the embodiments are not limited thereto, and for example, the power budget of the storage device 10 may be provided by a power management integrated circuit (PMIC), may be determined in advance, or may be determined by the storage controller 20 within the storage device 10.

[0038] The power budget allocated to storage device 10 indicates the maximum power that storage device 10 can use. Alternatively, the power budget allocated to storage device 10 may indicate the maximum current or maximum voltage that the non-volatile memory devices 30 within storage device 10 can tolerate. When the non-volatile memory devices 30 in storage device 10 operate simultaneously and exceed the maximum current or maximum power, it is difficult to ensure the normal operation of storage device 10.

[0039] In some embodiments, each of the plurality of non-volatile memory devices 31, 33 in the non-volatile memory device 30 may include current management circuitry 31_1, 33_1. According to some embodiments, the current management circuitry 31_1, 33_1 may generate peak information associated with a command CMD received from the memory controller 20. For example, the current management circuitry 31_1, 33_1 may generate peak information in response to the command CMD. Here, the peak information associated with the command CMD may include information about a peak current section, which is a section of concentrated power consumption of the plurality of non-volatile memory devices 31, 33 in response to the command CMD. The current management circuitry 31_1, 33_1 may send peak information to at least a portion of the plurality of non-volatile memory devices 31, 33 within the non-volatile memory device 30, or receive peak information generated from at least a portion of the plurality of non-volatile memory devices 31, 33.

[0040] In some embodiments, current management circuits 31_1 and 33_1 can determine command execution timing based on peak information. Current management circuits 31_1 and 33_1 can control command execution timing based on peak information, ensuring that the peak current segments of the multiple non-volatile memory devices 31 and 33 do not overlap, and that the power consumed by the memory device 10 is managed to be below the power budget. (Referring later...) Figures 2 to 4B A detailed description of the current management circuits 31_1 and 33_1 is provided. In one embodiment, the current management circuits 31_1 and 33_1 may determine the execution timing of the command based on peak information of the peak current segment used for the command, which is shared by the power budget.

[0041] A portion of the current management circuits 31_1 and 33_1 may malfunction. For example, a portion of the current management circuits 31_1 and 33_1 may output incorrect information about peak current segments as peak information. Alternatively, even if peak current segments overlap and the power consumed by the storage device 10 exceeds the power budget, a portion of the current management circuits 31_1 and 33_1 may fail to control command execution timing. Optionally, even if peak current segments do not overlap, a portion of the current management circuits 31_1 and 33_1 may delay command execution timing. These malfunctions may lead to degradation of the storage device 10. Therefore, the storage device 10 needs to detect and respond to malfunctions in the current management circuits 31_1 and 33_1. In the following text, the malfunctioning current management circuit (i.e., the current management circuit in the current management circuits 31_1 and 33_1 that malfunctions) is referred to as a faulty (or abnormal) current management circuit.

[0042] In some embodiments, the memory controller 20 may include a peak manager 21 and a queue manager 23. The memory controller 20 may enter a test mode to locate a faulty current management circuit. Specifically, the memory controller 20 may generate a dummy command DCMD for locating the faulty current management circuit and send the dummy command DCMD to a plurality of non-volatile memory devices 31, 33. In some embodiments, the peak manager 21 may generate pseudo peak information (Pseudo Peak_Inf) and output the pseudo peak information (Pseudo Peak_Inf) together with or after the dummy command DCMD to the plurality of non-volatile memory devices 31, 33. The peak manager 21 may output a logic high level pseudo peak information (Pseudo Peak_Inf) during the peak current segment. The length of the peak current segment may be predetermined. However, the embodiments are not limited thereto, and the peak manager 21 may also output a logic low level pseudo peak information (Pseudo Peak_Inf) during the peak current segment. Peak manager 21 can output pseudo peak information (Pseudo Peak_Inf) to multiple non-volatile memory devices 31, 33, so that current management circuits 31_1, 33_1 control the execution timing of dummy command DCMD. Peak manager 21 can output pseudo peak information (Pseudo Peak_Inf) to multiple non-volatile memory devices 31, 33, so that current management circuits 31_1, 33_1 queue the dummy command DCMD in the command queue based on the peak current segment of pseudo peak information (Pseudo Peak_Inf), and execute the dummy command DCMD when the peak current segment of pseudo peak information (Pseudo Peak_Inf) ends.

[0043] In some embodiments, the plurality of non-volatile memory devices 31, 33 may not generate peak information about the dummy command DCMD in test mode or may not share peak information about the dummy command DCMD. In some embodiments, the plurality of non-volatile memory devices 31, 33 may output elapsed time information (Telapse) to the memory controller 20 in response to the dummy command DCMD and the pseudo peak information (Pseudo Peak_Inf). Here, the elapsed time information (Telapse) may include information about the peak current segment within the pseudo peak information (Pseudo Peak_Inf) and information about the actual internal operating time of the plurality of non-volatile memory devices 31, 33 via the dummy command DCMD. In some embodiments, the peak manager 21 may obtain the internal operating time of the plurality of non-volatile memory devices 31, 33 from the elapsed time information (Telapse) via the dummy command DCMD, and determine the faulty current management circuit based on the internal operating time. For example, the peak manager 21 may power off or disable the faulty current management circuit.

[0044] In some embodiments, queue manager 23 may perform queue management operations on non-volatile memory devices that include faulty current management circuitry. Specifically, queue manager 23 may determine a command to be sent to the non-volatile memory device including the faulty current management circuitry, or determine the timing of sending the command to the non-volatile memory device including the faulty current management circuitry. Optionally, queue manager 23 may change the settings of operating parameters for the non-volatile memory device including the faulty current management circuitry. (Refer to later...) Figures 9 to 14 A detailed description of Peak Manager 21 and Queue Manager 23.

[0045] Figure 2 This is a block diagram of a storage device according to some embodiments. The storage device 100 according to some embodiments can be... Figure 1 The storage device 10 corresponds to this.

[0046] Reference Figure 2 The non-volatile memory device 210 and the memory controller 200 can be connected via multiple channels CH1, CH2, ..., CHm (where m is an integer greater than 1). For example, the memory device 100 can be implemented as a memory device such as a solid-state drive (SSD). The non-volatile memory device 210 may include multiple non-volatile memory devices NVM11, NVM12, ..., NVMmn (where n is an integer greater than 1). The multiple non-volatile memory devices NVM11, NVM12, ..., NVMmn can be connected to... Figure 1The multiple non-volatile memory devices 31, 33 correspond to each other. The multiple non-volatile memory devices NVM11, NVM12, ..., NVMmn can be connected to the memory controller 200 via multiple channels CH1, CH2, ..., CHm. In some embodiments, each of the non-volatile memory devices NVM11, NVM12, ..., NVMmn can be implemented as any memory cell operable according to individual commands from the memory controller 200. For example, each of the non-volatile memory devices NVM11, NVM12, ..., NVMmn can be a memory die, and thus the memory device 100 can be a packaged chip including multiple dies; however, the embodiments are not limited to this, and for example, each of the non-volatile memory devices NVM11, NVM12, ..., NVMmn can be memory in a single packaged chip.

[0047] The memory controller 200 can control the non-volatile memory device 210 through multiple channels CH1, CH2, ..., CHm. For example, the memory controller 200 can send commands CMD, addresses ADDR, and data DATA to or receive data DATA from the non-volatile memory device 210 through multiple channels CH1, CH2, ..., CHm. Furthermore, the memory controller 200 can receive a ready / busy signal RNB from the non-volatile memory device 210 through multiple channels CH1, CH2, ..., CHm.

[0048] In some embodiments, a plurality of non-volatile memory devices NVM11, NVM12, ..., NVMmn may include a plurality of pads PAD1, PAD2, PAD3. The plurality of non-volatile memory devices NVM11, NVM12, ..., NVMmn can send and receive a shared clock signal PCLK and peak information Peak_Inf through shared input / output lines IO connected to the plurality of pads PAD1, PAD2, PAD3.

[0049] In some embodiments, multiple non-volatile memory devices NVM11, NVM12, ..., NVMmn can share a shared clock signal PCLK via a shared clock line Lc of a shared input / output line IO. Furthermore, the multiple non-volatile memory devices NVM11, NVM12, ..., NVMmn can send and receive peak information Peak_Inf via a shared data line Lp of a shared input / output line IO. Specifically, the first non-volatile memory device NVM11 among the multiple non-volatile memory devices NVM11, NVM12, ..., NVMmn can output the shared clock signal PCLK to the shared clock line Lc. In some embodiments, the first non-volatile memory device NVM11 among the multiple non-volatile memory devices NVM11, NVM12, ..., NVMmn can operate as a master device and output the shared clock signal PCLK. Multiple current management circuits within the multiple non-volatile memory devices NVM11, NVM12, ..., NVMmn ( Figure 1 The current management circuits 31_1 and 33_1 in the memory controller 200 can generate peak information Peak_Inf associated with the command CMD in response to receiving the command CMD from the memory controller 200, and transmit the peak information Peak_Inf to another non-volatile memory device via the shared data line Lp in synchronization with a specific period of the shared clock signal PCLK. For example, the first non-volatile memory device NVM11 can transmit the peak information Peak_Inf to other non-volatile memory devices NVM12, ..., NVMmn in synchronization with a specific period of the shared clock signal PCLK via the shared data line Lp. The first non-volatile memory device NVM11 can receive the peak information Peak_Inf output in synchronization with a specific period of the shared clock signal PCLK from the other non-volatile memory devices NVM12, ..., NVMmn. In some embodiments, each of the plurality of pads PAD1, PAD2, and PAD3 can be a transmit-only pad, a receive-only pad, or a transmit / receive combination pad. For example, a pad connected to the shared data line Lp (e.g., PAD2) may be a transmit / receive combination pad, a pad connected to the shared clock line Lc in the first non-volatile memory device NVM11 (e.g., PAD1) may be a transmit-only pad, and a pad connected to the shared clock line Lc in the remaining non-volatile memory devices NVM12, ..., NVMmn (e.g., PAD3) may be a receive-only pad, but the embodiments are not limited thereto.

[0050] In some embodiments, the peak information Peak_Inf associated with command CMD may include a first level indicating a peak current segment associated with command CMD and a second level indicating a non-peak current segment associated with command CMD. For example, when the non-volatile memory device NVM11 executes command CMD, if the non-volatile memory device NVM11 enters a peak current segment, the peak information Peak_Inf may have a first level (e.g., a logic high level). When the non-volatile memory device NVM11 executes command CMD, if the non-volatile memory device NVM11 has not yet entered a peak current segment, the peak information Peak_Inf may have a second level (e.g., a logic low level). However, embodiments are not limited thereto, and when entering a peak current segment, the peak information Peak_Inf may have a second level (e.g., a logic low level), and when not entering a peak current segment, the peak information Peak_Inf may have a first level (e.g., a logic high level).

[0051] Figure 2 The non-volatile memory device 210 shown communicates with the memory controller 200 through m channels and includes n non-volatile memory devices corresponding to each channel, but the number of channels and the number of non-volatile memory devices connected to a channel may vary.

[0052] Figure 3 This is a diagram illustrating a semiconductor package according to some embodiments. Specifically, Figure 3 This is a diagram illustrating a structure for sending and receiving peak information through multiple memory dies according to some embodiments.

[0053] Reference Figure 3 The semiconductor package 300 may include a package substrate SUB, a controller die DIEc, and multiple memory dies DIE1, DIE2, DIE3, and DIE4.

[0054] The controller die DIEc and multiple memory dies DIE1, DIE2, DIE3, and DIE4 can be placed on the upper surface of the package substrate SUB. In some embodiments, the package substrate SUB can be a ceramic substrate, PCB, organic substrate, intermediate substrate, etc. In some embodiments, the package substrate SUB can be referred to as a board or board substrate.

[0055] The controller die DIEc can be connected to the package substrate SUB via bump 310, and the package substrate SUB can be rewired by extending the bump 310 to an external area. Therefore, the package substrate SUB can be referred to as a redistribution substrate. The controller die DIEc can send and receive signals for requests, etc., to the outside via external connection terminals 330 and bump 310 located on the underside of the package substrate SUB. Multiple memory dies DIE1, DIE2, DIE3, and DIE4 can be stacked on the package substrate SUB in a direction perpendicular to the package substrate SUB, and at least some of the multiple memory dies DIE1, DIE2, DIE3, and DIE4 can be stacked on top of each other in a planar manner. Each of the multiple memory dies DIE1, DIE2, DIE3, and DIE4 can be connected to each other via first wires 321 connected to pads P1 to P4 arranged on each of the multiple memory dies DIE1, DIE2, DIE3, and DIE4. Furthermore, each of the plurality of memory dies DIE1, DIE2, DIE3 and DIE4 can be connected to each other via a second wire 323 connected to pads P5 to P8 arranged on each of the plurality of memory dies DIE1, DIE2, DIE3 and DIE4.

[0056] In some embodiments, the first memory die DIE1 can operate as the master device among a plurality of memory dies DIE1, DIE2, DIE3, and DIE4 and output an internal shared clock signal to the other memory dies DIE2, DIE3, and DIE4 via a first wire 321. Each of the plurality of memory dies DIE1, DIE2, DIE3, and DIE4 can transmit and receive peak information synchronously with a specific period of the internal shared clock signal via a second wire 323. For example, the first memory die DIE1 can transmit peak information synchronously with a first period of the internal shared clock signal, and the second memory die DIE2 can transmit peak information synchronously with a second period of the internal shared clock signal.

[0057] The configuration of semiconductor packages and memory devices is not limited to this. For example, when multiple memory dies DIE1, DIE2, DIE3, and DIE4 send and receive peak information in a master-slave manner, the fourth memory die DIE4 may have a higher priority than the third memory die DIE3, the third memory die DIE3 may have a higher priority than the second memory die DIE2, and the second memory die DIE2 may have a higher priority than the first memory die DIE1. In this case, the fourth memory die DIE4 may send its peak information to the third memory die DIE3, the third memory die DIE3 may send its peak information to the second memory die DIE2, and the second memory die DIE2 may send its peak information to the first memory die DIE1. That is, each of the multiple memory dies DIE1, DIE2, DIE3, and DIE4 can receive peak information from a memory die with a higher priority than itself and send peak information to a memory die with a lower priority than itself. Optionally, multiple memory dies DIE1, DIE2, DIE3, and DIE4 can form multiple groups, and the memory dies within the multiple groups can send and receive peak information in a master-slave manner. The semiconductor package 300 may include only one of the first wire 321 and the second wire 323 for sending and receiving peak information.

[0058] Figure 4A and Figure 4B This illustrates operation according to some embodiments. Figure 3 A diagram illustrating the method of using a memory die.

[0059] Reference Figure 4A The first memory die DIE1 and the second memory die DIE2 can receive the command CMD (see...). Figure 1 And execute commands simultaneously. The first memory die DIE1 and the second memory die DIE2 can output ready / busy signals RNB1 and RNB2, respectively, indicating busy status, while executing commands. When the first memory die DIE1 and the second memory die DIE2 execute commands simultaneously, the peak current segment PP1 of the first memory die DIE1 and the peak current segment PP2 of the second memory die DIE2 can overlap.

[0060] In this manner, when the peak current segment PP1 of the first memory die DIE1 and the peak current segment PP2 of the second memory die DIE2 overlap, the memory device including the first memory die DIE1 and the second memory die DIE2 (e.g., Figure 1The total current of the storage device 10 may be higher than a predetermined threshold TH, which may degrade the storage device 10. Here, the predetermined threshold TH may correspond to the power budget allocated to the storage device 10.

[0061] Reference Figure 4B First memory die DIE1 and second memory die DIE2 can simultaneously receive commands. Hereinafter, a command received via first memory die DIE1 is referred to as a first command, and a command received via second memory die DIE2 is referred to as a second command. In some embodiments, first memory die DIE1 may have a higher priority than second memory die DIE2. The first memory die DIE1 with higher priority can, in its slave memory controller (… Figure 1 The memory controller 20) executes the first command immediately upon receiving it. Furthermore, the first memory die DIE1 can generate peak information Peak_Inf associated with the first command and send the Peak_Inf associated with the first command to the second memory die DIE2.

[0062] The second memory die DIE2 can receive peak information Peak_Inf associated with the first command from the first memory die DIE1, and can delay the execution of the second command based on the peak information Peak_Inf. For example, the second memory die DIE2 can queue the second command in a command queue. In some embodiments, the peak information Peak_Inf may have a first level 410 during the peak current segment PP11 associated with the first command, and may have a second level 420 at the end of the peak current segment PP11. Specifically, when the peak current segment PP11 of the first memory die DIE1 overlaps with the peak current segment PP12 of the second memory die DIE2, the second memory die DIE2 can delay the execution of the second command by queuing the second command in a command queue during the queuing segment OP. Thereafter, the second memory die DIE2 can determine whether the peak current segment PP11 of the first memory die DIE1 has ended based on the peak information Peak_Inf, and execute the second command in response to determining that the peak current segment PP11 of the first memory die DIE1 has ended. Therefore, the total current of storage device 10 can be kept lower than a predetermined threshold TH, and the power consumed by storage device 10 can be managed to be below the power budget.

[0063] In some embodiments, the memory controller 20 can detect abnormal operation of the current management circuitry within the first memory die DIE1 and the second memory die DIE2 from the ready / busy signals RNB1 and RNB2. The memory controller 20 can compare the time when the ready / busy signals RNB1 and RNB2 transition from a busy state (e.g., logic low) to a ready state (e.g., logic high) with the predicted operation completion time for each memory die. The memory controller 20 can detect abnormal operation of the current management circuitry based on the comparison result. In some embodiments, the timing of the transition from a busy state (logic low) to a ready state (logic high) of the ready / busy signals RNB1 and RNB2 can be significantly earlier or later than the expected completion time of the operation. For example, even if the first memory die DIE1 has peak information Peak_Inf, the second memory die DIE2 may execute the second command immediately upon receiving it, or the second memory die DIE2 may not execute the operation according to the second command even if the peak current segment according to the peak information Peak_Inf of the first memory die DIE1 has ended. If the time when the ready / busy signals RNB1 and RNB2 change from the busy state (logic low level) to the ready state (logic high level) is too early or too late compared to the expected operation completion time, the memory controller 20 according to some embodiments may enter a test mode for testing the performance of the current management circuitry.

[0064] However, the embodiments are not limited thereto, and the storage controller 20 may enter a test mode for the current management circuit at predetermined intervals.

[0065] Figure 5 yes Figure 1 Block diagram of the storage controller.

[0066] In some embodiments, the storage controller 500 may include a processor 510, a peak manager 520, a queue manager 530, a host interface 540, a buffer memory 550, a memory interface 560, and a bus 570.

[0067] Bus 570 provides a channel between components of storage controller 500.

[0068] Host interface 540 is configured to communicate with an external device (e.g., a host device) under the control of processor 510. Host interface 540 may be configured to communicate using at least one of various communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Fast (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), Load Reduction DIMM (LRDIMM), etc.

[0069] Buffer memory 550 can store commands and data executed and processed by storage controller 500. Buffer memory 550 can temporarily store data already stored in a non-volatile memory device or data to be stored. In some embodiments, buffer memory 550 can store reference values ​​for operating parameters of multiple non-volatile memory devices. Here, the reference value can be an initial setting value of the operating parameter or a first measured value of the operating parameter. For example, the reference value can be a setting value of the operating parameter corresponding to the non-volatile memory device and a peak current value corresponding to the setting value of the operating parameter. In addition, the operating parameters may include, but are not limited to, programming time tPROG, read time, etc.

[0070] The memory interface 560 is configured to communicate with multiple non-volatile memory devices under the control of the processor 510. The memory interface 560 may be implemented in accordance with standard protocols such as Toggle or Open NAND Flash Interface (ONFI).

[0071] The processor 510 can control the overall operation of the memory controller 500 and perform logical operations. In some embodiments, the processor 510 may be based on a non-volatile memory device ( Figure 1 The ready / busy signal of the non-volatile memory device 30) determines whether to enter the test mode to test the current management circuit (e.g., Figure 1The performance of the current management circuits 31_1 and 33_1 is assessed. In some embodiments, the processor 510 may generate a dummy command for testing the current management circuits and send the dummy command to the non-volatile memory device 30. For example, the dummy command may be a programming command for testing the current management circuits 31_1 and 33_1, and may cause the voltage of some logic within the non-volatile memory device 30 to be cut off. Although the description herein assumes that the dummy command is a programming command, the embodiments are not limited thereto, and the dummy command may be a read command or an erase command. The voltage of some logic within the non-volatile memory device 30 may be cut off by the dummy command. Reference will be made later. Figures 6 to 8 A description of the structure of the non-volatile memory device 30 and the operation method of the non-volatile memory device 30 using dummy commands.

[0072] Figure 6 yes Figure 1 Block diagram of a non-volatile memory device.

[0073] like Figure 6 As shown, the non-volatile memory device 600 may include a memory cell array 610, a voltage generator 620, an address decoder 630, a page buffer 640, and control logic 650.

[0074] The memory cell array 610 may include multiple memory blocks BLK1, BLK2, ..., BLKn. Each of the multiple memory blocks BLK1, BLK2, ..., BLKn is connected to the address decoder 630 via the word line WL, the serial select line SSL, and the ground select line GSL, and is connected to the page buffer 640 via the bit line BL.

[0075] The memory cell array 610 may include multiple memory cells disposed in a region intersecting multiple word lines WL and multiple bit lines BL. Each memory cell may be used as a cell type (e.g., single-level cell SLC, multi-level cell MLC, three-level cell TLC, four-level cell QLC, etc.).

[0076] The memory cell array 610 may include non-volatile memory cells. For example, the memory cell array 610 may include a two-dimensional 2D NAND memory array or a three-dimensional 3D vertical NAND (V-NAND) memory array.

[0077] The voltage generator 620 can receive power PWR, adjust the voltage signal Vg for memory operation based on the voltage control signal VCTRL, and provide the voltage signal Vg to the memory cell array 610 through the address decoder 630.

[0078] The voltage generator 620 can generate various types of voltages for performing programming and erasing operations on the memory cell array 610 based on the voltage control signal VCTRL.

[0079] Address decoder 630 can be connected to memory cell array 610 via multiple word lines WL, multiple serial select lines SSL, and multiple ground select lines GSL. Address decoder 630 can decode row address R_ADDR to select at least one of multiple memory blocks BLK1, BLK2, ..., BLKn. That is, address decoder 630 can use row address R_ADDR to select word line WL, serial select line SSL, and ground select line GSL. Address decoder 630 can provide voltage signal Vg supplied from voltage generator 620 to word line WL.

[0080] Page buffer 640 may include page buffers 640_1, 640_2, ..., 640_s from page buffer 640_1 to page buffer 640_s from page buffer 640_1 to page buffer 640_s from page buffer 640_s to page buffer 640_s from page buffer 640_s to page buffer 640_s from page buffer 640_s to page buffer 640_s, each of which can be connected to multiple memory cells via multiple bit lines BL (where s is an integer greater than or equal to 3). Page buffer 640 can select at least one bit line from the multiple bit lines BL based on the column address C_ADDR.

[0081] Control logic 650 can provide each control signal related to memory operation to voltage generator 620, address decoder 630, and page buffer 640. Control logic 650 can control the overall operation of the non-volatile memory device 600. Control logic 650 can be based on data from the memory controller (…). Figure 1 The memory controller 20) receives at least one of the address ADDR, command CMD, and control signal CTRL, and uses the internal control signal to control the non-volatile memory device 600.

[0082] In some embodiments, control logic 650 may include current management circuitry 651. Current management circuitry 651 may output peak information Peak_Inf from non-volatile memory device 600 regarding command CMD received from memory controller 20. Current management circuitry 651 may also output peak information (Peak_Inf) from memory device 600. Figure 1 The storage device 10) receives peak information Peak_Inf from another non-volatile memory device. The current management circuit 651 can determine the execution timing of the command (CMD) based on the peak information Peak_Inf received from the other non-volatile memory device.

[0083] In some embodiments, control logic 650 may receive a dummy command DCMD and pseudo peak information (Pseudo Peak_Inf) from storage controller 20 for testing current management circuitry 651. Current management circuitry 651 may determine the execution timing of dummy command DCMD based on dummy command DCMD and pseudo peak information (Pseudo Peak_Inf).

[0084] In some embodiments, control logic 650 may output a select signal SEL based on a dummy command DCMD to control address decoder 630. Address decoder 630 may not select any block within memory cell array 610 based on a logic high level for the select signal SEL. Non-volatile memory device 600 may block the voltage applied to word line WL of memory blocks based on the dummy command DCMD. For example, non-volatile memory device 600 may isolate word line WL based on the dummy command DCMD. See reference. Figure 7 and Figure 8 Provide a detailed explanation of this.

[0085] Figure 7 It is used for explanation Figure 6 A circuit diagram of a memory block within a memory cell array. Included in... Figure 6 Each of the multiple memory blocks BLK1, BLK2, ..., BLKn in the memory cell array 610 can have the same as... Figure 7 The memory block BLKa has the same or similar structure.

[0086] Reference Figure 7 The memory block BLKa may include multiple memory NAND strings NS11, NS12, ..., NS33 connected between "multiple bit lines BL1, BL2, BL3 extending in the first direction D1 and the common source line CSL".

[0087] Each of the plurality of memory NAND strings NS11, NS12, ..., NS33 may include a string select transistor SST, a plurality of memory cells MC1, MC2, ..., MC8, and a ground select transistor GST. The gate of the string select transistor SST may be connected to the corresponding string select lines SSL1, SSL2, SSL3. The plurality of memory cells MC1, MC2, ..., MC8 may each be connected to the corresponding word lines WL1, WL2, ..., WL8. The word lines WL1, WL2, ..., WL8 may be gate lines. The gate of the ground select transistor GST may be connected to the corresponding ground select lines GSL1, GSL2, GSL3. The string select transistor SST may be connected to the corresponding bit lines BL1, BL2, BL3, and the ground select transistor GST may be connected to the common source line CSL. In one embodiment, the string select transistor SST, the plurality of memory cells MC1, MC2, ..., MC8, and the ground select transistor GST are stacked on a third direction D3, and the ground select lines GSL1, GSL2, GSL3 extend on a second direction D2.

[0088] Memory cells at the same height among the multiple memory cells MC1, MC2, ..., MC8 of each of the multiple memory NAND strings NS11, NS12, ..., NS33 can share the same word line WL. For example, the first memory cell MC1 of each of the multiple memory NAND strings NS11, NS12, ..., NS33 can share the first word line WL1. The second memory cell MC2 of each of the multiple memory NAND strings NS11, NS12, ..., NS33 can share the second word line WL2. Similarly, the third to eighth memory cells MC3 of each of the multiple memory NAND strings NS11, NS12, ..., NS33 can each share the third to eighth word lines WL3 to WL8.

[0089] Memory cells sharing the same word line can form a physical page (not shown). For example, a physical page may include memory cells arranged in the region where word line WL4 and multiple bit lines BL1, BL2, BL3 intersect. Having, for example... Figure 7 NAND flash memory devices with this structure can perform erase operations on a block-by-block basis and perform programming operations on a physical page basis corresponding to each word line WL1, WL2, ..., WL8.

[0090] Figure 7 The memory block BLKa shown is exemplary, and the number of memory NAND strings (NS), the number of cell transistors (GST, MC, SST, etc.), and the number of lines connected to the cell transistors (BL, WL, CSL, SSL, GSL, etc.) can be increased or decreased.

[0091] Figure 8 This is a diagram illustrating the operation of a non-volatile memory device according to some embodiments. Specifically, a method is described for a non-volatile memory device operating in a test mode for testing current management circuitry to receive a dummy command.

[0092] In some embodiments, the non-volatile memory device 800 may include a memory block BLKa, a voltage generator 810, a block decoder 820, and a transmission transistor circuit 830. The memory block BLKa may be connected to... Figure 7 The memory block BLKa corresponds to it, and the voltage generator 810 can be used with... Figure 6 The voltage generator 620 corresponds to this. The block decoder 820 and the transmission transistor circuit 830 may be included in... Figure 6 In the address decoder 630. The block decoder 820 can provide the block select signal BLKSEL to the transmission transistor circuit 830 via the block select line BLKWL.

[0093] A block select signal BLKSEL can be provided to the gate terminals of a plurality of transfer transistors PTS1, PTS2, PTS3, PT1 to PT8, PTg included in transfer transistor circuit 830. For example, when the block select signal BLKSEL is activated, the plurality of transfer transistors PTS1, PTS2, PTS3, PT1 to PT8, PTg in transfer transistor circuit 830 are turned on, and therefore, memory block BLKa can be selected. Although a block select line BLKWL is shown as being commonly connected to the plurality of transfer transistors PTS1, PTS2, PTS3, PT1 to PT8, PTg, the embodiments are not limited thereto. In some embodiments, at least two of the plurality of transfer transistors PTS1, PTS2, PTS3, PT1 to PT8, PTg may be individually connected to two or more block select lines. The non-volatile memory device 800 may include a plurality of memory blocks, and memory operations can be performed on the memory block selected based on the block select signal BLKSEL.

[0094] The voltage generator 810 can be connected to the transmission transistor circuit 830 via the serial select line drive signal lines SS1, SS2, SS3, word line drive signal lines SI1, SI2, ..., SI8, and ground select line drive signal line GS. Specifically, the serial select line drive signal lines SS1, SS2, SS3, word line drive signal lines SI1, SI2, ..., SI8, and ground select line drive signal line GS can be respectively connected to one end of a plurality of transmission transistors (PTS1, PTS2, PTS3, PT1 to PT8, PTg) in the transmission transistor circuit 830.

[0095] The transmission transistor circuit 830 can be connected to the memory block BLKa via the serial select lines SSL1, SSL2, SSL3, multiple word lines WL1, WL2, ..., WL8 and the ground select line GSL.

[0096] When the block select signal BLKSEL is activated, multiple transmission transistors (PTS1, PTS2, PTS3, PT1 to PT8, PTg) can provide the drive signals provided by the serial select line drive signal lines SS1, SS2, SS3, word line drive signal lines SI1, SI2, ..., SI8, and ground select line drive signal line GS to the serial select line SSL1, SSL2, SSL3, multiple word lines WL1, WL2, ..., WL8, and ground select line GSL, respectively.

[0097] In some embodiments, control logic ( Figure 6 The control logic 650 can output the selection signal SEL to the block decoder 820 within the address decoder 630 based on the dummy command DCMD received from the memory controller. For example, when the block decoder 820 receives the logic high-level selection signal SEL, the block decoder 820 can deactivate the block selection signal BLKSEL input to the transmission transistor circuit 830 via the block selection line BLKWL. Specifically, the block decoder 820 can block the voltages applied from the voltage generator 810 to the word lines WL1, WL2, ..., WL8 of the memory block BLKa by deactivating the block selection signal BLKSEL provided to the gate terminal of the transmission transistor circuit 830 via the block selection line BLKWL. This also applies to all memory blocks in the non-volatile memory device 800. Figure 6 The memory blocks BLK1, BLK2, ..., BLKn in the memory device 800 are shown. According to some embodiments, the non-volatile memory device 800 may deactivate the block select signal BLKSEL provided to the gate terminal of the transfer transistor circuit 830 to prevent the selection of all memory blocks within the non-volatile memory device 800. This prevents unnecessary programming / erase cycles from being performed on the memory block BLK1 in test mode. In one embodiment, the memory block BLK1 may include string select transistors SST1, SST2, and SST3.

[0098] Reference Figure 5 The storage controller 500 includes a peak manager 520, and the peak manager 520 may include a peak information generator 521 and a peak width detector 522. When the storage controller 500 outputs a dummy command DCMD in test mode, the peak information generator 521 can output dummy peak information to multiple non-volatile memory devices 31, 33 (see [link to test mode]). Figure 1 ), which enables current management circuits 31_1 and 33_1 (see Figure 1The timing of the execution of dummy commands is controlled. Pseudo-peak information may include a first level representing the peak current segment and a second level representing the non-peak current segment. The pseudo-peak information may remain at the first level during the peak current segment.

[0099] In some embodiments, the peak width detector 522 can receive elapsed time information from multiple non-volatile memory devices 31, 33 via a dummy command, and use the elapsed time information to determine or confirm a faulty current management circuit. (Refer to...) Figures 9 to 11 Provides a detailed description of the peak width detector 522 and elapsed time information.

[0100] Figures 9 to 11 This is a timing diagram illustrating the operation method of a non-volatile memory device according to some embodiments.

[0101] Specifically, Figures 9 to 11 This diagram illustrates how a non-volatile memory device, receiving a dummy command DCMD and pseudo-peak information (PseudoPeak_Inf) in test mode, generates the elapsed time information Telapse. In each figure, the non-volatile memory device can be compared with… Figures 1 to 8 One of the corresponding non-volatile memory devices described herein, and for ease of explanation, assuming according to Figure 9 The non-volatile memory device includes normal current management circuitry, and according to Figure 10 and Figure 11 The non-volatile memory device includes fault current management circuitry. The clock signal CLK can be a clock signal received from an external source or an internal clock signal of the non-volatile memory device. In some embodiments, the non-volatile memory device can receive a dummy command DCMD and pseudo peak information (Pseudo Peak_Inf) in test mode. In test mode, the non-volatile memory device may not generate or share peak information for the dummy command DCMD. In test mode, the non-volatile memory device can queue the dummy command DCMD in a command queue based on the pseudo peak information and execute the dummy command DCMD when the peak current segment according to the pseudo peak information ends.

[0102] Reference Figure 9 The first non-volatile memory device NVM1 may receive a first dummy command DCMD1 for programming operations from the memory controller at time t10. The first non-volatile memory device NVM1 may receive pseudo peak information (Pseudo Peak_Inf) from the memory controller at time t11.

[0103] Pseudo-peak information (Pseudo Peak_Inf) can be indicated by a signal. A logic high level of the signal indicates the peak current segment. Figure 9 The pseudo-peak information (Pseudo Peak_Inf) shown indicates the peak current segment from time t11 to time t12. The first non-volatile memory device NVM1 can queue the first dummy command DCMD1 in the command queue during the peak current segment (from time t11 to time t12) according to the pseudo-peak information (Pseudo Peak_Inf). The first non-volatile memory device NVM1 can determine whether the peak current segment has ended (i.e., when the pseudo-peak information (Pseudo Peak_Inf) goes low), and if the peak current segment according to the pseudo-peak information (Pseudo Peak_Inf) has ended at time t12, the first non-volatile memory device NVM1 can perform an operation according to the first dummy command DCMD1.

[0104] In some embodiments, the first non-volatile memory device NVM1 may output a first ready / busy signal RNB1 indicating a busy state while performing internal operations according to the first dummy command DCMD1. In some embodiments, the actual internal operation time (from time t12 to time t13) according to the first dummy command DCMD1 may be equal to, but not limited to, a predetermined programming time tPROG for the first non-volatile memory device NVM1. According to some embodiments, because the block select signal BLKSEL is invalid while the internal operation is performed according to the first dummy command DCMD1, only the non-volatile memory device ( Figure 6 Some logic operations are possible within the non-volatile memory device 600.

[0105] In some embodiments, the first non-volatile memory device NVM1 may further include a counter. Specifically, the counter counts the periods of the clock signal CLK from the time the first non-volatile memory device NVM1 receives pseudo-peak information (PseudoPeak_Inf) of a logic high level to the time when the actual internal operation according to the first dummy command DCMD1 is completed. (Refer to...) Figure 9 The counter can count the period of the clock signal CLK from the time t11 when it receives the pseudo peak information (Pseudo Peak_Inf) of the logic high level from the first non-volatile memory device NVM1 to the time t13 when the first ready / busy signal RNB1 changes from the busy state to the ready state, and can output the count information "5" as the first elapsed time information Telapse1.

[0106] In some embodiments, the peak width detector ( Figure 5The peak width detector 522 can obtain the internal operating time of the first non-volatile memory device NVM1 from the first elapsed time information Telapse1. Specifically, the peak width detector 522 can determine the remaining time of the peak current segment after excluding the pseudo peak information (Pseudo Peak_Inf) from the first elapsed time information Telapse1 as the internal operating time tAP1 of the first non-volatile memory device NVM1.

[0107] In some embodiments, the peak width detector 522 may compare a reference value of the internal operating time with the internal operating time tAP1 of the first non-volatile memory device NVM1 obtained from the first elapsed time information Telapse1. The reference value of the internal operating time may be an initial set value predetermined according to the specifications of the non-volatile memory device, or it may be stored as a first measured value in the memory controller. Figure 5 The value in the buffer memory 550 within the storage controller 500. The peak width detector 522 can determine that the difference between the reference value of the internal operating time and the internal operating time tAP1 obtained from the first elapsed time information Telapse1 is within a predetermined range, and the current management circuit in the first non-volatile memory device NVM1 can be determined to be operating normally.

[0108] Reference Figure 10 The second non-volatile memory device NVM2 may receive a second dummy command DCMD2 for programming operations at time t20, and perform internal operations according to the second dummy command DCMD2 during the peak current segment (from time t21 to time t22) based on pseudo peak information (Pseudo Peak_Inf). Specifically, even if the second dummy command DCMD2 should be queued in the command queue during the peak current segment (from time t21 to time t22) based on pseudo peak information (Pseudo Peak_Inf), the second non-volatile memory device NVM2 may also output a second ready / busy signal RNB2 indicating a busy state from time t21 to time t23 by performing internal operations according to the second dummy command DCMD2. In some embodiments, the time for performing actual internal operations according to the second dummy command DCMD2 (from time t21 to time t23) may be equal to, but not limited to, a predetermined programming time tPROG for the second non-volatile memory device NVM2.

[0109] In some embodiments, a counter within the second non-volatile memory device NVM2 may count the periods of the clock signal CLK from the time the second non-volatile memory device NVM2 receives pseudo-peak information (Pseudo Peak_Inf) of a logic high level until the second non-volatile memory device NVM2 completes its actual internal operation according to the second dummy command DCMD2. (Refer to...) Figure 10 The counter can count the period of the clock signal CLK from the time t21 when it receives the pseudo peak information (Pseudo Peak_Inf) of the logic high level from the second non-volatile memory device NVM2 to the time t23 when the second ready / busy signal RNB2 changes from the busy state to the ready state, and can output the count information "3" as the second elapsed time information Telapse2.

[0110] In some embodiments, the peak width detector 522 may determine the remaining time of the peak current segment after excluding pseudo peak information (Pseudo Peak_Inf) from the second elapsed time information Telapse2 as the internal operating time tAP2 of the second non-volatile memory device NVM2. In some embodiments, the peak width detector 522 may compare a reference value of the internal operating time with the internal operating time tAP2 of the second non-volatile memory device NVM2 obtained from the second elapsed time information Telapse2, and determine that the difference between the reference value of the internal operating time and the internal operating time tAP2 is greater than a predetermined range. Therefore, the peak width detector 522 may determine that the second non-volatile memory device NVM2 includes a faulty current management circuit, and may shut off (or disable) the power to the faulty current management circuit within the second non-volatile memory device NVM2.

[0111] Reference Figure 11Even though the peak current interval (from time t31 to time t32) according to the pseudo peak information (Pseudo Peak_Inf) has ended, the third non-volatile memory device NVM3 does not perform the internal operation according to the third dummy command DCMD3. In one embodiment, the third non-volatile memory device NVM3 may receive the third dummy command DCMD3, which commands the programming operation, at time t30. Specifically, at time t32, although the pseudo peak information (Pseudo Peak_Inf) transitions from a logic high level to a logic low level, the internal operation according to the third dummy command DCMD3 is not executed. The third non-volatile memory device NVM3 performs the internal operation according to the third dummy command DCMD3 at time t33. In some embodiments, the time for performing the actual internal operation according to the third dummy command DCMD3 (from time t33 to time t34) may be equal to, but not limited to, a predetermined programming time tPROG.

[0112] In some embodiments, a counter within the third non-volatile memory device NVM3 may count the cycles of the clock signal CLK from the time the third non-volatile memory device NVM3 receives pseudo-peak information (Pseudo Peak_Inf) of a logic high level until the time the third non-volatile memory device NVM3 completes its actual internal operation according to the third dummy command DCMD3. (Refer to...) Figure 11 The counter can count the period of the clock signal CLK from the time t31 when it receives the pseudo peak information (Pseudo Peak_Inf) of the logic high level from the third non-volatile memory device NVM3 to the time t34 when the third ready / busy signal RNB3 changes from the busy state to the ready state, and can output the count information "6" as the third elapsed time information Telapse3.

[0113] In some embodiments, the peak width detector 522 may determine the remaining time of the peak current segment after excluding pseudo peak information (Pseudo Peak_Inf) from the third elapsed time information Telapse3 as the internal operating time tAP3 of the third non-volatile memory device NVM3. In some embodiments, the peak width detector 522 may compare a reference value of the internal operating time with the internal operating time tAP3 of the third non-volatile memory device NVM3 obtained from the third elapsed time information Telapse3, and determine that the difference between the reference value of the internal operating time and the internal operating time tAP3 is greater than a predetermined range. Therefore, the peak width detector 522 determines that the third non-volatile memory device NVM3 includes a faulty current management circuit, and may shut off (or disable) the power to the faulty current management circuit within the third non-volatile memory device NVM3.

[0114] This assumes that the dummy command DCMD is a programming command PRGM, and that the actual internal operation time of the non-volatile memory device based on the dummy command DCMD is the programming time tPROG; however, the embodiments are not limited to this. For example, the dummy command DCMD can be a read command, and the actual internal operation time of the non-volatile memory device based on the dummy command DCMD can be the read time.

[0115] Reference Figure 5 In some embodiments, the storage controller 500 may include a queue manager 530. The queue manager 530 may determine a command to be sent to a non-volatile memory device that includes faulty current management circuitry, or determine the time to send a command to a non-volatile memory device that includes faulty current management circuitry. Optionally, the queue manager 530 may change the settings of operating parameters for the non-volatile memory device that includes faulty current management circuitry. See also... Figures 12 to 15 Provides a detailed description of the queue manager 530.

[0116] Figure 12 This is a block diagram of a queue manager according to some embodiments. Figure 13 This is a timing diagram illustrating the operation method of a queue manager according to some embodiments, and Figure 14 This is a diagram showing the peak current value based on parameter settings of a non-volatile memory device according to some embodiments.

[0117] In some embodiments, the queue manager 530 may include queue control logic 531 and parameter control logic 532.

[0118] In some embodiments, queue control logic 531 may determine commands to be sent to a non-volatile memory device including a faulty current management circuit. Queue control logic 531 may assign commands with relatively low peak current (e.g., peak current below a preset threshold) to the non-volatile memory device including the faulty current management circuit based on peak information. Specifically, queue control logic 531 may assign commands with relatively low peak current to the non-volatile memory device including the faulty current management circuit based on peak information of the non-volatile memory device, such that the peak current of memory device 10 does not exceed a maximum current value due to the operation of multiple non-volatile memory devices. Here, a command with relatively low peak current (e.g., peak current below a preset threshold) may refer to (but is not limited to) a read command.

[0119] In some embodiments, queue control logic 531 can determine when to send a command to a non-volatile memory device that includes faulty current management circuitry. (See also...) Figure 13Assume that the third non-volatile memory device NVM3 includes fault current management circuitry.

[0120] In some embodiments, the first non-volatile memory device NVM1 and the second non-volatile memory device NVM2 may receive a first command CMD1 and a second command CMD2 at time t50, respectively. The first non-volatile memory device NVM1 and the second non-volatile memory device NVM2 may determine the operation time of the first command CMD1 and the second command CMD2 based on their respective peak information. For example, the first non-volatile memory device NVM1 may output first peak information Peak_Inf1 regarding the first command CMD1 and execute the first command CMD1 at time t51. The second non-volatile memory device NVM2 may queue the second command CMD2 in the command queue based on the first peak information Peak_Inf1. The second non-volatile memory device NVM2 may output the second peak information Peak_Inf2 at time t52, at the end of the peak current segment of the first non-volatile memory device NVM1, and execute the second command CMD2.

[0121] In some embodiments, queue control logic 531 may receive first peak information Peak_Inf1 from a first non-volatile memory device NVM1, receive second peak information Peak_Inf2 from a second non-volatile memory device NVM2, and determine the timing of sending a third command CMD3. For example, queue control logic 531 may, based on the first peak information Peak_Inf1 and the second peak information Peak_Inf2, control the sum of the peak currents of multiple non-volatile memory devices NVM1, NVM2, and NVM3 to not exceed a maximum current value by sending the third command CMD3 at time t53 when the peak current segment of the second non-volatile memory device NVM2 ends. Therefore, the total current of the multiple non-volatile memory devices NVM1, NVM2, and NVM3 may be lower than the maximum current, and the power consumed by the multiple non-volatile memory devices NVM1, NVM2, and NVM3 may be managed within a power budget.

[0122] Reference Figure 12 In some embodiments, the queue manager 530 may include parameter control logic 532. The parameter control logic 532 can change the set values ​​of operating parameters of the non-volatile memory device, including faulty current management circuitry. Here, operating parameters may include, but are not limited to, programming time tPROG, read time tR, etc. Specifically, refer to... Figure 14As the programming time tPROG of a non-volatile memory device is increased, the peak current of the non-volatile memory device can be reduced. For example, if the programming time tPROG of a non-volatile memory device including faulty current management circuitry is set to 300 ns, the peak current of the non-volatile memory device including faulty current management circuitry can be reduced by changing the programming time tPROG of the non-volatile memory device including faulty current management circuitry to 400 ns. However, this is only an example, and the actual programming time and peak current can vary.

[0123] In some embodiments, parameter control logic 532 can change the settings of the operating parameters of a non-volatile memory device including faulty current management circuitry based on a predetermined peak current value according to the settings of the operating parameters. This also allows for efficient power budget management of the memory device without controlling the timing of command transmission to the non-volatile memory device including faulty current management circuitry.

[0124] In some embodiments, the queue manager 530 can manage the power consumption of the storage device within a power budget by simultaneously or selectively operating the queue control logic 531 and the parameter control logic 532.

[0125] Figure 15 This is a flowchart illustrating a method of operating a storage device according to some embodiments.

[0126] In some embodiments, during operation S1510, the memory controller may send a command to the memory device and receive a ready / busy signal RNB corresponding to the command from the memory device. The memory controller may detect abnormal operation of the current management circuitry in the memory device based on the ready / busy signal RNB.

[0127] In some embodiments, during operation S1520, the memory controller may compare the predicted completion time of an operation of the memory device with the time (tBUSY) when the ready / busy signal RNB transitions from a busy state to a ready state. For example, the memory controller may predict when the operation of the memory device will complete based on the command passed to the memory device, and may compare the predicted completion time of the operation of the memory device with the time when the ready / busy signal RNB transitions from a busy state to a ready state.

[0128] The memory controller can detect abnormal operation of the current management circuitry by comparing the timing of the transition from a busy to a ready state in the ready / busy signal RNB with the timing of the expected completion of the memory device's operation. Specifically, if the time for the ready / busy signal RNB to transition from a busy state to a ready state is significantly greater than or less than the expected value, the memory controller can enter a test mode for testing the current management circuitry. For example, if the time for the ready / busy signal RNB to transition from a busy state to a ready state differs from the expected value by more than a threshold, the memory controller can enter a test mode for testing the current management circuitry. However, the embodiments are not limited to this; the memory controller can enter a test mode for testing the current management circuitry during a predetermined time period.

[0129] In some embodiments, the memory controller may generate a dummy command DCMD to test the current management circuit and send the dummy command DCMD to the memory device. In operation S1530, the memory controller may send pseudo peak information (Pseudo Peak_Inf) to the memory device simultaneously with or after the dummy command DCMD. The memory controller may send the pseudo peak information (Pseudo Peak_Inf) to the memory device to control the timing of the execution of the dummy command DCMD.

[0130] In some embodiments, during operation S1540, the memory device may send elapsed time information Telapse to the memory controller in response to the dummy command DCMD and pseudo peak information (Pseudo Peak_Inf). The elapsed time information Telapse may include information for the memory device to determine the actual internal operating time based on the peak current segment within the pseudo peak information (Pseudo Peak_Inf) and the dummy command DCMD.

[0131] In some embodiments, the memory controller may obtain the internal operating time of the memory device from the elapsed time information (Telapse). The memory device may determine the remaining time of the peak current segment excluding the pseudo peak information (Pseudo Peak_Inf) from the elapsed time information (Telapse) as the internal operating time of the memory device.

[0132] In some embodiments, during operation S1550, the memory controller may compare the internal operating time of the memory device with a set value of the operating parameters of the memory device and identify a faulty current management circuit. For example, if the difference between the internal operating time of the memory device and the set value of the operating parameters of the memory device exceeds a threshold, the memory device may be determined to include a faulty current management circuit.

[0133] In some embodiments, the memory controller may perform a queue management operation (S1560) on a memory device including a faulty current management circuit. Specifically, the memory controller may assign low peak current commands to the memory device including the faulty current management circuit. Optionally, the memory controller may determine when to assign commands to the memory device including the faulty current management circuit based on peak information of the memory device. Optionally, the memory controller may change the operating parameter settings of the memory device including the faulty current management circuit.

[0134] Figure 16 This is a block diagram illustrating an SSD system of an application storage device according to some embodiments.

[0135] Reference Figure 16 The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 exchanges signals SIG with the host 1100 through a signal connector 1201 and receives power PWR through a power connector 1202. The SSD 1200 may include an SSD controller 1210, multiple flash memory modules 1221, 1222, ..., 122m, an auxiliary power supply 1230, and a cache memory 1240.

[0136] Multiple flash memory modules 1221, 1222, ..., 122m can be connected to the SSD controller 1210 via multiple channels. The SSD controller 1210 can control the multiple flash memory modules 1221, 1222, ..., 122m in response to the SIG signal received from the host 1100. The SSD controller 1210 can store internally generated or externally transmitted signals (e.g., the SIG signal transmitted from the host 1100) in the buffer memory 1240.

[0137] Multiple flash memory modules 1221, 1222, ..., 122m can operate under the control of SSD controller 1210. These modules can be interconnected via shared input / output lines (I / O), and can be configured as described above. Figures 1 to 15 Describes multiple non-volatile memory devices. Shared input / output lines (I / O) can be used with... Figure 2 The shared input / output lines (IOs) correspond to and are applied in the system. Figure 2 Description of shared input / output lines (IOs) in the memory. Current management circuits within multiple flash memory modules 1221, 1222, ..., 122m can output and share peak information containing information about peak current ranges via shared input / output lines (IOs).

[0138] In some embodiments, the SSD controller 1210 can test current management circuits within a plurality of flash memory modules 1221, 1222, ..., 122m. The SSD controller 1210 can send dummy commands and spurious peak information for testing the current management circuits within the plurality of flash memory modules 1221, 1222, ..., 122m, and can receive elapsed time information for the plurality of flash memory modules 1221, 1222, ..., 122m based on the dummy commands and spurious peak information received from the current management circuits within the plurality of flash memory modules 1221, 1222, ..., 122m. The SSD controller 1210 can determine, from the elapsed time information, the faulty current management circuit among the current management circuits in the plurality of flash memory modules 1221, 1222, ..., 122m.

[0139] In some embodiments, the SSD controller 1210 may perform queue management operations on flash memory that includes a faulty current management circuit among a plurality of flash memory ...

[0140] Auxiliary power supply 1230 can be connected to host 1100 via power connector 1202. Auxiliary power supply 1230 can receive power PWR from host 1100 and charge it. When the power supply from host 1100 is not smooth, auxiliary power supply 1230 can provide power to SSD 1200.

[0141] Figure 17 This is a block diagram illustrating a UFS system according to some embodiments.

[0142] The UFS System 2000 is a system conforming to the UFS standard announced by the Joint Electronic Devices Engineering Committee (JEDEC) and may include a UFS host 2100, a UFS device 2200, and a UFS interface 2300. In conjunction with... Figure 17 To the extent that the following descriptions do not conflict, the above descriptions Figures 1 to 15 The description of storage device 10 can also be applied to Figure 17 UFS system 2000.

[0143] Reference Figure 17The UFS host 2100 may include a UFS host controller 2110, an application 2120, a UFS driver 2130, host memory 2140, and a UFS interconnect (UIC) layer 2150. The UFS device 2200 may include a UFS device controller 2210, non-volatile memory 2220, a storage interface 2230, device memory 2240, a UIC layer 2250, and a regulator 2260. The non-volatile memory 2220 may consist of multiple memory cells 2221_0 to 2221_N-1, and these memory cells may include V-NAND flash memory with a 2D or 3D structure, but may also include other types of non-volatile memory (such as phase-change memory (PRAM) and / or resistive random access memory (RRAM)). The UFS device controller 2210 and the non-volatile memory 2220 may be interconnected via the storage interface 2230. The storage interface 2230 can be implemented to conform to standard protocols (such as Toggle or ONFI).

[0144] Multiple memory cells 2221_0 to 2221_N-1 can be implemented as described above. Figures 1 to 15 The description includes multiple non-volatile memory devices, and multiple memory cells 2221_0 to 2221_N-1 are interconnected via shared input / output lines (IO). The shared input / output lines (IO) are... Figure 2 The shared input / output lines correspond to I / O, and Figure 2 Descriptions of shared input / output lines (IOs) can be applied.

[0145] Each of the plurality of memory cells 2221_0 to 2221_N-1 may include a memory cell array and control circuitry for controlling the operation of the memory cell array and for using operation delays (queuing) of the memory cell array to avoid overlap of peak current periods. The memory cell arrays may include two-dimensional or three-dimensional memory cell arrays. A three-dimensional memory cell array may include vertically oriented vertical NAND strings such that at least one memory cell is positioned above another memory cell.

[0146] Multiple memory cells 2221_0 to 2221_N-1 can share peak information by sharing input / output lines (IO). The UFS device 2200 can avoid overlapping peak power intervals without deploying complex dedicated circuitry in the UFS device controller 2210 via shared input / output lines (IO).

[0147] In some embodiments, the UFS device controller 2210 can test current management circuitry within a plurality of memory cells 2221_0 to 2221_N-1. The UFS device controller 2210 can send dummy commands and pseudo-peak information for testing the current management circuitry within the plurality of memory cells 2221_0 to 2221_N-1, and can receive elapsed time information of the plurality of memory cells 2221_0 to 2221_N-1 based on the dummy commands and pseudo-peak information from the current management circuitry within the plurality of memory cells 2221_0 to 2221_N-1.

[0148] UFS device controller 2210 can determine the faulty current management circuit among the current management circuits in multiple memory cells 2221_0 to 2221_N-1 from the elapsed time information.

[0149] In some embodiments, the UFS device controller 2210 may perform queue management operations for memory cells including faulty current management circuits among a plurality of memory cells 2221_0 to 2221_N-1. For example, the UFS device controller 2210 may assign commands with low peak current to memory cells including faulty current management circuits, determine the command allocation timing for memory cells including faulty current management circuits based on peak information of the plurality of memory cells 2221_0 to 2221_N-1, or change the operating parameter settings of memory cells including faulty current management circuits.

[0150] Application 2120 may refer to a program that wishes to communicate with UFS device 2200 to utilize the functionality of UFS device 2200. Application 2120 may send input / output requests to UFS drive 2130 for input / output to UFS device 2200. Input / output requests may mean, but are not limited to, requests to read data, requests to write data, and / or requests to discard data.

[0151] UFS driver 2130 can manage UFS host controller 2110 via UFS-HCI (Host Controller Interface). UFS driver 2130 can convert input / output requests generated by application 2120 into UFS commands defined by the UFS standard and send the converted UFS commands to UFS host controller 2110.

[0152] UFS commands can be commands primarily defined by the SCSI standard, but they can also be UFS standard-specific commands.

[0153] The UFS host controller 2110 can send UFS commands translated by the UFS driver 2130 to the UIC layer 2250 of the UFS device 2200 via the UIC layer 2150 and the UFS interface 2300. In this process, the UFS host register 2111 of the UFS host controller 2110 can be used as a command queue.

[0154] The UIC layer 2150 on the UFS host 2100 side may include MIPI M-PHY 2151 and MIPI UniPro 2152, and the UIC layer 2250 on the UFS device 2200 side may also include MIPI M-PHY 2251 and MIPI UniPro 2252.

[0155] The UFS interface 2300 may include a line for transmitting a reference clock (REF_CLK), a line for transmitting a hardware reset signal (RESET_n) for the UFS device 2200, a pair of lines for transmitting differential input signal pairs (DIN_T and DIN_C), and a pair of lines for transmitting differential output signal pairs (DOUT_T and DOUT_C).

[0156] The frequency value of the reference clock provided from the UFS host 2100 to the UFS device 2200 can be one of four values: 19.2MHz, 26MHz, 38.4MHz, and 52MHz, but the embodiment is not limited to these. The UFS host 2100 can even change the frequency value of the reference clock simultaneously during operation (i.e., while data transmission and reception are being performed between the UFS host 2100 and the UFS device 2200). The UFS device 2200 can generate clocks of various frequencies based on the reference clock provided from the UFS host 2100 using a phase-locked loop (PLL) or the like. Furthermore, the UFS host 2100 can also set the data rate value between the UFS host 2100 and the UFS device 2200 using the frequency value of the reference clock. In other words, the data rate value can be determined based on the frequency value of the reference clock.

[0157] The UFS interface 2300 can support multiple paths, and each path can be implemented as a differential pair. For example, the UFS interface may include one or more receive paths and one or more transmit paths. Figure 17 In this system, a pair of lines transmitting differential input signal pairs (DIN_T and DIN_C) can form a receiving path, and a pair of lines transmitting differential output signal pairs (DOUT_T and DOUT_C) can form a transmitting path. Although Figure 17 It shows one transmit path and one receive path, but the number of transmit and receive paths can be changed.

[0158] The receiving and transmitting paths can transmit data in a serial communication manner, and due to the separate structure of the receiving and transmitting paths, full-duplex communication between the UFS host 2100 and the UFS device 2200 is feasible.

[0159] Furthermore, control data (such as commands from UFS host 2100 to UFS device 2200) and user data that UFS host 2100 wants to store in or read from the non-volatile memory 2220 of UFS device 2200 can be transmitted through the same path. Therefore, in addition to a pair of receive paths and a pair of transmit paths, no separate path is required for data transmission between UFS host 2100 and UFS device 2200.

[0160] The UFS device controller 2210 of the UFS device 2200 can control the overall operation of the UFS device 2200. The UFS device controller 2210 can manage the non-volatile memory 2220 through logic units (LUs) (e.g., logic units #0 to logic units #N-1) 2211, which are logic data storage units.

[0161] The UFS device controller 2210 may include a flash translation layer (FTL) and can use the address mapping information of the FTL to translate logical data addresses (such as logical block addresses (LBAs)) sent from the UFS host 2100 into physical data addresses (such as physical block addresses (PBAs)). In the UFS system 2000, logical blocks used to store user data may have a size within a predetermined range. For example, the minimum size of a logical block may be set to 4 kilobytes.

[0162] When a command from the UFS host 2100 is input to the UFS device 2200 through the UIC layer 2250, the UFS device controller 2210 can perform an operation according to the input command, and when the operation is completed, send a completion response to the UFS host 2100.

[0163] In one example, if UFS host 2100 wants to store user data on UFS device 2200, UFS host 2100 can send a data storage instruction to UFS device 2200. When it receives a response from UFS device 2200 indicating that the user data is ready to be transmitted (ready to transmit), UFS host 2100 can transmit the user data to UFS device 2200. UFS device controller 2210 can temporarily store the received user data in device memory 2240, and store the user data temporarily stored in device memory 2240 in a selected location of non-volatile memory 2220 based on FTL address mapping information.

[0164] As another example, when UFS host 2100 wants to read user data stored in UFS device 2200, UFS host 2100 can send a data read command to UFS device 2200. The UFS device controller 2210, receiving the command, can read the user data from non-volatile memory 2220 based on the data read command and temporarily store the read user data in device memory 2240. During this read process, UFS device controller 2210 can use a built-in error correction code (ECC) engine to detect and correct errors in the read user data. More specifically, the ECC engine can generate parity bits for the write data to be written to non-volatile memory 2220, and thus the generated parity bits can be stored in non-volatile memory 2220 along with the write data. When reading data from non-volatile memory 2220, the ECC engine can use the parity bits read from non-volatile memory 2220 along with the read data to correct errors in the read data and output the error-corrected read data.

[0165] In addition, the UFS device controller 2210 can send user data temporarily stored in the device memory 2240 to the UFS host 2100.

[0166] The Advanced Encryption Standard (AES) engine can use a symmetric key algorithm to perform at least one of encryption and decryption operations on the data input to the UFS device controller 2210.

[0167] The UFS host 2100 can sequentially store commands to be sent to the UFS device 2200 in a UFS host register 2111 that can be used as a command queue, and send the commands to the UFS device 2200 in sequence. Simultaneously, even if a previously sent command is still being processed by the UFS device 2200 (i.e., even before receiving notification that a previously sent command has been completed by the UFS device 2200), the UFS host 2100 can also send the next command waiting in the command queue to the UFS device 2200. Therefore, even while processing a previously sent command, the UFS device 2200 can receive the next command from the UFS host 2100. The maximum number of commands that can be stored in such a command queue (queue depth) can be, for example, 32. Furthermore, the command queue can be implemented as a circular queue type, with a head pointer and a tail pointer indicating the start and end of the command sequence stored in the queue, respectively.

[0168] UFS host 2100 can determine the total power available in UFS system 2000 and determine the amount of power that can be allocated to UFS device 2200 from the determined total power. UFS host 2100 can, but is not limited to, communicate the power budget allocated to UFS device 2200 to UFS device controller 2210.

[0169] VCC, VCCQ1, VCCQ2, etc. can be used as electrical voltages and input to the UFS device 2200.

[0170] VCCQ1 is a power supply voltage used to supply a low range of voltages, primarily for the UFS device controller 2210. VCCQ1 can have a value from 1.14V to 1.26V. VCCQ2 is a power supply voltage primarily used to supply input / output interfaces (such as MIPI M-PHY2251) with a voltage range below VCC but above VCCQ1, and can have a value from 1.7V to 1.95V. These power voltages can be supplied to each component of the UFS device 2200 via regulator 2260.

[0171] The regulator 2260 can be implemented as a set of unit regulators, each unit regulator being connected to a different power supply voltage among the aforementioned power supply voltages.

[0172] In some embodiments, according to example implementations, by Figure 1 , Figure 2 , Figure 5 , Figure 6 , Figure 8 , Figure 12 , Figure 16 and Figure 17 Each of the components represented by the boxes shown can be implemented as various numbers of hardware and / or firmware structures to perform the corresponding functions described above. For example, at least one of these components may include various hardware components comprising digital circuits, programmable or non-programmable logic devices or arrays, application-specific integrated circuits (ASICs), transistors, capacitors, logic gates, or other circuits using direct circuit structures (such as memory, processors, logic circuits, lookup tables, etc.) that can perform the corresponding functions under the control of one or more microprocessors or other control devices. Furthermore, at least one of these components may also include a processor (such as a central processing unit (CPU) performing the corresponding functions), a microprocessor, etc., or may be implemented by a processor (such as a central processing unit (CPU) performing the corresponding functions), a microprocessor, etc. The functional aspects of the example embodiments may be implemented in algorithms executed on one or more processors. Furthermore, the components, elements, modules, or units represented by blocks or processing steps may employ any number of related techniques for electronic configuration, signal processing, control, and / or data processing, etc.

[0173] While various aspects of the embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: A first non-volatile memory device includes a first current management circuit configured to receive a first command and first peak information in a first mode and determine the execution timing of the first command based on the first peak information, wherein the first non-volatile memory device is configured to output first elapsed time information indicating the internal operation time according to the first command. A second non-volatile memory device includes a second current management circuit configured to receive a second command and first peak information in a first mode and determine the execution timing of the second command based on the first peak information, wherein the second non-volatile memory device is configured to output second elapsed time information indicating internal operation time according to the second command; and The storage controller includes a peak manager circuit configured to output first peak information and deactivate a faulty current management circuit in either the first or second current management circuit based on first elapsed time information and second elapsed time information.

2. The storage device according to claim 1, wherein: The first non-volatile memory device further includes: a plurality of memory blocks, including a plurality of memory cells connected to a plurality of word lines, and The first non-volatile memory device is also configured to isolate the multiple word lines based on a first command.

3. The storage device according to claim 2, wherein, The first non-volatile memory device also includes: A voltage generator is configured to generate a voltage signal for memory operation according to a first command; Multiple transmission transistors are connected to the multiple word lines and configured to send voltage signals to the multiple memory cells; and A block decoder is configured to output a memory block selection signal for selecting the plurality of memory blocks to the gate of the plurality of transmission transistors.

4. The storage device according to claim 3, wherein, The block decoder is also configured to deactivate the memory block selection signal based on the first command.

5. The storage device according to claim 1, wherein, The first elapsed time information includes time information indicating the time when the first non-volatile memory device receives the first peak information and the time when the first non-volatile memory device completes its internal operation according to the first command.

6. The storage device according to claim 1, wherein, The first peak information has a first level during a predetermined time period and a second level outside the predetermined time period.

7. The storage device according to claim 6, wherein, The peak manager circuit is also configured to: determine the remaining time as the difference between the first elapsed time indicated by the first elapsed time information and the predetermined time, compare the remaining time with a reference time for memory operations corresponding to the first command, and deactivate the first current management circuit based on the difference between the remaining time and the reference time exceeding a threshold.

8. The storage device according to claim 1, wherein: The second non-volatile memory device is also configured to receive a third command in a second mode, different from the first mode. The second current management circuit is also configured to generate second peak information regarding the third command, and The storage controller also includes a queue manager circuit, which is configured to perform queue management operations on the first non-volatile memory device based on the deactivation of the first current management circuit.

9. The storage device according to claim 8, wherein, The queue manager circuit is also configured to assign commands with peak currents below a preset threshold to the first non-volatile memory device based on second peak information.

10. The storage device according to claim 9, wherein, Commands with peak currents below a preset threshold are read commands.

11. The storage device according to claim 8, wherein, The queue manager circuit is also configured to: queue the fourth command in the command queue based on the second peak information, determine the execution timing of the fourth command by the first non-volatile memory device based on the second peak information, and send the fourth command to the first non-volatile memory device according to the execution timing of the fourth command.

12. The storage device according to claim 8, further comprising: The buffer memory is configured to store set values ​​of operating parameters corresponding to the first non-volatile memory device and peak current values ​​corresponding to the set values ​​of the operating parameters. The queue manager circuit is further configured to change the set value of the operating parameters corresponding to the first non-volatile memory device based on the set value of the operating parameters corresponding to the first non-volatile memory device stored in the buffer memory and the peak current value corresponding to the set value of the operating parameters.

13. The storage device according to claim 12, wherein, The operation parameters include programming time and reading time.

14. The storage device according to any one of claims 1 to 13, wherein, The storage controller is also configured to output the first command at a predetermined time period.

15. A storage controller, comprising: The processor is configured to: output commands to control memory operations on a non-volatile memory device comprising multiple memory cells, and output dummy commands to control test operations on current management circuitry within the non-volatile memory device based on signals representing the internal state of the non-volatile memory device. The peak manager circuit is configured to: output pseudo-peak information indicating the peak current segment based on a dummy command, receive elapsed time information indicating the internal operating time of the non-volatile memory device according to the dummy command, and determine the performance of the current management circuit based on the elapsed time information. as well as The queue manager circuit is configured to perform queue management operations on non-volatile memory devices based on the performance of the current management circuit.

16. The storage controller according to claim 15, wherein, The processor is also configured to: predict the operation completion time of the non-volatile memory device according to the command, compare the first time when the signal transitions from a first state to a second state different from the first state with the predicted operation completion time, and output a dummy command based on the difference between the first time and the predicted operation completion time exceeding a threshold.

17. The storage controller of claim 15, further comprising: A buffer memory is configured to store reference values ​​for operating parameters used in non-volatile memory devices. The memory controller is configured to: determine the internal operating time of the non-volatile memory device for a dummy command based on the peak current segment of the pseudo-peak information and the elapsed time information, and determine the performance of the current management circuit by comparing the internal operating time with reference values ​​of the operating parameters for the non-volatile memory device.

18. The storage controller according to claim 17, wherein, The operation parameters include programming time and reading time.

19. The storage controller according to claim 17, wherein, The buffer memory is also configured to store the peak current value corresponding to the set value of the operating parameters, and The queue manager circuit is also configured to change the set value of the operating parameters of the non-volatile memory device based on the peak current value corresponding to the set value of the operating parameters.

20. A general-purpose flash memory storage system, comprising: A general-purpose flash storage host is configured to determine a power budget; as well as General-purpose flash memory devices, The general-purpose flash memory storage devices include: Multiple non-volatile memories, wherein one of the multiple non-volatile memories includes current management circuitry configured to: determine the execution timing of the command based on peak information of a peak current segment for a command, which is shared according to a power budget; and A general-purpose flash memory controller is configured to: output a dummy command for testing the performance of a current management circuit and a pseudo-peak signal including a predefined peak current segment; control the power of the current management circuit based on the internal operating time of the plurality of non-volatile memories according to the dummy command and the pseudo-peak signal; and perform queue management operations on the plurality of non-volatile memories based on the internal operating time of the plurality of non-volatile memories.

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