Memory and operating method thereof, memory system

Abstract

The present disclosure provides a memory and an operating method thereof, a memory system, the memory including a memory cell array and a peripheral circuit coupled to the memory cell array, the peripheral circuit configured to perform a write operation of writing M+2*N-bit data into a first memory cell and a second memory cell, wherein, in a write operation phase, the peripheral circuit is configured to: obtain first state group information and second state group information based on received M-bit data; perform a programming operation to program the first memory cell to a first target state within a first target state group based on the first state group information and received N-bit data, and program the second memory cell to a second target state within a second target state group based on the second state group information and received another N-bit data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to memory and its operation methods, and memory systems. Background Technology

[0002] Since its introduction, the core driving force behind the development of NAND technology, in both the 2D and 3D eras, has been improving performance, extending lifespan, enhancing reliability, increasing storage density, and reducing the cost per unit storage cell. Achieving increased storage density and reduced cost per unit storage cell primarily relies on expanding the capacity of NAND memory. A key method of capacity expansion is logical scaling, which refers to increasing storage density by expanding the number of bits in the storage cell. Currently, NAND memory has successively evolved through SLC, MLC, TLC, and QLC. While providing increased storage density, logical scaling also brings challenges in manufacturing processes and sacrifices in reliability. Summary of the Invention

[0003] This disclosure provides a memory and its operation method, as well as a memory system.

[0004] In a first aspect, embodiments of this disclosure provide a memory, including:

[0005] Storage cell array;

[0006] The peripheral circuitry, coupled to the memory cell array, is configured to perform a write operation that writes M+2*N bits of data into the first and second memory cells, where M and N are both positive integers; wherein, during the write operation phase, the peripheral circuitry is configured as follows:

[0007] Based on the received M-bit data, first state group information and second state group information are obtained. The first state group information indicates that the first storage unit will be programmed into a first target state group among multiple state groups, and the second state group information indicates that the second storage unit will be programmed into a second target state group among the multiple state groups.

[0008] Perform programming operations to program the first storage unit to a first target state within the first target state group based on the first state group information and the received N bits of data, and to program the second storage unit to a second target state within the second target state group based on the second state group information and the received additional N bits of data.

[0009] Secondly, embodiments of this disclosure provide yet another type of memory, including:

[0010] A storage cell array includes multiple storage cells, each of which is in a state within a state group of multiple state groups, and every two of the storage cells are configured to jointly store M+2*N bits of data, where M and N are both positive integers.

[0011] The peripheral circuitry, coupled to the memory cell array, is configured as follows:

[0012] A state group read operation is performed to determine the state group to which the storage unit belongs, thereby obtaining the first state group information of the first storage unit and the second state group information of the second storage unit in every two storage units, and determining M bits of data based on the first state group information and the second state group information.

[0013] A state read operation is performed to determine the state of the storage unit within its state group, thereby obtaining N bits of data stored in the first storage unit and another N bits of data stored in the second storage unit.

[0014] Thirdly, embodiments of this disclosure provide a memory system, including:

[0015] At least one memory as described in any one of claims 1 to 17;

[0016] A memory controller, coupled to the memory, is configured to control the memory to perform write and read operations.

[0017] Fourthly, embodiments of this disclosure provide a method for operating a memory, the method comprising:

[0018] During the write operation phase of writing M+2*N bits of data into the first storage unit and the second storage unit, first state group information and second state group information are obtained based on the received M bits of data. The first state group information indicates that the first storage unit will be programmed into the first target state group among multiple state groups, and the second state group information indicates that the second storage unit will be programmed into the second target state group among the multiple state groups.

[0019] During the write operation phase, a programming operation is performed to program the first storage unit to a first target state within the first target state group based on the first state group information and the received N bits of data, and to program the second storage unit to a second target state within the second target state group based on the second state group information and the received additional N bits of data.

[0020] Fifthly, this disclosure provides another method for operating a memory, the memory comprising a plurality of storage units, each storage unit being in a state within a state group of a plurality of state groups, and every two storage units being configured to jointly store M+2*N bits of data, where M and N are both positive integers; the operation method includes:

[0021] A state group read operation is performed to determine the state group to which the storage unit belongs, thereby obtaining the first state group information of the first storage unit and the second state group information of the second storage unit in every two storage units, and determining M bits of data based on the first state group information and the second state group information.

[0022] A state read operation is performed to determine the state of the storage unit within its state group, thereby obtaining N bits of data stored in the first storage unit and another N bits of data stored in the second storage unit.

[0023] In this embodiment, the peripheral circuit can obtain first state group information and second state group information based on M-bit data. Then, by performing a programming operation, the first storage unit is programmed into the first target state within the first target state group according to the first state group information and the received N-bit data. Similarly, the second storage unit is programmed into the second target state within the second target state group according to the second state group information and the received additional N-bit data, thereby writing M+2*N bits of data into both the first and second storage units. The solution provided by this embodiment uses two storage units to store M+2*N bits of data, which increases the storage density of the memory. Furthermore, since each storage unit requires relatively few states to store N+M / 2 bits of data, the probability of errors during write and read operations is relatively low, resulting in relatively high reliability. It also reduces the requirements for the read window, thus lowering the difficulty of the storage unit fabrication process and improving feasibility. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of an exemplary system provided for an embodiment of the present disclosure.

[0025] Figure 2a This is a schematic diagram of a memory card provided in an embodiment of this disclosure.

[0026] Figure 2b A schematic diagram of an SSD provided in an embodiment of this disclosure.

[0027] Figure 3 This is a schematic diagram of a memory including peripheral circuitry provided for an embodiment of this disclosure.

[0028] Figure 4 This is a schematic diagram of a memory cell array including NAND memory strings, provided for an embodiment of this disclosure.

[0029] Figure 5 This is a schematic diagram illustrating the bit changes of a storage unit provided in an embodiment of this disclosure.

[0030] Figure 6 A schematic diagram of the peripheral circuit provided in an embodiment of this disclosure.

[0031] Figure 7 The first embodiment of this disclosure provides a correspondence between the state group combination of two storage units and 3-bit data.

[0032] Figure 8 The correspondence between the eight states and 3 bits of data in each of the three state groups provided in the embodiments of this disclosure.

[0033] Figure 9 This is a schematic diagram illustrating the change in threshold voltage distribution during a two-step programming operation provided in an embodiment of this disclosure.

[0034] Figure 10 A schematic diagram of the peripheral circuit including a page buffer provided for embodiments of this disclosure. Figure 1 .

[0035] Figure 11 The correspondence between location information, M-bit data, state groups, and state group information provided in the embodiments of this disclosure.

[0036] Figure 12 Schematic diagram 2 shows the peripheral circuitry including the page buffer provided for an embodiment of this disclosure.

[0037] Figure 13 The command sequence for the first step of the programming operation provided in the embodiments of this disclosure.

[0038] Figure 14 The command sequence for the second programming operation provided in the embodiments of this disclosure.

[0039] Figure 15 A schematic diagram of data reading operations on pages 0 to 9 provided in this embodiment of the disclosure. Figure 1 .

[0040] Figures 16a to 16c This is a schematic diagram illustrating the process of reading a status group according to an embodiment of the present disclosure.

[0041] Figure 17 A schematic diagram of a page buffer and read logic circuitry provided for embodiments of this disclosure.

[0042] Figure 18 The command sequence for the state group read operation phase provided in the embodiments of this disclosure.

[0043] Figure 19This is a schematic diagram illustrating the state reading operation process provided in an embodiment of this disclosure.

[0044] Figure 20 The command sequence for the status read operation phase provided in the embodiments of this disclosure.

[0045] Figure 21 The second part describes the correspondence between the state group combination of the two storage units and the 3-bit data provided in the embodiments of this disclosure.

[0046] Figure 22 The correspondence between N-bit data provided in the embodiments of this disclosure and multiple states within each state group.

[0047] Figure 23 Based on Figure 22 The diagram illustrates the corresponding relationship between the read operation methods.

[0048] Figure 24 Illustration of the operation method provided in the embodiments of this disclosure Figure 1 .

[0049] Figure 25 Schematic diagram 2 shows the operation method provided in the embodiments of this disclosure. Detailed Implementation

[0050] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0051] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0052] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0053] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0055] Increasing storage density to reduce the cost per unit storage cell has always been the direction and driving force for the development of NAND flash memory. Achieving this primarily relies on expanding the capacity of NAND flash memory. One important method of expansion is logical expansion. Logical expansion refers to increasing storage density by expanding the number of bits in the storage cell. Currently, NAND products have evolved from SLC to MLC to TLC to QLC, with QLC products now largely mature. Furthermore, the concept of PLC (Programmable Logic Controller) has also been proposed. While logical expansion provides increased storage density, it also comes at the cost of performance and lifespan. For a PLC, if a storage cell stores 5 bits of data, it needs 32 states. The more states a storage cell is divided into, the more difficult it becomes to increase the read margin between adjacent states. Therefore, for PLC products to achieve mass production, further breakthroughs in technology and algorithms are needed.

[0056] Considering both storage capacity and reliability, having two storage units jointly store 9 bits of data, or one storage unit storing 4.5 bits of data, becomes a feasible solution. This solution can further meet the market's demand for memory capacity under current technological conditions and is highly achievable.

[0057] Figure 1 This is a block diagram of an exemplary system including memory, provided for embodiments of this disclosure. The exemplary system 100 may include a host 110 and a memory system 120. The exemplary system 100 may include, but is not limited to, a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory 122 therein; the host 110 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)).

[0058] In one embodiment of this disclosure, host 110 may be configured to send data to or receive data from memory system 120. Here, memory system 120 may include memory controller 121 and one or more memories 122. The memories 122 may include, but are not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc.

[0059] In one embodiment of this disclosure, a memory controller 121 may be coupled to a memory 122 and a host 110 and is used to control the memory 122. Exemplarily, the memory controller 121 may be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, and mobile phones. In some embodiments, the memory controller 121 may also be designed to operate in a high duty cycle environment, such as a Solid State Disk (SSD) or an embedded Multi-Media Card (eMMC), and the SSD or eMMC may be used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0060] Furthermore, the memory controller 121 can manage the data in the memory 122 and communicate with the host. The memory controller 121 can be configured to control operations such as reading, erasing, and programming of the memory 122; it can also be configured to manage various functions related to data stored or to be stored in the memory 122, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; and it can also be configured to process error checking and correction (ECC) codes for data read from or written to the memory 122. In addition, the memory controller 121 can perform any other suitable functions, such as formatting the memory 122, or communicating with external devices (e.g., according to a specific communication protocol) according to a specific communication protocol. Figure 1The memory controller 121 communicates with the external host (110). For example, the memory controller 121 can communicate with the external host via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Development Equipment (IDE), FireWire, etc.

[0061] In one embodiment of this disclosure, the memory controller 121 and one or more memories 122 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 120 can be implemented and packaged into different types of end electronic products. Figure 2a As shown, the memory controller 121 and a single memory 122 can be integrated together to form a memory card 210. The memory card 210 may include a PC card (Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), RS-MMC (Reduced-Size MMC), MMCmicro, an SD card (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), UFS, etc. The memory card 210 may also include a connector for connecting the memory card 210 to a host computer (e.g., Figure 1 The memory card connector 211 is coupled to the host 110. In such a way... Figure 2bIn another embodiment shown, the memory controller 121 and a plurality of memories 122 may be integrated together to form an SSD 220. The SSD 220 may also include a connection between the SSD 220 and a host (e.g., Figure 1 The SSD connector 221 is coupled to the host 110. In some embodiments, the storage capacity and / or operating speed of the SSD 220 is greater than that of the memory card 210.

[0062] It should be noted that the memory involved in one embodiment of this disclosure can be a semiconductor memory, which is a solid-state electronic device for storing data information manufactured using semiconductor integrated circuit technology. Figure 3 This is a schematic diagram of a memory including peripheral circuitry provided in an embodiment of the present disclosure, wherein the memory 300 may be... Figures 1 to 2b Memory 122 in the memory. For example... Figure 3 As shown, the memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. Here, the memory cell array may be a NAND flash memory cell array, wherein the memory cells are arranged in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above the substrate. In some embodiments, each NAND memory string 308 may include a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the memory cell region. Additionally, each memory cell 306 in the aforementioned memory cell array 301 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0063] like Figure 3 As shown, each NAND memory string 308 may include a source select transistor 310 at its source terminal and a drain select transistor 312 at its drain terminal. The source select transistor may also be referred to as a bottom select transistor, and the drain select transistor may also be referred to as an top select transistor. The source select transistor 310 and the drain select transistor 312 may be configured to activate the selected NAND memory string 308 (column of the array) during read and program operations.

[0064] In some implementations, the sources of NAND memory strings 308 within the same block 304 are coupled via a common source line (SL) 314 (e.g., a common source line). In other words, according to some implementations, all NAND memory strings 308 within the same block 304 have an array common source (ACS). According to some implementations, the drain selection transistor 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, allowing data to be read from or written to the bit line 316 via an output bus (not shown).

[0065] In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than a threshold voltage having a drain-select transistor 312) or a deselection voltage (e.g., 0V) to the gate of the corresponding drain-select transistor 312 via one or more drain-select gate lines (DSG lines) 313; and / or by applying a selection voltage (e.g., higher than a threshold voltage having a source-select transistor 310) or a deselection voltage (e.g., 0V) to the gate of the corresponding source-select transistor 310 via one or more source-select gate lines 315. The NAND memory strings 308 can thus be distinguished as selected NAND memory strings or unselected NAND memory strings. The selection voltage can also be referred to as a control turn-on voltage, used to turn on the corresponding transistor, and the deselection voltage can also be referred to as a control turn-off voltage, used to turn off the corresponding transistor.

[0066] like Figure 3 As shown, the NAND memory string 308 can be organized into multiple blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is a basic data unit for an erase operation, i.e., all memory cells 306 on the same block 304 are erased simultaneously. To erase memory cells 306 in a selected block, an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher), can be used to bias the source line 314 of the selected block and the unselected blocks on the same plane as the selected block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks.

[0067] Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320 and gate lines coupling the control gates.

[0068] Figure 4 This is a schematic diagram of a memory cell array including NAND memory strings, provided as an embodiment of this disclosure. Figure 4 As shown, the NAND memory string 308 can extend vertically through the memory stack layer 404 above the substrate 402. The substrate 402 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0069] The memory stack 404 may include alternating gate conductive layers 406 and dielectric layers 408, wherein the number of pairs of gate conductive layers 406 and dielectric layers 408 determines the number of memory cells 306 in the memory cell array 301. The gate conductive layer 406 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. The gate conductive layer 406 may extend laterally at the top of the memory stack 404 as a drain select gate line 313, laterally at the bottom of the memory stack 404 as a source select gate line 315, or laterally between the drain select gate line 313 and the source select gate line 315 as a word line 318. It should be understood that although... Figure 3 The diagram shows a source select gate line (SSG line) 315 and a drain select gate line (DSG line) 313, but the number of source select gate lines 315 and drain select gate lines 313 (and the number of source select transistors 310 and drain select transistors 312 coupled to source select gate lines 315 and drain select gate lines 313, respectively) can vary in other examples.

[0070] like Figure 4As shown, the NAND memory string 308 includes a channel structure 412 extending vertically through the memory stack layer 404. In some embodiments, the channel structure 412 includes channel holes filled with a semiconductor material (e.g., as a semiconductor channel 420) and a dielectric material (e.g., as a memory film 418). In some embodiments, the semiconductor channel 420 includes silicon, for example, polysilicon. In some embodiments, the memory film 418 is a composite dielectric layer including a tunneling layer 426, a storage layer 424 (also referred to as a "charge trapping layer"), and a barrier layer 422. The channel structure 412 may have a pillar shape (e.g., a cylindrical shape). According to some embodiments, the semiconductor channel 420, tunneling layer 426, storage layer 424, and barrier layer 422 are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 424 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 422 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film 418 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0071] In some embodiments, such as Figure 4 As shown, a well 414 (e.g., a P-well and / or an N-well) is formed in the substrate 402, and the source terminal of the NAND memory string 308 contacts the well 414. For example, a source line 314 may be coupled to the well 414 to apply an erase voltage to the well 414 (i.e., the source of the NAND memory string 308) during an erase operation. In some embodiments, the NAND memory string 308 also includes a channel plug 416 at the drain terminal of the NAND memory string 308, for example, as part of the drain terminal of the NAND memory string 308. It should be understood that... Figure 4 The structure of channel structure 412 depicted is for illustrative purposes only and may be modified in other examples. It should be understood that, although in Figure 4 Additional components, not shown, may also form the memory cell array 301. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0072] Figure 5 A schematic diagram illustrating the bit changes of a storage cell provided in an embodiment of this disclosure. In some embodiments, the storage cell (e.g., Figure 3The storage cell 306 can be a single-level cell (SLC) having two possible storage states and thus being able to store one bit of data. For example, the first storage state "0" can correspond to a first threshold voltage distribution, and the second storage state "1" can correspond to a second threshold voltage distribution. In other embodiments, the storage cell can be a multi-level cell capable of storing more than one bit of data in more than four storage states. For example, a storage cell can store two bits of data in four storage states, referred to as a two-level cell or a multi-level cell (MLC). A storage cell can also store three bits of data in eight memory states, referred to as a triple-level cell (TLC). A storage cell can also store four bits of data in sixteen states, referred to as a quad-level cell (QLC). Alternatively, a storage cell can also store five bits of data in thirty-two states, referred to as a penta-level cell (PLC).

[0073] The division of the state of a storage unit can be understood as dividing the storage layer (e.g., Figure 4 The storage layer (424) is divided according to the number of electrons. Taking MLC as an example, less than 10 electrons are classified as P1 state, 11-20 electrons as P2 state, 21-30 electrons as P3 state, and more than 30 electrons as P4 state. P1 to P4 states are... Figure 5 The four states corresponding to MLC. For example... Figure 5 As shown, with the increase in the number of bits stored in a memory cell, more and more data is stored in a single memory cell, resulting in increased storage density and reduced cost per unit. However, at the same time, the electrons in a memory cell are divided more finely, so during write operations, the control over the number of electrons entering the storage layer needs to be more precise, thus increasing the write time. Similarly, reading requires a higher read voltage, which may prolong the read time and reduce the read speed. Furthermore, as... Figure 5 As shown, the read window between the threshold voltage distributions of adjacent states becomes smaller and smaller, increasing the probability of errors when writing or reading data, thus reducing the reliability of the storage unit. Therefore, in terms of performance, from PLC to SLC, reliability gradually deteriorates and read / write speeds gradually decrease.

[0074] The present disclosure proposes a storage unit that stores 4.5 bits of data, falling between QLC and PLC. This storage unit can store 4.5 bits of data across 24 states, compared to the 32 states required by a QLC. The larger read window between these 24 states results in better performance and easier implementation. Furthermore, compared to a QLC, a single storage unit can store more data, leading to higher storage density and lower cost. Storing 4.5 bits of data in a single unit reduces manufacturing complexity and improves feasibility, while simultaneously achieving higher storage density than QLC, thus meeting market demands.

[0075] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, source select gate line 315, and drain select gate line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for implementing write and read operations on the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, source select gate line 315, and drain select gate line 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 The schematic diagram of the peripheral circuitry provided in this embodiment of the disclosure shows that peripheral circuitry 302 includes a page buffer / logic circuitry 504, a column decoder / BL driver 506, a row decoder / WL driver 508, a voltage generator 510, control logic 512, a register 514, an interface (I / F) 516, and a data bus 518. It should be understood that in some examples, it may also include... Figure 6 Additional peripheral circuitry not shown.

[0076] Page buffer / logic circuit 504 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / logic circuit 504 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / logic circuit 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / logic circuit 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during a read operation.

[0077] The column decoder / BL driver 506 can be configured to be controlled by control logic 512 and to select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0078] The row decoder / word WL driver 508 can be configured to be controlled by control logic 512 and to select / deselect block 304 of the memory cell array 301 and word lines 318 in block 304 according to control signals generated by the control logic. The row decoder / WL driver 508 can also be configured to drive word lines 318 using different word line voltages generated from voltage generator 510. In some embodiments, the row decoder / WL driver 508 can also select / deselect source select gate line 315 and drain select gate line 313. The row decoder / WL driver 508 is configured to drive source select gate line 315 using different SSG line voltages generated from voltage generator 510, and / or drive drain select gate line 313 using different DSG line voltages generated from voltage generator 510.

[0079] Voltage generator 510 can be configured to be controlled by control logic 512 and generate various word line voltages (e.g., read voltage, programming voltage, pass voltage, verification voltage, etc.), bit line voltages, ground voltages, various SSG line voltages (e.g., select voltage, deselect voltage) and various DSG line voltages (e.g., select voltage, deselect voltage) to be supplied to memory cell array 301.

[0080] Control logic 512 can be coupled to each of the peripheral circuit sections described above and is configured to control the operation of each peripheral circuit section. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register to store status information, command opcodes, and command addresses for controlling the operation of the peripheral circuits. In some embodiments, control logic 512 can receive commands from a memory controller (e.g., Figure 1 The memory controller 106 issues programming commands and sends control signals to various peripheral circuit sections, such as row decoder / word line driver 508, column decoder / bit line driver 506, and voltage generator 510, to perform programming operations on the source selection transistor coupled to the source selection gate line.

[0081] Interface 516 can be coupled to control logic 512 and act as a control buffer to buffer control commands (e.g., programming commands) received from the memory controller or host and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the memory controller or host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and act as a data input / output (I / O) interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0082] See back Figure 5 A single memory cell stores 4.5 bits of data, which is achieved by two memory cells jointly storing 9 bits of data. This disclosure provides a programming operation method and a reading operation method for implementing the joint storage of 9 bits of data in two memory cells. These methods are applicable not only to this but also to the joint storage of M+2*N bits of data in two memory cells, where M and N are positive integers. In some embodiments, the memory includes: a memory cell array and peripheral circuitry coupled to the memory cell array. The peripheral circuitry is configured to perform a write operation that writes M+2*N bits of data into the first and second memory cells; wherein, during the write operation phase, the peripheral circuitry is configured to:

[0083] Based on the received M-bit data, first state group information and second state group information are obtained. The first state group information indicates that the first storage unit will be programmed into the first target state group among multiple state groups, and the second state group information indicates that the second storage unit will be programmed into the second target state group among multiple state groups.

[0084] Perform programming operations to program the first storage unit into the first target state within the first target state group based on the first state group information and the received N bits of data, and to program the second storage unit into the second target state within the second target state group based on the second state group information and the received additional N bits of data.

[0085] The memory in this embodiment can be Figures 1 to 6 The memory shown in any embodiment includes a memory cell array, which comprises a plurality of memory cells arranged in an array, wherein the memory cells are NAND flash memory cells. For example, the memory cell array may be... Figure 3 and Figure 6 The storage cell array 301 in the middle, the storage cell can be Figures 3 to 5 The storage unit shown in any of the embodiments.

[0086] This disclosure will now be explained using the example of M-bit data being represented as three-bit data and N-bit data being represented as three-bit data.

[0087] In this embodiment, two storage units jointly store 3 + 2 * 3 bits (9 bits) of data, with each storage unit storing 4.5 bits of data. Therefore, each storage unit requires 24 states, and the two storage units can be combined into 24 * 24 = 576 combinations, or 576 states. Referring to QLC and PLC, it can be understood that storing 9 bits of data requires 2... 9 = 512 states, and the 576 combinations of two storage units can cover the 512 states. Therefore, each storage unit has 24 states, and 2 storage units can store 9 bits of data.

[0088] In this paper, the two storage units that jointly store 9 bits of data will be referred to as storage unit A and storage unit B, respectively. Storage unit A and storage unit B are two completely equal storage units, each with 24 states, and the threshold voltage distributions corresponding to the 24 states are also the same. In the 9 bits of data, the first 3 bits are jointly stored by storage unit A and storage unit B, and of the last 6 bits, 3 bits are stored separately by storage unit A, and the remaining 3 bits are stored separately by storage unit B.

[0089] In some embodiments, the 9-bit data consists of one bit of data from each of nine half-pages. The nine half-pages are, in order, page0, page1, page2, page3, page4, page5, page6, page7, and page8. For ease of representation, each bit of the 9-bit data is represented by the corresponding page number. Page0 / page1 / page2 are jointly stored by the first storage unit A and the second storage unit B. Page3 / page5 / page7 are stored by one of the storage units, and page4 / page6 / page8 are stored by the other storage unit. This embodiment uses the example of page3 / page5 / page7 being stored in the first storage unit A and page4 / page6 / page8 being stored in the second storage unit B. It should be understood that the first storage unit A and the second storage unit B are identical; therefore, conversely, it is also possible for page3 / page5 / page7 to be stored in the second storage unit B and page4 / page6 / page8 to be stored in the first storage unit A.

[0090] In some embodiments, the first storage unit A and the second storage unit B can jointly store 3 bits of data in the following manner. Specifically, the 24 states of each storage unit are divided into three state groups SG0, SG1, and SG2, with each state group including 8 states. Therefore, the first storage unit has three state groups, and the second storage unit has three state groups, resulting in 9 possible combinations of the state groups from the two storage units. Eight of these nine combinations can be used to store the eight numerical values ​​corresponding to the 3 bits of data: 000, 001, 010, 011, 100, 101, 110, and 111.

[0091] Figure 7 This diagram illustrates the correspondence between the state group combinations of two storage units provided in this embodiment and 3-bit data. The horizontal axis represents the three state groups of the first storage unit A (Cell_A), the vertical axis represents the three state groups of the second storage unit B (Cell_B), and the data in the 3x3 grid represents the possible values ​​of the 3-bit data they jointly store. Figure 7 As shown, the eight state group combinations of the first storage unit A and the second storage unit B correspond to eight numerical values. Taking the data in the first column of the 3x3 grid as an example, if the first storage unit A is in the SG0 state group, the second storage unit B stores the value 111 if it is in the SG0 state group, 110 if it is in the SG1 state group, and 100 if it is in the SG2 state group. The correspondence between other numerical values ​​and state group combinations can be found in [reference needed]. Figure 7 Among them, there is an additional state group combination, namely, the first storage unit A is in the SG2 state group and the second storage unit B is in the SG0 state group, which is not used.

[0092] Figure 7 The diagram only shows one correspondence between the nine state group combinations and the three-bit data. It should be understood that different correspondences can be used in different implementations as needed.

[0093] based on Figure 7 From the correspondence in the diagram, we can understand that if we want to write a certain value, we need to configure the first storage unit A and the second storage unit B according to... Figure 7 The corresponding relationships are programmed into the state group corresponding to the value. For example, if page0 / page1 / page2 is 110, then during the write operation phase, the first storage unit A needs to be programmed into state group SG0, and the second storage unit B needs to be programmed into state group SG1. Similarly, if page0 / page1 / page2 is 011, then during the write operation phase, the first storage unit A needs to be programmed into state group SG2, and the second storage unit B needs to be programmed into state group SG2.

[0094] During the write operation phase, the state group programmed to the first memory cell A is called the first target state group, which is one of three state groups. The state group programmed to the second memory cell B is called the second target state group, which is also one of three state groups. The first target state group and the second target state group may be the same or different. For example, when page0 / page1 / page2 is 110, the first target state group and the second target state group are different, but when page0 / page1 / page2 is 011, they are the same.

[0095] In some embodiments, during the write operation phase, the peripheral circuitry can program the first memory cell A and the second memory cell B to their respective corresponding state groups in the following manner. Specifically, the peripheral circuitry can obtain the first state group information and the second state group information based on page 0 / page 1 / page 2, wherein the first state group information indicates that the first memory cell will be programmed to a first target state group, and the second state group information indicates that the second memory cell will be programmed to a second target state group.

[0096] For example, the state group information is multi-bit in length, meaning it comprises multiple bits. The state group information can be encoded using Gray code, thus comprising multiple Gray code bits. In this embodiment, since there are three state groups, the state group information can include two Gray codes. Two Gray codes have four possible digits: 00, 01, 10, and 11. Three of these four digits can be used to represent the three state groups. For example... Figure 7 In this context, 11 represents state group SG0, 01 represents state group SG1, and 00 represents state group SG2. It's understandable that since each memory cell is identical, the correspondence between state groups and their information is consistent regardless of whether it's the first or second memory cell. Furthermore, it should be noted that... Figure 7 Only one correspondence between state groups and state group information is shown. In different implementations, different correspondences may be used as needed.

[0097] When using state group information to represent state groups, a direct correspondence between 3-bit data and state group information can be established. See also... Figure 7 The eight combinations of the first and second state group information correspond to eight numerical values. For example, if page0 / page1 / page2 is 111, the corresponding first state group information is 11, and the second state group information is 01. Similarly, if page0 / page1 / page2 is 011, the corresponding first state group information is 00, and the second state group information is 00. Other cases can be found in [reference needed]. Figure 7 Continue to understand.

[0098] Therefore, it can be understood that if you want to write a certain value, you can first follow the steps... Figure 7 The correspondence in the code converts the numerical values ​​into information for the first state group and the second state group, and then the programming is performed based on the information for the first state group and the second state group.

[0099] This disclosure details the process of writing the last 6 bits of data to the first storage unit A and the second storage unit B. Taking writing Page 3 / Page 5 / Page 7 to the first storage unit A and Page 4 / Page 6 / Page 8 to the second storage unit B as an example.

[0100] In some embodiments, each state group includes multiple states, and N bits of data can be stored using the multiple states within a state group. In this embodiment, each state group includes 8 states. Therefore, the first storage unit A can be used to store Page 3 / page 5 / page 7 using the 8 states in the first target state group, and the second storage unit B can be used to store Page 4 / page 6 / page 8 using the 8 states in the second target state group. It can be understood that the first target state group and the second target state group are one of multiple state groups, so each of the 8 states in each state group may store 3 bits of data, and there is a correspondence between each of the 8 states and 8 numerical values.

[0101] For example, the SG0 state group includes states S0 to S7, the SG1 state group includes states S8 to S15, and the SG2 state group includes states S16 to S23. Figure 8 The diagram shows the correspondence between the eight states in each of the three state groups and the three-bit data. Figure 8 The third and fourth columns (Gery code) show the state group information corresponding to the state group. For example, SG0 state group corresponds to state group information 11, SG1 state group corresponds to state group information 01, and SG2 state group corresponds to state group information 00. This is consistent with... Figure 7 The middle is consistent. Figure 8 Columns 5 through 7 show the correspondence between the 8 states and 8 values ​​within each state group.

[0102] For example, the 3-bit data stored separately in the first and second storage units are both encoded using Gray code. Figure 8As shown, within each state group, each of the eight states corresponds to one of eight numerical values ​​(also known as codes). However, the correspondence between the eight states, ordered from smallest to largest according to the threshold voltage distribution, and the eight codes can differ between different state groups. For example, in the SG0 state group, states S0 to S7 correspond to 111, 011, 001, 000, 010, 110, 100, and 101, respectively. In the SG1 state group, the order of the eight values ​​changes, with states S8 to S15 corresponding to 101, 111, 011, 010, 110, 100, 000, and 001, respectively. In the SG2 state group, the order of the eight values ​​changes again. (See [reference needed]). Figure 8 Within each state group, the correspondence between the eight states and eight values ​​affects the order and number of voltages applied during the read operation. A suitable correspondence can shorten the read operation time and reduce power consumption. This disclosure will describe this in detail in subsequent embodiments of the read operation. However, it is understood that... Figure 8 The correspondence shown is not unique; different correspondences may be used in different embodiments as needed.

[0103] Furthermore, it should be noted that in this embodiment, each storage unit is equal, so the correspondence between the states within the state groups of the first and second storage units and the 3-bit data is also the same. Figure 8 The values ​​in columns 5 through 7 can be any of the possible values ​​from page 3 / page 5 / page 7, or from page 4 / page 6 / page 8.

[0104] See also Figure 8 Two bits of state group information can determine the target state group to which the storage unit belongs, and three bits of data can determine the target state of the storage unit within the target state group. Therefore, for each storage unit, we obtain... Figure 8 The 5 bits of information shown can be programmed into one of 24 states. Furthermore, both the first and second storage units are programmed into their respective target states, allowing for the storage of 9 bits of data.

[0105] In summary, the embodiments of this disclosure propose that the peripheral circuit can obtain the first state group information and the second state group information based on the data of page0 / page1 / page2. Then, by performing a programming operation, the first storage unit is programmed into the first target state within the first target state group according to the first state group information and the received page3 / page5 / page7, and the second storage unit is programmed into the second target state within the second target state group according to the second state group information and the received page4 / page6 / page8, thereby writing 9 bits of data from page0 to page8 into the first and second storage units. Compared to QLC, the solution provided by this disclosure increases the storage density of the memory. Compared to PLC, each storage unit in the solution provided by this disclosure has 24 states, which is less than the 32 states of PLC, reducing the requirement for the read window. Therefore, it can reduce the difficulty of the storage unit manufacturing process and improve feasibility. Furthermore, since the number of states corresponding to each storage unit is reduced, the probability of errors during write and read operations is relatively low, and the reliability is relatively high.

[0106] In some embodiments, M can also be 5, or even a larger odd number. The number of state groups in each storage unit is related to M, and the number of combinations of state groups in the first and second storage units must be greater than or equal to the number of possible values ​​for the M-bit data. For example, when M bits are 5 bits, each storage unit needs to have 6 state groups, and the first and second storage units can be combined in 6*6=36 combinations to achieve 5-bit (2^32) data. 5 =32) Data storage. The length of the state group information can be 3 bits to indicate six state groups.

[0107] In some embodiments, N can also be an even number such as 2, 4, or even larger. The number of states within each state group is related to N, and each state group should include 2... N There are 4 states. For example, when N is 2, each state group needs to include 4 states. If M is still 3 bits, then the first and second storage units can jointly store 7 bits of data.

[0108] In some embodiments, the programming operation includes a first programming operation and a second programming operation. The peripheral circuitry is configured as follows:

[0109] Perform the first programming operation to program the first storage unit to the first target intermediate state corresponding to the first target state group based on the first state group information, and program the second storage unit to the second target intermediate state corresponding to the second target state group based on the second state group information;

[0110] Perform the second programming operation to program the first storage unit from the first target intermediate state to the first target state based on N bits of data, and program the second storage unit from the second target intermediate state to the second target state based on another N bits of data.

[0111] There are multiple intermediate states. The first target intermediate state is one of the multiple intermediate states, and the second target intermediate state is one of the multiple intermediate states. The first target intermediate state and the second target intermediate state may be the same intermediate state or they may not be the same intermediate state, depending on the state group information of the first storage unit and the second storage unit respectively.

[0112] For example, the number of intermediate states equals the number of state groups. Each state group corresponds to one intermediate state. A memory cell to be programmed into any state within a state group is first programmed into the corresponding intermediate state, and then programmed from the intermediate state into the target state. Although the concept of state groups is introduced when understanding the encoding scheme, in actual programming operations, the peripheral circuit can directly program the memory cell based on the state group information. As mentioned above, state group information can be represented using multi-bit Gray code. Therefore, in the first step of programming, the memory cell is programmed into an intermediate state based on the multi-bit Gray code, which is the same as programming the memory cell based on written data.

[0113] Figure 9 This diagram illustrates the change in threshold voltage distribution during a two-step programming operation provided in an embodiment of this disclosure. Figure 9 As shown, the programming operation can include a first programming operation and a second programming operation. The threshold voltage of the memory cell can be changed from the initial state to an intermediate state based on the first programming operation, and can be changed from the intermediate state to the programmed state based on the second programming operation.

[0114] The initial state is a state in which no programming operation has been performed, and the threshold voltage distribution of the memory cell can be in the erase state S0.

[0115] Through the first programming operation, the memory cells are programmed into one of three intermediate states S0′, S8′, and S16′ based on their respective state group information. For any given memory cell, the threshold voltage in the intermediate state is less than or equal to the threshold voltage in the target state to avoid overprogramming. This also ensures that the threshold voltage distribution of the intermediate states is less than or equal to the threshold voltage distribution of the lowest state within the state group. Figure 9 In the illustrated embodiments, the threshold voltage distribution of the intermediate states is close to the threshold voltage distribution of the lowest state within the state group. For example, intermediate state S0′ is close to state S0, intermediate state S8′ is close to state S8, and intermediate state S16′ is close to state S16. In other embodiments, the threshold voltage distribution of the intermediate states may be smaller than the threshold voltage distribution of the lowest state within the state group, and this disclosure does not impose any limitations on this.

[0116] In the implementation of the first programming operation, memory cells programmed to the lowest intermediate state S0′ can be disabled for programming and have the same threshold voltage as in the erase state S0. Memory cells programmed to other intermediate states S8′ and S16′ above the lowest intermediate state are allowed for programming and have a threshold voltage higher than that in the erase state S0.

[0117] In the second programming step, the storage unit is programmed from an intermediate state to a target state. The target state of the storage unit can be any state within the state group corresponding to the intermediate state. The target state can be determined from multiple states within the state group based on the N bits of data to be stored in each storage unit.

[0118] like Figure 9 As shown, a memory cell programmed to intermediate state S0′ can be programmed to any of states S0 to S7 through the second programming operation. A memory cell programmed to intermediate state S8′ can be programmed to any of states S8 to S16 through the second programming operation. A memory cell programmed to intermediate state S16′ can be programmed to any of states S16 to S23 through the second programming operation.

[0119] In some implementations of the second-step programming operation, the memory cell to be programmed to the lowest state within the state group can be disabled for programming and have the same threshold voltage as when it is in an intermediate state. Memory cells to be programmed to other states above the lowest state are allowed for programming and have threshold voltages higher than when they are in an intermediate state. In other implementations, all memory cells in intermediate states are allowed for programming and have threshold voltages greater than when they are in an intermediate state. For example, Figure 9 In the second programming operation, memory cells that will be programmed to states S0, S8, and S16 can be disabled from programming and have the same threshold voltage as when they are in the intermediate state, while memory cells that will be programmed to other states are allowed to be programmed to increase the threshold voltage.

[0120] In this embodiment, the first programming operation is based on state group information. This allows the peripheral circuit to receive only M bits of data to obtain the state group information, reducing the amount of data occupied by the latches in the page buffer. Consequently, the number of latches in the page buffer can be reduced, thus decreasing the page buffer area and facilitating device miniaturization. Furthermore, performing a second programming operation based on the first step allows for more refined programming, narrowing the threshold voltage distribution and increasing the read window between adjacent states.

[0121] In some embodiments, such as Figure 10As shown, the peripheral circuit includes multiple page buffers 610 coupled to the memory cell array. The multiple page buffers 610 include a first page buffer PB1 coupled to the first memory cell A and a second page buffer PB2 coupled to the second memory cell B.

[0122] The first page buffer PB1 is configured to obtain the first state group information based on the stored first position information and the received M bits of data.

[0123] The second page buffer PB2 is configured to obtain the second state group information based on the stored second position information and the received M bits of data.

[0124] As mentioned earlier, the peripheral circuit can obtain the first state group information and the second state group information based on the received M-bit data. There are multiple ways to implement this process. This disclosure provides one way to implement this process through the page buffer 610.

[0125] Storage cell arrays can be as follows Figure 3 or Figure 6 In any embodiment of the memory cell array 301, multiple bit lines BL are coupled to the memory cell array. For example, the coupling method between the multiple bit lines BL and the memory cell array can be... Figure 3 The bit line 316 is shown as being coupled to the memory cell array 301.

[0126] like Figure 10 As shown, multiple page buffers 610 are coupled to the memory cell array via multiple bit lines BL, and each page buffer 610 can be connected to one bit line BL. The multiple page buffers 610 can be configured to have the same circuit structure and achieve the same function. The first page buffer PB1 and the second page buffer PB2 are two of these page buffers.

[0127] In this embodiment, every two storage units jointly store M+2*N bits of data. Location information is used to indicate which of the two storage units the page buffer is coupled to. Specifically, first location information indicates that the page buffer is coupled to the first storage unit, and second location information indicates that the page buffer is coupled to the second storage unit. The first location information differs from the second location information, used to distinguish between the first page buffer coupled to the first storage unit and the second page buffer coupled to the second storage unit.

[0128] For example, the location information includes one bit. The first location information can be 0, the second location information can be 1, or vice versa; this disclosure does not impose any restrictions on this.

[0129] In this embodiment, each page buffer is configured to obtain state group information based on the stored location information and the received M bits of data. Figure 11The correspondence between location information, M-bit data, state groups, and state group information provided in the embodiments of this disclosure. Figure 11 The second column (PB index) shows the first position information of the first page buffer (First PB) and the second position information of the second page buffer (Second PB). In this embodiment, the first position information is 0 and the second position information is 1. Columns three to five show M bits of data, which are three bits in this embodiment, namely page0 / page1 / page2. The sixth column shows the cell state. The seventh column shows the state group information, which is represented by two Gray codes in this embodiment. Figure 11 The correspondence between the M-bit data, state groups, and state group information shown is as follows: Figure 7 same.

[0130] from Figure 11 It can be seen that the position information of the page buffer determines whether M-bit data is converted into the first state group information of the first memory cell or the second state group information of the second memory cell. Taking M-bit data as 110 as an example, if the first position information in the first page buffer is 0, then the M-bit data 110 is converted into the first state group information 11 in the first page buffer; if the position information in the second page buffer is 1, then the M-bit data 110 is converted into the second state group information 01 in the second page buffer.

[0131] For example, the location information in the page buffer can be written by control circuitry outside the page buffer. The control circuitry can be control logic (e.g., Figure 6 The control logic (512) can write position information to the page buffer at any time before the page buffer receives M bits of data.

[0132] The page buffer may include multiple latches, including a location latch and multiple first data latches. The location latch stores location information, and the multiple first data latches can receive and store M bits of data. The page buffer can perform logical operations based on the location information and the M bits of data to obtain state group information.

[0133] For example, the control logic can control the position latch to be reset or set, thereby storing different position information. For instance, the page buffer can be in a reset state by default to store position information 0. When using the storage method of storing M+2*N bits of data in two storage units provided in this embodiment, the control logic can control a portion of the page buffers to switch to the set state, thereby storing position information 1. Specifically, the storage units coupled to each pair of page buffers storing position information 0 and position information 1 respectively are used to jointly store M+2*N bits of data.

[0134] In some embodiments, the state group information may be stored in a second data latch, different from the location latch and the first data latch. In other embodiments, after the state group information is obtained, the location latch and the first data latch in the page buffer may be released, thereby storing the state group information in any latch of the page buffer, including the location latch and the first data latch. This disclosure does not specify the storage location of the state group information in the page buffer.

[0135] For example, the page buffer can obtain the state group information based on the location information and M-bit data in any way, and this disclosure is not limited thereto. In one embodiment, the location latch and the first data latch can be connected by a logic gate. The logic gate can be based on... Figure 11 The logical relationship between the location information, M-bit data, and state group information is determined.

[0136] The above describes the implementation process of converting M-bit data into status group information using page buffer 610 provided in this disclosure. In other embodiments, write logic circuitry can also be provided outside the page buffer. Here, the page buffer may not have a position latch and may not store position information. The write logic circuitry may be included in... Figure 6 In the page buffer / logic circuit 504 shown, a write logic circuit is coupled to a first page buffer and a second page buffer (excluding position latches) and configured to convert M-bit data into first state group information and second state group information, and send them to the first page buffer and the second page buffer respectively. For example, the write logic circuit may include logic gates that implement this conversion process. Also for example, the write logic circuit may store a first mapping table between M-bit data and the first state group information, and a second mapping table between M-bit data and the second state group information, and is configured to obtain the first state group information based on the received M-bit data and the first mapping table, and obtain the second state group information based on the received M-bit data and the second mapping table. Compared to this method, implementing the conversion process through page buffers requires less modification to existing peripheral circuitry, thus offering higher reliability and shortening the design and verification cycle.

[0137] In some embodiments, the first page buffer PB1 is configured to store first state group information and perform a first-step programming operation based on the first state group information to write the first state group information into a first storage unit. The second page buffer PB2 is configured to store second state group information and perform a first-step programming operation based on the second state group information to write the second state group information into a second storage unit.

[0138] In some embodiments, during the second programming operation phase, the first page buffer PB1 is configured to: store first state group information and receive N bits of data, and perform the second programming operation on the first memory cell based on the first state group information and the N bits of data. The second page buffer PB2 is configured to: store second state group information and receive another N bits of data, and perform the second programming operation on the second memory cell based on the second state group information and the other N bits of data.

[0139] For example, after the first programming operation, the page buffer can continue storing state group information until the second programming operation. In other examples, the page buffer can also clear the state group information after the first programming operation, and in the second programming operation, it can receive M bits of data again, or receive M bits of data and position information, and convert them to obtain state group information. In the second programming operation, the step of the page buffer receiving M bits of data and converting them to obtain state group information can be performed before receiving N bits of data.

[0140] See back Figure 8 In the second programming step, the first page buffer can store... Figure 8 The state group information and three-bit data for page 3 / page 5 / page 7 are shown. The second page buffer can store the state group information and three-bit data for page 4 / page 6 / page 8. In some embodiments, a position latch and a data latch can be used to store the two-bit Gray code state group information, and three additional data latches can be used to store either the three-bit data for page 3 / page 5 / page 7 or the three-bit data for page 4 / page 6 / page 8. As mentioned earlier, the state group information and the three-bit data determine which of the 24 states the memory cell will be programmed into. In the second programming operation, the page buffer can perform relevant steps on the memory cell based on the state group information and N-bit data.

[0141] In some embodiments, the first storage cell and the second storage cell are coupled to the same word line, and the number of first storage cells and the number of second storage cells are equal and there are multiple of each. That is, as shown in the figure... Figure 12 As shown, multiple storage units on the word line WL can be divided into a first storage unit group and a second storage unit group. The first storage unit group includes Q first storage units A, and the second storage unit group includes Q second storage units B. The i-th first storage unit in the first storage unit group and the i-th second storage unit in the second storage unit group form a pair and jointly store M+2*N bits of data, where i is any from 0 to Q.

[0142] It should be noted that multiple storage cells within each storage cell group can be arranged consecutively. For example, in Figure 2, Q first storage cells A and Q second storage cells B are arranged consecutively. In another embodiment, first storage cells A and second storage cells B can also be arranged alternately, and adjacent first and second storage cells can form a pair storing M+2*N bits of data. Of course, first storage cells A and second storage cells B can also be arranged in any other way, and this disclosure does not limit this. In practical applications, a suitable arrangement method can be adopted by comprehensively considering the design of peripheral circuits, etc.

[0143] In some embodiments, the peripheral circuitry is configured to: receive M half-pages of data, each half-page including multiple bits; transfer the multiple bits of data in each of the M half-pages to a plurality of first page buffers coupled to a plurality of first memory cells; wherein each first page buffer receives M bits of data; and transfer the multiple bits of data in each of the M half-pages to a plurality of second page buffers coupled to a plurality of second memory cells; wherein each second page buffer receives M bits of data.

[0144] One page of data includes 2Q bits, and the total number of the first storage cell A and the second storage cell B coupled to the word line WL is equal. In this embodiment, data is input in half-pages (0.5 pages), and half-page data includes Q bits.

[0145] For example, the memory controller (e.g., Figures 1 to 2b Each time the memory controller 121 shown sends half a page of data to the memory, the peripheral circuitry within the memory receives half a page of data (Q bits of data) and transfers it to the Q first page buffers PB1 coupled to the Q first memory cells A in the first memory cell group, and to the Q second page buffers PB2 coupled to the Q second memory cells B in the second memory cell group. After the memory controller inputs M half pages of data to the memory, each first page buffer PB1 will receive M bits of data, and each second page buffer PB2 will also receive M bits of data. The M bits of data received by the first page buffer PB1 coupled to the i-th first memory cell A and the second page buffer PB2 coupled to the i-th second memory cell B are the same.

[0146] In some embodiments, the peripheral circuitry is configured to simultaneously perform the first programming operation on both the first and second memory cells. That is, within the memory, programming operations are still performed in units of pages.

[0147] After the data transfer of M half-pages is completed, each of the 2Q page buffers coupled to the 2Q memory cells on the same word line receives M bits of data and converts it into the corresponding state group information of the memory cell, such as any one of 11, 01, and 00. Then, programming operations can be performed on a page-by-page basis to write the state group information in the 2Q page buffers into the corresponding 2Q memory cells.

[0148] In some embodiments, the peripheral circuitry is further configured to: receive 2*N half-pages of data; transfer multiple bits of data within each of the N half-pages to multiple first page buffers coupled to multiple first memory units; wherein each first page buffer receives N bits of data; and transfer multiple bits of data within each of the other N half-pages to multiple second page buffers coupled to multiple second memory units; wherein each second page buffer receives another N bits of data.

[0149] In this embodiment, the memory controller still transmits data to the memory in half-page units, with each half-page including Q bits of data.

[0150] For example, when the peripheral circuit continuously receives 2*N half-pages of data, it can transfer the first N half-pages to Q first-page buffers coupled to the first memory cell group, and the next N half-pages to Q second-page buffers coupled to the second memory cell group. Also for example, the peripheral circuit can alternately transfer data to the Q first-page buffers and Q second-page buffers; for instance, it can transfer the first half-page to the Q first-page buffers, the second half-page to the Q second-page buffers, the third half-page to the Q first-page buffers, and so on, alternating the data transfer until N half-pages are transferred to the Q first-page buffers and the other N half-pages are transferred to the Q second-page buffers. In other embodiments, the peripheral circuit can also transfer data to the first-page buffer group and the second-page buffer group in other orders, which is not limited in this disclosure. It is certain that each first-page buffer will receive N bits of data, and each second-page buffer will receive another N bits of data.

[0151] In some embodiments, the peripheral circuitry is configured to simultaneously perform a second programming operation on both the first and second memory cells. That is, within the memory, the second programming operation is still performed on a page-by-page basis.

[0152] This disclosure will now describe in detail one specific implementation of the solution provided herein, taking a page containing 18KB of data as an example. 18KB includes 18*1024*8 bits. In this embodiment, on the same word line WL, the number of first storage units A used to store 9KB of data is 9*1024*8, and the number of second storage units B used to store 9KB of data is also 9*1024*8. Correspondingly, the number of first page buffers is 9*1024*8, and the number of second page buffers is 9*1024*8.

[0153] See Figure 13 When the memory controller sends write data to the memory, it first provides a page programming operation command 80h to the memory. The page programming operation command 80h can be written into the memory's command register. The page programming operation command 80h indicates the start of the data load cycle, after which the memory controller can sequentially provide address information ADD and serial data Data to the memory. Address information ADD can include row address and column address. Serial data Data is half a page of data, i.e., 9KB of data, to be written to the address provided in the address information. Figure 13 In the first command sequence, ADD(page0) points to page0 and Data (9KB) of half a page to be written to page0 is provided. The second command sequence provides ADD(page1) points to page1 and Data (9KB) of half a page to be written to page1 is provided. The third command sequence provides ADD(page2) points to page2 and Data (9KB) of half a page to be written to page2 is provided.

[0154] Since the data from page0 / page1 / page2 is used to collectively determine the state group information of the memory cell, the programming operation is only performed after all the data from page0 / page1 / page2 has been sent to memory. When sending the data from page0 / page1, the 1Ah command is used to instruct the data to be transferred to the page buffer, but programming of the data from page0 / page1 is prohibited. When sending the data from page2, the 10h command is used; 10h is the programming command, indicating the start of the programming cycle. The memory will then perform a programming cycle, writing the received data from page0 / page1 / page2 into the memory cell.

[0155] See also Figure 13 Data is input from the memory pads and eventually transferred to the corresponding page buffer. Specifically, 9KB of page 0 data is transferred to the first page buffer, which contains the same number of bits as 9KB. Figure 13The 9KB first page buffer is also correspondingly transferred to the second page buffer (which contains the same number of bits as the 9KB buffer). Figure 3 (The 9KB second page buffer). The i-th first page buffer and the i-th second page buffer receive the same bit of data. Similarly, 9KB of page 1 data is transmitted to both the 9KB first page buffer and the 9KB second page buffer. 9KB of page 2 data is also transmitted to both the 9KB first page buffer and the 9KB second page buffer.

[0156] After the data transfer on page 2 is complete, each first-page buffer receives 3 bits of data, consisting of one bit from each of page 0, page 1, and page 2. Each second-page buffer also receives 3 bits of data, consisting of one bit from each of page 0, page 1, and page 2. In response to the 10h command, the memory's peripheral circuitry performs the first step of the programming operation.

[0157] During the first step of the programming operation, the first page buffer obtains first state group information represented by two Gray codes based on 3-bit data, and the first state group information is stored in the first page buffer. For example, the first page buffer can obtain the first state group information based on three-bit data in any of the embodiments described above. Similarly, the second page buffer obtains second state group information represented by two Gray codes based on 3-bit data. The first and second page buffers are configured to synchronously perform the M-bit data to state group information conversion operation.

[0158] During the first programming operation, 18*1024*8 memory cells (the same number of bits as 18KB) coupled to the same word line are programmed simultaneously, each memory cell being programmed into its corresponding intermediate state. It can be understood that, regardless of whether it's the first or second page buffer, the stored state group information is, for example, any of 11, 01, and 00. The first programming operation is to program the corresponding memory cell based on 11, 01, or 00 stored in the page buffer, without distinguishing whether the memory cell is the first or second memory cell.

[0159] In some embodiments, the first step programming operation can be performed using Incremental Step Pulse Programming (ISPP). The first step programming operation includes multiple first programming cycles, each including a programming phase and a verification phase following the programming phase. During the programming phase, the word line driver (e.g., ...) Figure 6The row decoder / WL driver 508 applies a programming voltage to the select word line and a programming pass voltage to the non-select word line. Page buffers (including a first page buffer and a second page buffer) apply bit line voltages to the bit lines coupled to the memory cells. Based on the verification result of the memory cell using the state group information, the page buffers apply high and low voltages as bit line voltages to the corresponding bit lines. For example, a high voltage is applied to the bit line coupled to a verified memory cell to disable programming; a low voltage is applied to the bit line coupled to a verified memory cell to enable programming. In some embodiments, to narrow the threshold voltage distribution and widen the read window between adjacent programming states, at least one intermediate voltage between the high and low voltages can be applied to the corresponding bit line to achieve different degrees of programming for different memory cells.

[0160] For example, during the verification phase, the word line driver applies a verification voltage to the selected word line and a programming pass voltage to the non-selected word line. The page buffer's sensing node is coupled to the bit line and pre-charged. When the sensing node and bit line are turned on, different currents are generated in the bit line according to the threshold voltage of the memory cell, causing different degrees of change in the voltage of the sensing node. The page buffer determines whether the threshold voltage distribution of the target intermediate state has been reached based on the voltage change of the sensing node. If it is determined that it has been reached, the verification is successful, and the state group information is written to the memory cell. For example, after a preset number of first programming cycles, the first step of the programming operation ends. Alternatively, the first step of the programming operation ends after it is determined that all memory cells have been verified successfully.

[0161] After the first programming operation is completed, one of the 9*1024*8 first memory cells and 9*1024*8 second memory cells coupled to the word line is selected to be in one of the three intermediate states. The first target intermediate state of the i-th first memory cell and the second target intermediate state of the i-th second memory cell can jointly determine the three bits of data received by their page buffers.

[0162] Figure 14 The command sequence for the second programming step is shown. In this second step, the memory controller sends data for pages 4, 5, 6, 7, 8, and 9 to the memory. Figure 13Similarly, when sending half a page of data, the memory controller sends a page programming operation command 80h to the memory, followed by address information ADD and serial data Data to be written to the address indicated by the address information. When sending data from page 3 to page 7, the 1Ah command instructs the memory to transfer the data to the page buffer. When sending data from page 8, the 10h command instructs the entry into the programming cycle, writing the received data from page 3 to page 7 into the memory cell.

[0163] See also Figure 14 The first command sequence provides the address information ADD(page3) to page3 and half a page of data (9KB) to be written to page3. This 9KB of page3 data is transferred to the 9KB first page buffer. The second command sequence provides the address information ADD(page4) to page4 and half a page of data (9KB) to be written to page4. This 9KB of page4 data is transferred to the 9KB second page buffer. This process repeats alternately, with 9KB of page5 and 9KB of page7 data transferred to the 9KB first page buffer, and 9KB of page6 and 9KB of page8 data transferred to the 9KB second page buffer.

[0164] After the data transfer on page 8 is complete, each first-page buffer receives 3 bits of data, consisting of one bit each from page 3, page 5, and page 7. Each second-page buffer receives 3 bits of data, consisting of one bit each from page 4, page 6, and page 8.

[0165] In some embodiments, the memory controller resends the data for pages 0 / 1 / 2 to the memory before sending the data for page 3 to the memory. For example, this can be done using... Figure 13 The command sequence shown sends data for pages 0 and 1, while in the command sequence sending page 2 data, 10h is replaced by 1Ah to prevent the first step of the programming operation from being executed again. In response to the 1Ah command, the data for pages 0, 1, and 2 is transferred to the first page buffer and the second page buffer. The first and second page buffers generate and store first and second state group information based on their respective position information and the data for pages 0, 1, and 2, respectively. Next, the memory controller sends data for pages 3 to 8 to the memory.

[0166] In other embodiments, after the first programming operation, the page buffer can also be configured to store state group information. In this case, during the second programming operation, data from pages 3 to 8 can be directly sent to the memory without resending data from pages 0 to 2. In practical applications, the state group information of the memory cells can be stored in the corresponding page buffer before the programming cycle of the second programming operation, using either of the two methods described above, in conjunction with other operations in the data access operation. For example, if the memory is configured to pause the programming operation and perform read operations during the pause, since read operations occupy the page buffer, the first method can be considered, resending data from pages 0 to 1 during the data loading cycle of the second programming operation. In other words, the first method reduces the time the page buffer is occupied and can more flexibly adapt to various access operations. The second method, on the other hand, shortens the cycle of the second programming operation.

[0167] See also Figure 14 In response to the 10h command, the memory's peripheral circuitry simultaneously programs 18*1024*8 memory cells (the same number of bits as 18KB) coupled to the same word line, programming each memory cell from its respective intermediate state to the target state. It can be understood that both the first and second page buffers store five bits of information, consisting of a two-bit Gray code state group and a three-bit Gray code data. The second programming step involves programming the corresponding memory cell based on the five bits of information stored in the page buffers, regardless of whether the memory cell is the first or second memory cell.

[0168] In some embodiments, the second programming operation can be performed using Incremental Step Pulse Programming (ISPP). For example, the second programming operation includes multiple second programming cycles, each including a programming phase and a verification phase following the programming phase. During the programming phase, word line drivers apply programming voltages to selected word lines and programming pass voltages to non-selected word lines. Page buffers (including a first page buffer and a second page buffer) apply bit line voltages to the bit lines coupled to the memory cells. The page buffers apply high and low voltages as bit line voltages to the corresponding bit lines based on the state group information of the memory cell and the verification result of the three-bit data.

[0169] For example, during the verification phase, the word line driver applies a verification voltage to the selected word line and a programming voltage to the non-selected word line. The page buffer determines whether the threshold voltage distribution of the target state has been reached based on the voltage change of the sensing node. If the threshold voltage is reached, the verification is successful, and three bits of data are written to the memory cell.

[0170] After the second programming operation is completed, select one of the 9*1024*8 (the same number of bits included in 9KB) first memory cells and 9*1024*8 second memory cells coupled to the word line to be in one of the 24 states. Among them, the i-th first memory cell is in the first target state and the i-th second memory cell is in the second target state, so as to jointly store 9 bits of data.

[0171] The solution provided in this embodiment employs a two-step programming operation. In the first programming operation, the first state group information and the second state group information are written to the first storage unit and the second storage unit, respectively, to write M bits of data. In the second programming operation, N bits of data are written to the first storage unit, and another N bits of data are written to the second storage unit. During the second programming operation, if a programming pulse is applied, the storage unit in any intermediate state can move in the direction of increasing threshold voltage, for example... Figure 9 One memory cell in intermediate state S0′ may be programmed to state S1, while another memory cell in intermediate state S8′ may be programmed to state S9. This means that memory cells in each intermediate state can be programmed simultaneously, reducing the number of programming pulses and thus shortening the time of the second programming step. The first programming step involves only three intermediate states and has a relatively short programming time. Therefore, the two-step programming method provided in this disclosure has short programming times for each step, a more balanced programming operation, and reduces the impact of the IVS effect on the programming operation.

[0172] This disclosure also provides a read operation method corresponding to the above encoding method. The memory includes a memory cell array and peripheral circuitry. The memory cell array includes multiple memory cells, each memory cell being in one state within one of multiple state groups. Every two memory cells are configured to jointly store M+2*N bits of data, where M and N are both positive integers. The peripheral circuitry is configured as follows:

[0173] Perform a state group read operation to determine the state group to which the storage cell belongs, obtain the first state group information of the first storage cell and the second state group information of the second storage cell in every two storage cells, and determine M bits of data based on the first state group information and the second state group information.

[0174] Perform a state read operation to determine the state of the storage unit within the state group, and obtain N bits of data stored in the first storage unit and another N bits of data stored in the second storage unit.

[0175] For example, the storage cell array is configured to perform any feasible programming operation, including the programming operation described in the above embodiments, so that every two storage cells jointly store M+2*N bits of data.

[0176] The following describes the reading operation method provided in the embodiments of this disclosure, taking M-bit data as three-bit data and N-bit data as three-bit data as an example.

[0177] Figure 15 A schematic diagram of the data reading operation from page 0 to page 9 is shown, as follows: Figure 15 As shown, when two memory cells jointly store 3 + 2 * 3 bits (9 bits) of data, each memory cell is programmed into one of 24 states S0 to S23. These 24 states can be divided into three state groups: SG0, SG1, and SG2. Each state group includes 8 states, and each memory cell is programmed into one state within one of these three state groups. Of the 9 bits of data jointly stored by the two memory cells, the data for pages 0, 1, and 2 is jointly determined by the respective state groups of the two memory cells; the data for pages 3, 5, and 7 is determined solely by the state of the first memory cell within its own state group; and the data for pages 4, 6, and 8 is determined solely by the state of the second memory cell within its own state group.

[0178] In this embodiment of the disclosure, during the read operation, a state group read operation is first performed to determine the state group to which the storage unit belongs, so as to obtain the first state group information of the first storage unit and the second state group information of the second storage unit, and to obtain M bits of data based on the first state group information and the second state group information. The first state group information is used to indicate the state group to which the first storage unit belongs, and the second state group information is used to indicate the state group to which the second storage unit belongs.

[0179] In some embodiments, during a state group read operation, the peripheral circuitry is configured to perform multiple read operations using multiple read voltages capable of distinguishing adjacent state groups.

[0180] The read voltage is applied to the word line common to the first and second memory cells. The number of read voltages used in a state group read operation is equal to the number of state groups minus one. For example, two read voltages can be used to distinguish three state groups, e.g., Figure 15 The first reading voltage Vrd8 is used to distinguish between state groups SG0 and SG1, and the second reading voltage Vrd16 is used to distinguish between state groups SG1 and SG2.

[0181] The read voltage used during a state group read operation can be determined based on the threshold voltage distribution of the highest state in the lower state group and the threshold voltage distribution of the lowest state in the higher state group. For example, the first read voltage Vrd8 can be determined based on the threshold voltage distribution of state S7 in state group SG0 and the threshold voltage distribution of state S8 in state group SG1. In one specific embodiment, the first read voltage Vrd8 can be located between the threshold voltage distributions of state S7 and S8. The second read voltage Vrd16 can be determined based on the threshold voltage distribution of state S16 in state group SG1 and the threshold voltage distribution of state S17 in state group SG2. In one specific embodiment, the second read voltage Vrd16 can be located between the threshold voltage distributions of state S16 and S17.

[0182] The number of read operations performed during a state group read operation is greater than or equal to the number of read voltages, meaning that each read voltage may be used once or may be used multiple times.

[0183] In some embodiments, the operation of obtaining M-bit data based on the first state group information and the second state group information does not necessarily have to be performed after the state group read operation, but can be performed during the state group read operation. For example, if the state group information is represented by multi-bit Gray code, then one bit of the M-bit data can be obtained immediately after each partial bit of the first state group information is obtained, based on the requirement of reading the M-bit data bit by bit.

[0184] Specifically, both the first state group information and the second state group information include multiple bits; the peripheral circuit is configured to perform a state group reading operation based on the requirement of reading M bits of data bit by bit; wherein, when reading any bit of the M bits of data, the peripheral circuit is configured to perform a reading operation to obtain at least one bit of the first state group information and at least one bit of the second state group information, and obtain one bit of the M bits of data based on the obtained at least one bit of the first state group information and at least one bit of the second state group information.

[0185] This embodiment uses a bit-by-bit reading method for M bits of data, which allows one bit of data to be read from the memory cell array into the page buffer and then quickly transferred from the page buffer to the I / F (e.g., ...). Figure 6By shortening the time data resides in the page buffer (I / F 516), the page buffer's footprint can be reduced, thus facilitating device miniaturization and improving read speed. It is understood that in some embodiments, the operation of obtaining M-bit data based on the first and second state group information can be performed after the state group read operation. That is, the multi-bit Gray code of the first and second state group information can be obtained first through the state group read operation before the operation to obtain the M-bit data.

[0186] In some embodiments, the peripheral circuit is configured to perform a read operation to acquire one bit from the first state group information and one bit from the second state group information, and to obtain one bit from M bits of data based on the acquired one bit from the first state group information and one bit from the second state group information. This reduces the number of read operations during the state group read operation by acquiring only one bit from the first state group and one bit from the second state group at a time, thereby improving the read speed.

[0187] In some embodiments, both the first state group information and the second state group information include two bits. If one bit from the first state group information and one bit from the second state group information are read each time, there are four combinations: the first bit of the first state group information and the first bit of the second state group information; the second bit of the first state group information and the first bit of the second state group information; the first bit of the first state group information and the second bit of the second state group information; and the second bit of the first state group information and the second bit of the second state group information. Any three of these four combinations can be used to obtain the three bits of data for page0 / page1 / page2.

[0188] In some specific embodiments, the peripheral circuit is configured to: perform a read operation on the first storage cell and the second storage cell using the first read voltage Vrd8 to obtain the value of the first bit in the first state group information and the value of the first bit in the second state group information, and perform a first logical operation on the value of the first bit in the first state group information and the value of the second bit in the second state group information to obtain the value of the first bit in the M-bit data;

[0189] A first read voltage Vrd8 is used to perform a read operation on the first storage cell to obtain the first value in the first state group information. A second read voltage Vrd16 is used to perform a read operation on the second storage cell to obtain the second value in the second state group information. A second logical operation is performed on the first value in the first state group information and the second value in the second state group information to obtain the second value in the M-bit data.

[0190] A read operation is performed on the first storage cell using the second read voltage Vrd16 to obtain the value of the second bit in the first state group information. A read operation is performed on the second storage cell using the first read voltage Vrd8 to obtain the value of the first bit in the second state group information. A third logical operation is performed on the value of the second bit in the first state group information and the value of the first bit in the second state group information to obtain the value of the third bit in the M-bit data.

[0191] First read voltage, second read voltage, first logic operation, second logic operation, and third logic operation AND Figure 7 The correspondence between the M-bit data, state groups, and state group information shown is related. Figures 16a to 16c To demonstrate based on Figure 7 The process of obtaining M bits of data by performing a state group read operation based on the shown correspondence is as follows. First, it can be understood that the correspondence between state groups and state group information is unique, regardless of whether it is the first or second storage unit. For example... Figure 7 As shown, state group SG0 corresponds to state group information 11, state group SG1 corresponds to state group information 01, and state group SG2 corresponds to state group information 00. When reading from a memory cell using the first read voltage Vre8, regardless of whether it's the first or second memory cell, if the memory cell is in states S0-S7, the read value is 1; if the memory cell is in states S8-S16 or S17-S23, the read value is 0. This is consistent with the first bit of the state group information. When reading from a memory cell using the second read voltage Vre16, if the memory cell is in states S0-S7 or S8-S15, the read value is 1; if the memory cell is in states S16-S23, the read value is 0. This is consistent with the second bit of the state group information.

[0192] It should be noted that Vrd8 is not always necessary to read the first bit of the state group information. Similarly, Vrd16 is not always necessary to read the second bit of the state group information. For example, if state group SG0 corresponds to state group information 11, state group SG1 corresponds to state group information 10, and state group SG2 corresponds to state group information 00, then Vrd16 is needed to read the first bit of the state group information, and Vrd8 is needed to read the second bit. That is, in different implementations where the state groups and two Gray codes have different correspondences, the first and second reading voltages are not fixed, but can be determined based on this correspondence.

[0193] For example, corresponding to Figure 7 The correspondence shown uses an OR operation as the first logical operator. See also... Figure 16aThe first to third columns of the table show the eight possible values ​​for page0 / page1 / page2. The fourth and fifth columns show the state groups to which the first 9KB cell and the second 9KB cell are programmed, respectively, based on these eight values. The sixth and seventh columns show the values ​​read from the first and second 9KB cells in different state groups when the first and second 9KB cells are read using the first read voltage Vrd8, respectively. The eighth column shows the result of an OR operation on the values ​​in the sixth and seventh columns.

[0194] The following is based on Figure 16a Taking the data 110 in pages 0 / 1 / 2 as an example, we will analyze the process of obtaining the first bit of M-bit data by performing an OR operation on the first bit of the first state group information and the first bit of the second state group information. The data 110 in pages 0 / 1 / 2 indicates that the first storage unit is programmed to the SG0 state group, and the information in the first state group is 11. The second storage unit is programmed to the SG1 state group, and the information in the second state group is 01. In the state group read operation, the first storage unit is read using the first read voltage Vrd8. The threshold voltage of the first storage unit in the SG0 state group is less than Vrd8, so the first storage unit is turned on, thus outputting a value of 1, consistent with the first bit of the first state group information. The second storage unit is read using the first read voltage Vrd8. The threshold voltage of the first storage unit in the SG1 state group is greater than Vrd8, so the second storage unit is turned off, thus outputting a value of 0, consistent with the first bit of the second state group information. The result of the OR operation is 1, consistent with the value of page 0. For the analysis of cases where the data in pages 0 / 1 / 2 have other values, please refer to [link to relevant documentation]. Figure 16a ,based on Figure 16a Can.

[0195] In some embodiments, corresponding to Figure 8 The correspondence shown is such that the second logical operation is an XNOR operation. See also... Figure 16b , Figure 16b and Figure 16a The first six columns are identical. The sixth column shows the values ​​read from the first memory cell when it is in different state groups when read using the first read voltage Vrd8. Figure 16b The seventh column shows the value read from the second memory cell in different state groups when the second memory cell is read using the second read voltage Vrd16, and the eighth column shows the result of the XOR operation on the values ​​in the sixth and seventh columns.

[0196] The following is still based on Figure 16bTaking the data 110 in pages 0 / 1 / 2 as an example, let's analyze the process of obtaining the second bit of M-bit data by performing an XOR operation on the first bit of the first state group information and the second bit of the second state group information. The first storage cell is read using the first read voltage Vrd8; if the first storage cell is turned on, the output value is 1. The second storage cell is read using the second read voltage Vrd16; if the second storage cell is turned on, the output value is 1, consistent with the second bit of the second state group information. The result of the XOR operation is 1, consistent with the value of page 1. For the analysis of cases where the data in pages 0 / 1 / 2 has other values, please refer to [link to analysis]. Figure 16b .

[0197] In some embodiments, corresponding to Figure 7 The correspondence shown is such that the third logical operation is an XNOR operation. See also... Figure 16c , Figure 16c and Figure 16a The first five columns are the same. Figure 16c The sixth column shows the value read from the first memory cell when it is in a different state group when the first memory cell is read using the second read voltage Vrd16. The seventh column shows the value read from the second memory cell when it is in a different state group when the second memory cell is read using the first read voltage Vrd8. The eighth column shows the result of the XOR operation on the values ​​in the sixth and seventh columns.

[0198] The following is still based on Figure 16c Taking the data 110 in pages 0 / 1 / 2 as an example, let's analyze the process of obtaining the third bit of M-bit data by performing an XOR operation on the second bit of the first state group information and the first bit of the second state group information. The first memory cell is read using the second read voltage Vrd16; if the first memory cell is on, the output value is 1. The second memory cell is read using the first read voltage Vrd8; if the second memory cell is off, the output value is 0. The result of the XOR operation is 0, consistent with the value of page 2. For analysis of cases where the data in pages 0 / 1 / 2 has other values, please refer to [link to analysis]. Figure 16c .

[0199] like Figures 16a to 16c As shown, logical operations based on the first and second state group information can yield each bit of the M-bit data. It should be noted that when the correspondence between the state group information and the M-bit data is different... Figure 7 In this case, the first, second, and third logical operations may differ from the above embodiments, but it is certain that the logical operations can be determined based on the correspondence between the state group information and the M data.

[0200] In some embodiments, such as Figure 17As shown, the peripheral circuit includes: a first page buffer PB1, a second page buffer PB2, and a read logic circuit 620. The first page buffer PB1 is coupled to the first memory cell A and configured to acquire first state group information during the state group read operation phase. The second page buffer PB2 is coupled to the second memory cell B and configured to acquire second state group information during the state group operation phase. The read logic circuit 620 is coupled to the first page buffer PB1 and the second page buffer PB2 and configured to obtain M bits of data based on the first and second state group information.

[0201] For example, the first page buffer PB1 and the second page buffer PB2 are two of a plurality of page buffers 610. The page buffers 610 can perform the same sensing operations as in read operations of single-level and multi-level memory cells to obtain state group information. In this embodiment, a read logic circuit 620 is provided outside the page buffers 610. This read logic circuit can perform logical operations to obtain M bits of data. The addition of the read logic circuit requires minimal modification to the existing circuitry; it merely adds some logic circuitry without altering the overall architecture, thus shortening the design and verification cycle and improving memory reliability.

[0202] In some embodiments, when performing the above Figures 16a to 16c During the status group read operation shown, the peripheral circuitry is configured as follows:

[0203] A first read voltage is used to perform a read operation on the first storage unit and the second storage unit; wherein, the first page buffer PB1 obtains the value of the first bit in the first state group information, the second page buffer PB1 obtains the value of the first bit in the second state group information, and the read logic circuit 620 performs a first logic operation on the value of the first bit in the first state group information and the value of the second bit in the second state group information to obtain the value of the first bit in the M-bit data;

[0204] A first read voltage is used to perform a read operation on the first memory cell, and a second read voltage is used to perform a read operation on the second memory cell; wherein, the first page buffer PB1 obtains the first bit value in the first state group information, the second page buffer PB2 obtains the second bit value in the second state group information, and the read logic circuit 620 performs a second logic operation on the first bit value in the first state group information and the second bit value in the second state group information to obtain the second bit value in the M-bit data;

[0205] The first memory cell is read using the second read voltage, and the second memory cell is read using the first read voltage. The first page buffer PB1 obtains the value of the second bit in the first state group information, the second page buffer PB2 obtains the value of the first bit in the second state group information, and the read logic circuit 620 performs a third logic operation on the value of the second bit in the first state group information and the value of the first bit in the second state group information to obtain the value of the third bit in the M-bit data.

[0206] For example, the first logical operation is an OR operation, the second logical operation is an XNOR operation, and the third logical operation is an XNOR operation. This disclosure does not limit the specific circuit structure of the read logic circuit 620, and any read logic circuit that can implement the above logical operations is within the protection scope of this disclosure.

[0207] Figure 18 The command sequence for the read operation phase of the status group is shown. When the memory controller reads data from the memory, it first sends a read operation command 00h to the memory. The read operation command 00h can be written into the memory's command register. Afterward, the memory controller can send address information ADD and the 30h command to the memory. The address information can be written into the memory's address register. The 30h command instructs the memory to perform a data read operation.

[0208] In some embodiments, the memory controller supports reading data in half-page units, meaning the memory can output data in half-page units. However, the memory is not required to output data in half-page units; it can choose to output data in half-page units or in page units. Nevertheless, read operations within the memory are still performed in page units.

[0209] For example, a page is 18KB, and word lines are coupled to 18*1024*8 (the same number of bits as 18KB) memory units. These 18*1024*8 memory units can be divided into 9*1024*8 (the same number of bits as 9KB) first memory units and 9*1024*8 second memory units. The i-th first memory unit and the i-th second memory unit, with the same number, jointly store 3 + 2*3 bits (9 bits) of data. A word line-coupled memory unit stores 9 half-pages of data, each half-page containing 9KB of data.

[0210] In this embodiment, as Figure 17As shown, the first command sequence provides address information ADD(page0) pointing to page0, and the second command sequence provides address information ADD(page1 / 2) pointing to pages1 and 2. That is, in response to a read command to read page0, the memory outputs half a page of data; in response to a read command to read page1 / page2, the memory simultaneously outputs the data for page1 / page2, i.e., one page of data. Optionally, in other embodiments, the memory controller can send read commands for page1 and page2 separately, and the memory will output the data for page1 and page2 separately in response.

[0211] See also Figure 17 In response to a read command to read page0 data, the peripheral circuit applies a first read voltage Vrd8 to the select word line. Each page buffer performs a sensing operation to obtain the first bit of the status group information of the coupled memory cell. The read logic circuit can perform an OR operation on the first bit of the status group information stored in the coupled first page buffer and the first bit of the status group information stored in the second page buffer to obtain half a page of data for page0.

[0212] In response to the read command to read page1 / page2 data, the peripheral circuit sequentially applies the first read voltage Vrd8 and the second read voltage Vrd16 to the select word line. Each page buffer performs two sensing operations to obtain the first and second bits of the status group information of the coupled memory cell. However, the read logic circuit only performs an XOR operation on the first bit of the status group information stored in the first page buffer and the second bit of the status group information stored in the second page buffer to obtain half a page of page1 data.

[0213] The peripheral circuit applies the first read voltage Vrd8 and the second read voltage Vrd16 to the select word line again. Each page buffer performs two sensing operations to obtain the first and second bits of the status group information of the coupled memory cell. However, the read logic circuit only performs an XOR operation on the second bit of the status group information stored in the first page buffer and the first bit of the status group information stored in the second page buffer to obtain half a page of data for page 2.

[0214] For example, the memory outputs data to the memory controller in half-page units.

[0215] This disclosure does not limit the specific wiring connections between the read logic circuit and the first page buffer and the second page buffer. Any wiring connection that meets the functional requirements of the read logic circuit described above is within the scope of protection of this disclosure.

[0216] In summary, in the state group read operation provided by this disclosure, each page buffer obtains the data of page0 / page1 / page2 through 5 sensing operations (1+2+2). The number of sensing operations is small, which can improve the read speed.

[0217] After completing the state group read operation, the memory performs a state read operation. In some embodiments, during the state read operation, the peripheral circuitry is configured to use multiple read voltages to distinguish adjacent states within a state group. For example, read voltages already used during the state group read operation are not used during the state read operation, which reduces the number of read operations and improves read speed.

[0218] In some embodiments, during the state read operation phase, the peripheral circuitry is configured as follows:

[0219] Perform N read operations, each read operation using multiple read voltages that can determine one bit of N bits of data, so as to obtain the value of one bit of N bits of data stored in the first storage cell and the value of one bit of another N bits of data stored in the second storage cell in each read operation; wherein, each read voltage is determined based on the threshold voltage distribution of two adjacent states.

[0220] Here, performing N read operations means that the memory controller sends N read commands to the memory, and the memory responds to these N read commands by performing N read operations. Since the threshold voltage distributions corresponding to the multiple states of the first and second memory cells are the same, the read voltage used in the N read operations can be considered to be determined based on the multiple states of the first memory cell, or it can be considered to be determined based on the multiple states of the second memory cell.

[0221] In this disclosure, during each read operation, one bit of the N bits of data stored in the first storage unit and one bit of the other N bits of data stored in the second storage unit are read out. That is, the first storage unit and the second storage unit perform read operations synchronously, which can reduce the number of reads and improve the read speed.

[0222] In some embodiments, both the N-bit data and the additional N-bit data are three-bit data, and each of the multiple state groups includes eight states; the peripheral circuitry is configured as follows:

[0223] In the first read operation, seven read voltages are used to determine the value of the first bit in the N bits of data stored in the first memory cell and the value of the first bit in the other N bits of data stored in the second memory cell.

[0224] In the second read operation, seven read voltages are used to determine the value of the second bit in the N-bit data stored in the first memory cell and the value of the second bit in the other N-bit data stored in the second memory cell;

[0225] In the third read operation, seven read voltages are used to determine the value of the third bit in the N-bit data stored in the first memory cell and the value of the third bit in the other N-bit data stored in the second memory cell.

[0226] When the state group has three digits, and each group contains eight states, each memory unit can be programmed to one of 24 states. (See also: [link to previous page]) Figure 15 To distinguish the 24 states, at least 23 read voltages are required. Since two read voltages have already been used to distinguish state groups in the state group read operation, the remaining 21 voltages are needed to distinguish different states in the state read operation.

[0227] This embodiment proposes that, in each read operation, seven read voltages are used to read one bit from the first memory cell and one bit from the second memory cell. This makes the time of each read operation close, which is beneficial for controlling the timing of the read operations, thereby improving the speed at which all data is read and improving read performance.

[0228] In some embodiments, the multiple state groups include a first state group, a second state group, and a third state group. The first state group includes states one through eight, the second state group includes states nine through sixteen, and the third state group includes states seventeen through twenty-four.

[0229] The seven read voltages used in the first read operation are: the third read voltage that distinguishes between the first and second states, the fourth read voltage that distinguishes between the fifth and sixth states, the fifth read voltage that distinguishes between the tenth and eleventh states, the sixth read voltage that distinguishes between the twelfth and thirteenth states, the seventh read voltage that distinguishes between the fourteenth and fifteenth states, the eighth read voltage that distinguishes between the seventeenth and eighteenth states, and the ninth read voltage that distinguishes between the twenty-first and twenty-second states.

[0230] The seven read voltages used in the second read operation are: the tenth read voltage that distinguishes between the second and third states, the eleventh read voltage that distinguishes between the fourth and fifth states, the twelfth read voltage that distinguishes between the sixth and seventh states, the thirteenth read voltage that distinguishes between the ninth and tenth states, the fourteenth read voltage that distinguishes between the thirteenth and fourteenth states, the fifteenth read voltage that distinguishes between the nineteenth and twentieth states, and the sixteenth read voltage that distinguishes between the twenty-third and twenty-fourth states.

[0231] The seven reading voltages used in the third reading operation are: the seventeenth reading voltage between the third and fourth states, the eighteenth reading voltage between the seventh and eighth states, the nineteenth reading voltage between the eleventh and twelfth states, the twentieth reading voltage between the fifteenth and sixteenth states, the twenty-first reading voltage between the eighteenth and nineteenth states, the twenty-second reading voltage between the twentieth and twenty-first states, and the twenty-third reading voltage between the twenty-second and twenty-third states.

[0232] Figure 19 This is a schematic diagram illustrating the state reading operation provided in an embodiment of this disclosure. The following is in conjunction with... Figure 15 and Figure 19 The analysis is as follows: The first state group is state group SG0, which includes states S0 to S7. The second state group is state group SG1, which includes states S8 to S15. The third state group is state group SG2, which includes states S16 to S23.

[0233] Figure 19 The diagram shows the correspondence between the N-bit data and the multiple states within each state group. Figure 15 Same. For example... Figure 15 and Figure 19 As shown, in the first read operation of the status read operation, the following voltages are sequentially applied to the select word line: a third read voltage Vrd1 to distinguish between the first and second states, a fourth read voltage Vrd5 to distinguish between the fifth and sixth states, a fifth read voltage Vrd10 to distinguish between the tenth and eleventh states, a sixth read voltage Vrd12 to distinguish between the twelfth and thirteenth states, a seventh read voltage Vrd14 to distinguish between the fourteenth and fifteenth states, an eighth read voltage Vrd17 to distinguish between the seventeenth and eighteenth states, and a ninth read voltage Vrd21 to distinguish between the twenty-first and twenty-second states.

[0234] After each read voltage is applied to the select word line, the page buffers corresponding to the 18K memory cells coupled to the select word line perform a sensing operation to sense the level change on the bit line. After applying 7 read voltages to the select word line, the page buffers perform 7 sensing operations, reading the first bit in the corresponding memory cell. Specifically, the first page buffer coupled to the first memory cell reads the first bit in the first memory cell, and the second page buffer coupled to the second memory cell reads the first bit in the second memory cell. Through the first read operation, the first bit of 9*1024*8 first memory cells can be read to obtain half a page of data (9KB) for page 3, and the first bit of 9*1024*8 second memory cells can also be read to obtain half a page of data for page 4. For example, the memory can output only half a page of data each time. Also for example, the memory can output one page of data at a time, treating the data of page 3 and page 4 as one page of data each time.

[0235] See also Figure 15 and Figure 19 In the second read operation, the following voltages are sequentially applied to the select word line: the tenth read voltage Vrd2 to distinguish between the second and third states, the eleventh read voltage Vrd4 to distinguish between the fourth and fifth states, the twelfth read voltage Vrd6 to distinguish between the sixth and seventh states, the thirteenth read voltage Vrd9 to distinguish between the ninth and tenth states, the fourteenth read voltage Vrd13 to distinguish between the thirteenth and fourteenth states, the fifteenth read voltage Vrd19 to distinguish between the nineteenth and twentieth states, and the sixteenth read voltage Vrd23 to distinguish between the twenty-third and twenty-fourth states.

[0236] When the aforementioned seven read voltages are sequentially applied to the select word line, the page buffers corresponding to the 18*1024*8 memory cells coupled to the select word line perform seven sensing operations, reading the second bit in the corresponding memory cell. Specifically, the first page buffer coupled to the first memory cell reads the second bit in the first memory cell, and the second page buffer coupled to the second memory cell reads the second bit in the second memory cell. Through the second read operation, the second bits of 9*1024*8 first memory cells can be read to obtain half a page of data (9KB) for page 5, and the second bits of 9*1024*8 second memory cells can also be read to obtain half a page of data for page 6.

[0237] In the third read operation, the following voltages are sequentially applied to the select word line: the seventeenth read voltage Vrd3 (to distinguish between the third and fourth states), the eighteenth read voltage Vrd7 (to distinguish between the seventh and eighth states), the nineteenth read voltage Vrd11 (to distinguish between the eleventh and twelfth states), the twentieth read voltage Vrd15 (to distinguish between the fifteenth and sixteenth states), the twenty-first read voltage Vrd18 (to distinguish between the eighteenth and nineteenth states), the twenty-second read voltage Vrd20 (to distinguish between the twentieth and twenty-first states), and the twenty-third read voltage Vrd22 (to distinguish between the twenty-second and twenty-third states).

[0238] When the aforementioned seven read voltages are sequentially applied to the select word line, the page buffers corresponding to the 18K memory cells coupled to the select word line perform seven sensing operations, reading the third bit in the corresponding memory cell. Specifically, the first page buffer coupled to the first memory cell reads the third bit in the first memory cell, and the second page buffer coupled to the second memory cell reads the third bit in the second memory cell. Through the second read operation, the third bits of 9*1024*8 first memory cells can be read, obtaining half a page of data (9KB) for page 7, and the third bits of 9*1024*8 second memory cells can also be read, obtaining half a page of data for page 8.

[0239] like Figure 19 As shown in this disclosure, the values ​​corresponding to states S7 and S8 are the same, and the values ​​corresponding to states S15 and S16 are the same. In this way, when performing state group reading operations, states S7 and S8, as well as states S15 and S16, can be distinguished, so that it is not necessary to distinguish them in the state reading operation. This can reduce the number of sensing operations in the state reading operation and help to shorten the reading time.

[0240] In summary, this disclosure allows for the acquisition of data for pages 0, 1, and 2 through 5 sensing operations (1+2+2), and data for pages 3 to 8 through 21 sensing operations (7+7+7). In total, 26 sensing operations are required to acquire data for nine and a half pages (pages 0 to 8). The fewer sensing operations result in shorter reading time and faster reading speed. Furthermore, as... Figure 19 As shown, during the state read operation, the number of read voltages within each state group is relatively balanced during each read operation. For example, during the first read operation, the number of read voltages in the three state groups SG0 to SG2 are 2, 3, and 2 respectively; while during the second read operation, it is 3, 2, and 2; and during the third read operation, it is 2, 2, and 3. In other words, the encoding method of N-bit data and multiple states within each state group provided in this embodiment is beneficial for achieving balanced memory reads.

[0241] Figure 20 The command sequence for the status read operation phase is shown. Figure 18 Similarly, the memory controller sequentially sends a read command sequence 00h, address information, and 30h to the memory to control the memory to read data from the address indicated by the address information. The first command sequence provides the address information pointing to page 3 / page 4, and the memory responds to the first command sequence by executing... Figure 15 and Figure 19 The first read operation shown obtains the data for page 3 and page 4 by sequentially applying read voltages Vrd1, Vrd5, Vrd10, Vrd12, Vrd14, Vrd17 and Vrd21 to the select word line, and can output values ​​to the memory controller in half-page or full-page units.

[0242] The second command sequence provides the address information pointing to page 5 / page 6. The memory responds to the first command sequence by executing... Figure 15 and Figure 19 The second read operation shown obtains the data for page 5 and page 6 by sequentially applying read voltages Vrd2, Vrd4, Vrd6, Vrd9, Vrd13, Vrd19 and Vrd23 to the select word line, and can output values ​​to the memory controller in half-page or full-page units.

[0243] The third command sequence provides the address information pointing to page 7 / page 8. The memory responds to the first command sequence by executing... Figure 15 and Figure 19 The second read operation shown obtains the data for page 7 and page 8 by sequentially applying read voltages Vrd3, Vrd7, Vrd11, Vrd15, Vrd18, Vrd20 and Vrd22 to the select word line, and can output values ​​to the memory controller in half-page or one-page units.

[0244] This disclosure also provides another embodiment, Figure 21 This is the second correspondence between the state group combination of the two storage units and the 3-bit data provided in this embodiment of the disclosure. Figure 22 This discloses the correspondence between N-bit data and multiple states within each state group, as provided in the embodiments of this disclosure. Figure 23 For based on Figure 22 The diagram illustrates the corresponding relationship between the read operation methods.

[0245] In this embodiment, although the correspondence between state group combinations and M-bit data is different Figure 7Furthermore, the correspondence between N bits of data and multiple states within each state group differs from that between the two states. Figure 8 However, when writing data, the two-step programming operation provided in the above embodiments of this disclosure can still be performed. When reading data, the state group reading operation and the state reading operation can still be performed. The state group reading operation can be performed in the manner of 1+2+2 sensing operation, but the order of the reading voltage applied in the state reading operation may be different.

[0246] like Figure 22 and Figure 23 As shown, the status group read operation can be performed using the same method as... Figure 15 The same steps are followed in the illustrated embodiment. However, during the state readout operation, the timing order of the readout voltages differs because the correspondence between the N-bit data and the multiple states within each state group is not synchronized. For example... Figure 22 As shown, during the first read operation, the following voltages can be applied sequentially to the select word line: Vrd4 to distinguish between states S3 and S4, Vrd9 to distinguish between states S8 and S9, Vrd11 to distinguish between states S10 and S11, Vrd13 to distinguish between states S12 and S13, Vrd15 to distinguish between states S14 and S15, Vrd19 to distinguish between states S18 and S19, and Vrd23 to distinguish between states S22 and S23.

[0247] When the above 7 read voltages are applied sequentially to the select word line, the page buffer corresponding to the 18K memory cells coupled to the select word line performs 7 sensing operations, reads the first bit in the corresponding memory cell, and obtains half page data (9KB) of page3 and half page data of page4.

[0248] During the second read operation, the following voltages can be applied sequentially to the select word line: Vrd2 to distinguish between states S1 and S2, Vrd6 to distinguish between states S5 and S6, Vrd110 to distinguish between states S9 and S10, Vrd14 to distinguish between states S13 and S14, Vrd18 to distinguish between states S17 and S18, Vrd20 to distinguish between states S19 and S20, and Vrd22 to distinguish between states S21 and S22.

[0249] When the above 7 read voltages are applied sequentially to the select word line, the page buffer corresponding to the 18K memory cells coupled to the select word line performs 7 sensing operations, reads the first bit in the corresponding memory cell, and obtains half page data (9KB) of page 5 and half page data of page 6.

[0250] During the third read operation, the following read voltages can be applied sequentially to the select word line: Vrd1 to distinguish between states S0 and S1, Vrd3 to distinguish between states S2 and S3, Vrd5 to distinguish between states S4 and S5, Vrd7 to distinguish between states S6 and S7, Vrd12 to distinguish between states S11 and S12, Vrd17 to distinguish between states S16 and S17, and Vrd21 to distinguish between states S20 and S21.

[0251] When the above 7 read voltages are applied sequentially to the select word line, the page buffer corresponding to the 18K memory cells coupled to the select word line performs 7 sensing operations, reads the first bit in the corresponding memory cell, and obtains half page data of page 7 and half page data of page 8.

[0252] In this embodiment, during the first read operation, the number of read voltages in the three state groups SG0 to SG2 are 1, 4, and 2 respectively; the second read operation is 2, 2, and 3; and the third read operation is 4, 1, and 2. This also allows reading data from pages 3 to 8, but compared to... Figure 19 The illustrated embodiment is more conducive to memory read balance, resulting in better memory read performance. Additionally, Figure 19 and Figure 22 The embodiments shown can obtain data from page 0 to page 9 through 26 sensing operations, which is a small number of sensing operations and a fast reading speed.

[0253] This disclosure also provides a memory system including a memory and a memory controller. The memory can be the memory shown in any of the above embodiments. The memory controller is coupled to the memory and configured to control the memory to perform write and read operations. For example, the memory system can... Figures 1 to 2b Any of the memory systems shown.

[0254] This disclosure provides a method for operating a memory. Figure 24 Illustration of the operation method provided in the embodiments of this disclosure Figure 1 ,like Figure 24 As shown, the operation method includes:

[0255] S100: During the write operation stage of writing M+2*N bits of data into the first storage unit and the second storage unit, the first state group information and the second state group information are obtained based on the received M bits of data. The first state group information indicates that the first storage unit will be programmed into the first target state group among multiple state groups, and the second state group information indicates that the second storage unit will be programmed into the second target state group among multiple state groups.

[0256] S200: During the write operation phase, a programming operation is performed to program the first storage unit to the first target state within the first target state group based on the first state group information and the received N bits of data, and to program the second storage unit to the second target state within the second target state group based on the second state group information and the received additional N bits of data.

[0257] In some embodiments, step S200 specifically includes:

[0258] Perform the first programming operation to program the first storage unit to the first target intermediate state corresponding to the first target state group based on the first state group information, and program the second storage unit to the second target intermediate state corresponding to the second target state group based on the second state group information;

[0259] Perform the second programming operation to program the first storage unit from the first target intermediate state to the first target state based on N bits of data, and program the second storage unit from the second target intermediate state to the second target state based on another N bits of data.

[0260] In some embodiments, the peripheral circuitry includes a plurality of page buffers coupled to the memory cell array. Step S100 specifically includes:

[0261] The first page buffer, which is coupled to the first storage unit among multiple page buffers, obtains the first state group information based on the stored first location information and the received M-bit data; the second page buffer, which is coupled to the second storage unit among multiple page buffers, obtains the second state group information based on the stored second location information and the received M-bit data.

[0262] In some embodiments, performing the second programming operation includes:

[0263] The first page buffer stores the first state group information and receives N bits of data. Based on the first state group information and the N bits of data, it performs the second step of programming operation on the first memory cell. The second page buffer stores the second state group information and receives another N bits of data. Based on the second state group information and the other N bits of data, it performs the second step of programming operation on the second memory cell.

[0264] In some embodiments, the first storage cell and the second storage cell are coupled to the same word line, and the number of the first storage cell and the second storage cell are equal and there are multiple of each; the operation method further includes:

[0265] Receive M half-pages of data, each half-page containing multiple bits;

[0266] The data bits within each of the M half-pages are transferred to multiple first-page buffers coupled to multiple first-memory units; wherein each first-page buffer receives M bits of data.

[0267] The data bits within each of the M half-pages are transferred to multiple second-page buffers coupled to multiple second-memory units; each second-page buffer receives M bits of data.

[0268] In some embodiments, the method of operation further includes:

[0269] Receive 2*N half-pages of data;

[0270] The data bits within each of the N half-pages are transferred to multiple first-page buffers coupled to multiple first-memory units; each first-page buffer receives N bits of data.

[0271] The data bits within each of the other N half-pages are transferred to multiple second-page buffers coupled to multiple second-memory units; each second-page buffer receives the other N data bits.

[0272] This disclosure also provides a method for operating a memory. Figure 25 A second schematic diagram illustrating the operation method provided in this embodiment of the disclosure is shown below. Figure 25 As shown, the memory includes multiple storage cells, each storage cell being in one state within one of multiple state groups. Every two storage cells are configured to jointly store M+2*N bits of data, where M and N are both positive integers; as... Figure 25 As shown, the operation method includes:

[0273] S300: Perform a state group read operation to determine the state group to which the storage cell belongs, obtain the first state group information of the first storage cell and the second state group information of the second storage cell in every two storage cells, and determine M bits of data based on the first state group information and the second state group information.

[0274] S400: Perform a state read operation to determine the state of the storage cell within its state group, and obtain the N bits of data stored in the first storage cell and the other N bits of data stored in the second storage cell.

[0275] In some embodiments, both the first state group information and the second state group information include multiple bits; step S300 specifically includes:

[0276] The state group reading operation is performed based on the requirement of reading M bits of data bit by bit. When reading any bit of the M bits of data, a reading operation is performed to obtain at least one bit of the information in the first state group and at least one bit of the information in the second state group. Based on the obtained at least one bit of the information in the first state group and at least one bit of the information in the second state group, one bit of the M bits of data is obtained.

[0277] In some embodiments, the peripheral circuitry includes: a first page buffer coupled to a first memory cell, a second page buffer coupled to a second memory cell, and read logic circuitry coupled to the first page buffer and the second page buffer; step S300 specifically includes:

[0278] The first page buffer acquires the first state group information, the second page buffer acquires the second state group information, and the reading logic circuit obtains M bits of data based on the first and second state group information.

[0279] In some embodiments, step S400 specifically includes:

[0280] Perform N read operations, each read operation using multiple read voltages that can determine one bit of N bits of data, so as to obtain the value of one bit of N bits of data stored in the first storage cell and the value of one bit of another N bits of data stored in the second storage cell in each read operation; wherein, each read voltage is determined based on the threshold voltage distribution of two adjacent states.

[0281] In some embodiments, both the N-bit data and the additional N-bit data are three-bit data, and each of the multiple state groups includes eight states; the step performs N read operations, each read operation using multiple read voltages capable of determining one bit of the N-bit data, to obtain the value of one bit of the N-bit data stored in the first storage cell and the value of one bit of the additional N-bit data stored in the second storage cell in each read operation, specifically including:

[0282] In the first read operation, seven read voltages are used to determine the value of the first bit in the N bits of data stored in the first memory cell and the value of the first bit in the other N bits of data stored in the second memory cell.

[0283] In the second read operation, seven read voltages are used to determine the value of the second bit in the N-bit data stored in the first memory cell and the value of the second bit in the other N-bit data stored in the second memory cell;

[0284] In the third read operation, seven read voltages are used to determine the value of the third bit in the N-bit data stored in the first memory cell and the value of the third bit in the other N-bit data stored in the second memory cell.

[0285] The memory and its operation method, as well as the memory system provided in this disclosure, can store 9 bits of data in two memory units, which improves storage density compared to QLC; compared to PLC, the read window requirement is smaller, reducing the difficulty of the process and improving feasibility. Furthermore, from a circuit perspective, only a position latch and read logic circuit are added; these minor circuit modifications do not require changes to the overall architecture, thus resulting in a short design and verification cycle and high reliability.

[0286] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0287] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0288] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory, characterized in that, include: Storage cell array; The peripheral circuitry, coupled to the memory cell array, is configured to perform a write operation that writes M+2*N bits of data into the first and second memory cells, where M and N are both positive integers; wherein, during the write operation phase, the peripheral circuitry is configured as follows: Based on the received M-bit data, first state group information and second state group information are obtained. The first state group information indicates that the first storage unit will be programmed into a first target state group among multiple state groups, and the second state group information indicates that the second storage unit will be programmed into a second target state group among the multiple state groups. Perform programming operations to program the first storage unit to a first target state within the first target state group based on the first state group information and the received N bits of data, and to program the second storage unit to a second target state within the second target state group based on the second state group information and the received additional N bits of data.

2. The memory according to claim 1, characterized in that, The programming operation includes a first programming operation and a second programming operation; the peripheral circuit is configured as follows: Perform the first programming operation to program the first storage unit to the first target intermediate state corresponding to the first target state group based on the first state group information, and program the second storage unit to the second target intermediate state corresponding to the second target state group based on the second state group information; Perform a second programming operation to program the first storage unit from the first target intermediate state to the first target state based on the N-bit data, and to program the second storage unit from the second target intermediate state to the second target state based on the additional N-bit data.

3. The memory according to claim 1 or 2, characterized in that, The M-bit data is a three-bit data, and the number of state groups is three; Correspondingly, both the first state group information and the second state group information include two bits.

4. The memory according to claim 1 or 2, characterized in that, The N-bit data is three-bit data, and each of the multiple state groups includes eight states; The first target state is one of eight states within the first target state group; The second target state is one of the eight states within the second target state group.

5. The memory according to claim 2, characterized in that, The peripheral circuitry includes: a plurality of page buffers coupled to the memory cell array; among the plurality of page buffers... The first page buffer coupled to the first storage unit is configured to: obtain the first state group information based on the stored first location information and the received M-bit data; The second page buffer coupled to the second storage unit is configured to obtain the second state group information based on the stored second location information and the received M-bit data.

6. The memory according to claim 5, characterized in that, In the second step of the programming operation phase The first page buffer is configured to: store the first state group information and receive the N-bit data, and perform the second step programming operation on the first storage unit based on the first state group information and the N-bit data; The second page buffer is configured to: store the second state group information and receive the additional N bits of data, and perform the second step programming operation on the second storage unit based on the second state group information and the additional N bits of data.

7. The memory according to claim 5, characterized in that, The first storage cell and the second storage cell are coupled to the same word line, and the number of the first storage cell and the second storage cell are equal and there are multiple of each; The peripheral circuit is also configured to: Receive M half-pages of data, each half-page containing multiple bits; The multiple bits of data in each of the M half-pages are transmitted to multiple first page buffers coupled to multiple first storage units; wherein each first page buffer receives the M bits of data. The multiple bits of data in each of the M half-pages are transmitted to multiple second page buffers coupled to multiple second storage units; wherein each second page buffer receives the M bits of data.

8. The memory according to claim 7, characterized in that, The peripheral circuit is also configured to: Receive 2*N half-pages of data; The data bits within each of the N half-pages are transmitted to the plurality of first page buffers coupled to the plurality of first storage units; wherein each first page buffer receives the N bits of data. The data bits in each of the other N half-pages are transferred to the other N second page buffers coupled to the other N second storage units; wherein each second page buffer receives the other N data bits.

9. A memory, characterized in that, include: A storage cell array includes multiple storage cells, each of which is in a state within a state group of multiple state groups, and every two of the storage cells are configured to jointly store M+2*N bits of data, where M and N are both positive integers. The peripheral circuitry, coupled to the memory cell array, is configured as follows: A state group read operation is performed to determine the state group to which the storage unit belongs, thereby obtaining the first state group information of the first storage unit and the second state group information of the second storage unit in every two storage units, and determining M bits of data based on the first state group information and the second state group information. A state read operation is performed to determine the state of the storage unit within its state group, thereby obtaining N bits of data stored in the first storage unit and another N bits of data stored in the second storage unit.

10. The memory according to claim 9, characterized in that, The M-bit data is three-bit data, and the number of state groups is three; Both the first state group information and the second state group information include two bits.

11. The memory according to claim 9, characterized in that, Both the first state group information and the second state group information include multiple bits; the peripheral circuit is configured to perform the state group reading operation based on the requirement of reading the M bits of data bit by bit; wherein, when reading any bit of the M bits of data, the peripheral circuit is configured to: Perform a read operation to obtain at least one bit from the first state group information and at least one bit from the second state group information, and obtain one bit from the M-bit data based on the obtained at least one bit from the first state group information and at least one bit from the second state group information.

12. The memory according to claim 9 or 11, characterized in that, The peripheral circuit includes: The first page buffer, coupled to the first storage unit, is configured to: acquire the first state group information during the state group read operation phase; The second page buffer, coupled to the second storage unit, is configured to: acquire the second state group information during the execution of the state group operation phase; The read logic circuit, coupled to the first page buffer and the second page buffer, is configured to obtain the M-bit data based on the first state group information and the second state group information.

13. The memory according to claim 12, characterized in that, The M-bit data is three-bit data, and both the first state group information and the second state group information include two bits. During the state group read operation phase, the peripheral circuit is configured as follows: A first read voltage is used to perform a read operation on the first storage cell and the second storage cell; wherein, the first page buffer obtains the value of the first bit in the first state group information, the second page buffer obtains the value of the first bit in the second state group information, and the read logic circuit performs a first logic operation on the value of the first bit in the first state group information and the value of the second bit in the second state group information to obtain the value of the first bit in the M-bit data; The first read voltage is used to perform a read operation on the first memory cell, and the second read voltage is used to perform a read operation on the second memory cell; wherein, the first page buffer obtains the first bit value in the first state group information, the second page buffer obtains the second bit value in the second state group information, and the read logic circuit performs a second logic operation on the first bit value in the first state group information and the second bit value in the second state group information to obtain the second bit value in the M-bit data; The first memory cell is read using the second read voltage, and the second memory cell is read using the first read voltage; wherein, the first page buffer obtains the value of the second bit in the first state group information, the second page buffer obtains the value of the first bit in the second state group information, and the read logic circuit performs a third logic operation on the value of the second bit in the first state group information and the value of the first bit in the second state group information to obtain the value of the third bit in the M-bit data.

14. The memory according to claim 13, characterized in that, The first logical operation is an OR operation, the second logical operation is an XNOR operation, and the third logical operation is an XNOR operation.

15. The memory according to claim 9, characterized in that, During the state read operation phase, the peripheral circuit is configured as follows: Perform N read operations, each read operation using multiple read voltages that can determine one bit of N data, so as to obtain the value of one bit of N data stored in the first storage unit and the value of one bit of N data stored in the second storage unit in each read operation; wherein, each read voltage is determined based on the threshold voltage distribution of two adjacent states.

16. The memory according to claim 15, characterized in that, The N-bit data and the other N-bit data are both three-bit data, and each of the multiple state groups includes eight states. The peripheral circuit is configured as follows: In the first read operation, seven read voltages are used to determine the value of the first bit of the N-bit data stored in the first storage cell and the value of the first bit of the other N-bit data stored in the second storage cell; In the second read operation, seven read voltages are used to determine the value of the second bit in the N-bit data stored in the first storage cell and the value of the second bit in the other N-bit data stored in the second storage cell; In the third read operation, seven read voltages are used to determine the value of the third bit in the N-bit data stored in the first storage cell and the value of the third bit in the other N-bit data stored in the second storage cell.

17. The memory according to claim 16, characterized in that, The plurality of state groups include a first state group, a second state group, and a third state group. The first state group includes states one through eight, the second state group includes states nine through sixteen, and the third state group includes states seventeen through twenty-four. The seven reading voltages used in the first reading operation are: the third reading voltage that distinguishes between the first and second states, the fourth reading voltage that distinguishes between the fifth and sixth states, the fifth reading voltage that distinguishes between the tenth and eleventh states, the sixth reading voltage that distinguishes between the twelfth and thirteenth states, the seventh reading voltage that distinguishes between the fourteenth and fifteenth states, the eighth reading voltage that distinguishes between the seventeenth and eighteenth states, and the ninth reading voltage that distinguishes between the twenty-first and twenty-second states. The seven reading voltages used in the second reading operation are: the tenth reading voltage that distinguishes between the second and third states, the eleventh reading voltage that distinguishes between the fourth and fifth states, the twelfth reading voltage that distinguishes between the sixth and seventh states, the thirteenth reading voltage that distinguishes between the ninth and tenth states, the fourteenth reading voltage that distinguishes between the thirteenth and fourteenth states, the fifteenth reading voltage that distinguishes between the nineteenth and twentieth states, and the sixteenth reading voltage that distinguishes between the twenty-third and twenty-fourth states; The seven reading voltages used in the third reading operation are: the seventeenth reading voltage between the third and fourth states, the eighteenth reading voltage between the seventh and eighth states, the nineteenth reading voltage between the eleventh and twelfth states, the twentieth reading voltage between the fifteenth and sixteenth states, the twenty-first reading voltage between the eighteenth and nineteenth states, the twenty-second reading voltage between the twentieth and twenty-first states, and the twenty-third reading voltage between the twenty-second and twenty-third states.

18. A memory system, characterized in that, include: At least one memory as described in any one of claims 1 to 17; A memory controller, coupled to the memory, is configured to control the memory to perform write and read operations.

19. A method for operating a memory, characterized in that, The operation method includes: During the write operation phase of writing M+2*N bits of data into the first storage unit and the second storage unit, first state group information and second state group information are obtained based on the received M bits of data. The first state group information indicates that the first storage unit will be programmed into the first target state group among multiple state groups, and the second state group information indicates that the second storage unit will be programmed into the second target state group among the multiple state groups. During the write operation phase, a programming operation is performed to program the first storage unit to a first target state within the first target state group based on the first state group information and the received N bits of data, and to program the second storage unit to a second target state within the second target state group based on the second state group information and the received additional N bits of data.

20. The method of operating the memory according to claim 19, characterized in that, The execution of programming operations includes: Perform the first programming operation to program the first storage unit to the first target intermediate state corresponding to the first target state group based on the first state group information, and program the second storage unit to the second target intermediate state corresponding to the second target state group based on the second state group information; Perform a second programming operation to program the first storage unit from the first target intermediate state to the first target state based on the N-bit data, and to program the second storage unit from the second target intermediate state to the second target state based on the additional N-bit data.

21. The method of operating the memory according to claim 20, characterized in that, The memory includes a memory cell array and a plurality of page buffers coupled to the memory cell array; The process of obtaining the first state group information and the second state group information based on the received M-bit data includes: The first page buffer, which is coupled to the first storage unit among the plurality of page buffers, obtains the first state group information based on the stored first location information and the received M-bit data; The second page buffer coupled to the second storage unit obtains the second state group information based on the stored second location information and the received M-bit data.

22. The method of operating the memory according to claim 21, characterized in that, The second step of the programming operation includes: The first page buffer stores the first state group information and receives the N-bit data, and performs the second step programming operation on the first storage unit based on the first state group information and the N-bit data; The second page buffer stores the second state group information and receives the additional N bits of data. Based on the second state group information and the additional N bits of data, the second step of the programming operation is performed on the second storage unit.

23. The method of operating the memory according to claim 21, characterized in that, The first storage cell and the second storage cell are coupled to the same word line, and the number of the first storage cell and the second storage cell are equal and there are multiple of each; The operation method further includes: Receive M half-pages of data, each half-page containing multiple bits; The multiple bits of data in each of the M half-pages are transmitted to multiple first page buffers coupled to multiple first storage units; wherein each first page buffer receives the M bits of data. The multiple bits of data in each of the M half-pages are transmitted to multiple second page buffers coupled to multiple second storage units; wherein each second page buffer receives the M bits of data.

24. The method of operating the memory according to claim 23, characterized in that, The operation method further includes: Receive 2*N half-pages of data; The data bits within each of the N half-pages are transmitted to the plurality of first page buffers coupled to the plurality of first storage units; wherein each first page buffer receives the N bits of data. The data bits in each of the other N half-pages are transferred to the other N second page buffers coupled to the other N second storage units; wherein each second page buffer receives the other N data bits.

25. A method for operating a memory, characterized in that, The memory includes multiple storage units, each storage unit being in one state within one of multiple state groups, and every two storage units are configured to jointly store M+2*N bits of data, where M and N are both positive integers; the operation method includes: A state group read operation is performed to determine the state group to which the storage unit belongs, thereby obtaining the first state group information of the first storage unit and the second state group information of the second storage unit in every two storage units, and determining M bits of data based on the first state group information and the second state group information. A state read operation is performed to determine the state of the storage unit within its state group, thereby obtaining N bits of data stored in the first storage unit and another N bits of data stored in the second storage unit.

26. The method of operating the memory according to claim 25, characterized in that, Both the first state group information and the second state group information include multiple bits; The execution of a state group read operation to determine the state group to which the storage unit belongs, obtaining the first state group information of the first storage unit and the second state group information of the second storage unit in every two storage units, and determining M bits of data based on the first state group information and the second state group information, includes: The state group reading operation is performed based on the requirement of reading the M bits of data bit by bit. When reading any bit of the M bits of data, a reading operation is performed to obtain at least one bit of the first state group information and at least one bit of the second state group information. Based on the obtained at least one bit of the first state group information and at least one bit of the second state group information, one bit of the M bits of data is obtained.

27. The method of operating the memory according to claim 25, characterized in that, The memory includes: a first page buffer coupled to the first memory cell, a second page buffer coupled to the second memory cell, and read logic circuitry coupled to the first page buffer and the second page buffer; The execution of a state group read operation to determine the state group to which the storage unit belongs, obtaining the first state group information of the first storage unit and the second state group information of the second storage unit in every two storage units, and determining M bits of data based on the first state group information and the second state group information, includes: The first page buffer acquires the first state group information, and the second page buffer acquires the second state group information; The reading logic circuit obtains the M-bit data based on the first state group information and the second state group information.

28. The method of operating the memory according to claim 25, characterized in that, The execution of the state read operation for determining the state of the storage unit within its state group, to obtain the N bits of data stored in the first storage unit and the other N bits of data stored in the second storage unit, includes: Perform N read operations, each read operation using multiple read voltages that can determine one bit of N data, so as to obtain the value of one bit of N data stored in the first storage unit and the value of one bit of N data stored in the second storage unit in each read operation; wherein, each read voltage is determined based on the threshold voltage distribution of two adjacent states.

29. The method of operating the memory according to claim 28, characterized in that, The N-bit data and the other N-bit data are both three-bit data, and each of the multiple state groups includes eight states. The step of performing N read operations, each using multiple read voltages capable of determining one bit of N data, to obtain the value of one bit of the N data stored in the first storage unit and the value of one bit of the other N data stored in the second storage unit in each read operation, includes: In the first read operation, seven read voltages are used to determine the value of the first bit of the N-bit data stored in the first storage cell and the value of the first bit of the other N-bit data stored in the second storage cell; In the second read operation, seven read voltages are used to determine the value of the second bit in the N-bit data stored in the first storage cell and the value of the second bit in the other N-bit data stored in the second storage cell; In the third read operation, seven read voltages are used to determine the value of the third bit in the N-bit data stored in the first storage cell and the value of the third bit in the other N-bit data stored in the second storage cell.

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