Current compensation method for memory, memory and storage medium

Abstract

The application discloses a current compensation method of a memory, a memory and a storage medium, and belongs to the technical field of memories. The method comprises the following steps: acquiring a basic current of a target memory unit; acquiring a write frequency of the target memory unit, and acquiring a current adjustment coefficient of the target memory unit according to the write frequency; adjusting the basic current by using the current adjustment coefficient to obtain a write current of the target memory unit; and applying the write current to the target memory unit to complete a write operation. The application can accurately compensate for a voltage drop generated when current passes through a resistor due to an electric distance, thereby guaranteeing write consistency; and the dynamic adjustment coefficient which is self-adaptive to the write frequency can prolong the service life of the memory.

Description

Technical Field

[0001] This application relates to the field of memory technology, specifically to a current compensation method for a memory, a memory, and a storage medium. Background Technology

[0002] Read / write tolerance is a crucial indicator of memory reliability. Due to frequent read / write operations over extended periods and device aging, storage media often experience decreased reliability and increased read / write error rates towards the end of their lifespan. For traditional non-volatile memory, the more read / write cycles, the higher the probability of failure and the shorter the storage life. Unlike these types of memory, phase-change memory (PCM) has a significant characteristic: its data retention period is not strongly correlated with the number of read / write cycles it can withstand. This means that by ensuring its read / write capability, the overall lifespan of the PCM can be extended.

[0003] In practical use, after numerous read and write operations, some memory cells may become physically damaged beyond repair, while others may experience a decrease in their response to write current compared to their initial usage. If the factory-set write operation parameters are still used, write operations may fail, leading to them being mistakenly identified as damaged. Therefore, if appropriate technical means are used to improve the read and write resistance of memory cells and reduce the write error rate later in the lifespan of the memory, the lifespan of the storage medium can be effectively extended. Summary of the Invention

[0004] A current compensation method for a memory, a memory, and a storage medium are provided to solve the problem of decreased write reliability caused by differences in wiring distance.

[0005] In a first aspect, a current compensation method for a memory is provided, the memory including a driving transistor and a target memory cell controlled by the driving transistor; the method includes: Obtain the base current of the target memory cell; The number of writes to the target storage cell is obtained, and the current adjustment coefficient of the target storage cell is obtained based on the number of writes. The base current is adjusted using the current adjustment coefficient to obtain the write current of the target memory cell; The write current is applied to the target memory cell to complete the write operation; The target storage unit includes a first storage unit and a second storage unit. The electrical distance between the second storage unit and the driving transistor is greater than the electrical distance between the first storage unit and the driving transistor. The base current of the second storage unit is greater than the base current of the first storage unit, and for the same number of writes, the current adjustment coefficient of the second storage unit is not less than the current adjustment coefficient of the first storage unit.

[0006] In a second aspect, a memory is also provided, characterized in that it comprises: drive transistor; The target storage unit controlled by the driving transistor includes a first storage unit and a second storage unit, wherein the electrical distance between the second storage unit and the driving transistor is greater than the electrical distance between the first storage unit and the driving transistor; The current compensation module is configured as follows: Obtain the base current of the target memory cell; The number of writes to the target storage cell is obtained, and the current adjustment coefficient of the target storage cell is obtained based on the number of writes. The base current is adjusted using the current adjustment coefficient to obtain the write current of the target memory cell; The write current is applied to the target memory cell to complete the write operation; Wherein, the base current of the second storage cell is greater than the base current of the first storage cell, and for the same number of writes, the current adjustment coefficient of the second storage cell is not less than the current adjustment coefficient of the first storage cell.

[0007] Thirdly, this application also provides a computer-readable storage medium having a computer program stored thereon, the computer program being loaded by a processor to perform the steps in the current compensation method for the memory as described in any one of the first aspects.

[0008] Beneficial effects: This application effectively solves the problem of decreased write reliability caused by differences in wiring distance in memory by dynamically adjusting the write current. Specifically, firstly, different base currents are allocated according to the difference in electrical distance between the memory cell and the driving transistor (first / second memory cell), with a higher base current allocated to the far-distance cell (second memory cell) by default to compensate for line losses; secondly, the current adjustment coefficient is dynamically obtained in combination with the number of writes (reflecting the degree of aging), ensuring that the adjustment coefficient of the far-distance cell is not lower than that of the near-distance cell, thereby doubly offsetting the performance degradation caused by electrical distance and aging in long-term use. Its advantages include: accurately compensating for the voltage drop caused by current passing through the resistor due to electrical distance, ensuring write consistency; and extending the life of the memory through a dynamically adjusted coefficient that adapts to the number of writes.

[0009] Therefore, the dynamic compensation mechanism of this application can accurately offset the current attenuation caused by the difference in wiring impedance, ensuring that memory cells in different locations obtain equivalent effective write current, thereby significantly improving the write consistency and data reliability of the entire array of memory cells. Experimental verification shows that after 1.2M write operations on the second memory cell, the write threshold voltage increases by 50mV, significantly reducing the end-of-life bit error rate. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a graph showing the changes in storage cell characteristics with the number of write cycles provided in the embodiments of this application; Figure 2 This is one of the flowcharts of the memory current compensation method provided in the embodiments of this application; Figure 3 This is one of the schematic diagrams illustrating the calculation process of the write current provided in the embodiments of this application; Figure 4 This is a second schematic diagram illustrating the calculation process of the write current provided in the embodiments of this application; Figure 5 This is the third schematic diagram of the calculation process of the write current provided in the embodiments of this application; Figure 6 This is the fourth schematic diagram of the calculation process of the write current provided in the embodiments of this application; Figure 7 This is the fifth schematic diagram of the calculation process of the write current provided in the embodiments of this application; Figure 8 This is the sixth schematic diagram of the calculation process of the write current provided in the embodiments of this application; Figure 9 This is the seventh schematic diagram of the calculation process of the write current provided in the embodiments of this application; Figure 10 This is the second flowchart of the memory current compensation method provided in the embodiments of this application; Figure 11 This is the third flowchart of the memory current compensation method provided in the embodiments of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0013] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0014] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0015] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0016] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0017] Phase Change Memory (PCM) is a non-volatile memory that stores data by utilizing the resistance difference between a specific phase change material and its crystalline (low-resistance) and amorphous (high-resistance) states. Read and write operations on its memory cells are achieved by applying current / voltage pulses with different characteristics: 1) Write 0 (Reset operation): A short, strong current pulse is applied to raise the temperature of the phase change material above its melting point, followed by rapid quenching to form an amorphous state (high-resistance state, logic "0"). 2) Write 1 (Set operation): A long, moderate current pulse is applied to maintain the material temperature between its crystallization and melting points, resulting in a polycrystalline state (low-resistance state, logic "1") through slow cooling. 3) Read operation: A very weak probe pulse is applied, and the state is determined by measuring the cell resistance value.

[0018] To address the issue of decreased write reliability in the later stages of phase-change memory (PCM) due to cell performance degradation and the delay effect of wiring resistance-capacitance (RC), using a uniform amplification factor for the first cell (N cell) and the second cell (F cell) cannot accommodate the higher current demands of the F cell caused by wiring delay and lifespan degradation. Furthermore, the lack of an independent current compensation mechanism leads to insufficient writes to the F cell in the later stages of its lifespan. Therefore, this application addresses this issue by configuring differentiated amplification factors (k) for the F and N cells. 1F / k 2F k 1N / k 2N ), and introduce an independent control coefficient (k) for the compensation current. 1comp / k 2comp This enables dynamic matching of the current requirements of memory cells at different locations; as the number of writes (WE) increases, the compensation strength of the F cell is automatically increased, significantly extending the effective lifespan of the phase change memory.

[0019] Please refer to Figure 1 , Figure 1This paper presents the distribution and average values ​​of write current (ED Cur) for far-end (FF) and near-end (NN) cells in a phase-change memory (PCM) at different lifespan stages (TO, 100K, 500K, and 1M write operations). The graph on the left shows that the range and dispersion of write current distribution for FF and NN cells change with increasing lifespan (i.e., more write operations). The table on the right presents the average write current values ​​for FF and NN cells at different stages. For example, at the TO stage, the average value for FF is 100.75 and for NN is 90.3. Furthermore, as the number of write operations increases to 1M, the average value for FF reaches 128.5 and for NN is 99.23. This indicates that the write current characteristics of far-end (FF) and near-end (NN) cells differ throughout their lifespan, and this difference changes with increasing usage. The write current characteristics of PCM cells change due to two factors: the location of the cell (far-end F cell vs. near-end N cell) and the lifespan stage (increasing write operations). This change causes remote cells to require higher write currents later in their lifespan, which in turn affects the overall write reliability of the memory.

[0020] Therefore, it is necessary to implement differentiated current compensation strategies for storage cells at different locations and stages of use, and to ensure that each storage cell can achieve stable write performance throughout its entire lifespan by dynamically adjusting the compensation coefficient.

[0021] On the one hand, this embodiment provides a current compensation method for a memory, such as... Figure 2 As shown, the memory includes a driver transistor and a target memory cell controlled by the driver transistor; the method includes: S201, Obtain the base current of the target storage cell.

[0022] Understandably, an initial write current base value is preset for different memory cell regions. Its purpose is to perform "position compensation," that is, to offset the effects of "electrical distance." Since the second memory cell, which is farther from the drive transistor, experiences greater path resistance and signal attenuation during writing, a larger base current is set for it to ensure that, in the initial state, memory cells in different regions can obtain sufficient write drive capability, achieving write uniformity.

[0023] S202, obtain the number of writes to the target storage cell, and obtain the current adjustment coefficient of the target storage cell based on the number of writes.

[0024] Understandably, the write count (i.e., aging level) of the storage cell is obtained, and a corresponding current adjustment coefficient is derived based on this write count. Its purpose is to perform "aging compensation," that is, to counteract the impact of the "write count." As the write count increases, the write threshold of the storage cell drifts, and performance degrades. By obtaining the current adjustment coefficient related to the write count, an additional current stimulus is applied to the aging cell.

[0025] S203, the base current is adjusted using the current adjustment coefficient to obtain the write current of the target memory cell.

[0026] Understandably, the base current and current adjustment coefficient obtained from S201 and S202 are mathematically calculated (e.g., multiplied or added together). This process integrates both position and aging factors to generate the final write current command. This step ensures that the output write current value addresses issues of insufficient or excessive write current caused by electrical distance and write operation aging.

[0027] S204, the write current is applied to the target memory cell to complete the write operation; The target storage unit includes a first storage unit and a second storage unit. The electrical distance between the second storage unit and the driving transistor is greater than the electrical distance between the first storage unit and the driving transistor. The base current of the second storage unit is greater than the base current of the first storage unit, and for the same number of writes, the current adjustment coefficient of the second storage unit is not less than the current adjustment coefficient of the first storage unit.

[0028] Understandably, the obtained write current is applied to the target memory cell. Its function is to perform a compensated write operation. By applying a precisely compensated write current, data writing can be reliably and accurately completed during write operations, regardless of whether the memory cell is located at a distance or has been written to multiple times, thereby improving the overall lifespan and reliability of the memory.

[0029] Therefore, this application achieves dual cancellation of static non-uniformity and dynamic degradation through a synergistic mechanism of base current (such as compensating for location differences) and current adjustment coefficient (such as compensating for aging degree), thereby maintaining stable and reliable write operations throughout the entire life cycle of the memory.

[0030] In some embodiments, step S201, obtaining the base current of the target memory cell includes: Determine the electrical distance region where the target storage unit is located, and obtain the base current corresponding to the target storage unit based on the electrical distance region; the base current corresponding to different electrical distance regions is different.

[0031] Understandably, a pre-defined, static current grading system is used based on the positional relationship (e.g., electrical distance) between the memory cells and the drive circuit. Its purpose is to achieve "position compensation," that is, by dividing the entire memory array into several different "electrical distance regions" according to their distance from the drive source during initial design or power-on, and setting a progressively increasing base current value for each region. When writing to a target memory cell, the system first determines its region and automatically calls upon the corresponding larger base current. This pre-compensates for signal attenuation at distant cells caused by factors such as trace resistance during the write operation, ensuring that memory cells at different locations receive a relatively uniform write current.

[0032] In some embodiments, step S202, obtaining the current adjustment coefficient of the target memory cell based on the number of writes, includes: The write count region is determined, and the current adjustment coefficient corresponding to the target storage cell is obtained based on the write count region and the electrical distance region. The write count region includes multiple stages, different stages correspond to different current adjustment coefficients, and the same target storage cell includes at least two or two sets of different current adjustment coefficients.

[0033] Understandably, the current adjustment coefficient is dynamically obtained based on the electrical distance region and the write cycle (WE) region. Its function is to achieve fine-grained, adaptive aging compensation: it divides the memory's lifespan into multiple stages (e.g., WE < 100K, 100K ≤ WE < 1M, WE ≥ 1M, etc.), and presets a current adjustment coefficient (e.g., k) for each stage for memory cells with different electrical distances (e.g., near-end N, middle M, far-end F). 1N , k 2N , k 1F , k 2F (etc.). By determining the specific "location" and "lifespan" stage of the target storage cell, the system can apply the most suitable current adjustment factor. This allows for the use of a smaller current adjustment factor in the early stages of the lifespan, gradually increasing the current adjustment factor as the number of writes increases to overcome more severe aging effects, thereby maintaining write reliability throughout the entire lifespan.

[0034] Example 1: In some embodiments, the base current includes a reference current, and the current adjustment coefficient includes a reference adjustment coefficient; in step S203, adjusting the base current using the current adjustment coefficient to obtain the write current of the target memory cell includes: The obtained reference current is multiplied by the obtained reference adjustment coefficient to obtain the corresponding write current.

[0035] The advantage of this method is that the computational model is simple and efficient, and it can achieve the basic lifespan extension target with relatively small control overhead.

[0036] Example 2: In some embodiments, the memory includes a first electrical distance region and a second electrical distance region, the reference current includes a first reference current and a second reference current, the electrical distance of the first memory cell is located within the first electrical distance region, and the electrical distance of the second memory cell is located within the second electrical distance region; the memory also includes a first write count region and a second write count region corresponding to the first electrical distance region, a third write count region and a fourth write count region corresponding to the second electrical distance region, and the reference adjustment coefficient includes a first reference adjustment coefficient, a second reference adjustment coefficient, a third reference adjustment coefficient, and a fourth reference adjustment coefficient; The step of multiplying the acquired reference current by the acquired reference adjustment coefficient to obtain the corresponding write current includes: When the target storage unit is the first storage unit and the number of writes is within the first number of writes range, the first reference current is multiplied by the first reference adjustment coefficient to obtain the write current; When the target storage cell is the first storage cell and the number of writes is within the second number of writes region, the first reference current is multiplied by the second reference adjustment coefficient to obtain the write current; When the target storage cell is the second storage cell and the number of writes is within the third number of writes region, the second reference current is multiplied by the third reference adjustment coefficient to obtain the write current; When the target storage unit is the second storage unit and the number of writes is within the fourth number of writes region, the second reference current is multiplied by the fourth reference adjustment coefficient to obtain the write current.

[0037] The advantages of this method are: by setting different base currents for memory cells with different electrical distances, static compensation for "spatial non-uniformity" is achieved; simultaneously, by matching specific current amplification factors for different memory cells at different aging stages, dynamic compensation for "time degradation" is achieved. This compensation strategy, which couples location and lifetime dimensions, can more accurately match the actual state of each memory cell (for example, distant cells typically age faster, so their adjustment factor is set larger), thereby maximizing write efficiency and extending the lifespan of the memory.

[0038] Example 3: In some embodiments, the base current includes a reference current and a compensation current, and the current adjustment coefficient includes a reference adjustment coefficient and a compensation adjustment coefficient; adjusting the base current using the current adjustment coefficient to obtain the write current of the target memory cell includes: The obtained reference current is multiplied by the obtained reference adjustment coefficient to obtain a first adjustment component, and the obtained compensation current is multiplied by the obtained compensation adjustment coefficient to obtain a second adjustment component. The first adjustment component and the second adjustment component are added together to obtain the corresponding write current.

[0039] By decomposing the write current into two independent components—a "reference" and a "compensation" component—and adjusting each component separately before combining them to form the final write current, this method divides the compensation strategy into two parts: the first adjustment component, consisting of "reference current × reference adjustment coefficient," is primarily responsible for basic drive and handling uniform aging; while the second adjustment component, consisting of "compensation current × compensation adjustment coefficient," acts as an independently adjustable "additional stimulus" to specifically compensate for aging caused by factors such as location (e.g., far-end cells may age faster than near-end cells, requiring additional current increments). By adding the two adjustment components, fine-tuning compensation can be performed more flexibly. For example, in the early stages of life, the reference component can be relied upon primarily; as aging intensifies, the coefficient of the compensation component can be significantly increased to provide stronger write power without excessively amplifying the entire reference current, thereby improving energy efficiency and preventing overstress on the memory cells while ensuring write reliability.

[0040] Example 4: In some embodiments, the memory includes a first electrical distance region and a second electrical distance region, the compensation current includes a first compensation current and a second compensation current, the electrical distance of the first memory cell is located within the first electrical distance region, and the electrical distance of the second memory cell is located within the second electrical distance region; the memory also includes a first write count region and a second write count region, the reference adjustment coefficient includes a first reference adjustment coefficient and a second reference adjustment coefficient, and the compensation adjustment coefficient includes a first compensation adjustment coefficient, a second compensation adjustment coefficient, a third compensation adjustment coefficient, and a fourth compensation adjustment coefficient; The write current of the target memory cell includes: When the target storage unit is the first storage unit and the number of writes is within the first number of writes range, the reference current is multiplied by the first reference adjustment coefficient to obtain the first adjustment component, the first compensation current is multiplied by the first compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current. When the target storage cell is the first storage cell and the number of writes is within the second number of writes region, the reference current is multiplied by the second reference adjustment coefficient to obtain the first adjustment component, the first compensation current is multiplied by the second compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current. When the target storage unit is the second storage unit and the number of writes is within the first number of writes range, the reference current is multiplied by the first reference adjustment coefficient to obtain the first adjustment component, the second compensation current is multiplied by the third compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current. When the target storage unit is the second storage unit and the number of writes is within the second number of writes range, the reference current is multiplied by the second reference adjustment coefficient to obtain the first adjustment component, the second compensation current is multiplied by the fourth compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current.

[0041] Understandably, the memory cells contained in the memory are divided into a first electrical distance region and a second electrical distance region based on their electrical distance from the driving transistor. The first electrical distance region contains the first memory cells (near-end cells). The second electrical distance region contains the second memory cells (far-end cells). The base current includes a common reference current and two region-specific compensation currents: a first compensation current for the near-end cells and a second compensation current, typically larger, for the far-end cells. The entire lifespan is divided into two phases: a first write cycle region (e.g., early-stage use) and a second write cycle region (e.g., later-stage use).

[0042] The baseline adjustment coefficients include a first baseline adjustment coefficient for the first write count region and a second baseline adjustment coefficient, which is larger, for the second write count region. The compensation adjustment coefficients include a first compensation adjustment coefficient, a second compensation adjustment coefficient, a third compensation adjustment coefficient, and a fourth compensation adjustment coefficient. Specifically: The first compensation adjustment coefficient is used for the near-end unit in the first write count region. The second compensation adjustment coefficient is used for the near-end unit in the second write count region, and its value is greater than the first compensation adjustment coefficient. The third compensation adjustment coefficient is used for the far-end unit in the first write count region. The fourth compensation adjustment coefficient is used for the far-end unit in the second write count region, and its value is the largest of all compensation coefficients. In detail: When writing to a near-end cell (first memory cell) in its early stages of use (such as the first write cycle region), the system acquires a reference current and a first reference adjustment coefficient, multiplying them to obtain a first adjustment component; simultaneously, the system acquires a first compensation current and a first compensation adjustment coefficient, multiplying them to obtain a second adjustment component; finally, the first adjustment component and the second adjustment component are added together to obtain the write current applicable to this new near-end cell. At this time, the compensation amount is relatively small.

[0043] When writing to a frequently used near-end cell (first memory cell) (such as the second write count region), the system will use a larger second reference adjustment factor multiplied by the reference current to obtain an increased first adjustment component; at the same time, the system will use a larger second compensation adjustment factor multiplied by the first compensation current to obtain an increased second adjustment component; adding these two increased components together, a larger write current than initially obtained is obtained to compensate for the aging of the near-end cell.

[0044] When writing to a remote cell (second memory cell) in its initial stage of use (e.g., the first write cycle region), the system acquires a reference current and a first reference adjustment coefficient, multiplying them to obtain a first adjustment component (this component is the same as the near-end cell in its initial stage). Simultaneously, the system acquires a larger second compensation current and a third compensation adjustment coefficient, multiplying them to obtain a second adjustment component. Because the remote cell requires static compensation, this second adjustment component is larger than that of the near-end cell from the beginning. The sum of these two components results in a write current higher than that of the near-end cell during the same period, pre-compensating for signal loss due to the greater electrical distance.

[0045] When writing to a frequently used (e.g., the second write cycle region) remote cell (second memory cell), the system multiplies the second reference adjustment factor by the reference current to obtain an increased first adjustment component; simultaneously, the system multiplies the largest fourth compensation adjustment factor by the second compensation current to obtain a significantly increased second adjustment component. This is because remote cells typically age faster and require the strongest additional compensation. Adding these two components yields the highest write current of all cases, addressing the scenario of "farthest location and most severe aging."

[0046] The aforementioned method employs dual independent regulation: a baseline current path provides a basic current that increases overall with aging; while the compensation current path acts as an adjustable additional stimulus specifically targeting "location disadvantage" and its resulting "accelerated aging." By assigning different compensation current bases to memory cells in different locations and matching different compensation coefficients to different aging stages, an extremely fine and adaptive compensation strategy is achieved, ensuring that all memory cells can be reliably written to throughout their entire lifespan.

[0047] Example 5: In some embodiments, the memory includes a first electrical distance region and a second electrical distance region, the base current includes a first reference current, a second reference current, a first compensation current, and a second compensation current, the electrical distance of the first memory cell is located within the first electrical distance region, and the electrical distance of the second memory cell is located within the second electrical distance region; the memory also includes a first write count region and a second write count region corresponding to the first electrical distance region, a third write count region and a fourth write count region corresponding to the second electrical distance region, the reference adjustment coefficient includes a first reference adjustment coefficient, a second reference adjustment coefficient, a third reference adjustment coefficient, and a fourth reference adjustment coefficient, and the compensation adjustment coefficient includes a first compensation adjustment coefficient, a second compensation adjustment coefficient, a third compensation adjustment coefficient, and a fourth compensation adjustment coefficient; The write current of the target memory cell includes: When the target storage unit is the first storage unit and the number of writes is within the first number of writes range, the first reference current is multiplied by the first reference adjustment coefficient to obtain the first adjustment component, the first compensation current is multiplied by the first compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current. When the target storage cell is the first storage cell and the number of writes is within the second number of writes region, the first reference current is multiplied by the second reference adjustment coefficient to obtain the first adjustment component, the first compensation current is multiplied by the second compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current. When the target storage unit is the second storage unit and the number of writes is within the third number of writes region, the second reference current is multiplied by the third reference adjustment coefficient to obtain the first adjustment component, the second compensation current is multiplied by the third compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current. When the target storage unit is the second storage unit and the number of writes is within the fourth number of writes region, the second reference current is multiplied by the fourth reference adjustment coefficient to obtain the first adjustment component, the second compensation current is multiplied by the fourth compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current.

[0048] Understandably, the memory cells are divided into a first electrical distance region and a second electrical distance region based on their electrical distance from the driving transistor. The first electrical distance region contains the first memory cell (near-end cell), and the second electrical distance region contains the second memory cell (far-end cell). The base current includes a reference current and a compensation current. The reference current is a dedicated reference current set for each region. The near-end cell uses a smaller first reference current, and the far-end cell uses a larger second reference current. Similarly, a dedicated compensation current is set for each region: a first compensation current for the near-end cell and a second compensation current, typically larger, for the far-end cell. The write cycle regions are divided according to the lifespan. For example, the lifespan of the near-end cell is divided into a first write cycle region (e.g., initial stage) and a second write cycle region (e.g., later stage). The lifespan of the far-end cell is divided into a third write cycle region (e.g., initial stage) and a fourth write cycle region (e.g., later stage). The reference adjustment coefficients include a first reference adjustment coefficient, a second reference adjustment coefficient, a third reference adjustment coefficient, and a fourth reference adjustment coefficient. The first reference adjustment coefficient is used for the near-end cell in the first write cycle region. The second reference adjustment factor is used for the proximal unit in the second write count region. The third reference adjustment factor is used for the distal unit in the third write count region. The fourth reference adjustment factor is used for the distal unit in the fourth write count region. The compensation adjustment factors include the first compensation adjustment factor, the second compensation adjustment factor, the third compensation adjustment factor, and the fourth compensation adjustment factor. Specifically, the first compensation adjustment factor is used for the proximal unit in the first write count region. The second compensation adjustment factor is used for the proximal unit in the second write count region. The third compensation adjustment factor is used for the distal unit in the third write count region. The fourth compensation adjustment factor is used for the distal unit in the fourth write count region.

[0049] When writing to a near-end cell (first memory cell) in its early stages of use (e.g., the first write cycle region), the system acquires a small, pre-defined first reference current and multiplies it by a first reference adjustment factor applicable to this stage to obtain a first adjustment component. Simultaneously, the system acquires a pre-defined first compensation current and multiplies it by a first compensation adjustment factor applicable to this stage to obtain a second adjustment component. Finally, the first and second adjustment components are added together to obtain the write current applicable to this new near-end cell.

[0050] When writing to a frequently used near-end cell (first memory cell) (e.g., in the second write cycle region), the system continues to use the first reference current, but switches to a larger second reference adjustment factor, resulting in an increased first adjustment component. Simultaneously, the system continues to use the first compensation current, but switches to a larger second compensation adjustment factor, resulting in an also increased second adjustment component. Adding these two increased components yields a larger write current than in the first write cycle region (e.g., in the initial stage), to compensate for the aging of the near-end cell.

[0051] When writing to a remote cell (second memory cell) in its early stages of use (e.g., the third write cycle region), the system acquires a larger second reference current specifically configured for that cell, multiplying it by a third reference adjustment factor applicable to the early stages of the remote cell to obtain a first adjustment component. This first adjustment component is larger than the first adjustment component for a near-end cell in its early stages of use. Simultaneously, the system acquires an even larger second compensation current, multiplying it by a third compensation adjustment factor applicable to this stage to obtain a second adjustment component. The sum of these two components results in a write current significantly higher than that of a near-end cell in the same period, achieving strong static compensation.

[0052] When writing to a frequently used remote cell (second memory cell) (e.g., the fourth write cycle region), the system uses a second reference current and switches to what is likely the largest fourth reference adjustment factor, multiplying them to obtain a significantly increased first adjustment component. Simultaneously, the system uses a second compensation current and switches to what is also the largest fourth compensation adjustment factor, multiplying them to obtain a very strong second adjustment component. Adding these two significantly enhanced components yields the highest write current of all cases, powerfully addressing the "deep aging of remote cells" scenario.

[0053] The advantage of this method is that it achieves more precise compensation by configuring independent current bases and adjustment coefficients for cells at different locations at different stages of their lifespan. For the aging characteristics of near-end and far-end cells, an independent and complete compensation mechanism is established for each, ensuring the most accurate write energy is provided at different stages of their lifespan.

[0054] Example 6: In some embodiments, the memory further includes a first write count region and a second write count region; the current compensation method for the memory further includes: When the number of writes is within the first number of writes region, the current compensation method of the memory as described in Embodiment 1 or Embodiment 2 above is adopted; When the number of writes is within the second number of writes region, the current compensation method of the memory as described in Embodiment 3 or Embodiment 4 above is adopted.

[0055] Understandably, this embodiment dynamically switches between different current compensations based on different aging stages of the memory. Its purpose is to achieve a balanced optimization between compensation efficiency and accuracy. In the early stages of the memory's lifespan (e.g., the first write cycle region), the aging of the memory cells is relatively mild, and the single model described in Embodiment 1 or Embodiment 2 (i.e., reference current × reference adjustment coefficient) is used. This single model is simple to calculate, has a fast response, and can meet the initial compensation needs with low control overhead, prioritizing efficiency. When the memory enters the later stages of its lifespan (e.g., the second write cycle region), the aging of the memory cells intensifies, and the performance degrades nonlinearly. At this time, it switches to the reference-compensation dual-component superposition model described in Embodiment 3 or Embodiment 4. This superposition model provides more refined and powerful targeted compensation, better matching the nonlinear characteristics during deep aging, prioritizing accuracy. Through this staged strategy, a smooth transition from efficient compensation to accurate compensation is achieved throughout the entire lifespan of the memory, thereby optimizing system energy efficiency and lifespan while ensuring reliability.

[0056] The following are examples illustrating the above embodiments.

[0057] like Figure 3 As shown, Figure 3 This demonstrates the calculation of write current for near-end (N) cells and far-end (F) cells using a single model (i.e., reference current multiplied by a reference adjustment factor). Specifically, the cell lifetime is divided into three stages based on the number of writes (WE), and different reference adjustment factors (1, k1N, k2N and 1, k1F, k2F) are set for each stage. In other words, regardless of whether the cell is near-end or far-end, its dedicated reference current (I0) is used when it is in a brand-new state (WE < 100K). reset,N base and I reset,F base And the latter is greater than the former (to compensate for electrical distance loss), that is, when WE < 100K, I reset,N =I reset,N base I reset,F =I reset,F base As the number of write cycles increases, the write current is no longer fixed. Instead, each reference current is dynamically increased by multiplying it by a reference adjustment factor (k1, k2) greater than 1 to overcome performance degradation. That is, when 100K ≤ WE < 1M, I reset,N =I reset,N base ×k 1N I reset,F =I reset,F base ×k 1F When WE≥1M, I reset,N =I reset,N base ×k 2N I reset,F =I reset,F base×k 2F Among them, the reference adjustment factor k of the remote unit 1F and k 2F Set to k, which is not less than the corresponding near-end unit. 1N and k 2N , and k 2F Greater than k 1F k 2N Greater than k 1N .

[0058] like Figure 4 As shown, the memory can be further subdivided into three electrical distance regions, adding a compensation strategy for the intermediate electrical distance cell (i.e., cell M). The electrical distance of cell M is greater than that of cell N but less than that of cell F. The write current logic of cell M is consistent with that of cells N and F, all using a "reference current × reference adjustment coefficient" scheme. reset,M base Greater than I reset,N base And less than I reset,F base k 1M and k 2M Set to be no greater than k respectively 1F and k 2F And not less than k 1N and k 2N Furthermore, the memory can be divided into four, five, or even more electrically isolated regions; the memory can also be divided into four, five, or even more write-restricted regions; its write current logic AND... Figure 3 and Figure 4 The same applies, so I won't repeat it here.

[0059] like Figure 5 As shown, Figure 5 This demonstrates the distinction between near-end and far-end cells and the use of different compensation paths. For near-end cells (N cells), only a single reference current path is used for compensation throughout their entire lifecycle, which can be considered as the compensation adjustment factor for near-end cells being 0. For example, when WE < 100K, the write current of the near-end cell is the reference current (I0). reset,N base When 100K≤WE<1M, the write current is the reference current (I). reset,N base Multiply by the first reference adjustment factor (k1); when WE≥1M, the write current is the reference current (I). reset,N base The current is multiplied by the second reference adjustment factor (k2). For the far-end cell (F cell), a dual-path superposition model of "reference current path + compensation current path" is introduced. For example, when WE < 100K, the write current of the far-end cell is the reference current (I). reset,N base ) and compensation current (I reset,comp,F The sum of the two values ​​can be considered as the reference adjustment factor and the compensation adjustment factor both being 1; when 100K≤WE<1M, the write current is determined by the reference current (I).reset,N base The first adjustment component, obtained by multiplying the first reference adjustment factor (k1) by the first adjustment component, is combined with an independent compensation current (I). reset,comp,F Multiply by the first compensation adjustment factor (k) 1comp,F The second adjustment component obtained is added together; when WE≥1M, the write current is composed of the reference current (I). reset,N base The first adjustment component, obtained by multiplying the first adjustment component by the second reference adjustment factor (k2), is combined with an independent compensation current (I). reset,comp,F Multiply by the second compensation adjustment factor (k) 2comp,F The second adjustment component obtained is added together. This allows the system to provide dual compensation for remote units: the baseline path addresses basic aging, while the independent compensation path can be configured with a larger compensation adjustment coefficient (such as k). 1comp,F k 2comp,F This provides a powerful and precise additional stimulus to address the accelerated aging that may occur due to the long electrical distance, thereby enabling more reliable writing during the deep aging stage.

[0060] like Figure 6 As shown, Figure 6 exist Figure 5 Based on the "baseline + compensation" dual-path compensation model, a compensation scheme for intermediate electrical distance units (i.e., M units) has been added, thus finely dividing the storage array into three electrical distance regions: near (N), middle (M), and far (F). This means that M units fall between N and F units in terms of electrical distance and aging characteristics. Their static loss and aging rate are insufficient to be compensated solely through the base path like N units, but not as severe as F units. Therefore, by configuring M units with a compensation current and compensation adjustment coefficient smaller than those of F units, i.e., I... reset,comp,M reset,comp,F k 1comp,M <k 1comp,F k 2comp,M <k 2comp,F This achieves a three-level refined compensation system with gradient enhancement from near to far, enabling more precise matching of the non-uniform aging degree of cells at different locations, and achieving a better overall balance between reliability and energy efficiency. Similarly, the memory can be divided into four, five, or even more electrical distance regions; the memory can also be divided into four, five, or even more write cycle regions; its write current logic and... Figure 5 and Figure 6 The same applies, so I won't repeat it here.

[0061] like Figure 7 As shown, Figure 7 A hybrid compensation strategy is presented, which employs a differentiated compensation model for memory cells with different electrical distances (near-end N-cell, middle M-cell, and far-end F-cell) and in combination with their write count (WE) lifetime.​

[0062] For near-end cells (N cells), a single "reference current path" model is used for compensation throughout their entire lifecycle. Write current (I0) reset，N Based on its own reference current (I) reset，N base The calculation is performed using the following method: In the brand new state (WE < 100K), the reference current is used directly; as the number of writes increases, the reference current is multiplied by a corresponding reference adjustment factor (k) greater than 1. 1N ,k 2N This is used to increase write current in order to address performance degradation.

[0063] For the intermediate (M) and far-end (F) cells, a more refined "dual-path compensation" model is introduced. This model includes two paths: one based on the near-end cell reference current (I0). reset，N base One is the baseline path, and the other is based on the compensation current (I) of each unit. reset,comp,M Or I reset,comp,F The compensation path is as follows: In the brand new state (WE < 100K), the write current is formed by directly adding the reference current and the compensation current (e.g., I). reset，M base =I reset，N base +I reset,comp,M This is used to offset the initial losses caused by the long electrical distance. As the number of write cycles increases (WE≥100K), the write current consists of the sum of two adjustment components. The first adjustment component is the reference current multiplied by the reference adjustment factor (k). 1M / k 2M or k 1F / k 2F The first component is used to address the underlying aging effects; the second component is the compensation current multiplied by the compensation adjustment factor (k). 1comp,M / k 2comp,M or k 1comp,F / k 2comp,F This is designed to specifically address dynamic aging that may be exacerbated by greater electrical distance. The compensation adjustment factor can be set to be greater than 1, and for F-cells with even greater electrical distance, its compensation adjustment factor (k) is... 1comp,F / k 2comp,F The coefficient (k) is set to be no less than the corresponding coefficient of unit M. 1comp,M / k 2comp,M This allows for a gradient enhancement of the compensation intensity.

[0064] Figure 7 The strategy reflects the flexibility of the compensation method, that is, a simple model is used for the proximal units with relatively mild aging, while a stronger and more precise dual-path additional stimulus is used for the mid and far units with more significant aging.

[0065] like Figure 8 As shown, Figure 8 and Figure 7 The difference lies in the fact that, in the new state (WE < 100K), the write current models of the intermediate cells (M cells) and the far cells (F cells) are no longer directly superimposed with the compensation current. Specifically, in Figure 7 In the initial stage, the M and F elements adopted a fixed superposition mode of "near-end reference current + compensation current"; while Figure 8 Then, instead, the reference current of each cell (i.e., I) is used directly. reset,M bas e and I reset,F base This means that, in the new state, the difference in write current between different electrical distance cells is directly defined in their respective reference values, resulting in a simpler model structure. Only when the number of writes increases (WE≥100K) and the cell enters the aging stage are dynamic adjustment components based on compensation current (such as I) introduced for the M and F cells. reset,comp M ×k 1comp,M (in order to address the worsening performance degradation).

[0066] In other words, Figure 8 For cells with three different electrical distances—near-end (N), middle (M), and far-end (F)—in the brand-new state (WE < 100K), each cell uses its own reference current (I0, I ... reset,N base ,I reset,M base ,I reset,F base A simplified model is used, where the reference currents for cells M and F already include compensation for initial electrical distance loss; as the number of writes increases (WE≥100K), for cell N, a single reference current multiplied by an adjustment factor (k) continues to be used. 1N ,k 2N The model is as follows: for the M and F elements, a more refined "reference adjustment + compensation adjustment" dual-path model is introduced, that is, the reference current is multiplied by the adjustment coefficient (k). 1M / k 2M ,k 1F / k 2F On top of this, an independent compensation current (I) is superimposed. reset,comp,M / I reset,comp,F Multiply by the compensation adjustment factor (k) 1comp,M / k 2comp,M ,k 1comp,F / k 2comp,F The dynamic compensation component constitutes the middle and far-end units, thereby achieving more accurate and powerful gradient compensation during the aging stage.

[0067] like Figure 9 As shown, the compensation mechanism for the remote cell (F cell) during the deep aging stage is adjusted. For the F cell, in the early stage of aging (e.g., WE < 500K), the write current of the F cell is adjusted from the base value (I0). reset,N base +I reset,comp,FMultiply the whole by the benchmark adjustment factor (k) 1F ,k 2F In the deep aging stage (e.g., WE≥500K), the compensation mechanism is upgraded to a dual-component independent control hybrid model, i.e., the compensation current I... reset,comp,F First multiply by the corresponding compensation adjustment coefficient (k) 3comp,F or k 4comp,F ) is independently amplified, and then compared with the reference current (I) reset，N base After adding them together, multiply the result by the corresponding baseline adjustment factor (k). 3F or k 4F This application demonstrates a switch to a more refined and powerful dual-path compensation model at more severe aging stages (e.g., WE≥500K), thereby enabling the most accurate and powerful targeted compensation for accelerated aging of remote cells.

[0068] In other embodiments, please refer to Figure 10 , Figure 10 This is a flowchart illustrating the calculation of the write current (Ireset, N) of the first memory cell, provided in an embodiment of this application. The example assumes the memory includes only the first and second cells, and the write count region includes the first, second, and third write count regions. The memory current compensation method includes the following steps: S401, determine whether it is the first storage unit.

[0069] If it is the first storage unit, then execute S402; if it is not the first storage unit, then execute S406.

[0070] S402, determine the number of writes to the first storage unit (WE).

[0071] If the number of writes WE is less than the first preset value (e.g., 100K), i.e., WE<100K, then S403 is executed.

[0072] If the number of writes WE is between the first preset value (e.g., 100K) and the second preset value (e.g., 1M), i.e. 100K≤WE<1M, then execute S404.

[0073] If the number of writes WE is greater than or equal to the second preset value (e.g., 1M), i.e. WE≥1M, then execute S405.

[0074] S403, using the first reference current (I) of the first memory cell reset,N base ) as the write current of the first memory cell (I reset,N ), i.e. I reset,N =I reset,N base .

[0075] S404, using the first reference current (I) of the first memory cell reset,N baseMultiply by the first benchmark adjustment factor (k) 1N ), to obtain the write current (I) of the first memory cell. reset,N ), i.e. I reset,N =I reset,N base ×k 1N .

[0076] S405, using the first reference current (I) of the first memory cell reset,N base Multiply by the second benchmark adjustment factor (k) 2N ), to obtain the write current (I) of the first memory cell. reset,N ), i.e. I reset,N =I reset,N base ×k 2N .

[0077] S406, determine the number of writes to the second storage unit (WE).

[0078] If the number of writes WE is less than the first preset value (e.g., 100K), i.e., WE<100K, then S407 is executed.

[0079] If the number of writes WE is between the first preset value (e.g., 100K) and the second preset value (e.g., 1M), i.e. 100K≤WE<1M, then execute S308.

[0080] If the number of writes WE is greater than or equal to the second preset value (e.g., 1M), i.e. WE≥1M, then execute S409.

[0081] S407, Obtain the second reference current (I) of the second memory cell. reset,F base ) as the write current of the second memory cell (I reset,F ), i.e. I reset,F =I reset,F base .

[0082] S408, using the second reference current (I) of the second memory cell reset,F base Multiply by the third benchmark adjustment factor (k) 1F ), to obtain the write current (I) of the second memory cell reset,F ), i.e. I reset,F =I reset,F base ×k 1F .

[0083] S409, using the second reference current (I) of the second memory cell reset,F base Multiply by the fourth benchmark adjustment factor (k) 2F ), to obtain the write current (I) of the second memory cell reset,F ), i.e. I reset,F =I reset,F base ×k 2F .

[0084] The above steps demonstrate the use of different baseline adjustment factors (k) based on the type of storage cell (first storage cell N Cell or second storage cell FCell) and different lifespan stages (determined by the number of writes WE). 1N k 2N k 1F k 2F This is used to calculate the write current of the corresponding memory cell in order to compensate for the write performance of the memory.

[0085] In other embodiments, please refer to Figure 11 , Figure 11 This application embodiment provides a method for calculating the write current (I) of the second memory cell. reset,F The flowchart of the current compensation method for the memory includes the following steps: S501, determine whether it is the first storage unit.

[0086] If it is the first storage cell (N Cell), then execute S502; if it is not the first storage cell, then execute S506.

[0087] S502, determine the number of writes to the first storage unit (WE).

[0088] If the number of writes WE is less than the first preset value (e.g., 100K), i.e., WE<100K, then S503 is executed.

[0089] If the number of writes WE is between the first preset value (e.g., 100K) and the second preset value (e.g., 1M), i.e. 100K≤WE<1M, then S504 is executed.

[0090] If the number of writes WE is greater than or equal to the second preset value (e.g., 1M), i.e. WE≥1M, then S505 is executed.

[0091] S503 uses the reference current (I) of the first memory cell. reset,N base ) as the write current of the first memory cell (I reset,N ), i.e. I reset,N =I reset,N base .

[0092] S504 uses the reference current (I) of the first memory cell. reset,N base Multiplying this by the first reference adjustment factor (k1) yields the write current (I) of the first memory cell. reset,N ), i.e. I reset,N =I reset,N base ×k1.

[0093] S505 uses the reference current (I) of the first memory cell. reset,N baseMultiplying this by the second reference adjustment factor (k2) yields the write current (I) of the first memory cell. reset,N ), i.e. I reset,N =I reset,N base ×k2.

[0094] S506, determine the number of writes to the second storage unit (WE).

[0095] If the number of writes WE is less than the first preset value (e.g., 100K), i.e., WE<100K, then S507 is executed.

[0096] If the number of writes WE is between the first preset value (e.g., 100K) and the second preset value (e.g., 1M), i.e. 100K≤WE<1M, then execute S508.

[0097] If the number of writes WE is greater than or equal to the second preset value (e.g., 1M), i.e. WE≥1M, then execute S509.

[0098] S507, obtain the reference current (I) of the first memory cell. reset,N base ) and compensation current (I reset comp,F The sum of these two values ​​is used as the write current (I) of the second memory cell. reset,F ), i.e. I reset,F =I reset,N base + I reset comp,F .

[0099] S508 uses the reference current (I) of the first memory cell. reset,N base Multiplying this by the first baseline adjustment factor (k1) yields the first adjustment component (I). reset,N base ×k1); and will compensate the current (I) reset comp,F Multiply by the first compensation adjustment factor k 1comp The second adjustment component (I) is obtained. reset comp ×k 1comp The first adjustment component and the second adjustment component are added together to obtain the write current (I) of the second memory cell. reset,F ), i.e. I reset,F =I reset,N base ×k1+ I reset comp,F ×k 1comp .

[0100] S509, using the base current (I) of the first memory cell reset,N base Multiplying this by the second baseline adjustment factor (k2) yields the third adjustment component (I). reset,N base ×k2); and will compensate the current (I) reset comp,F Multiply by the second compensation adjustment factor k 2comp The fourth adjustment component (I) is obtained. reset comp,F ×k 2compThe third adjustment component and the fourth adjustment component are added together to obtain the write current (I) of the second memory cell. reset,F ), i.e. I reset,F =I reset,N base ×k2+ I reset comp,F ×k 2comp .

[0101] The above steps demonstrate the use of different current adjustment coefficients (k1, k2, k...) based on the type of storage cell (first storage cell N Cell or second storage cell FCell) and different lifespan stages (which can be determined by the number of writes WE). 1comp k 2comp This is used to calculate the write current of the corresponding memory cell in order to compensate for the write performance of the memory.

[0102] On the other hand, this embodiment provides a memory, including: drive transistor; The target storage unit controlled by the driving transistor includes a first storage unit and a second storage unit, wherein the electrical distance between the second storage unit and the driving transistor is greater than the electrical distance between the first storage unit and the driving transistor; The current compensation module is configured as follows: Obtain the base current of the target memory cell; The number of writes to the target storage cell is obtained, and the current adjustment coefficient of the target storage cell is obtained based on the number of writes. The base current is adjusted using the current adjustment coefficient to obtain the write current of the target memory cell; The write current is applied to the target memory cell to complete the write operation; Wherein, the base current of the second storage cell is greater than the base current of the first storage cell, and for the same number of writes, the current adjustment coefficient of the second storage cell is not less than the current adjustment coefficient of the first storage cell.

[0103] Understandably, this memory can adopt a three-dimensional array structure (i.e., a memory array), containing driver transistors and multiple groups of memory cells (such as N-cells and F-cells) controlled by them. Each driver transistor controls a local group of memory cells to form a compensation domain. The cell status is fed back in real time through a monitoring circuit, achieving precise current control throughout the entire lifecycle. Among these, F-cells exhibit significant RC delay due to their longer wiring distance. The dynamic compensation mechanism of the current compensation module is as follows: 1) The current is adjusted in stages according to the number of writes (WE). Initially (e.g., WE < 100K times), a reference current is used; in the middle stage (e.g., 100K ≤ WE < 1M times), the initial current adjustment coefficient (e.g., k1 / k) is used. 1N / k1F or k 1comp Later (e.g., WE≥1M times), switch to higher-order coefficients (k2 / k). 2N / k 2F or k 2comp ); 2) Differentiated compensation strategy, using an independent near-end amplification factor or reference adjustment factor to adjust the base current (e.g., I) for the near-end N-cell. reset,N base For the remote F-cell, enhanced compensation is achieved through an independent remote coefficient or a combination of "baseline adjustment coefficient + compensation adjustment coefficient". Experimental verification shows that this application can increase the threshold voltage of the F-cell by 50mV after 1.2M WE cycles, effectively solving the problem of F-cell write failure caused by uniform compensation in traditional solutions.

[0104] This embodiment also provides a computer-readable storage medium having a computer program stored thereon, the computer program being loaded by a processor to perform the steps of any of the methods in the above embodiments.

[0105] In the embodiments of this application, the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0106] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0107] The foregoing has provided a detailed description of a current compensation method for a memory, the memory itself, and the storage medium provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A current compensation method for a memory, characterized in that, The memory includes a driver transistor and a target memory cell controlled by the driver transistor; the method includes: Obtain the base current of the target memory cell; The number of writes to the target storage cell is obtained, and the current adjustment coefficient of the target storage cell is obtained based on the number of writes. The base current is adjusted using the current adjustment coefficient to obtain the write current of the target memory cell; The write current is applied to the target memory cell to complete the write operation; The target storage unit includes a first storage unit and a second storage unit. The electrical distance between the second storage unit and the driving transistor is greater than the electrical distance between the first storage unit and the driving transistor. The base current of the second storage unit is greater than the base current of the first storage unit, and for the same number of writes, the current adjustment coefficient of the second storage unit is not less than the current adjustment coefficient of the first storage unit.

2. The current compensation method for a memory according to claim 1, characterized in that, Obtaining the base current of the target memory cell includes: Determine the electrical distance region where the target storage unit is located, and obtain the base current corresponding to the target storage unit based on the electrical distance region; the base current corresponding to different electrical distance regions is different.

3. The current compensation method for the memory according to claim 1, characterized in that, The current adjustment coefficient of the target memory cell is obtained based on the number of writes, including: Determine the write count region where the write count is located, and obtain the current adjustment coefficient corresponding to the target storage cell based on the write count region and the electrical distance region; The write count region includes multiple stages, with different stages corresponding to different current adjustment coefficients, and the same target storage cell includes at least two or two sets of different current adjustment coefficients.

4. The current compensation method for the memory according to any one of claims 1 to 3, characterized in that, The base current includes a reference current, and the current adjustment coefficient includes a reference adjustment coefficient; adjusting the base current using the current adjustment coefficient to obtain the write current of the target memory cell includes: The obtained reference current is multiplied by the obtained reference adjustment coefficient to obtain the corresponding write current.

5. The current compensation method for a memory according to claim 4, characterized in that, The memory includes a first electrical distance region and a second electrical distance region. The reference current includes a first reference current and a second reference current. The electrical distance of the first memory cell is located within the first electrical distance region, and the electrical distance of the second memory cell is located within the second electrical distance region. The memory also includes a first write count region and a second write count region corresponding to the first electrical distance region, a third write count region and a fourth write count region corresponding to the second electrical distance region, and the reference adjustment coefficient includes a first reference adjustment coefficient, a second reference adjustment coefficient, a third reference adjustment coefficient, and a fourth reference adjustment coefficient. The step of multiplying the acquired reference current by the acquired reference adjustment coefficient to obtain the corresponding write current includes: When the target storage unit is the first storage unit and the number of writes is within the first number of writes range, the first reference current is multiplied by the first reference adjustment coefficient to obtain the write current; When the target storage cell is the first storage cell and the number of writes is within the second number of writes region, the first reference current is multiplied by the second reference adjustment coefficient to obtain the write current; When the target storage cell is the second storage cell and the number of writes is within the third number of writes region, the second reference current is multiplied by the third reference adjustment coefficient to obtain the write current; When the target storage unit is the second storage unit and the number of writes is within the fourth number of writes region, the second reference current is multiplied by the fourth reference adjustment coefficient to obtain the write current.

6. The current compensation method for the memory according to any one of claims 1 to 3, characterized in that, The base current includes a reference current and a compensation current, and the current adjustment coefficient includes a reference adjustment coefficient and a compensation adjustment coefficient; The step of adjusting the base current using the current adjustment coefficient to obtain the write current of the target memory cell includes: The obtained reference current is multiplied by the obtained reference adjustment coefficient to obtain a first adjustment component, and the obtained compensation current is multiplied by the obtained compensation adjustment coefficient to obtain a second adjustment component. The first adjustment component and the second adjustment component are added together to obtain the corresponding write current.

7. The current compensation method for a memory according to claim 6, characterized in that, The memory includes a first electrical distance region and a second electrical distance region, and the compensation current includes a first compensation current and a second compensation current. The electrical distance of the first memory cell is located within the first electrical distance region, and the electrical distance of the second memory cell is located within the second electrical distance region. The memory also includes a first write count region and a second write count region. The reference adjustment coefficient includes a first reference adjustment coefficient and a second reference adjustment coefficient. The compensation adjustment coefficient includes a first compensation adjustment coefficient, a second compensation adjustment coefficient, a third compensation adjustment coefficient, and a fourth compensation adjustment coefficient. The write current of the target memory cell includes: When the target storage unit is the first storage unit and the number of writes is within the first number of writes range, the reference current is multiplied by the first reference adjustment coefficient to obtain the first adjustment component, the first compensation current is multiplied by the first compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current. When the target storage cell is the first storage cell and the number of writes is within the second number of writes region, the reference current is multiplied by the second reference adjustment coefficient to obtain the first adjustment component, the first compensation current is multiplied by the second compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current. When the target storage unit is the second storage unit and the number of writes is within the first number of writes range, the reference current is multiplied by the first reference adjustment coefficient to obtain the first adjustment component, the second compensation current is multiplied by the third compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current. When the target storage unit is the second storage unit and the number of writes is within the second number of writes range, the reference current is multiplied by the second reference adjustment coefficient to obtain the first adjustment component, the second compensation current is multiplied by the fourth compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current.

8. The current compensation method for a memory according to claim 6, characterized in that, The memory includes a first electrical distance region and a second electrical distance region. The base current includes a first reference current, a second reference current, a first compensation current, and a second compensation current. The electrical distance of the first memory cell is located within the first electrical distance region, and the electrical distance of the second memory cell is located within the second electrical distance region. The memory also includes a first write count region and a second write count region corresponding to the first electrical distance region, a third write count region and a fourth write count region corresponding to the second electrical distance region, and the reference adjustment coefficient includes a first reference adjustment coefficient, a second reference adjustment coefficient, a third reference adjustment coefficient, and a fourth reference adjustment coefficient. The compensation adjustment coefficient includes a first compensation adjustment coefficient, a second compensation adjustment coefficient, a third compensation adjustment coefficient, and a fourth compensation adjustment coefficient. The write current of the target memory cell includes: When the target storage unit is the first storage unit and the number of writes is within the first number of writes range, the first reference current is multiplied by the first reference adjustment coefficient to obtain the first adjustment component, the first compensation current is multiplied by the first compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current. When the target storage cell is the first storage cell and the number of writes is within the second number of writes region, the first reference current is multiplied by the second reference adjustment coefficient to obtain the first adjustment component, the first compensation current is multiplied by the second compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current. When the target storage unit is the second storage unit and the number of writes is within the third number of writes region, the second reference current is multiplied by the third reference adjustment coefficient to obtain the first adjustment component, the second compensation current is multiplied by the third compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current. When the target storage unit is the second storage unit and the number of writes is within the fourth number of writes region, the second reference current is multiplied by the fourth reference adjustment coefficient to obtain the first adjustment component, the second compensation current is multiplied by the fourth compensation adjustment coefficient to obtain the second adjustment component, and the first adjustment component and the second adjustment component are added to obtain the write current.

9. The current compensation method for a memory according to claim 1, characterized in that, Also includes: The memory also includes a first write count region and a second write count region; When the number of writes is within the first number of writes region, the current compensation method for the memory as described in claim 4 or 5 is adopted; When the number of writes is within the second number of writes region, the current compensation method of the memory as described in claim 6 or 7 is adopted.

10. A memory, characterized in that, include: drive transistor; The target storage unit controlled by the driving transistor includes a first storage unit and a second storage unit, wherein the electrical distance between the second storage unit and the driving transistor is greater than the electrical distance between the first storage unit and the driving transistor; The current compensation module is configured as follows: Obtain the base current of the target memory cell; The number of writes to the target storage cell is obtained, and the current adjustment coefficient of the target storage cell is obtained based on the number of writes. The base current is adjusted using the current adjustment coefficient to obtain the write current of the target memory cell; The write current is applied to the target memory cell to complete the write operation; Wherein, the base current of the second storage cell is greater than the base current of the first storage cell, and for the same number of writes, the current adjustment coefficient of the second storage cell is not less than the current adjustment coefficient of the first storage cell.

11. A computer-readable storage medium, characterized in that, It stores a computer program, which is loaded by a processor to execute the steps of the current compensation method for the memory according to any one of claims 1-9.

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