A circuit monitoring method and apparatus

Abstract

Embodiments of the present application disclose a circuit monitoring method and device; the embodiments of the present application can perform Fourier transform processing on the current signals of each power supply circuit in a preset time window to obtain a current vector corresponding to each power supply circuit, the current vector including a real part and an imaginary part; for the current vector corresponding to each power supply circuit, the real part and the imaginary part of the current vector are encoded respectively to obtain a real part floating point value and an imaginary part floating point value; the real part floating point value is determined and written into a corresponding real part floating point storage area, and the imaginary part floating point value is determined and written into a corresponding imaginary part floating point storage area, so that a host device reads the real part floating point value and the imaginary part floating point value corresponding to each power supply circuit from the floating point storage area of an edge gateway device, and determines the running state of the corresponding power supply circuit based on the real part floating point value and the imaginary part floating point value of any power supply circuit. Thus, the embodiments of the present application improve the data acquisition efficiency and analysis flexibility of the host device side.

Description

Technical Field

[0001] This application relates to the field of smart grid monitoring technology, specifically to a circuit monitoring method and device. Background Technology

[0002] With the development of the Internet of Things in the power industry, edge computing architecture is being gradually applied in substation monitoring systems. Edge gateway devices are deployed at the substation site to collect current and voltage signals from each power supply circuit nearby. After completing the data processing locally, the processing results are uploaded to the main station system.

[0003] However, most existing solutions employ two modes: one is to upload the original sampled waveform to the central node, which results in a large communication load and poor real-time performance; the other is for the edge terminal to directly calculate and upload the effective current value, which reduces bandwidth requirements but provides a single dimension of output data, making it difficult to support the diverse analysis needs of the main station. Both modes have limitations in balancing data volume and communication efficiency, making them unsuitable for efficient monitoring and comprehensive analysis in large-scale loop scenarios. Summary of the Invention

[0004] This application provides a circuit monitoring method and apparatus. By extracting the real and imaginary parts of the current vector corresponding to each power supply circuit locally on the edge gateway device, and encoding them in floating-point format, the data is written into a floating-point storage area independently configured for that circuit. This avoids the high communication load of uploading the original waveform and provides a richer data dimension than the effective value. It realizes the structured storage and efficient reading of multi-power supply circuit data, and improves the data acquisition efficiency and analysis flexibility on the main control device side.

[0005] This application provides a circuit monitoring method applied to an edge gateway device. The edge gateway device includes at least one power supply circuit and multiple floating-point storage areas corresponding to each power supply circuit. The floating-point storage areas corresponding to different power supply circuits do not overlap. The method includes:

[0006] Acquire the current signal of each power supply circuit within a preset time window;

[0007] Fourier transform is performed on the current signal corresponding to each power supply circuit to obtain the current vector corresponding to each power supply circuit. The current vector includes a real part and an imaginary part. The real part represents the projection component of the corresponding current signal on the reference cosine component, and the imaginary part represents the projection component of the corresponding current signal on the reference sine component.

[0008] For each power supply circuit, the real and imaginary parts of the current vector are encoded according to a preset floating-point format to obtain the real floating-point value and the imaginary floating-point value.

[0009] From the multiple floating-point storage areas corresponding to the power supply circuit, determine the real floating-point storage area corresponding to the real floating-point value and the imaginary floating-point storage area corresponding to the imaginary floating-point value;

[0010] The real part floating-point value is written to the corresponding real part floating-point storage area, and the imaginary part floating-point value is written to the corresponding imaginary part floating-point storage area, so that the master control device can read the real part floating-point value and imaginary part floating-point value corresponding to each power supply circuit from the floating-point storage area of ​​the edge gateway device, and determine the operating status of the corresponding power supply circuit based on the real part floating-point value and imaginary part floating-point value of any power supply circuit.

[0011] This application also provides a circuit monitoring device applied to an edge gateway device. The edge gateway device includes at least one power supply circuit and multiple floating-point storage areas corresponding to each power supply circuit. The floating-point storage areas corresponding to different power supply circuits do not overlap. The device includes:

[0012] The signal acquisition unit is used to acquire the current signal of each power supply circuit within a preset time window;

[0013] The signal transformation unit is used to perform Fourier transform processing on the current signals corresponding to each power supply circuit to obtain the current vector corresponding to each power supply circuit. The current vector includes a real part and an imaginary part. The real part represents the projection component of the corresponding current signal on the reference cosine component, and the imaginary part represents the projection component of the corresponding current signal on the reference sine component.

[0014] The encoding unit is used to encode the real part and imaginary part of the current vector for each power supply circuit according to a preset floating-point format, so as to obtain the real part floating-point value and the imaginary part floating-point value.

[0015] The region determination unit is used to determine, from multiple floating-point storage regions corresponding to the power supply circuit, the real floating-point storage region corresponding to the real floating-point value and the imaginary floating-point storage region corresponding to the imaginary floating-point value;

[0016] The floating-point value writing unit is used to write the real part floating-point value into the corresponding real part floating-point storage area and the imaginary part floating-point value into the corresponding imaginary part floating-point storage area, so that the master control device can read the real part floating-point value and imaginary part floating-point value corresponding to each power supply circuit from the floating-point storage area of ​​the edge gateway device, and determine the operating status of the corresponding power supply circuit based on the real part floating-point value and imaginary part floating-point value of any power supply circuit.

[0017] In some embodiments, acquiring the current signal of each power supply circuit within a preset time window includes:

[0018] The current of each power supply circuit is sampled according to the preset sampling frequency, and the current sampled values ​​are cached.

[0019] For each power supply circuit, when the number of buffered current sample values ​​reaches the preset number of samples corresponding to the preset time window, the buffered current sample values ​​are used as the current signal of the corresponding power supply circuit within the preset time window.

[0020] In some embodiments, the current signal is a discrete sequence of multiple current sample values ​​collected in chronological order within a preset time window for the corresponding power supply circuit.

[0021] Perform Fourier transform on the current signals corresponding to each power supply circuit to obtain the current vector for each power supply circuit. The current vector includes a real part and an imaginary part, including:

[0022] For the current signal of each power supply circuit, the harmonic angle index corresponding to each current sample value is calculated based on the preset harmonic order and the sampling point number corresponding to each current sample value.

[0023] Based on the harmonic angle index, the corresponding reference cosine value and reference sine value are obtained from the preset cosine lookup table and sine lookup table respectively;

[0024] The real part of the current vector is obtained by multiplying each current sample value within the preset time window with its corresponding reference cosine value and summing the results.

[0025] The imaginary part of the current vector is obtained by multiplying each current sample value within a preset time window with its corresponding reference sine value and summing the results.

[0026] In some embodiments, after encoding the real and imaginary parts of the current vector for each power supply circuit according to a preset floating-point format to obtain the real floating-point value and the imaginary floating-point value, the method further includes:

[0027] The real part floating-point value and the imaginary part floating-point value are split into multiple real part data fragments and multiple imaginary part data fragments respectively.

[0028] From the multiple floating-point storage areas corresponding to the power supply circuit, determine the real floating-point storage area corresponding to the real floating-point value and the imaginary floating-point storage area corresponding to the imaginary floating-point value, including:

[0029] From the multiple floating-point storage areas corresponding to the power supply circuit, determine the real floating-point storage area corresponding to each real data segment and the imaginary floating-point storage area corresponding to each imaginary data segment;

[0030] Writing the real part floating-point value to the corresponding real part floating-point storage area and writing the imaginary part floating-point value to the corresponding imaginary part floating-point storage area include:

[0031] Write each real part data segment to its corresponding real part floating-point storage area, and write each imaginary part data segment to its corresponding imaginary part floating-point storage area.

[0032] In some embodiments, before acquiring the current signal of each power supply circuit within a preset time window, the method further includes:

[0033] Obtain the number of power supply circuits with at least one power supply circuit;

[0034] Based on the number of power supply circuits, the number of floating-point value types corresponding to each power supply circuit, and the number of data fragments for each type of floating-point value, determine the total number of floating-point storage areas required.

[0035] Allocate the total number of floating-point storage areas from the local storage space of the edge gateway device.

[0036] In some embodiments, after allocating the total number of floating-point storage regions from the local storage space of the edge gateway device, the method further includes:

[0037] Based on the floating-point value type corresponding to each power supply circuit and the number of data segments for each floating-point value, a preset mapping relationship is established between the floating-point storage area and the floating-point value data segments;

[0038] From the multiple floating-point storage areas corresponding to the power supply circuit, determine the real floating-point storage area corresponding to the real floating-point value and the imaginary floating-point storage area corresponding to the imaginary floating-point value, including:

[0039] Based on the preset mapping relationship, the real part floating-point storage area corresponding to the real part floating-point value and the imaginary part floating-point value corresponding to the imaginary part floating-point value are determined from multiple floating-point storage areas corresponding to the power supply circuit.

[0040] In some embodiments, a preset mapping relationship between floating-point storage areas and floating-point data segments is established based on the floating-point value type corresponding to each power supply circuit and the number of data segment divisions for each floating-point value, including:

[0041] Based on the total number of floating-point storage areas, the floating-point value type corresponding to each power supply circuit, and the number of data fragments for each floating-point value, a region identifier is assigned to each floating-point storage area. The region identifiers of floating-point storage areas corresponding to different power supply circuits do not overlap.

[0042] Establish a preset mapping relationship between the region identifier of the floating-point storage area corresponding to each power supply circuit and the floating-point value data segment;

[0043] Based on a preset mapping relationship, the real floating-point storage region corresponding to the real floating-point value and the imaginary floating-point storage region corresponding to the imaginary floating-point value are determined from multiple floating-point storage regions corresponding to the power supply circuit, including:

[0044] From the preset mapping relationship, obtain the real region identifier corresponding to the real part floating-point value and the imaginary region identifier corresponding to the imaginary part floating-point value;

[0045] The real part floating-point storage area corresponding to the real part floating-point value is determined based on the real part region identifier, and the imaginary part floating-point storage area corresponding to the imaginary part floating-point value is determined based on the imaginary part region identifier.

[0046] In some embodiments, it also includes:

[0047] Receive communication requests sent by the master control device, the communication requests carrying the target address identifier;

[0048] When the target address identifier matches the device address of the edge gateway device, a communication response is returned to the master control device. The communication response contains the real part floating-point value and the imaginary part floating-point value corresponding to each power supply circuit.

[0049] In some embodiments, it also includes:

[0050] When the target address identifier does not match the device address of the edge gateway device, the communication request is discarded and no response is returned to the master device.

[0051] This application also provides an electronic device, including a processor and a memory, wherein the memory stores multiple instructions; the processor loads instructions from the memory to execute the steps in any of the circuit monitoring methods provided in this application.

[0052] This application also provides a computer-readable storage medium storing a plurality of instructions adapted for loading by a processor to execute the steps in any of the circuit monitoring methods provided in this application.

[0053] This application also provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps in any of the circuit monitoring methods provided in this application.

[0054] In this application, after acquiring the current signals of each power supply circuit within a preset time window, the edge gateway device performs Fourier transform processing on the current signals corresponding to each power supply circuit to obtain a current vector for each power supply circuit, which includes a real part and an imaginary part. This transform compresses the original time-domain waveform into frequency-domain fundamental characteristics, avoiding the uploading of high-sampling-rate original waveform data to the main control device, thereby significantly reducing the subsequent communication load. Subsequently, for the current vector corresponding to each power supply circuit, the real and imaginary parts of the current vector are encoded separately according to a preset floating-point format to obtain real floating-point values ​​and imaginary floating-point values. This encoding method converts continuous vector components into standard floating-point representations, which, compared to only uploading scalar effective values, preserves the complete complex characteristics of the current signal and facilitates interfacing with register data formats in industrial communication protocols. Furthermore, from the multiple floating-point storage areas corresponding to the power supply circuit, the real floating-point storage area corresponding to the real part floating-point value and the imaginary floating-point storage area corresponding to the imaginary floating-point value are determined. The real floating-point value is then written into the corresponding real floating-point storage area, and the imaginary floating-point value is written into the corresponding imaginary floating-point storage area. Since the floating-point storage areas corresponding to different power supply circuits do not overlap, and the real and imaginary parts are mapped to independent floating-point storage areas respectively, the data of each power supply circuit is physically or logically isolated and structurally organized. Through this mechanism, the data of each power supply circuit is stored independently and structurally, facilitating efficient on-demand reading by external master control equipment. Compared to uploading the raw waveform of the current signal (high communication load) or only uploading the valid value (single data dimension), this scheme significantly reduces communication overhead while providing complex data containing more feature information, thereby achieving structured organization and efficient access to multi-power supply circuit data. This improves the data acquisition efficiency and analysis flexibility of the master control equipment. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic flowchart of a circuit monitoring method provided in an embodiment of this application;

[0057] Figure 2 This is a schematic diagram of the structure of a circuit monitoring device provided in an embodiment of this application. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0059] This application provides a circuit monitoring method and apparatus.

[0060] One type of circuit monitoring device can be integrated into an electronic device, such as a terminal or server. The terminal can be a mobile phone, tablet, smart Bluetooth device, laptop, or personal computer (PC); the server can be a single server or a server cluster consisting of multiple servers.

[0061] In some embodiments, the circuit monitoring device can also be integrated into multiple electronic devices. For example, the circuit monitoring device can be integrated into multiple servers, and the circuit monitoring method of this application can be implemented by multiple servers.

[0062] In some embodiments, the server may also be implemented as a terminal.

[0063] The following sections provide detailed descriptions of each example. It should be noted that the sequence numbers of the following embodiments are not intended to limit the preferred order of the embodiments.

[0064] In this embodiment, a circuit monitoring method is provided, applied to an edge gateway device. The edge gateway device includes at least one power supply circuit and multiple floating-point storage areas corresponding to each power supply circuit. The floating-point storage areas corresponding to different power supply circuits do not overlap. Figure 1 The specific process of this circuit monitoring method can be shown as follows:

[0065] Among them, edge gateway devices refer to intelligent terminal devices deployed in circuit monitoring scenarios (such as substations, power distribution rooms, etc.), which have data acquisition, local computing and communication capabilities, are used to connect one or more power supply circuits and provide the processed monitoring data to the main control device; the device usually integrates analog signal acquisition modules, microcontrollers and communication interfaces (such as RS-485, Ethernet, etc.), and can complete signal processing and protocol conversion at a location close to the data source.

[0066] A power supply loop refers to an independent electrical path from a power source to an electrical load, such as a feeder, an outgoing line bay, or a distribution branch. Each power supply loop can be configured with a current transformer (CT) for real-time sampling of its current signal. In this application, the edge gateway device can monitor multiple power supply loops simultaneously, with each loop electrically isolated and logically independent from the others.

[0067] A floating-point storage area refers to a logical or physical storage unit in the local storage space of an edge gateway device used to store floating-point format data. Each power supply loop corresponds to multiple floating-point storage areas, which are used to store different types of floating-point data such as their real floating-point values ​​and imaginary floating-point values. The floating-point storage areas corresponding to different power supply loops do not overlap, ensuring data isolation and conflict-free access.

[0068] 101. Obtain the current signal of each power supply circuit within the preset time window.

[0069] The preset time window refers to a pre-configured time interval of fixed duration used to limit the acquisition cycle of the current signal. This time window is usually set to an integer multiple of the power grid frequency cycle (e.g., 20ms for a 50Hz system) (e.g., 1, 2, or 10 cycles) to ensure that the Fourier transform processing meets the whole-cycle sampling condition, avoids spectral leakage, and thus improves the accuracy of current vector calculation.

[0070] The current signal refers to the digital sequence formed by analog current values ​​collected in real time from each power supply circuit through a current transformer (CT) or similar sensing device and then converted from analog to digital. In this application, the current signal is specifically represented as a time-domain sequence composed of discrete current sample values ​​continuously collected at a preset sampling frequency within a preset time window, which is used for subsequent Fourier transform processing.

[0071] In some embodiments, by performing fixed-frequency sampling and counting control under the timer interrupt mechanism of the edge gateway device, it is ensured that the current signal of each power supply circuit strictly covers a complete and aligned power frequency cycle time window. This provides input data that meets the integer cycle sampling condition for subsequent Fourier transforms, effectively avoiding spectral leakage caused by non-integer cycle truncation, and significantly improving the calculation accuracy of the current vector (real and imaginary parts). Simultaneously, in resource-constrained environments without an operating system, this mechanism ensures the stability and real-time performance of multi-circuit data acquisition with deterministic timing and minimal buffer overhead, obtaining the current signal of each power supply circuit within a preset time window, including:

[0072] The current of each power supply circuit is sampled according to the preset sampling frequency, and the current sampled values ​​are cached.

[0073] For each power supply circuit, when the number of buffered current sample values ​​reaches the preset number of samples corresponding to the preset time window, the buffered current sample values ​​are used as the current signal of the corresponding power supply circuit within the preset time window.

[0074] The preset sampling frequency refers to the effective frequency at which current sampling is performed on each power supply circuit in the edge gateway device, determined by its timer interrupt mechanism (e.g., a 1ms timer interrupt). This frequency is determined by the interrupt period and the number of power supply circuits polled in each interrupt.

[0075] The current sample value refers to the digital current value obtained from the power supply circuit through the current transformer (CT) and analog-to-digital conversion circuit at a certain moment. It is usually represented in the form of a signed integer or fixed-point number and is the basic unit that constitutes the current signal.

[0076] The number of current sample values ​​refers to the cumulative number of current sample values ​​that have been cached for a specific power supply circuit within the current sampling period, which increases in real time as the sampling process progresses.

[0077] The preset sampling quantity refers to the total number of current sample values ​​that need to be collected within a preset time window for each power supply circuit to meet the requirements of full-cycle frequency domain analysis. This quantity is determined by the duration of the preset time window and the effective sampling frequency of the circuit, and is used to determine whether a complete analysis window of data acquisition has been completed in the timed interrupt process of the edge gateway device; when the number of current sample values ​​buffered in a power supply circuit reaches the preset sampling quantity, the subsequent Fourier transform processing is triggered.

[0078] For example, in a 50Hz power grid system, to meet the requirement of full-cycle sampling for the Fast Fourier Transform (FFT), the system needs to ensure that the acquired current signal covers an integer number of power frequency cycles (each cycle is 20ms). If a 128-point FFT is used for fundamental frequency analysis, the preset sampling number is set to 128. In this embodiment, the edge gateway device is a bare-metal embedded terminal, and the sampling process is driven by a 1ms timer interrupt. Assuming that the system needs to monitor 8 power supply circuits simultaneously, each circuit is sampled once in each 1ms interrupt service routine, that is, each circuit is sampled once every 8ms, and its effective sampling frequency is 125Hz. To ensure that the 128 sampling points exactly cover an integer number of power frequency cycles, the preset time window is configured as: 128 points × 8ms / point = 1024ms. Since 1024ms ÷ 20ms = 51.2, which is not an integer, the window length will be adjusted to the nearest integer multiple of the power frequency cycle in actual engineering. For example, 51 cycles (1020ms) can be selected to correspond to 127.5 points (not feasible). Or, more reasonably, a 64-point FFT + 512ms window (25.6 cycles) can be selected → adjusted to 26 cycles = 520ms → 65 points. However, for the sake of simplicity, this embodiment takes 128 points and a 1024ms window as an example. In the software, the spectrum leakage is ensured to be controllable by aligning the sampling start phase or compensating the window function. Alternatively, with hardware support, the interrupt cycle can be fine-tuned (e.g., 0.992ms) to make the 128 points strictly aligned with 51 cycles (1020ms).

[0079] In actual operation, each time a 1ms interrupt occurs, the system polls the current power supply circuit, performs an A / D conversion, obtains a current sample value, appends it to the sampling buffer of that circuit, and increments the current sample value count of that circuit by 1. When the number of sample values ​​for a circuit reaches the preset sampling count (e.g., 128), it is determined that the data acquisition of a complete analysis window has been completed. Subsequently, Fourier transform processing of the current signal of that circuit is triggered to generate the real and imaginary parts of the current vector, which are then encoded according to the preset floating-point format and written to the corresponding floating-point storage area.

[0080] In some embodiments, by pre-planning storage resources dynamically, it is ensured that all types of floating-point values ​​(such as real and imaginary parts) of each power supply circuit have independent and fixed storage locations, avoiding runtime address conflicts or fragmentation, improving the determinism and efficiency of the main control device reading data through standard industrial protocols (such as MODBUS), and reducing the complexity of memory management in an operating system-less environment. Before acquiring the current signal of each power supply circuit within a preset time window, the following steps are also included:

[0081] Obtain the number of power supply circuits with at least one power supply circuit;

[0082] Based on the number of power supply circuits, the number of floating-point value types corresponding to each power supply circuit, and the number of data fragments for each type of floating-point value, determine the total number of floating-point storage areas required.

[0083] Allocate the total number of floating-point storage areas from the local storage space of the edge gateway device.

[0084] The number of power supply circuits refers to the total number of power supply circuits connected to and monitored by the current edge gateway device, such as 8 or 16. This number can be obtained through hardware configuration or software parameter settings during the device initialization phase.

[0085] The number of floating-point value types refers to the number of different types of floating-point data that need to be generated and stored for each power supply circuit. In this application, at least the real and imaginary parts of the current vector are included, so the number of floating-point value types is usually 2; if the support for parameters such as voltage and power is extended, this number can be increased accordingly.

[0086] The data fragmentation count refers to the number of consecutive data fragments into which a floating-point value (such as a 32-bit IEEE 754 single-precision floating-point number) is split according to the target communication protocol or register width requirements. For example, in the MODBUS protocol, each register is 16 bits, and a 32-bit floating-point value needs to be split into two fragments: the high 16 bits and the low 16 bits. In this case, the data fragmentation count is 2.

[0087] The total quantity refers to the total number of floating-point storage areas allocated to all power supply circuits. The formula for calculating the total quantity is: Total quantity = Number of power supply circuits × Number of floating-point value types × Number of data fragments.

[0088] Local storage space refers to the non-volatile or volatile memory (such as SRAM, Flash, or register mapping area) integrated inside the edge gateway device, used to cache the processed monitoring data. Its address space can be directly accessed by the master control device through the communication interface.

[0089] For example, assuming the edge gateway device connects to 8 power supply loops (number of power supply loops = 8), each loop needs to store the real and imaginary parts of the current vector (number of floating-point value types = 2), and each 32-bit floating-point value needs to be split into two 16-bit data segments according to the MODBUS protocol (number of data segment splits = 2), then the total number of floating-point storage areas required is: 8 × 2 × 2 = 32. During the initialization phase, the system allocates 32 floating-point storage areas (actually 32 16-bit register units) continuously or according to rules from the local storage space and establishes an index mapping relationship. Subsequently, when writing real / imaginary floating-point values, the corresponding floating-point storage area can be directly located, and the master control device can also efficiently read complete complex data through standard register addresses.

[0090] 102. Perform Fourier transform processing on the current signals corresponding to each power supply circuit to obtain the current vector corresponding to each power supply circuit. The current vector includes a real part and an imaginary part. The real part represents the projection component of the corresponding current signal on the reference cosine component, and the imaginary part represents the projection component of the corresponding current signal on the reference sine component.

[0091] The current vector, in this context, refers to the complex form obtained by performing a Fourier transform on the current signal of the power supply circuit. It is used to characterize the amplitude and phase information of the current at a specified frequency (such as the fundamental frequency or a certain harmonic). The current vector consists of a real part and an imaginary part. Its magnitude (amplitude) reflects the effective value of the current, and its argument reflects the phase shift relative to the reference phase.

[0092] The real part refers to the projection of the current vector onto the reference cosine component (i.e., the in-phase component). Mathematically, it is equal to the inner product of the current signal and the reference cosine function within a preset time window, and is used to characterize the in-phase component of the current and the reference cosine wave.

[0093] The reference cosine component refers to the standard cosine function used in Fourier transform to extract the in-phase component of a current signal. Its frequency is consistent with the harmonic frequency to be analyzed, and its initial phase is usually set to 0. This component, together with the reference sine component, forms a set of orthogonal basis functions, which are used to decompose the time-domain current signal into real (in-phase) and imaginary (orthogonal) components with clear physical meaning, thereby preserving the amplitude and phase information of the current.

[0094] The imaginary part refers to the projection of the current vector onto the reference sine component (i.e., the orthogonal component). Mathematically, it is equal to the inner product of the current signal and the reference sine function within a preset time window, and is used to characterize the orthogonal component of the current and the reference sine wave.

[0095] The reference sine component refers to the standard sine function used in Fourier transform to extract the orthogonal components of a current signal. Its frequency is consistent with the harmonic frequency to be analyzed, and its initial phase is usually set to 0. This component is orthogonal to the reference cosine component (90° out of phase), together forming an orthogonal basis on the complex plane, used to decompose the phase information of the current signal.

[0096] In some embodiments, the core operation of Fourier transform is implemented by using a lookup table method, avoiding real-time trigonometric function calculations, significantly reducing the processor's computational burden, improving algorithm execution efficiency, and making it suitable for resource-constrained embedded leakage current monitoring devices, while ensuring harmonic analysis accuracy. The current signal is a discrete sequence composed of multiple current sample values ​​collected sequentially within a preset time window for the corresponding power supply circuit;

[0097] Perform Fourier transform on the current signals corresponding to each power supply circuit to obtain the current vector for each power supply circuit. The current vector includes a real part and an imaginary part, including:

[0098] For the current signal of each power supply circuit, the harmonic angle index corresponding to each current sample value is calculated based on the preset harmonic order and the sampling point number corresponding to each current sample value.

[0099] Based on the harmonic angle index, the corresponding reference cosine value and reference sine value are obtained from the preset cosine lookup table and sine lookup table respectively;

[0100] The real part of the current vector is obtained by multiplying each current sample value within the preset time window with its corresponding reference cosine value and summing the results.

[0101] The imaginary part of the current vector is obtained by multiplying each current sample value within a preset time window with its corresponding reference sine value and summing the results.

[0102] The time sequence refers to the order in which the current sampling values ​​are arranged according to the actual time of occurrence, ensuring the integrity of the signal timing.

[0103] The current sampling value refers to the digital quantity obtained by quantizing the phase current of the power supply circuit at a specific moment through a current transformer and an analog-to-digital converter (ADC). The unit is usually an integer or floating-point value.

[0104] A discrete sequence refers to a digital signal sequence consisting of a finite number of current sample values ​​arranged in time sequence; it is a discretized representation of a continuous current signal.

[0105] The preset harmonic order refers to the multiple of the target analysis frequency set by the user or system relative to the fundamental frequency. For example, 1 represents the fundamental frequency (50Hz), 3 represents the third harmonic (150Hz), etc.

[0106] The sampling point number refers to the position number of each current sampling value within a preset time window. It starts from 0 or 1 and increments sequentially. It is used to identify the relative time position of each sampling point in the window. Specifically, it can be i=0,1,…,N−1.

[0107] Harmonic Angle Index The "%" symbol represents the modulo operation, which is used to map angles to the valid index range of the lookup table.

[0108] The cosine lookup table is a pre-calculated and stored array of reference cosine values ​​that corresponds one-to-one with the sampling point number, satisfying... .

[0109] A sine lookup table refers to a pre-calculated and stored array of reference sine values ​​that corresponds one-to-one with the sampling point index, satisfying... .

[0110] The reference cosine value refers to the reference cosine function value cos(2π·π / 2) at the i-th sampling point under a specified harmonic frequency. ·i / N), where Where is the harmonic order, N is the total number of sampling points, and i is the sampling point number.

[0111] The reference sine value refers to the reference sine function value sin(2π·π / 2) at the i-th sampling point under a specified harmonic frequency. ·i / N), meaning the same as above.

[0112] The specific calculation process for performing Fourier transform on the current signal of the power supply circuit is as follows:

[0113] ,For example =1 indicates that the fundamental frequency is being analyzed. =3 represents the third harmonic;

[0114] ;

[0115] org[i]: The i-th current sample value, i=0,1,…,N−1;

[0116] , This indicates a modulo operation, ensuring that the index is in the range [0, N−1].

[0117] , , That is, the inner product of the current sample value and the reference cosine value;

[0118] , , That is, the inner product of the current sample value and the reference sine value.

[0119] 103. For the current vector corresponding to each power supply circuit, encode the real part and imaginary part of the current vector according to the preset floating-point format to obtain the real part floating-point value and the imaginary part floating-point value.

[0120] The preset floating-point format refers to the pre-configured binary floating-point encoding standard used to represent the real or imaginary part of the value. In this embodiment, the IEEE 754 single-precision (32-bit) or double-precision (64-bit) floating-point format is typically used; preferably, to balance accuracy and storage efficiency, the IEEE 754 single-precision floating-point format (32-bit) is used, which consists of 1 sign bit, 8 exponent bits, and 23 mantissa bits.

[0121] The real part floating-point value refers to the floating-point number obtained by encoding the real part of the current vector according to the preset floating-point format, which is used to characterize the active component characteristics of the current signal.

[0122] The imaginary floating-point value refers to the floating-point number obtained by encoding the imaginary part of the current vector (i.e., the projection component of the fundamental current on the orthogonal axis) according to the preset floating-point format, and is used to characterize the reactive component characteristics of the current signal.

[0123] For example, after completing a 128-point FFT, the current vector calculation result for a certain power supply circuit is: real part = 120.5A, imaginary part = -45.3A. The edge gateway device encodes these two values ​​according to the IEEE 754 single-precision floating-point format, generating two 32-bit binary floating-point values: the real floating-point value and the imaginary floating-point value. If subsequent upload via the MODBUS protocol is required, each 32-bit floating-point value will be further split into two 16-bit register data (high word and low word), written to the corresponding floating-point storage area, for the master control device to read and reassemble into a complete complex number.

[0124] Understandably, this encoding process converts the original real and imaginary parts (usually fixed-point numbers or integer intermediate results) of the Fourier transform output into a standardized floating-point representation, which facilitates compatibility with industrial communication protocols (such as MODBUS and IEC61850) and supports the main control device to directly parse the complex form of current characteristics, thereby improving data interaction efficiency and analysis flexibility.

[0125] 104. From the multiple floating-point storage areas corresponding to the power supply circuit, determine the real floating-point storage area corresponding to the real floating-point value and the imaginary floating-point storage area corresponding to the imaginary floating-point value.

[0126] The real-part floating-point storage area refers to one or more contiguous storage units specifically allocated for a particular power supply circuit to store the real-part floating-point value of its current vector. This storage area is predetermined during the system initialization phase based on the power supply circuit number, floating-point value type identifier (such as the real part), and the number of data segment splits. Its address is public and fixed to the main control device.

[0127] The virtual floating-point storage area refers to one or more contiguous storage units specifically allocated for the same power supply circuit to store the virtual floating-point values ​​of its current vector. It is physically or logically isolated from the real floating-point storage area, has an independent address space, and is also mapped during initialization to ensure that the virtual data can be accessed independently and unambiguously by the master device.

[0128] For example, for power supply circuit number 3, if the IEEE 754 single-precision floating-point format (32-bit) is used, and each floating-point value needs to be split into two 16-bit registers according to the MODBUS protocol, then the real floating-point storage area may correspond to register addresses 40010–40011, and the imaginary floating-point storage area may correspond to 40012–40013. When writing, the edge gateway device writes the high / low words of the real floating-point value to 40010 and 40011 respectively, and the imaginary floating-point value to 40012 and 40013; the master control device can completely reconstruct the current vector of the circuit by reading these four registers.

[0129] Understandably, by allocating logically separate and fixed-address storage areas for different types of floating-point values ​​(such as real and imaginary parts) of each power supply circuit, the master control device can directly read complete complex current information according to predefined address mapping rules, avoiding data confusion. This improves communication reliability and access efficiency while effectively reducing the amount of data that needs to be transmitted, thereby reducing communication bandwidth usage.

[0130] 105. Write the real part floating-point value into the corresponding real part floating-point storage area and write the imaginary part floating-point value into the corresponding imaginary part floating-point storage area, so that the master control device can read the real part floating-point value and imaginary part floating-point value corresponding to each power supply circuit from the floating-point storage area of ​​the edge gateway device, and determine the operating status of the corresponding power supply circuit based on the real part floating-point value and imaginary part floating-point value of any power supply circuit.

[0131] The main control equipment refers to the upper-level system located in the substation monitoring center or remote dispatch platform, which is used to centrally manage multiple edge gateway devices and perform functions such as data acquisition, status diagnosis, alarm judgment, and visualization. It can access the floating-point storage area of ​​the edge gateway devices through standard industrial communication protocols (such as MODBUS TCP / RTU, IEC61850, etc.).

[0132] Operating status refers to the current electrical working condition of the power supply circuit, including but not limited to: normal operation, overload, abnormal residual current (leakage), phase shift, abnormal power factor, etc. This status can be calculated by the main control equipment based on the read real and imaginary floating-point values. For example, it can be used to determine whether the current amplitude exceeds the limit by using complex modulus values, or to identify ground fault characteristics by calculating phase angles.

[0133] For example, the main control device reads the real part floating-point value (e.g., 120.5A) and imaginary part floating-point value (e.g., -45.3A) of a power supply circuit via the MODBUS protocol, combines them into a complex current vector I = 120.5 − j45.3, and further calculates its amplitude. If the rated threshold (e.g., 125A) is exceeded, the circuit is determined to be in an overload state. If the absolute value of the imaginary part increases significantly while the real part does not change much, it may indicate insulation deterioration or leakage fault. Thus, the main control equipment can promptly trigger alarms, record events, or link protection devices to achieve accurate perception and proactive operation and maintenance of the power supply circuit's operating status.

[0134] Understandably, by completing the structured storage of complex current characteristics on the edge gateway device side, the main control device can directly obtain high-information-density monitoring data without processing the original waveform or relying on intermediate calculations, which significantly improves the overall analysis efficiency and response speed of the system.

[0135] In some embodiments, by splitting a single floating-point value into multiple standard-length data segments according to communication protocol or register width requirements and mapping them to pre-allocated independent storage units, the master control device can efficiently read complete complex current information with minimal granularity through conventional industrial protocols (such as MODBUS), avoiding parsing failures or additional conversion overhead caused by data format mismatches, while improving the parallelism and determinism of multi-loop data access. After encoding the real and imaginary parts of the current vector for each power supply loop according to a preset floating-point format to obtain the real and imaginary floating-point values, the method further includes:

[0136] The real part floating-point value and the imaginary part floating-point value are split into multiple real part data fragments and multiple imaginary part data fragments respectively.

[0137] From the multiple floating-point storage areas corresponding to the power supply circuit, determine the real floating-point storage area corresponding to the real floating-point value and the imaginary floating-point storage area corresponding to the imaginary floating-point value, including:

[0138] From the multiple floating-point storage areas corresponding to the power supply circuit, determine the real floating-point storage area corresponding to each real data segment and the imaginary floating-point storage area corresponding to each imaginary data segment;

[0139] Writing the real part floating-point value to the corresponding real part floating-point storage area and writing the imaginary part floating-point value to the corresponding imaginary part floating-point storage area include:

[0140] Write each real part data segment to its corresponding real part floating-point storage area, and write each imaginary part data segment to its corresponding imaginary part floating-point storage area.

[0141] In this context, a real part data segment refers to one or more consecutive data units obtained by splitting a real part floating-point value (such as a 32-bit IEEE 754 single-precision floating-point number) according to the register width specified by the target communication protocol (usually 16 bits). For example, a 32-bit real part floating-point value can be split into two real part data segments: a high 16-bit segment and a low 16-bit segment.

[0142] The virtual part data segment refers to one or more consecutive data units obtained by splitting a virtual floating-point value according to the register width requirement. Its splitting method is the same as that of the real part data segment, and it is used to independently store and transmit virtual part information.

[0143] For example, the real part of a power supply circuit has a floating-point value of 0x42F10000 (approximately 120.5 in decimal) in IEEE 754 single-precision format, and an imaginary part floating-point value of 0xC235999A (approximately -45.3). Under the MODBUS protocol, each register only supports 16 bits of data. Therefore, the real part floating-point value is split into two real part data segments: a high word of 0x42F1 and a low word of 0x0000; the imaginary part floating-point value is split into two imaginary part data segments: a high word of 0xC235 and a low word of 0x999A. The system writes these four data segments into the four floating-point storage areas corresponding to the power supply circuit (e.g., register addresses 40010 to 40013) according to a preset address mapping rule. The master device only needs to continuously read these four registers to reassemble the complete real and imaginary floating-point values ​​in high-low word order, thereby restoring the current vector and achieving efficient and unambiguous data interaction.

[0144] In some embodiments, by statically constructing an address mapping table or calculating rules during system initialization, precise writing of floating-point data fragments to storage locations and efficient reading by the main control device can be achieved without dynamic lookup or parsing of configurations at runtime, significantly improving the determinism, real-time performance, and protocol compatibility of data access in an operating system-free environment. After allocating the total number of floating-point storage areas from the local storage space of the edge gateway device, the system further includes:

[0145] Based on the floating-point value type corresponding to each power supply circuit and the number of data segments for each floating-point value, a preset mapping relationship is established between the floating-point storage area and the floating-point value data segments;

[0146] From the multiple floating-point storage areas corresponding to the power supply circuit, determine the real floating-point storage area corresponding to the real floating-point value and the imaginary floating-point storage area corresponding to the imaginary floating-point value, including:

[0147] Based on the preset mapping relationship, the real part floating-point storage area corresponding to the real part floating-point value and the imaginary part floating-point value corresponding to the imaginary part floating-point value are determined from multiple floating-point storage areas corresponding to the power supply circuit.

[0148] The floating-point value type refers to the floating-point data of different semantic categories that need to be generated and stored for each power supply circuit. In this application, at least the real and imaginary parts of the current vector are included, so there are usually two floating-point value types; if the support for parameters such as voltage and active power is extended, the number of types will increase accordingly.

[0149] The number of data fragments for a floating-point value refers to the number of consecutive data units that a complete floating-point value (such as a 32-bit IEEE 754 single-precision floating-point number) must be split into according to the target communication protocol or hardware register width requirements. For example, in the MODBUS protocol, each register is 16 bits, and a 32-bit floating-point value needs to be split into two fragments: the high 16 bits and the low 16 bits. In this case, the number of data fragments is 2.

[0150] Pre-defined mapping relationships refer to the deterministic correspondence rules established in advance during the edge gateway device initialization phase, based on the power supply circuit number, floating-point value type, and data segment sequence number, from logical data items to physical / logical storage addresses. This mapping relationship can be implemented using array indexes, address offset formulas, or lookup tables, ensuring that any data segment can be directly located to its corresponding floating-point storage area through simple calculations.

[0151] For example, suppose an edge gateway device monitors 8 power supply loops. Each loop needs to store two types of floating-point values: real and imaginary (number of floating-point value types = 2). Each floating-point value is split into two 16-bit data segments according to MODBUS requirements (number of data segment splits = 2). During system initialization, four consecutive 16-bit registers are allocated for the i-th loop (i starts from 0), with a starting address of Base + i × 4. Here, Base is a starting address (or base address) used to represent the unified entry offset position of the floating-point storage area of ​​all power supply loops in the local storage space of the edge gateway device. For example, in the MODBUS protocol, it may be the starting number of a holding register, such as 40001 (in practice, it is often indexed starting from 0, written as 40000 corresponding to address 0); inside the embedded system, it may be the starting address of a buffer in SRAM (such as 0x20001000).

[0152] Establish the following preset mapping relationship:

[0153]

[0154] When processing loop number 3 (i=3), the system, according to the above mapping relationship, writes the real part high word to Base+12, the real part low word to Base+13, the imaginary part high word to Base+14, and the imaginary part low word to Base+15. The master control device can also accurately reconstruct the complete complex current information by reading these four consecutive registers according to the same rules.

[0155] In some embodiments, by assigning non-overlapping region identifiers to each type of floating-point data segment and establishing a static mapping relationship between them and power supply circuits and data semantics, different types of floating-point values, such as real and imaginary parts, have unique and definite storage locations in the shared storage space. This not only avoids address conflicts between data from multiple circuits but also enables the master control device to directly read complete complex current information according to predefined rules, significantly improving the reliability, real-time performance, and protocol compatibility of data interaction, making it particularly suitable for edge monitoring scenarios without an operating system and with limited resources. Based on the floating-point value type corresponding to each power supply circuit and the number of data segment divisions for each type of floating-point value, a preset mapping relationship is established between the floating-point storage area and the floating-point value data segments, including:

[0156] Based on the total number of floating-point storage areas, the floating-point value type corresponding to each power supply circuit, and the number of data fragments for each floating-point value, a region identifier is assigned to each floating-point storage area. The region identifiers of floating-point storage areas corresponding to different power supply circuits do not overlap.

[0157] Establish a preset mapping relationship between the region identifier of the floating-point storage area corresponding to each power supply circuit and the floating-point value data segment;

[0158] Based on a preset mapping relationship, the real floating-point storage region corresponding to the real floating-point value and the imaginary floating-point storage region corresponding to the imaginary floating-point value are determined from multiple floating-point storage regions corresponding to the power supply circuit, including:

[0159] From the preset mapping relationship, obtain the real region identifier corresponding to the real part floating-point value and the imaginary region identifier corresponding to the imaginary part floating-point value;

[0160] The real part floating-point storage area corresponding to the real part floating-point value is determined based on the real part region identifier, and the imaginary part floating-point storage area corresponding to the imaginary part floating-point value is determined based on the imaginary part region identifier.

[0161] The region identifier refers to the register address or address offset of the floating-point storage region in the local storage space of the edge gateway device, used to uniquely identify a 16-bit data storage unit. This identifier is jointly determined by the base address Base, the power supply circuit number i, the floating-point value type, and the data segment number, and is in the form Base+i×N+k (where N is the number of registers occupied by each circuit, and k is the segment index). It is fixed during system initialization and remains unchanged during operation.

[0162] Preset mapping relationships refer to the static calculation rules established during the system initialization phase, which map floating-point data segments (such as "the high word of the real part of the i-th loop") to their corresponding register addresses (i.e., region identifiers). These rules are usually expressed as address generation formulas, requiring no additional storage of mapping tables and supporting direct addressing with O(1) time complexity.

[0163] The real part region identifier refers to the register address corresponding to a data segment (such as a high word or a low word) of the real part of the current vector of a certain power supply circuit. For example, the region identifier of the high word of the real part of the i-th circuit is Base+i×4+0, and the region identifier of the low word of the real part is Base+i×4+1.

[0164] The imaginary region identifier refers to the register address corresponding to a data segment of the imaginary part of the current vector of the same power supply circuit. For example, the high word of the imaginary part is Base+i×4+2 and the low word of the imaginary part is Base+i×4+3. It is continuous with the real region identifier in the address space but semantically separate and does not conflict with each other.

[0165] For example, suppose the edge gateway device monitors 4 power supply loops (i=0~3). Each loop needs to store two types of floating-point values: real and imaginary. Each type of floating-point value is split into two 16-bit data segments according to the MODBUS protocol. Then each loop occupies 4 consecutive registers, requiring a total of 16 register units.

[0166] With the system configured with base address Base=1000 (representing the starting offset of the MODBUS holding register, corresponding to the externally visible address 41001), the region identifiers (i.e., register address offsets) for each data segment are as follows:

[0167]

[0168] When processing power supply circuit number 2 (i=2): write the real part high word to address 1008 (i.e., area identifier = 1008), write the real part low word to 1009, write the imaginary part high word to 1010, and write the imaginary part low word to 1011.

[0169] The master device can reconstruct the complete current vector of the loop by reading register addresses 41009–41012 (corresponding to internal offsets 1008–1011) via the MODBUS protocol. The entire process does not require maintaining a separate ID table; the area identifier is the physically accessible address, which greatly simplifies the implementation logic of the bare-metal system.

[0170] In some embodiments, a fixed interval may be set between the area identifiers of the floating-point storage areas corresponding to adjacent power supply circuits to reserve expansion space or meet the address alignment requirements of the communication protocol.

[0171] For example, assuming each power supply loop requires four consecutive 16-bit registers (for storing the high / low words of the real and imaginary floating-point values), but the system is configured to allocate an address span of eight registers per loop, then: the floating-point storage area corresponding to the first power supply loop (i=1) is region identifier 1000 to 1003; the floating-point storage area corresponding to the second power supply loop (i=2) is region identifier 1008 to 1011; the intermediate region identifiers 1004 to 1007 are reserved as fixed intervals and are not allocated to any loop. Under this configuration, the starting region identifier of the i-th power supply loop can be represented as: Base + (i−1) × S, where Base = 1000 is the starting base address, S = 8 is the address span allocated to each loop (including the effective region and the interval), the actual number of registers used is 4, and the interval is 4. This design ensures that the data of each loop is neatly distributed in the address space, making it easy for the main control device to access the data in batches at fixed steps. At the same time, it reserves storage space for future additions of monitoring parameters (such as harmonic components, power factor, etc.), improving the scalability and compatibility of the system.

[0172] In some embodiments, by using device address-based request filtering and structured data responses, it is ensured that the edge gateway only uploads high-value complex current information when explicitly addressed, avoiding bus conflicts and invalid communication. Simultaneously, since the real and imaginary parts are encoded in a preset format and stored in a fixed address area, communication responses can be directly assembled from local storage without real-time calculation or format conversion, significantly reducing response latency and CPU overhead, and improving communication determinism and system stability in multi-device coexisting networks. It also includes:

[0173] Receive communication requests sent by the master control device, the communication requests carrying the target address identifier;

[0174] When the target address identifier matches the device address of the edge gateway device, a communication response is returned to the master control device. The communication response contains the real part floating-point value and the imaginary part floating-point value corresponding to each power supply circuit.

[0175] Among them, the communication request refers to the data reading instruction initiated by the master control device to the edge gateway device through the industrial communication bus (such as RS-485, Ethernet). It follows the preset communication protocol (such as MODBUSRTU / TCP, IEC60870-5-103, etc.) and is used to request the specific device to return monitoring data.

[0176] The target address identifier is a unique address field in a communication request used to specify the target slave device (i.e., the target edge gateway device). For example, in the MODBUS protocol, this field is a 1-byte slave address (value 1~247); in the DL / T645 protocol, it is a 6-byte meter address. The master device sets this identifier to indicate which edge gateway device it expects to interact with.

[0177] The device address is a unique identifier for the edge gateway device in the communication network. It is pre-set by a hardware DIP switch, configuration register, or firmware parameter and loaded into the protocol parsing module during the communication initialization phase. This address is used to compare with the target address identifier in the communication request to determine whether to respond to the request.

[0178] A communication response refers to the response message generated by the edge gateway device according to the communication protocol format after confirming that the target address identifier matches. This message contains the requested monitoring data. In this embodiment, the response data includes at least the real and imaginary floating-point values ​​of each power supply circuit (usually arranged in address order as split 16-bit data segments), which are used by the main control device to reassemble the complex current vector and analyze the operating status.

[0179] In some embodiments, this mechanism effectively avoids invalid responses from non-target edge gateway devices to the master control device, preventing communication conflicts or data frame collisions caused by simultaneous responses from multiple devices, and is particularly suitable for half-duplex multi-point bus architectures such as RS-485. In edge gateway devices without an operating system and with limited resources, this strategy significantly reduces protocol processing overhead—the device only parses subsequent instructions and organizes responses when the address matches, and ignores the message in other cases, thereby improving system real-time performance, communication robustness, and overall network throughput efficiency. It also includes:

[0180] When the target address identifier does not match the device address of the edge gateway device, the communication request is discarded and no response is returned to the master device.

[0181] Understandably, the communication employs a master-slave polling mechanism, where the master device (host) actively initiates requests, and the edge gateway device (slave) only returns a response when addressed, forming a "question and answer" interaction mode. The communication protocol includes an address code field; the edge gateway will only parse the instruction and return data if the target address in the request matches the local device address; otherwise, the request is discarded without any response.

[0182] To ensure polling efficiency, the system sets a communication timeout threshold of 500ms. If the host does not receive a response within this time, it determines that the current device has failed to communicate and immediately starts querying the next device, thus avoiding overall polling shutdown due to a single point of failure.

[0183] In this application, the edge gateway device performs full-cycle sampling and 128-point FFT calculation of the current signal locally, and only uploads the real and imaginary parts (in floating-point form) of the current vector corresponding to each power supply circuit to the main control device, instead of transmitting the original time-domain sampled waveform. This design significantly reduces the communication load. Taking a typical configuration as an example: if the original waveform is uploaded in the traditional way (e.g., 64 points per cycle, 64 32-bit sampled values ​​are collected every 20ms in a 50Hz system), the data volume of a single upload for 16 channels is: 16 × 64 × 4 = 4096 bytes (approximately 4KB); while this application only uploads the fundamental vector result (2 floating-point numbers + channel identifier per channel, calculated at 10 bytes / channel), the total data volume for 16 channels is only 160 bytes. The communication data volume is reduced by 96% (1−160 / 4096≈96.1%), which greatly alleviates the bandwidth pressure of low-speed serial buses (e.g., 9600bps RS-485). By combining a master-slave polling mechanism with an address filtering strategy, the full data upload time for a single device can be controlled within 170ms, and dozens of devices in the entire network can complete a full round of monitoring within 20 seconds. Even if some nodes time out, they can be quickly skipped, ensuring the overall real-time performance of the system.

[0184] More importantly, this solution embodies the core idea of ​​collaborative optimization between edge computing and protocols:

[0185] Edge gateway devices perform high-density sampling, FFT transformation, and complex encoding to transform the original waveform (high bandwidth, low information density) into a structured vector (low bandwidth, high semantic value).

[0186] The main control device uses a lightweight, address-addressable industrial protocol, transmitting only necessary status characteristics.

[0187] This architecture not only significantly reduces communication overhead, but also improves the system's scalability (supporting more loops or device access), real-time performance (fast response, low-latency polling), and reliability (reducing bus conflicts and packet loss risks). It perfectly aligns with the development trend of "intelligent front-end and lightweight back-end" in the Industrial Internet of Things (IIoT), providing an efficient and economical implementation path for large-scale power distribution monitoring.

[0188] In summary, this application extracts the real and imaginary parts of the current vector corresponding to each power supply circuit locally on the edge gateway device, encodes them in floating-point format, and writes them into a floating-point storage area independently configured for that circuit. This avoids the high communication load of uploading the original waveform and provides a richer data dimension than the effective value. It realizes the structured storage and efficient reading of multi-power supply circuit data, and improves the data acquisition efficiency and analysis flexibility on the main control device side.

[0189] To better implement the above methods, this application also provides a circuit monitoring device, which can be integrated into an electronic device, such as a terminal or server. The terminal can be a mobile phone, tablet computer, smart Bluetooth device, laptop computer, or personal computer; the server can be a single server or a server cluster composed of multiple servers.

[0190] For example, in this embodiment, a circuit monitoring device specifically integrated into an electronic device will be used as an example to describe the method of this application embodiment in detail.

[0191] For example, such as Figure 2 As shown, this circuit monitoring device is applied to an edge gateway device. The edge gateway device includes at least one power supply circuit and multiple floating-point storage areas corresponding to each power supply circuit. The floating-point storage areas corresponding to different power supply circuits do not overlap. It may include a signal acquisition unit 201, a signal conversion unit 202, an encoding unit 203, a region determination unit 204, and a floating-point value writing unit 205, as follows:

[0192] (a) Signal acquisition unit 201.

[0193] The signal acquisition unit 201 is used to acquire the current signal of each power supply circuit within a preset time window.

[0194] In some embodiments, acquiring the current signal of each power supply circuit within a preset time window includes:

[0195] The current of each power supply circuit is sampled according to the preset sampling frequency, and the current sampled values ​​are cached.

[0196] For each power supply circuit, when the number of buffered current sample values ​​reaches the preset number of samples corresponding to the preset time window, the buffered current sample values ​​are used as the current signal of the corresponding power supply circuit within the preset time window.

[0197] In some embodiments, before acquiring the current signal of each power supply circuit within a preset time window, the method further includes:

[0198] Obtain the number of power supply circuits with at least one power supply circuit;

[0199] Based on the number of power supply circuits, the number of floating-point value types corresponding to each power supply circuit, and the number of data fragments for each type of floating-point value, determine the total number of floating-point storage areas required.

[0200] Allocate the total number of floating-point storage areas from the local storage space of the edge gateway device.

[0201] In some embodiments, after allocating the total number of floating-point storage regions from the local storage space of the edge gateway device, the method further includes:

[0202] Based on the floating-point value type corresponding to each power supply circuit and the number of data segments for each floating-point value, a preset mapping relationship is established between the floating-point storage area and the floating-point value data segments;

[0203] From the multiple floating-point storage areas corresponding to the power supply circuit, determine the real floating-point storage area corresponding to the real floating-point value and the imaginary floating-point storage area corresponding to the imaginary floating-point value, including:

[0204] Based on the preset mapping relationship, the real part floating-point storage area corresponding to the real part floating-point value and the imaginary part floating-point value corresponding to the imaginary part floating-point value are determined from multiple floating-point storage areas corresponding to the power supply circuit.

[0205] In some embodiments, a preset mapping relationship between floating-point storage areas and floating-point data segments is established based on the floating-point value type corresponding to each power supply circuit and the number of data segment divisions for each floating-point value, including:

[0206] Based on the total number of floating-point storage areas, the floating-point value type corresponding to each power supply circuit, and the number of data fragments for each floating-point value, a region identifier is assigned to each floating-point storage area. The region identifiers of floating-point storage areas corresponding to different power supply circuits do not overlap.

[0207] Establish a preset mapping relationship between the region identifier of the floating-point storage area corresponding to each power supply circuit and the floating-point value data segment;

[0208] Based on a preset mapping relationship, the real floating-point storage region corresponding to the real floating-point value and the imaginary floating-point storage region corresponding to the imaginary floating-point value are determined from multiple floating-point storage regions corresponding to the power supply circuit, including:

[0209] From the preset mapping relationship, obtain the real region identifier corresponding to the real part floating-point value and the imaginary region identifier corresponding to the imaginary part floating-point value;

[0210] The real part floating-point storage area corresponding to the real part floating-point value is determined based on the real part region identifier, and the imaginary part floating-point storage area corresponding to the imaginary part floating-point value is determined based on the imaginary part region identifier.

[0211] (ii) Signal conversion unit 202.

[0212] The signal transformation unit 202 is used to perform Fourier transform processing on the current signal corresponding to each power supply circuit to obtain the current vector corresponding to each power supply circuit. The current vector includes a real part and an imaginary part. The real part represents the projection component of the corresponding current signal on the reference cosine component, and the imaginary part represents the projection component of the corresponding current signal on the reference sine component.

[0213] In some embodiments, the current signal is a discrete sequence of multiple current sample values ​​collected in chronological order within a preset time window for the corresponding power supply circuit.

[0214] Perform Fourier transform on the current signals corresponding to each power supply circuit to obtain the current vector for each power supply circuit. The current vector includes a real part and an imaginary part, including:

[0215] For the current signal of each power supply circuit, the harmonic angle index corresponding to each current sample value is calculated based on the preset harmonic order and the sampling point number corresponding to each current sample value.

[0216] Based on the harmonic angle index, the corresponding reference cosine value and reference sine value are obtained from the preset cosine lookup table and sine lookup table respectively;

[0217] The real part of the current vector is obtained by multiplying each current sample value within the preset time window with its corresponding reference cosine value and summing the results.

[0218] The imaginary part of the current vector is obtained by multiplying each current sample value within a preset time window with its corresponding reference sine value and summing the results.

[0219] (iii) Encoding unit 203.

[0220] The encoding unit 203 is used to encode the real part and imaginary part of the current vector for each power supply circuit according to a preset floating-point format, so as to obtain the real part floating-point value and the imaginary part floating-point value.

[0221] (iv) Region determination unit 204.

[0222] The region determination unit 204 is used to determine, from multiple floating-point storage regions corresponding to the power supply circuit, the real floating-point storage region corresponding to the real floating-point value and the imaginary floating-point storage region corresponding to the imaginary floating-point value.

[0223] (v) Floating-point value writing unit 205.

[0224] The floating-point value writing unit 205 is used to write the real part floating-point value into the corresponding real part floating-point storage area and the imaginary part floating-point value into the corresponding imaginary part floating-point storage area, so that the master control device can read the real part floating-point value and imaginary part floating-point value corresponding to each power supply circuit from the floating-point storage area of ​​the edge gateway device, and determine the operating status of the corresponding power supply circuit based on the real part floating-point value and imaginary part floating-point value of any power supply circuit.

[0225] In some embodiments, after encoding the real and imaginary parts of the current vector for each power supply circuit according to a preset floating-point format to obtain the real floating-point value and the imaginary floating-point value, the method further includes:

[0226] The real part floating-point value and the imaginary part floating-point value are split into multiple real part data fragments and multiple imaginary part data fragments respectively.

[0227] From the multiple floating-point storage areas corresponding to the power supply circuit, determine the real floating-point storage area corresponding to the real floating-point value and the imaginary floating-point storage area corresponding to the imaginary floating-point value, including:

[0228] From the multiple floating-point storage areas corresponding to the power supply circuit, determine the real floating-point storage area corresponding to each real data segment and the imaginary floating-point storage area corresponding to each imaginary data segment;

[0229] Writing the real part floating-point value to the corresponding real part floating-point storage area and writing the imaginary part floating-point value to the corresponding imaginary part floating-point storage area include:

[0230] Write each real part data segment to its corresponding real part floating-point storage area, and write each imaginary part data segment to its corresponding imaginary part floating-point storage area.

[0231] In some embodiments, it also includes:

[0232] Receive communication requests sent by the master control device, the communication requests carrying the target address identifier;

[0233] When the target address identifier matches the device address of the edge gateway device, a communication response is returned to the master control device. The communication response contains the real part floating-point value and the imaginary part floating-point value corresponding to each power supply circuit.

[0234] In some embodiments, it also includes:

[0235] When the target address identifier does not match the device address of the edge gateway device, the communication request is discarded and no response is returned to the master device.

[0236] In practice, each of the above units can be implemented as an independent entity or can be arbitrarily combined to be implemented as the same or several entities. For the specific implementation of each of the above units, please refer to the previous method embodiments, which will not be repeated here.

[0237] Therefore, this embodiment of the application extracts the real and imaginary parts of the current vector corresponding to each power supply circuit locally on the edge gateway device, and writes them into a floating-point storage area configured independently for that circuit after encoding in floating-point format. This avoids the high communication load of uploading the original waveform and provides a richer data dimension than the effective value. It realizes the structured storage and efficient reading of multi-power supply circuit data, and improves the data acquisition efficiency and analysis flexibility on the main control device side.

[0238] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0239] Therefore, embodiments of this application provide a computer-readable storage medium storing a plurality of instructions that can be loaded by a processor to execute the steps in any of the circuit monitoring methods provided in embodiments of this application.

[0240] The storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0241] Since the instructions stored in the storage medium can execute the steps of any of the circuit monitoring methods provided in the embodiments of this application, the beneficial effects that any of the circuit monitoring methods provided in the embodiments of this application can achieve can be realized, as detailed in the preceding embodiments, and will not be repeated here.

[0242] According to one aspect of this application, a computer program product or computer program is provided, comprising a computer program / instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer program / instructions from the computer-readable storage medium and executes the computer program / instructions, causing the electronic device to perform the method provided in the circuit monitoring aspect of the above embodiments.

[0243] The circuit monitoring method and apparatus provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A circuit monitoring method, characterized in that, The method is applied to an edge gateway device, which includes at least one power supply loop and multiple floating-point storage areas corresponding to each power supply loop, wherein the floating-point storage areas corresponding to different power supply loops do not overlap. Acquire the current signal of each power supply circuit within a preset time window; Fourier transform is performed on the current signal corresponding to each power supply circuit to obtain the current vector corresponding to each power supply circuit. The current vector includes a real part and an imaginary part. The real part represents the projection component of the corresponding current signal on the reference cosine component, and the imaginary part represents the projection component of the corresponding current signal on the reference sine component. For each power supply circuit, the real and imaginary parts of the current vector are encoded according to a preset floating-point format to obtain the real floating-point value and the imaginary floating-point value. From the multiple floating-point storage areas corresponding to the power supply circuit, determine the real floating-point storage area corresponding to the real floating-point value and the imaginary floating-point storage area corresponding to the imaginary floating-point value; The real floating-point value is written into the corresponding real floating-point storage area, and the imaginary floating-point value is written into the corresponding imaginary floating-point storage area, so that the master control device can read the real and imaginary floating-point values ​​corresponding to each power supply circuit from the floating-point storage area of ​​the edge gateway device, and determine the operating status of the corresponding power supply circuit based on the real and imaginary floating-point values ​​of any power supply circuit.

2. The method as described in claim 1, characterized in that, The acquisition of the current signal of each power supply circuit within a preset time window includes: The current of each power supply circuit is sampled according to the preset sampling frequency, and the current sampled values ​​are cached. For each power supply circuit, when the number of cached current sample values ​​reaches the preset number of samples corresponding to the preset time window, the cached current sample values ​​are used as the current signal of the corresponding power supply circuit within the preset time window.

3. The method as described in claim 1, characterized in that, The current signal is a discrete sequence of multiple current sample values ​​collected in chronological order within the preset time window for the corresponding power supply circuit. The Fourier transform processing of the current signals corresponding to each power supply circuit yields a current vector for each power supply circuit. The current vector includes a real part and an imaginary part, comprising: For the current signal of each power supply circuit, the harmonic angle index corresponding to each current sample value is calculated according to the preset harmonic order and the sampling point number corresponding to each current sample value. Based on the harmonic angle index, the corresponding reference cosine value and reference sine value are obtained from the preset cosine lookup table and sine lookup table, respectively. The real part of the current vector is obtained by multiplying each current sample value within the preset time window with its corresponding reference cosine value and summing the results. The imaginary part of the current vector is obtained by multiplying each current sample value within the preset time window with its corresponding reference sine value and summing the results.

4. The method as described in claim 1, characterized in that, After encoding the real and imaginary parts of the current vector for each power supply circuit according to a preset floating-point format to obtain the real and imaginary floating-point values, the method further includes: The real part floating-point value and the imaginary part floating-point value are split into multiple real part data segments and multiple imaginary part data segments respectively. Determining the real-part floating-point storage area corresponding to the real-part floating-point value and the imaginary-part floating-point storage area corresponding to the imaginary-part floating-point value from the plurality of floating-point storage areas corresponding to the power supply circuit includes: From the multiple floating-point storage areas corresponding to the power supply circuit, determine the real floating-point storage area corresponding to each real data segment and the imaginary floating-point storage area corresponding to each imaginary data segment; The step of writing the real part floating-point value into the corresponding real part floating-point storage area and writing the imaginary part floating-point value into the corresponding imaginary part floating-point storage area includes: Each real part data segment is written to its corresponding real part floating-point storage area, and each imaginary part data segment is written to its corresponding imaginary part floating-point storage area.

5. The method as described in claim 1, characterized in that, Before acquiring the current signal of each power supply circuit within a preset time window, the method further includes: Obtain the number of power supply circuits of the at least one power supply circuit; Based on the number of power supply circuits, the number of floating-point value types corresponding to each power supply circuit, and the number of data segment splits for each type of floating-point value, determine the total number of floating-point storage areas required. Allocate the total number of floating-point storage areas from the local storage space of the edge gateway device.

6. The method as described in claim 5, characterized in that, After allocating the total number of floating-point storage areas from the local storage space of the edge gateway device, the method further includes: Based on the floating-point value type corresponding to each power supply circuit and the number of data segments for each floating-point value, a preset mapping relationship is established between the floating-point storage area and the floating-point value data segments; Determining the real-part floating-point storage area corresponding to the real-part floating-point value and the imaginary-part floating-point storage area corresponding to the imaginary-part floating-point value from the plurality of floating-point storage areas corresponding to the power supply circuit includes: Based on the preset mapping relationship, the real part floating-point storage area corresponding to the real part floating-point value and the imaginary part floating-point value corresponding to the imaginary part floating-point value are determined from multiple floating-point storage areas corresponding to the power supply circuit.

7. The method as described in claim 6, characterized in that, The step of establishing a preset mapping relationship between floating-point storage areas and floating-point data segments based on the floating-point value type corresponding to each power supply circuit and the number of data segments for each floating-point value includes: Based on the total number of floating-point storage areas, the floating-point value type corresponding to each power supply circuit, and the number of data segment splits for each floating-point value, a region identifier is assigned to each floating-point storage area, and the region identifiers of floating-point storage areas corresponding to different power supply circuits do not overlap. Establish a preset mapping relationship between the region identifier of the floating-point storage area corresponding to each power supply circuit and the floating-point value data segment; The step of determining, based on the preset mapping relationship, the real part floating-point storage area corresponding to the real part floating-point value and the imaginary part floating-point storage area corresponding to the imaginary part floating-point value from multiple floating-point storage areas corresponding to the power supply circuit includes: From the preset mapping relationship, obtain the real region identifier corresponding to the real part floating-point value and the imaginary region identifier corresponding to the imaginary part floating-point value; The real part floating-point storage area corresponding to the real part floating-point value is determined based on the real part region identifier, and the imaginary part floating-point storage area corresponding to the imaginary part floating-point value is determined based on the imaginary part region identifier.

8. The method as described in claim 1, characterized in that, Also includes: Receive a communication request sent by the master control device, wherein the communication request carries a target address identifier; When the target address identifier matches the device address of the edge gateway device, a communication response is returned to the master control device. The communication response contains the real part floating-point value and the imaginary part floating-point value corresponding to each power supply circuit.

9. The method as described in claim 8, characterized in that, Also includes: When the target address identifier does not match the device address of the edge gateway device, the communication request is discarded and no response is returned to the master control device.

10. A circuit monitoring device, characterized in that, An edge gateway device is applied to an edge gateway device, the edge gateway device including at least one power supply loop and multiple floating-point storage areas corresponding to each power supply loop, wherein the floating-point storage areas corresponding to different power supply loops do not overlap, the device comprising: The signal acquisition unit is used to acquire the current signal of each power supply circuit within a preset time window; The signal transformation unit is used to perform Fourier transform processing on the current signal corresponding to each power supply circuit to obtain the current vector corresponding to each power supply circuit. The current vector includes a real part and an imaginary part. The real part represents the projection component of the corresponding current signal on the reference cosine component, and the imaginary part represents the projection component of the corresponding current signal on the reference sine component. The encoding unit is used to encode the real part and imaginary part of the current vector corresponding to each power supply circuit according to a preset floating-point format, so as to obtain the real part floating-point value and the imaginary part floating-point value. The region determination unit is used to determine, from multiple floating-point storage regions corresponding to the power supply circuit, the real floating-point storage region corresponding to the real floating-point value and the imaginary floating-point storage region corresponding to the imaginary floating-point value. The floating-point value writing unit is used to write the real part floating-point value into the corresponding real part floating-point storage area and to write the imaginary part floating-point value into the corresponding imaginary part floating-point storage area, so that the master control device can read the real part floating-point value and imaginary part floating-point value corresponding to each power supply circuit from the floating-point storage area of ​​the edge gateway device, and determine the operating status of the corresponding power supply circuit based on the real part floating-point value and imaginary part floating-point value of any power supply circuit.

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